SCLS398G − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP (Output Ground Bounce) D D D 1OE 1A1 1Y1 1A2 1Y2 1A3 1Y3 GND <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C Support Mixed-Mode Voltage Operation on All Ports Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 2OE 2A2 2Y2 2A1 2Y1 1A4 1Y4 SN54LV367A . . . FK PACKAGE (TOP VIEW) 1A1 1OE NC VCC 2OE D SN54LV367A . . . J OR W PACKAGE SN74LV367A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) description/ordering information 1Y1 1A2 NC 1Y2 1A3 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2A2 2Y2 NC 2A1 2Y1 1Y3 GND NC 1Y4 1A4 The ’LV367A devices are hex buffers and line drivers designed for 2-V to 5.5-V VCC operation. These devices are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’LV367A devices are organized as dual 4-line and 2-line buffers/drivers with active-low output-enable (1OE and 2OE) inputs. When OE is low, the device passes noninverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. NC − No internal connection To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION SN74LV367AD Reel of 2500 SN74LV367ADR SOP − NS Reel of 2000 SN74LV367ANSR 74LV367A SSOP − DB Reel of 2000 SN74LV367ADBR LV36A Reel of 2000 SN74LV367APWR Reel of 250 SN74LV367APWT TVSOP − DGV Reel of 2000 SN74LV367ADGVR LV367A CDIP − J Tube of 25 SNJ54LV367AJ SNJ54LV367AJ CFP − W Tube of 150 SNJ54LV367AW SNJ54LV367AW LCCC − FK Tube of 55 SNJ54LV367AFK TSSOP − PW −55°C −55 C to 125 125°C C TOP-SIDE MARKING Tube of 40 SOIC − D −40°C −40 C to 85 85°C C ORDERABLE PART NUMBER PACKAGE† TA LV367A LV367A SNJ54LV367AFK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2005, Texas Instruments Incorporated !"#$% !%&% ' %()#&% !"))$% & ( *"+,!&% &$- )"! !%()# *$!(!&% *$) $ $)# ( $.& %)"#$% &%&) /&))&%0)"!% *)!$%1 $ % %$!$&),0 %!,"$ $%1 ( &,, *&)&#$$)POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCLS398G − APRIL 1998 − REVISED APRIL 2005 FUNCTION TABLE (each buffer/driver) INPUTS OE A OUTPUT Y L H H L L L H X Z logic diagram (positive logic) 1OE 1A1 1 2 2OE 3 1Y1 2A1 15 12 To Three Other Channels 11 2Y1 To One Other Channel Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Output voltage range applied in the high or low state, VO (see Notes 1 and 2) . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCLS398G − APRIL 1998 − REVISED APRIL 2005 recommended operating conditions (see Note 4) SN54LV367A VCC VIH Supply voltage High-level input voltage VIL Low-level input voltage VI Input voltage VO Output voltage IOH IOL ∆t/∆v High-level output current Low-level output current Input transition rise or fall rate VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V SN74LV367A MIN MAX 2 5.5 1.5 MIN MAX 2 5.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 0.5 0 High or low state 0 3-state 0 VCC × 0.3 5.5 VCC 5.5 V 0.5 VCC × 0.3 VCC × 0.3 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V V 1.5 VCC × 0.7 VCC × 0.7 VCC = 2 V VCC = 2.3 V to 2.7 V UNIT VCC × 0.3 VCC × 0.3 0 0 0 VCC × 0.3 5.5 V V VCC 5.5 V µA VCC = 2 V VCC = 2.3 V to 2.7 V −50 −50 −2 −2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V −8 −8 −16 −16 VCC = 2 V VCC = 2.3 V to 2.7 V 50 50 2 2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 8 8 16 16 VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V 200 200 100 100 VCC = 4.5 V to 5.5 V 20 20 mA µA mA ns/V TA Operating free-air temperature −55 125 −40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. ' %()#&% !%!$)% *)"! % $ ()#&2$ ) $1% *&$ ( $2$,*#$%- '&)&!$)! && &% $) *$!(!&% &)$ $1% 1&,- $.& %)"#$% )$$)2$ $ )1 !&%1$ ) !%%"$ $$ *)"! /" %!$- POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SCLS398G − APRIL 1998 − REVISED APRIL 2005 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LV367A PARAMETER VOH VOL TEST CONDITIONS IOH = −50 µA IOH = −2 mA VCC MIN 2 V to 5.5 V IOL = 50 µA IOL = 2 mA IOL = 8 mA IOL = 16 mA MAX MIN VCC−0.1 2 VCC−0.1 2 3V 2.48 2.48 4.5 V 3.8 2.3 V IOH = −8 mA IOH = −16 mA SN74LV367A TYP TYP MAX UNIT V 3.8 2 V to 5.5 V 0.1 0.1 2.3 V 0.4 0.4 3V 0.44 0.44 4.5 V 0.55 0.55 0 to 5.5 V ±1 ±1 µA 5.5 V ±5 ±5 µA 20 20 µA 5 µA V II IOZ VI = 5.5 V or GND VO = VCC or GND ICC Ioff VI = VCC or GND, IO = 0 VI or VO = 0 to 5.5 V 5.5 V Ci VI = VCC or GND VI = VCC or GND 3.3 V 3 3 pF 3.3 V 5.2 5.2 pF Co 0 5 switching characteristics over recommended operating VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tpd ten A Y OE Y tdis OE Y tpd ten A OE tdis OE LOAD CAPACITANCE free-air TA = 25°C MIN TYP MAX temperature SN54LV367A range, SN74LV367A MIN MAX MIN MAX 6.4* 12.7* 1* 16* 1 16 6.9* 14.9* 1* 20* 1 20 6.4* 14.9* 1* 20* 1 20 Y 8.6 17.5 1 21 1 21 Y 9.4 19.7 1 25 1 25 10.1 19.7 1 25 1 25 CL = 15 pF CL = 50 pF Y tsk(o) 2 UNIT ns ns 2 * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE TA = 25°C MIN TYP MAX temperature SN54LV367A MIN MAX MIN MAX A Y 4.7* 8.3* 1* 10* 1 10 OE Y 5.1* 10.5* 1* 12.5* 1 12.5 tdis OE Y 4.9* 10.5* 1* 12.5* 1 12.5 tpd ten A Y 6.2 11.8 1 13.5 1 13.5 OE Y 6.8 14 1 16 1 16 tdis OE 7.3 13.6 1 15.5 1 15.5 Y CL = 15 pF CL = 50 pF tsk(o) 1.5 ' %()#&% !%!$)% *)"! % $ ()#&2$ ) $1% *&$ ( $2$,*#$%- '&)&!$)! && &% $) *$!(!&% &)$ $1% 1&,- $.& %)"#$% )$$)2$ $ )1 !&%1$ ) !%%"$ $$ *)"! /" %!$- POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 range, SN74LV367A tpd ten * On products compliant to MIL-PRF-38535, this parameter is not production tested. 4 free-air 1.5 UNIT ns ns SCLS398G − APRIL 1998 − REVISED APRIL 2005 switching characteristics over recommended operating VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tpd ten A Y OE Y tdis OE tpd A ten OE Y tdis OE LOAD CAPACITANCE MIN free-air TA = 25°C TYP MAX temperature SN54LV367A MIN range, SN74LV367A MAX MIN MAX 3.6* 5.9* 1* 7* 1 7 3.8* 7.2* 1* 8.5* 1 8.5 Y 2.6* 7.2* 1* 8.5* 0 8.5 Y 4.5 7.9 1 9 1 9 4.9 9.2 1 10.5 1 10.5 4.5 9.2 1 10.5 0 10.5 CL = 15 pF CL = 50 pF Y tsk(o) 1 UNIT ns ns 1 * On products compliant to MIL-PRF-38535, this parameter is not production tested. noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5) SN74LV367A PARAMETER MIN TYP MAX UNIT VOL(P) VOL(V) Quiet output, maximum dynamic VOL 0.5 0.8 V Quiet output, minimum dynamic VOL −0.2 −0.8 V VOH(V) VIH(D) Quiet output, minimum dynamic VOH 3 High-level dynamic input voltage V 2.31 V VIL(D) Low-level dynamic input voltage NOTE 5: Characteristics are for surface-mount packages only. 0.99 V VCC 3.3 V TYP UNIT 5V 17.4 operating characteristics, TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS CL = 50 pF, f = 10 MHz 14.9 pF ' %()#&% !%!$)% *)"! % $ ()#&2$ ) $1% *&$ ( $2$,*#$%- '&)&!$)! && &% $) *$!(!&% &)$ $1% 1&,- $.& %)"#$% )$$)2$ $ )1 !&%1$ ) !%%"$ $$ *)"! /" %!$- POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SCLS398G − APRIL 1998 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input tw tsu VCC 50% VCC Input 50% VCC 0V th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC 50% VCC Input 50% VCC tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output 0V VOH 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 50% VCC 50% VCC 0V tPLZ tPZL ≈VCC 50% VCC Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ tPZH tPLH 50% VCC VCC Output Control 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LV367AD ACTIVE SOIC D 16 SN74LV367ADBR ACTIVE SSOP DB SN74LV367ADBRE4 ACTIVE SSOP SN74LV367ADBRG4 ACTIVE SN74LV367ADE4 40 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM DB 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SSOP DB 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV367ADG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV367ADGVR ACTIVE TVSOP DGV 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV367ADGVRE4 ACTIVE TVSOP DGV 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV367ADGVRG4 ACTIVE TVSOP DGV 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV367ADR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV367ADRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV367ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV367ANSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV367ANSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV367ANSRG4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV367APWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV367APWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV367APWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV367APWT ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV367APWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV367APWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV367AQPWRQ1 OBSOLETE TSSOP PW 16 TBD Call TI (1) Call TI The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.6 2.5 12.0 16.0 Q1 SN74LV367ADBR SSOP DB 16 2000 330.0 16.4 8.2 SN74LV367ADGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 SN74LV367ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74LV367ANSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74LV367APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV367APWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV367ADBR SSOP DB 16 2000 367.0 367.0 38.0 SN74LV367ADGVR TVSOP DGV 16 2000 367.0 367.0 35.0 SN74LV367ADR SOIC D 16 2500 333.2 345.9 28.6 SN74LV367ANSR SO NS 16 2000 367.0 367.0 38.0 SN74LV367APWR TSSOP PW 16 2000 367.0 367.0 35.0 SN74LV367APWT TSSOP PW 16 250 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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