MX29LA641D H/L 64M-BIT [4M x 16/8M x 8] CMOS EQUAL SECTOR FLASH MEMORY FEATURES GENERAL FEATURES • 8M Bytes/4M Words switchable • 128 Equal Sectors with 64K Bytes (32K words) each - Any combination of sectors can be erased with erase suspend/resume function • Single Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations • Latch-up protected to 100mA from -1.0V to 1.5 x Vcc • Low Vcc write inhibit is equal to or less than VLKO • Compatible with JEDEC standard - Pinout and software compatible to single power supply Flash PERFORMANCE • High Performance - Access time: 90ns - Program time: 11us/word - Erase time: 0.7s/sector, 45s/chip (typical) • Low Power Consumption - Low active read current: 9mA (typical) at 5MHz - Low standby current: 5uA(typical) • 100,000 erase/program cycles (typical) • 10 years data retention SOFTWARE FEATURES • Support Common Flash Interface (CFI) - Flash device parameters stored on the device and provide the host system to access • Erase Suspend/ Erase Resume - Suspends sector erase operation to read data from or program data to another sector which is not being erased • Status Reply - Data# polling & Toggle bits provide detection of program and erase operation completion or not HARDWARE FEATURES • Ready/Busy (RY/BY#) Output - Provides a hardware method of detecting program and erase operation completion • Hardware Reset (RESET#) Input - Provides a hardware method to reset the internal state machine to read mode • ACC input pin - Provides accelerated program capability • WP#/ACC input - Write protect (WP#) function allows protection highest or lowest sector, regardless of sector protection settings SECURITY • Sector Protection/Chip Unprotect - Provides sector protect function to prevent program or erase operation in the protected sector - Provides chip unprotect function to allow code changes - Provides temporary sector unprotect function for code changes in previously protected sector • Sector Permanent Lock - A unique lock bit feature allows the content to be permanently locked P/N:PM1289 REV. 1.1, JAN. 06, 2009 1 MX29LA641D H/L (Please contact Macronix sales for specific information regarding this permanent lock feature) • Secured Silicon Sector - Provides a 128-word area for code or data that can be permanently protected - Once this sector is protected, it is prohibited to program or erase within the sector again PACKAGE • 64-ball BGA • All Pb-free devices are RoHS Compliant GENERAL DESCRIPTION MX29LA641D H/L is a 64Mbit flash memory that can be organized as 8Mbytes of 8 bits each or as 4Mbytes of 16 bits each. These devices operate over a voltage range of 2.7V to 3.6V typically using a 3V power supply input. The memory array is divided into 128 equal 64 Kilo byte blocks. The MX29LA641D H/L is offered in a 64-ball BGA(LFBGA) JEDEC standard package. The package is offered in leaded, as well as lead-free version that is compliant to the RoHS specifications. The software algorithm used for this device also adheres to the JEDEC standard for single power supply devices. These flash parts can be programmed in system or on commercially available EPROM/Flash programmers. Separate OE# and CEx (Output Enable and Chip Enable) signals are provided to simplify system design. When used with high speed processors, the 90ns read access time of this flash memory permits operation with minimal time lost due to system timing delays. The automatic write algorithm provided on Macronix flash memories perform an automatic erase prior to write. The user only needs to provide a write command to the command register. The on-chip state machine automatically controls the program and erase functions including all necessary internal timings. Since erase and write operations take much longer time than read operations, erase/write can be interrupted to perform read operations in other sectors of the device. For this, Erase Suspend operation along with Erase Resume operation are provided. Data# polling or Toggle bits are used to indicate the end of the erase/write operation. The device is manufactured at the Macronix fabrication facility using the time tested and proven MXIC advanced technology. This proprietary non-epi process provides a very high degree of latch-up protection for stresses up to 100 milliamperes on address and data pins from -1V to 1.5xVCC. With low power consumption and enhanced hardware and software features, this flash memory retains data reliably for at least ten years. Erase and programming functions have been tested to meet a typical specification of 100,000 cycles of operation. P/N:PM1289 REV. 1.1, JAN. 06, 2009 2 MX29LA641D H/L PIN CONFIGURATION Please contact Macronix sales for specific information regarding 64-ball BGA (10x13mm) package pin configuration. PIN DESCRIPTION SYMBOL A0~A21/A-1 Q0~Q15 CE0~CE2 WE# OE# RESET# WP#/ACC RY/BY# BYTE# VCC VI/O GND NC LOGIC SYMBOL PIN NAME Address Input/LSB addr (Byte Mode) 16 Data Inputs/Outputs Chip Enable Input (CEx) Write Enable Input Output Enable Input Hardware Reset Pin, Active Low Hardware Write Protect Input/ Hardware Acceleration Pin Read/Busy Output Select 8 bit or 16 bit mode +3.0V single power supply Output Power Supply (2.7V~3.6V), which is tied to VCC Device Ground Pin Not Connected Internally 22 A0-A21 (A-1) 16 Q0-Q15 CEx OE# WE# RESET# WP#/ACC RY/BY# V I/O P/N:PM1289 REV. 1.1, JAN. 06, 2009 3 MX29LA641D H/L Chip Enable Truth Table DEVICE CE0 CE1 CE2 Enabled VIL VIL VIL Disabled VIL VIH VIL Enabled VIL VIL VIH Enabled VIL VIH VIH Disabled VIH VIL VIL Disabled VIH VIH VIL Enabled VIH VIL VIH Disabled VIH VIH VIH Note: For Single-chip applications, CE2 and CE1 can be strapped to GND. P/N:PM1289 REV. 1.1, JAN. 06, 2009 4 MX29LA641D H/L BLOCK DIAGRAM VCC GND CEx OE# WE# RESET# WP# ACC WRITE CONTROL LOGIC STATE HIGH VOLTAGE MACHINE (WSM) LATCH BUFFER STATE FLASH REGISTER ARRAY ARRAY Y-DECODER AND X-DECODER ADDRESS A0-A21 PROGRAM/ERASE INPUT Y-PASS GATE SOURCE HV COMMAND DATA DECODER SENSE AMPLIFIER PGM DATA HV COMMAND DATA LATCH PROGRAM DATA LATCH Q0-Q15 I/O BUFFER V I/O P/N:PM1289 REV. 1.1, JAN. 06, 2009 5 MX29LA641D H/L Table 1. BLOCK STRUCTURE MX29LA641D SECTOR ARCHITECTURE Sector Size Kbytes Kwords 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 Sector Address A21-A15 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 0010100 0010101 0010110 0010111 0011000 0011001 0011010 0011011 0011100 0011101 0011110 0011111 0100000 0100001 0100010 0100011 0100100 0100101 P/N:PM1289 (x8) Address Range 000000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh (x16) Address Range 000000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh REV. 1.1, JAN. 06, 2009 6 MX29LA641D H/L Sector Size Kbytes Kwords 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 Sector SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 Sector Address A21-A15 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 P/N:PM1289 (x8) Address Range 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh 400000h-40FFFFh 410000h-41FFFFh 420000h-42FFFFh 430000h-43FFFFh 440000h-44FFFFh 450000h-45FFFFh 460000h-46FFFFh 470000h-47FFFFh 480000h-48FFFFh 490000h-49FFFFh 4A0000h-4AFFFFh 4B0000h-4BFFFFh 4C0000h-4CFFFFh 4D0000h-4DFFFFh (x16) Address Range 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh 200000h-207FFFh 208000h-20FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh 230000h-237FFFh 238000h-23FFFFh 240000h-247FFFh 248000h-24FFFFh 250000h-257FFFh 258000h-25FFFFh 260000h-267FFFh 268000h-26FFFFh REV. 1.1, JAN. 06, 2009 7 MX29LA641D H/L Sector Size Kbytes Kwords 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 Sector SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 Sector Address A21-A15 1001110 1001111 1010000 1010001 1010010 1010011 1010100 1010101 1010110 1010111 1011000 1011001 1011010 1011011 1011100 1011101 1011110 1011111 1100000 1100001 1100010 1100011 1100100 1100101 1100110 1100111 1101000 1101001 1101010 1101011 1101100 1101101 1101110 1101111 1110000 1110001 1110010 1110011 1110100 1110101 P/N:PM1289 (x8) Address Range 4E0000h-4EFFFFh 4F0000h-4FFFFFh 500000h-50FFFFh 510000h-51FFFFh 520000h-52FFFFh 530000h-53FFFFh 540000h-54FFFFh 550000h-55FFFFh 560000h-56FFFFh 570000h-57FFFFh 580000h-58FFFFh 590000h-59FFFFh 5A0000h-5AFFFFh 5B0000h-5BFFFFh 5C0000h-5CFFFFh 5D0000h-5DFFFFh 5E0000h-5EFFFFh 5F0000h-5FFFFFh 600000h-60FFFFh 610000h-61FFFFh 620000h-62FFFFh 630000h-63FFFFh 640000h-64FFFFh 650000h-65FFFFh 660000h-66FFFFh 670000h-67FFFFh 680000h-68FFFFh 690000h-69FFFFh 6A0000h-6AFFFFh 6B0000h-6BFFFFh 6C0000h-6CFFFFh 6D0000h-6DFFFFh 6E0000h-6EFFFFh 6F0000h-6FFFFFh 700000h-70FFFFh 710000h-71FFFFh 720000h-72FFFFh 730000h-73FFFFh 740000h-74FFFFh 750000h-75FFFFh (x16) Address Range 270000h-277FFFh 278000h-27FFFFh 280000h-287FFFh 288000h-28FFFFh 290000h-297FFFh 298000h-29FFFFh 2A0000h-2A7FFFh 2A8000h-2AFFFFh 2B0000h-2B7FFFh 2B8000h-2BFFFFh 2C0000h-2C7FFFh 2C8000h-2CFFFFh 2D0000h-2D7FFFh 2D8000h-2DFFFFh 2E0000h-2E7FFFh 2E8000h-2EFFFFh 2F0000h-2F7FFFh 2F8000h-2FFFFFh 300000h-307FFFh 308000h-30FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh 368000h-36FFFFh 370000h-377FFFh 378000h-37FFFFh 380000h-387FFFh 388000h-38FFFFh 390000h-397FFFh 398000h-39FFFFh 3A0000h-3A7FFFh 3A8000h-3AFFFFh REV. 1.1, JAN. 06, 2009 8 MX29LA641D H/L Sector Size Kbytes Kwords 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 Sector SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 Sector Address A21-A15 1110110 1110111 1111000 1111001 1111010 1111011 1111100 1111101 1111110 1111111 P/N:PM1289 (x8) Address Range 760000h-76FFFFh 770000h-77FFFFh 780000h-78FFFFh 790000h-79FFFFh 7A0000h-7AFFFFh 7B0000h-7BFFFFh 7C0000h-7CFFFFh 7D0000h-7DFFFFh 7E0000h-7EFFFFh 7F0000h-7FFFFFh (x16) Address Range 3B0000h-3B7FFFh 3B8000h-3BFFFFh 3C0000h-3C7FFFh 3C8000h-3CFFFFh 3D0000h-3D7FFFh 3D8000h-3DFFFFh 3E0000h-3E7FFFh 3E8000h-3EFFFFh 3F0000h-3F7FFFh 3F8000h-3FFFFFh REV. 1.1, JAN. 06, 2009 9 MX29LA641D H/L BUS OPERATION Table 2-1. BUS OPERATION Mode Select Device Reset Standby Mode RESET# L CEx X Vcc±0.3V disable WE# OE# Address Q8~Q15 Data (I/O) WP#/ Word Byte Q0~Q7 ACC X X X HighZ HighZ HighZ L/H X X X HighZ HighZ HighZ H HighZ HighZ HighZ L/H DOUT L/H Note 3 Note 2 Note 3 Vhv Output Disable H enable H H X Read Mode H enable H L AIN DOUT Q8~Q15 =HighZ Write (Program/Erase) H enable L H AIN Note 3 Q8~Q15 =HighZ Accelerate Program H enable L H AIN Note 3 Q8~Q15 =HighZ Temporary Sector Vhv X X X AIN Vhv enable L H Sector Address, Note 3 HighZ Note 3 Note 2 X X Note 3 H X X Note 3 H Unprotect Sector Protect (Note 2) A6=L, A1=H, A0=L Chip Unprotect Vhv enable L H Sector Address, (Note 2) A6=H, A1=H, A0=L Legend: L=Logic LOW=Vil, H=Logic High=Vih, Vhv=10.0±0.5V, X=Don't Care, AIN=Address IN, DIN=Data IN, DOUT=Data OUT Notes: 1. Through programming equipment, the sector protect and chip unprotect functions can also be implemented. 2. If WP#=L, all sectors are protected. If WP# remove to H, all sectors recover previous protected or unprotected status, determined by "sector protect" or "chip unprotect" function. 3. By following the requests of command sequence, sector protection, or data polling algorithm, Q0~Q15 would be Data Input or Data Output. 4. In Word mode, A21~A0 are address pins. In Byte mode A21~A-1 are address pins. In both modes, A21~A15 are sector address. P/N:PM1289 REV. 1.1, JAN. 06, 2009 10 MX29LA641D H/L Table 2-2. BUS OPERATION Control Input Description A21 A14 to CEx Sector Lock to A8 A9 OE# WE# A15 A10 to A6 A7 A5 A3 to to A4 A2 A1 A0 Q8 Q7 to to Q15 Q0 enable L H SA X Vhv X L X L H L X Note 1 enable L H X X Vhv X L X L H H X Note 2 enable L H X X Vhv X L X L L L 00 C2h L L H 22 7Eh H H L 22 13h 641DH H H H 22 01h 641DL H H H 22 00h Status Verification Read Indicator Bit(Q7) For Security Sector Read Manufacturer ID Read Device ID--1st cycle 2nd cycle 3rd cycle enable L H X X Vhv X L X Legend: L=Logic Low=VIL, H=Logic High=VIH, SA=Sector Address, X=Don't care. Notes: 1. Sector unprotected code: 00h, sector protected code:01h. 2. Factory locked code: For 29LA641DL: 88h. For 29LA641DH: 98h. Factory unlocked code: For 29LA641DL: 08h. For 29LA641DH: 18h. P/N:PM1289 REV. 1.1, JAN. 06, 2009 11 MX29LA641D H/L WRITE COMMANDS/COMMAND SEQUENCES To write a command to the device, system must drive WE# and CEx to Vil, and OE# to Vih. In a command cycle, all address are latched at the later falling edge of CEx and WE#, and all data are latched at the earlier rising edge of CE# and WE#. Figure 1 illustrates the AC timing waveform of a write command, and Table 3 defines all the valid command sets of the device. System is not allowed to write invalid commands not defined in this datasheet. Writing an invalid command will bring the device to an undefined state. REQUIREMENTS FOR READING ARRAY DATA Read array action is to read the data stored in the array. While the memory device is in powered up or has been reset, it will automatically enter the status of read array. If the microprocessor wants to read the data stored in the array, it has to drive CEx (device enable control pin) and OE# (Output control pin) as Vil, and input the address of the data to be read into address pin at the same time. After a period of read cycle (Tce or Taa), the data being read out will be displayed on output pin for microprocessor to access. If CEx or OE# is Vih, the output will be in tri-state, and there will be no data displayed on output pin at all. After the memory device completes embedded operation (automatic Erase or Program), it will automatically return to the status of read array, and the device can read the data in any address in the array. In the process of erasing, if the device receives the Erase suspend command, erase operation will be stopped temporarily after a period of time no more than Tready and the device will return to the status of read array. At this time, the device can read the data stored in any address except the sector being erased in the array. In the status of erase suspend, if user wants to read the data in the sectors being erased, the device will output status data onto the output. Similarly, if program command is issued after erase suspend, after program operation is completed, system can still read array data in any address except the sectors to be erased. The device needs to issue reset command to enable read array operation again in order to arbitrarily read the data in the array in the following two situations: 1. In program or erase operation, the programming or erasing failure causes Q5 to go high. 2. The device is in auto select mode or CFI mode. In the two situations above, if reset command is not issued, the device is not in read array mode and system must issue reset command before reading array data. ACCELERATED PROGRAM OPERATION The accelerated program can improve programming performance compared with word/byte program. By applying Vhv on WP#/ACC pin, the device will enter accelerated program and draw current no more than IACC from WP#/ACC pin. Removing the Vhv from WP#/ACC pin will put the device back to normal operation (not accelerated). P/N:PM1289 REV. 1.1, JAN. 06, 2009 12 MX29LA641D H/L RESET# OPERATION Driving RESET# pin low for a period more than Trp will reset the device back to read mode. If the device is in program or erase operation, the reset operation will take at most a period of Tready for the device to return to read array mode. Before the device returns to read array mode, the RY/BY# pin remains low (busy status). When RESET# pin is held at GND±0.3V, the device consumes standby current(Isb).However, device draws larger current if RESET# pin is held at Vil but not within GND±0.3V. It is recommended that the system to tie its reset signal to RESET# pin of flash memory, so that the flash memory will be reset during system reset and allows system to read the boot-up firware from flash memory. SECTOR PROTECT OPERATION When a sector is protected, program or erase operation will be disabled on these sectors. MX29LA641D H/L provides two methods for sector protection. Once the sector is protected, the sector remains protected until next chip unprotect, or is temporarily unprotected by asserting RESET# pin at Vhv. Refer to temporary sector unprotect operation for further details. The first method is by applying Vhv on RESET# pin. Refer to Figure 14 for timing diagram and Figure 15 for the algorithm for this method. The other method is asserting Vhv on A9 and OE# pins, with A6 and CEx at Vil. The protection operation begins at the falling edge of WE# and terminates at the rising edge. Contact Macronix for details. CHIP UNPROTECT OPERATION MX29LA641D H/L provides two methods for chip unprotect. The chip unprotect operation unprotects all sectors within the device. It is recommended to protect all sectors before activating chip unprotect mode. All sectors groups are unprotected when shipped from the factory. The first method is by applying Vhv on RESET# pin. Refer to Figure 14 for timing diagram and Figure 15 for algorithm of the operation. The other method is asserting Vhv on A9 and OE# pins, with A6 at Vih and CE# at Vil (see Table 2). The unprotect operation begins at the falling edge of WE# and terminates at the rising edge. Contact Macronix for details. TEMPORARY SECTOR UNPROTECT OPERATION System can apply RESET# pin at Vhv to place the device in temporary unprotect mode. In this mode, previously protected sectors can be programmed or erased just as it is unprotected. The devices returns to normal operation once Vhv is removed from RESET# pin and previously protected sectors are again protected. P/N:PM1289 REV. 1.1, JAN. 06, 2009 13 MX29LA641D H/L WRITE PROTECT (WP#) This Write Protect function provides a hardware protection method to protect all sectors without using Vhv. By driving the WP#/ACC pin Low, the device disable program and erase function in all sectors. If the WP#/ACC is held high (Vih to Vcc), these sectors revert to their previous protected/unprotected status. AUTOMATIC SELECT OPERATION When the device is in Read array mode, erase-suspended read array mode or CFI mode, user can issue read silicon ID command to enter read silicon ID mode. After entering read silicon ID mode, user can query several silicon IDs continuously and does not need to issue read silicon ID mode again. In read silicon ID mode, issuing reset command will reset device back to read array mode or erase-suspended read array mode. MX29LA641D H/L provides hardware method to access the silicon ID read operation. Which method requires Vhv on A9 pin, Vil on CEx, OE# and A6 pins. Which apply A1=Vil, A0=Vil, the device will output MXIC's manufacture code of C2h. Which apply A1=Vil, A0=Vih, the device will output device code of 227Eh. Table 2 shows the sequence for reading MX29LA641D H/L device codes. VERIFY SECTOR PROTECT STATUS OPERATION MX29LA641D H/L provides hardware sector protection against Program and Erase operation for protected sectors. The sector protect status can be read through Sector Protect Verify command. This method requires Vhv on A9 pin, Vih on WE# and A1 pins, Vil on CEx, OE#, A6 and A0 pins, and sector address on A15 to A21 pins. If the read out data is 01H, the designated sector is protected. Oppositely, if the read out data is 00H, the designated sector is not protected. SECURITY SECTOR FLASH MEMORY REGION The Security Sector region is an extra OTP memory space of 128 words in length. The security sectors can be locked upon shipping from factory, or it can be locked by customer after shipping. Customer can issue Security Sector Factory Protect Verify and/or Security Sector Protect Verify to query the lock status of the device. In factory-locked device, security sector region is protected when shipped from factory and the security silicon sector indicator bit is set to "1". In customer lockable device, security sector region is unprotected when shipped from factory and the security silicon indicator bit is set to "0". Factory Locked: Security Sector Programmed and Protected at the Factory In a factory locked device, the security silicon region is permanently locked after shipping from factory. The device will have a 16-byte (8-word) ESN in the security region at address : 000000h - 000007h. The secured silicon sector address space in this device is allocated as follows. Secured Silicon Sector Address Range 000000h-000007h Standard Factory Locked ESN 000008h-00007Fh Unavailable Express Flash Factory Locked ESN or Determined by Customer Determined by Customer P/N:PM1289 Customer Lockable Determined by Customer REV. 1.1, JAN. 06, 2009 14 MX29LA641D H/L Customer Lockable: Security Sector NOT Programmed or Protected at the Factory When the security feature is not required, the security region can act as an extra memory space. Security silicon sector can also be protected by two methods. Note that once the security silicon sector is protected, there is no way to unprotect the security silicon sector and the content of it can no longer be altered. The first method is to write a three-cycle command of Enter Security Region, and then follow the sector protect algorithm as illustrated in Figure 15, except that RESET# pin may at either Vih or Vhv. The other method is to write a three-cycle command of Enter Security Region, and then follow the alternate method of sector protect with A9, OE# at Vhv. After the security silicon is locked and verified, system must write Exit Security Sector Region, go through a power cycle, or issue a hardware reset to return the device to read normal array mode. DATA PROTECTION To avoid accidental erasure or programming of the device, the device is automatically reset to read array mode during power up. Besides, only after successful completion of the specified command sets will the device begin its erase or program operation. Other features to protect the data from accidental alternation are described as followed. LOW VCC WRITE INHIBIT The device refuses to accept any write command when Vcc is less than VLKO. This prevents data from spuriously altered. The device automatically resets itself when Vcc is lower than VLKO and write cycles are ignored until Vcc is greater than VLKO. System must provide proper signals on control pins after Vcc is larger than VLKO to avoid unintentional program or erase operation WRITE PULSE "GLITCH" PROTECTION CEx, WE#, OE# pulses shorter than 5ns are treated as glitches and will not be regarded as an effective write cycle. LOGICAL INHIBIT A valid write cycle requires both CEx and WE# at Vil with OE# at Vih. Write cycle is ignored when either CEx at Vih, WE# a Vih, or OE# at Vil. POWER-UP SEQUENCE Upon power up, MX29LA641D H/L is placed in read array mode. Furthermore, program or erase operation will begin only after successful completion of specified command sequences. P/N:PM1289 REV. 1.1, JAN. 06, 2009 15 MX29LA641D H/L POWER-UP WRITE INHIBIT When WE#, CEx is held at Vil and OE# is held at Vih during power up, the device ignores the first command on the rising edge of WE#. POWER SUPPLY DECOUPLING A 0.1uF capacitor should be connected between the Vcc and GND to reduce the noise effect. P/N:PM1289 REV. 1.1, JAN. 06, 2009 16 MX29LA641D H/L SOFTWARE COMMAND DEFINITIONS Table 3 indicates all valid command sequences. Please note that if you give wrong address and data, or write them by wrong command sequence, the device will be reset into read mode. While WE# or CEx goes low, the falling edge of which happens later will latch all address. While WE# or CEx goes high, and the rising edge of which happens first will latch all data. TABLE 3. MX29LA641D H/L COMMAND DEFINITIONS A utom atic S elec t Read Res et M ode M ode W ord B y te W ord B y te W ord B y te W ord B y te A ddr A ddr XXX 555 AAA 555 AAA 555 AAA 555 AAA Data Data F0 AA AA AA AA AA AA AA AA A ddr 2A A 555 2A A 555 2A A 555 2A A 555 Data 55 55 55 55 55 55 55 55 A ddr 555 AAA 555 AAA 555 AAA 555 AAA Data 90 90 90 90 90 90 Com m and Hex 1s t B us Cy c 2nd B us Cy c 3rd B us Cy c 4th B us Cy c 5th B us Cy c 6th B us Cy c M anufac turer ID Dev ic e ID S ec urity S ec tor F ac tory S ec tor P rotec t (* Notes ) P rotec t V erify V erify 90 90 (S ec tor) (S ec tor) A ddr X 00 X 00 X 01 X 02 X 03 X 06 X 02 X 04 Data C2H C2H ID1 ID1 98/18 (H) 98/18 (H) 00/01 00/01 88/08 (L) 88/08 (L) A ddr X0E Data ID2 ID2 A ddr X0F X1E Data ID3 ID3 X1C Enter Security Sector Region Exit Security Command 1st Bus Cyc 2nd Bus Cyc 3rd Bus Cyc 4th Bus Cyc 5th Bus Cyc 6th Bus Cyc Enable Sector Program Chip Erase Sector Erase Hex Word Byte Word Byte Word Byte Word Byte Word Byte Addr 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA Data AA AA AA AA AA AA AA Addr 2AA 555 2AA 555 2AA 555 2AA 555 2AA 555 Data 55 55 55 55 55 Addr 555 AAA 555 555 AAA Data 88 88 55 AA 55 AA 55 55 AAA 555 AAA 555 AAA 80 80 555 AAA Data XXX XXX Addr Addr 555 AAA 00 00 Data Data AA AA AA AA Addr 2AA 555 2AA 555 55 55 Addr 90 55 AA 90 A0 A0 80 80 Data 55 Addr 555 AAA Sector Sector Data 10 P/N:PM1289 55 10 30 CFI Read Erase Erase Suspend Resume Word Byte Byte/Word Byte/Word XXX XXX 55 AA 98 98 B0 30 30 REV. 1.1, JAN. 06, 2009 17 MX29LA641D H/L Notes: ID1 Device ID ID2 ID3 MX29LA641DH Word 227E Byte 7E Word 2213 Byte 13 Word 2201 Byte 01 MX29LA641DL 227E 7E 2213 13 2200 00 Interface P/N:PM1289 REV. 1.1, JAN. 06, 2009 18 MX29LA641D H/L RESET In the following situations, executing reset command will reset device back to read array mode: • Among erase command sequence (before the full command set is completed) • Sector erase time-out period • Erase fail (while Q5 is high) • Among program command sequence (before the full command set is completed, erase-suspended program included) • Program fail (while Q5 is high, and erase-suspended program fail is included) • Read silicon ID mode • Sector protect verify • CFI mode While device is at the status of program fail or erase fail (Q5 is high), user must issue reset command to reset device back to read array mode. While the device is in read silicon ID mode, sector protect verify or CFI mode, user must issue reset command to reset device back to read array mode. When the device is in the progress of programming (not program fail) or erasing (not erase fail), device will ignore reset command. AUTOMATIC SELECT COMMAND SEQUENCE Automatic Select mode is used to access the manufacturer ID, device ID and to verify whether or not secured silicon is locked and whether or not a sector is protected. The automatic select mode has four command cycles. The first two are unlock cycles, and followed by a specific command. The fourth cycle is a normal read cycle, and user can read at any address any number of times without entering another command sequence. The reset command is necessary to exit the Automatic Select mode and back to read array. The following table shows the identification code with corresponding address. Identifier Code Word/Byte Mode Address Data (Hex) Manufacturer ID Word X00 C2 Byte X00 C2 Word X01 227E Byte X02 7E Word X0E 2213 Byte X1C 13 Word X0F 2201/2200 Byte X1E 01/00 29LA641D H/L Word X03 98/18 (H) Factory locked/unlocked Device ID, cycle 1 Device ID, cycle 2 Device ID, cycle 3 Secured Silicon Representation 88/08 (L) Byte X06 98/18 (H) Factory locked/unlocked 88/08 (L) Sector Protect Verify Word (Sector address) X 02 00/01 Unprotected/protected Byte (Sector address) X 04 00/01 Unprotected/protected There is an alternative method to that shown in Table 2, which is intended for EPROM programmers and requires Vhv on address bit A9. P/N:PM1289 REV. 1.1, JAN. 06, 2009 19 MX29LA641D H/L AUTOMATIC PROGRAMMING The MX29LA641D H/L can provide the user program function by the form of Byte-Mode or Word-Mode. As long as the users enter the right cycle defined in the Table.3 (including 2 unlock cycles and A0H), any data user inputs will automatically be programmed into the array. Once the program function is executed, the internal write state controller will automatically execute the algorithms and timings necessary for program and verification, which includes generating suitable program pulse, verifying whether the threshold voltage of the programmed cell is high enough and repeating the program pulse if any of the cells does not pass verification. Meanwhile, the internal control will prohibit the programming to cells that pass verification while the other cells fail in verification in order to avoid over-programming. With the internal write state controller, the device requires the user to write the program command and data only. Programming will only change the bit status from "1" to "0". That is to say, it is impossible to convert the bit status from "0" to "1" by programming. Meanwhile, the internal write verification only detects the errors of the "1" that is not successfully programmed to "0". Any command written to the device during programming will be ignored except hardware reset, which will terminate the program operation after a period of time no more than Tready. When the embedded program algorithm is complete or the program operation is terminated by hardware reset, the device will return to the reading array data mode. The typical chip program time at room temperature of the MX29LA641D H/L is less than 45 seconds. When the embedded program operation is on going, user can confirm if the embedded operation is finished or not by the following methods: Status Q7 Q6 Q5 RY/BY#*2 In progress*1 Q7# Toggling 0 0 Finished Q7 Stop toggling 0 1 Exceed time limit Q7# Toggling 1 0 *1: The status "in progress" means both program mode and erase-suspended program mode. *2: RY/BY# is an open drain output pin and should be weakly connected to VDD through a pull-up resistor. *3: When an attempt is made to program a protected sector, Q7 will output its complement data or Q6 continues to toggle for about 1us or less and the device returns to read array state without programing the data in the protected sector. P/N:PM1289 REV. 1.1, JAN. 06, 2009 20 MX29LA641D H/L CHIP ERASE Chip Erase is to erase all the data with "1" and "0" as all "1". It needs 6 cycles to write the action in, and the first two cycles are "unlock" cycles, the third one is a configuration cycle, the fourth and fifth are also "unlock" cycles, and the sixth cycle is the chip erase operation. During chip erasing, all the commands will not be accepted except hardware reset or the working voltage is too low that chip erase will be interrupted. After Chip Erase, the chip will return to the state of Read Array. When the embedded chip erase operation is on going, user can confirm if the embedded operation is finished or not by the following methods: Status Q7 Q6 Q5 Q2 RY/BY# In progress 0 Toggling 0 Toggling 0 Finished 1 Stop toggling 0 1 1 Exceed time limit 0 Toggling 1 Toggling 0 SECTOR ERASE Sector Erase is to erase all the data in a sector with "1" and "0" as all "1". It requires six command cycles to issue. The first two cycles are "unlock cycles", the third one is a configuration cycle, the fourth and fifth are also "unlock cycles" and the sixth cycle is the sector erase command. After the sector erase command sequence is issued, there is a timeout period of 50us counted internally. During the time-out period, additional sector address and sector erase command can be written multiply. Once user enters another sector erase command, the time-out period of 50us is recounted. If user enters any command other than sector erase or erase suspend during time-out period, the erase command would be aborted and the device is reset to read array condition. The number of sectors could be from one sector to all sectors. After time-out period passing by, additional erase command is not accepted and erase embedded operation begins. During sector erasing, all commands will not be accepted except hardware reset and erase suspend and user can check the status as chip erase. When the embedded erase operation is on going, user can confirm if the embedded operation is finished or not by the following methods: Status Q7 Q6 Q5 Q3 Q2 RY/BY#*2 Time-out period 0 Toggling 0 0 Toggling 0 In progress 0 Toggling 0 1 Toggling 0 Finished 1 Stop toggling 0 1 1 1 Exceed time limit 0 Toggling 1 1 Toggling 0 *1: The status Q3 is the time-out period indicator. When Q3=0, the device is in time-out period and is acceptible to another sector address to be erased. When Q3=1, the device is in erase operation and only erase suspend is valid. *2: RY/BY# is open drain output pin and should be weakly connected to VDD through a pull-up resistor. *3: When an attempt is made to erase a protected sector, Q7 will output its complement data or Q6 continues to toggle for 100us or less and the device returned to read array status without erasing the data in the protected sector. P/N:PM1289 REV. 1.1, JAN. 06, 2009 21 MX29LA641D H/L SECTOR ERASE SUSPEND During sector erasure, sector erase suspend is the only valid command. If user issue erase suspend command in the time-out period of sector erasure, device time-out period will be over immediately and the device will go back to erasesuspended read array mode. If user issue erase suspend command during the sector erase is being operated, device will suspend the ongoing erase operation, and after the Tready1 (<=20us) suspend finishes and the device will enter erase-suspended read array mode. User can judge if the device has finished erase suspend through Q6, Q7, and RY/ BY#. After device has entered erase-suspended read array mode, user can read other sectors not at erase suspend by the speed of Taa; while reading the sector in erase-suspend mode, device will output its status. User can use Q6 and Q2 to judge the sector is erasing or the erase is suspended. Status Q7 Q6 Q5 Q3 Q2 RY/BY# 1 No toggle 0 N/A Toggle 1 Erase suspend read in non-erase suspended sector Data Data Data Data Data 1 Erase suspend program in non-erase suspended sector Q7# Toggle 0 N/A N/A 0 Erase suspend read in erase suspended sector When the device has suspended erasing, user can execute the command sets except sector erase and chip erase, such as read silicon ID, sector protect verify, program, CFI query and erase resume. SECTOR ERASE RESUME Sector erase resume command is valid only when the device is in erase suspend state. After erase resume, user can issue another erase suspend command, but there should be a 4ms interval between erase resume and the next erase suspend. If user issue infinite suspend-resume loop, or suspend-resume exceeds 1024 times, the time for erasing will increase. P/N:PM1289 REV. 1.1, JAN. 06, 2009 22 MX29LA641D H/L QUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODE MX29LA641D H/L features CFI mode. Host system can retrieve the operating characteristics, structure and vendorspecified information such as identifying information, memory size, byte/word configuration, operating voltages and timing information of this device by CFI mode. The device enters the CFI Query mode when the system writes the CFI Query command "98H" to address "55H" any time the device is ready to read array data. The system can read CFI information at the addresses given in Table 4. A reset command is required to exit CFI mode and go back to ready array mode or erase suspend mode. The system can write the CFI Query command only when the device is in read mode, erase suspend, standby mode or automatic select mode. Table 4-1. CFI mode: Identification Data Values (All values in these tables are in hexadecimal) Description Query-unique ASCII string "QRY" Primary vendor command set and control interface ID code Address for primary algorithm extended query table Alternate vendor command set and control interface ID code Address for alternate algorithm extended query table Address (h) (Word Mode) 10 11 12 13 14 15 16 17 18 19 1A Address (h) (Byte Mode) 20 22 24 26 28 2A 2C 2E 30 32 34 Data (h) Address (h) (Word Mode) 1B 1C 1D 1E 1F 20 21 Address (h) (Byte Mode) 36 38 3A 3C 3E 40 42 Data (h) 22 23 24 25 26 44 46 48 4A 4C 0000 0005 0000 0004 0000 0051 0052 0059 0002 0000 0040 0000 0000 0000 0000 0000 Table 4-2. CFI Mode: System Interface Data Values Description Vcc supply minimum program/erase voltage Vcc supply maximum program/erase voltage VPP supply minimum program/erase voltage VPP supply maximum program/erase voltage Typical timeout per single word/byte write, 2n us Typical timeout for maximum-size buffer write, 2n us Typical timeout per individual block erase, 2n ms Typical timeout for full chip erase, 2n ms Maximum timeout for word/byte write, 2n times typical Maximum timeout for buffer write, 2n times typical Maximum timeout per individual block erase, 2n times typical Maximum timeout for chip erase, 2n times typical P/N:PM1289 0027 0036 0000 0000 0004 0000 000A REV. 1.1, JAN. 06, 2009 23 MX29LA641D H/L Table 4-3. CFI Mode: Device Geometry Data Values Description Address (h) (Word Mode) Address (h) (Byte Mode) Data (h) Device size = 2n in number of bytes 27 4E 0017 Flash device interface description (02=asynchronous x8/x16) 28 50 0002 29 52 0000 2A 54 0000 2B 56 0000 Number of erase regions within device 2C 58 0001 Index for Erase Bank Area 1 2D 5A 007F [2E,2D] = # of same-size sectors in region 1-1 2E 5C 0000 [30, 2F] = sector size in multiples of 256-bytes 2F 5E 0000 30 60 0001 31 62 0000 32 64 0000 33 66 0000 34 68 0000 35 6A 0000 36 6C 0000 37 6E 0000 38 70 0000 39 72 0000 3A 74 0000 3B 76 0000 3C 78 0000 n Maximum number of bytes in buffer write = 2 (not support) Index for Erase Bank Area 2 Index for Erase Bank Area 3 Index for Erase Bank Area 4 P/N:PM1289 REV. 1.1, JAN. 06, 2009 24 MX29LA641D H/L Table 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values Description Address (h) (Word Mode) Address (h) (Byte Mode) Data (h) 40 80 0050 41 82 0052 42 84 0049 Major version number, ASCII 43 86 0031 Minor version number, ASCII 44 88 0033 Unlock recognizes address (0= recognize, 1= don't recognize) 45 8A 0000 Erase suspend (2= to both read and program) 46 8C 0002 Sector protect (N= # of sectors/group) 47 8E 0004 Temporary sector unprotect (1=supported) 48 90 0001 Sector protect/Chip unprotect scheme 49 92 0004 Simultaneous R/W operation (0=not supported) 4A 94 0000 Burst mode (0=not supported) 4B 96 0000 Page mode (0=not supported) 4C 98 0000 Minimum acceleration supply (0= not supported), [D7:D4] for volt, 4D 9A 0095 4E 9C 00A5 4F 9E 0004/ Query - Primary extended table, unique ASCII string, PRI [D3:D0] for 100mV Maximum acceleration supply (0= not supported), [D7:D4] for volt, [D3:D0] for 100mV Low/High boot block indicator 04h=Low boot device, 0005 05h=High boot device P/N:PM1289 REV. 1.1, JAN. 06, 2009 25 MX29LA641D H/L ABSOLUTE MAXIMUM STRESS RATINGS Surrounding Temperature with Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65oC to +125oC Storage Temperature . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65oC to +150oC Voltage Range Vcc . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V RESET#, A9, ACC and OE# . .. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +10.5 V The other pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .-0.5 V to Vcc +0.5 V Output Short Circuit Current (less than one second) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 mA Note: 1. Minimum voltage may undershoot to -2V during transition and for less than 20ns during transitions. 2. Maximum voltage may overshoot to Vcc+2V during transition and for less than 20ns during transitions. OPERATING TEMPERATURE AND VOLTAGE Commercial (C) Grade Surrounding Temperature (TA ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° C to +70° C Industrial (I) Grade Surrounding Temperature (TA ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40° C to +85° C VCC Supply Voltages VCC range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.7 V to 3.6 V P/N:PM1289 REV. 1.1, JAN. 06, 2009 26 MX29LA641D H/L DC CHARACTERISTICS Symbol Description Iilk Input Leak Iilk9 A9 Leak Iolk Output Leak Icr1 Read Current(5MHz) Min Typ Max Remark ± 1.0uA 35uA A9=10V ± 1.0uA 9mA 16mA CE#=Vil, OE#=Vih Icr2 Read Current(1MHz) 2mA 4mA CE#=Vil, OE#=Vih Icw Write Current 26mA 30mA CE#=Vil, OE#=Vih, WE#=Vil Isb Standby Current 5uA 15uA Vcc=Vcc max, other pin disable Isbr Reset Current 5uA 15uA Vcc=Vccmax, Reset# enable, other pin disable Isbs Sleep Mode Current 5uA 15uA Icp1 Accelerated Pgm Current, 5mA 10mA WP#/Acc pin(Word/Byte) Icp2 CE#=Vil, OE#=Vih, Accelerated Pgm Current, 15mA 30mA Vcc pin,(Word/Byte) CE#=Vil, OE#=Vih, Vil Input Low Voltage -0.5V 0.8V Vih Input High Voltage 0.7xVcc Vcc+0.3V Vhv Very High Voltage for hardware 9.5V 10.5V Protect/Unprotect/Auto Select/ Temporary Unprotect/ Accelerated Program Vol Output Low Voltage 0.45V Voh1 Ouput High Voltage 0.85xVcc Ioh1=-2mA Voh2 Ouput High Voltage Vcc-0.4V Ioh2=-100uA Vlko Low Vcc Lock-out Voltage 2.3V P/N:PM1289 Iol=4.0mA 2.5V REV. 1.1, JAN. 06, 2009 27 MX29LA641D H/L SWITCHING TEST CIRCUITS Vcc R2 TESTED DEVICE 0.1uF +3.3V CL R1 DIODES=IN3064 OR EQUIVALENT R1=6.2K ohm R2=2.7K ohm Test Condition Output Load : 1 TTL gate Output Load Capacitance,CL : 30pF Rise/Fall Times : 5ns In/Out reference levels :1.5V Input Pulse level : 0.0 ~ 3.0V SWITCHING TEST WAVEFORMS 3.0V 1.5V 1.5V Test Points 0.0V INPUT OUTPUT P/N:PM1289 REV. 1.1, JAN. 06, 2009 28 MX29LA641D H/L AC CHARACTERISTICS Symbol Description Taa Min Typ Max Unit Valid data output after address 90 ns Tce Valid data output after CEx low 90 ns Toe Valid data output after OE# low 30 ns Tdf Data output floating after OE# high 30 ns Toh Output hold time from the earliest rising edge of address, 0 ns CEx, OE# Trc Read period time 90 ns Twc Write period time 90 ns Tcwc Command write period time 90 ns Tas Address setup time 0 ns Tah Address hold time 45 ns Tds Data setup time 45 ns Tdh Data hold time 0 ns Tvcs Vcc setup time 100 us Tcs Chip enable Setup time 0 ns Tch Chip enable hold time 0 ns Toes Output enable setup time 0 ns Read 0 ns Toggle & 10 ns Toeh Toeh Output enable hold time Data# Polling Tws WE# setup time 0 ns Twh WE# hold time 0 ns Tcep CEx pulse width 45 ns Tceph CEx pulse width high 30 ns Twp WE# pulse width 35 ns Twph WE# pulse width high 30 ns Tbusy Program/Erase active time by RY/BY# Tghwl Read recover time before write 0 ns Tghel Read recover time before write 0 ns Twhwh1 Program operation 11 us Twhwh1 Acc Program operation(Word/Byte) 7 us Twhwh2 Sector Erase Operation 0.7 sec Tbal Sector Add hold time 90 50 P/N:PM1289 ns us REV. 1.1, JAN. 06, 2009 29 MX29LA641D H/L Figure 1. COMMAND WRITE OPERATION Tcwc CEx Disable Enable Tch Tcs WE# Vih Vil Toes OE# Twph Twp Vih Vil Addresses Vih VA Vil Tah Tas Tdh Tds Vih Data Vil DIN VA: Valid Address P/N:PM1289 REV. 1.1, JAN. 06, 2009 30 MX29LA641D H/L READ/RESET OPERATION Figure 2. READ TIMING WAVEFORMS Tce Disable CEx Enable Vih WE# Vil Toeh Tdf Toe Vih OE# Vil Toh Taa Trc Vih ADD Valid Addresses Vil Outputs Voh HIGH Z DATA Valid HIGH Z Vol P/N:PM1289 REV. 1.1, JAN. 06, 2009 31 MX29LA641D H/L AC CHARACTERISTICS Item Description Setup Speed Unit Trp1 RESET# Pulse Width (During Automatic Algorithms) MIN 10 us Trp2 RESET# Pulse Width (NOT During Automatic Algorithms) MIN 500 ns Trh RESET# High Time Before Read MIN 50 ns Trb1 RY/BY# Recovery Time (to CE#, OE# go low) MIN 0 ns Trb2 RY/BY# Recovery Time (to WE# go low) MIN 50 ns Tready1 RESET# PIN Low (During Automatic Algorithms) MAX 20 us MAX 500 ns to Read or Write Tready2 RESET# PIN Low (NOT During Automatic Algorithms) to Read or Write Figure 3. RESET# TIMING WAVEFORM Trb1 CEx, OE# Trb2 WE# Tready1 RY/BY# RESET# Trp1 Reset Timing during Automatic Algorithms CEx, OE# Trh RY/BY# RESET# Trp2 Tready2 Reset Timing NOT during Automatic Algorithms P/N:PM1289 REV. 1.1, JAN. 06, 2009 32 MX29LA641D H/L ERASE/PROGRAM OPERATION Figure 4. AUTOMATIC CHIP ERASE TIMING WAVEFORM Disable CEx Enable Tch Twhwh2 Twp WE# Twph Tcs Tghwl OE# Last 2 Erase Command Cycle Twc Address Read Status Tah Tas 2AAh VA SA Tds Tdh 55h VA In Progress Complete 10h Data Tbusy Trb RY/BY# SA: 555h for chip erase P/N:PM1289 REV. 1.1, JAN. 06, 2009 33 MX29LA641D H/L Figure 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 10H Address 555H Data# Polling Algorithm or Toggle Bit Algorithm NO Data=FFh ? YES Auto Chip Erase Completed P/N:PM1289 REV. 1.1, JAN. 06, 2009 34 MX29LA641D H/L Figure 6. AUTOMATIC SECTOR ERASE TIMING WAVEFORM Read Status Disable CEx Enable Tch Twhwh2 Twp WE# Twph Tcs Tghwl OE# Tbal Last 2 Erase Command Cycle Twc Address Tas Sector Address 0 2AAh Tds Tdh 55h Sector Address 1 Sector Address n Tah VA VA In Progress Complete 30h 30h 30h Data Tbusy Trb RY/BY# P/N:PM1289 REV. 1.1, JAN. 06, 2009 35 MX29LA641D H/L Figure 7. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 30H Sector Address Last Sector to Erase NO YES Data# Polling Algorithm or Toggle Bit Algorithm Data=FFh NO YES Auto Sector Erase Completed P/N:PM1289 REV. 1.1, JAN. 06, 2009 36 MX29LA641D H/L Figure 8. ERASE SUSPEND/RESUME FLOWCHART START Write Data B0H NO ERASE SUSPEND Toggle Bit checking Q6 not toggled YES Read Array or Program Reading or Programming End NO YES Write Data 30H ERASE RESUME Continue Erase Another Erase Suspend ? NO YES P/N:PM1289 REV. 1.1, JAN. 06, 2009 37 MX29LA641D H/L Figure 9. SECURED SILICON SECTOR PROTECTED ALGORITHMS FLOWCHART START Enter Secured Silicon Sector Wait 1us First Wait Cycle Data=60h Second Wait Cycle Data=60h A6=0, A1=1, A0=0 Wait 300us No Data = 01h ? Yes Device Failed Write Reset Command Secured Sector Protect Complete P/N:PM1289 REV. 1.1, JAN. 06, 2009 38 MX29LA641D H/L Figure 10. AUTOMATIC PROGRAM TIMING WAVEFORMS Disable CEx Enable Tch Twhwh1 Twp WE# Tcs Twph Tghwl OE# Last 2 Program Command Cycle 555h Address Last 2 Read Status Cycle Tah Tas VA PA Tds VA Tdh A0h Status PD DOUT Data Tbusy Trb RY/BY# Figure 11. Accelerated Program Timing Diagram (9.5V ~ 10.5V) Vhv WP#/ACC Vil or Vih Vil or Vih 250nS 250nS P/N:PM1289 REV. 1.1, JAN. 06, 2009 39 MX29LA641D H/L Figure 12. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data A0H Address 555H Write Program Data/Address Data# Polling Algorithm or Toggle Bit Algorithm next address Read Again Data: Program Data? No YES No Last Word to be Programed YES Auto Program Completed P/N:PM1289 REV. 1.1, JAN. 06, 2009 40 MX29LA641D H/L Figure 13. CEx CONTROLLED WRITE TIMING WAVEFORM WE# Twhwh1 or Twhwh2 Tcep Disable CEx Enable Tceph Tghwl OE# Tah Tas Address 555h VA PA Tds VA Tdh A0h Status PD DOUT Data Tbusy RY/BY# P/N:PM1289 REV. 1.1, JAN. 06, 2009 41 MX29LA641D H/L SECTOR PROTECT/CHIP UNPROTECT Figure 14. SECTOR PROTECT/CHIP UNPROTECT WAVEFORM (RESET# Control) 150uS: Sector Protect 15mS: Chip Unprotect 1us CEx Disable Enable WE# OE# Verification 60h Data SA, A6 A1, A0 60h 40h VA VA Status VA Vhv Vih RESET# VA: valid address P/N:PM1289 REV. 1.1, JAN. 06, 2009 42 MX29LA641D H/L Figure 15-1. IN-SYSTEM SECTOR PROTECT WITH RESET#=Vhv START Retry count=0 RESET#=Vhv Wait 1us Temporary Unprotect Mode No First CMD=60h? Yes Set Up Sector Address Write Sector Address with [A6,A1,A0]:[0,1,0] data: 60h Wait 150us Reset PLSCNT=1 Write Sector Address with [A6,A1,A0]:[0,1,0] data: 40h Retry Count +1 Read at Sector Address with [A6,A1,A0]:[0,1,0] No No Retry Count=25? Data=01h? Yes Yes Device fail Protect another sector? Yes No Temporary Unprotect Mode RESET#=Vih Write RESET CMD Sector Protect Done P/N:PM1289 REV. 1.1, JAN. 06, 2009 43 MX29LA641D H/L Figure 15-2. CHIP UNPROTECT ALGORITHMS WITH RESET#=Vhv START Retry count=0 RESET#=Vhv Wait 1us Temporary Unprotect No First CMD=60h? Yes All sectors protected? No Protect All Sectors Yes Write [A6,A1,A0]:[1,1,0] data: 60h Wait 15ms Write [A6,A1,A0]:[1,1,0] data: 40h Retry Count +1 Read [A6,A1,A0]:[1,1,0] No No Retry Count=1000? Data=00h? Yes Device fail Yes Last sector No verified? Yes Temporary Unprotect RESET#=Vih Write reset CMD Chip Unprotect Done P/N:PM1289 REV. 1.1, JAN. 06, 2009 44 MX29LA641D H/L AC CHARACTERISTICS Parameter Description Test Setup All Speed Options Unit Tvlht Voltage transition time Min. 4 us Twpp1 Write pulse width for sector protect Min. 100 ns Twpp2 Write pulse width for chip unprotect Min. 100 ns Toesp OE# setup time to WE# active Min. 4 us Figure 16. SECTOR PROTECT TIMING WAVEFORM (A9, OE# Control) A1 A6 10V 3V A9 Tvlht Verify 10V 3V OE# Tvlht Tvlht Twpp1 WE# Toesp Disable CEx Enable Data 01H F0H Toe A21-A15 Sector Address P/N:PM1289 REV. 1.1, JAN. 06, 2009 45 MX29LA641D H/L Figure 17. SECTOR PROTECTION ALGORITHM (A9, OE# Control) START Set Up Sector Addr PLSCNT=1 OE#=Vhv, A9=Vhv, CEx=Vil A6=Vil Activate WE# Pulse Time Out 150us Set WE#=Vih, CEx=OE#=Vil A9 should remain Vhv Read from Sector Addr=SA, A1=1 No PLSCNT=32? . No Data=01H? Yes Device Failed Protect Another Sector? Yes Remove Vhv from A9 Write Reset Command Sector Protection Complete P/N:PM1289 REV. 1.1, JAN. 06, 2009 46 MX29LA641D H/L Figure 18. CHIP UNPROTECT TIMING WAVEFORM (A9, OE# Control) A1 10V 3V A9 Tvlht A6 Verify 10V 3V OE# Tvlht Tvlht Twpp2 WE# Disable Toesp CEx Enable Data 00H F0H Toe P/N:PM1289 REV. 1.1, JAN. 06, 2009 47 MX29LA641D H/L Figure 19. CHIP UNPROTECT FLOWCHART (A9, OE# Control) START Protect All Sectors PLSCNT=1 Set OE#=A9=Vhv CEx=Vil, A6=1 Activate WE# Pulse Time Out 15ms Increment PLSCNT Set OE#=CEx=Vil A9=Vhv, A1=1 Set Up First Sector Addr Read Data from Device No Data=00H? Increment Sector Addr Yes No All sectors have been verified? No PLSCNT=1000? Yes Device Failed Yes Remove Vhv from A9 Write Reset Command Chip Unprotect Complete * It is recommended before unprotect whole chip, all sectors should be protected in advance. P/N:PM1289 REV. 1.1, JAN. 06, 2009 48 MX29LA641D H/L AC CHARACTERISTICS Parameter Alt Description Condition Speed Unit Trpvhh Tvidr RESET# Rise Time to Vhv and Vhv Fall Time to RESET# MIN 500 ns Tvhhwl Trsp RESET# Vhv to WE# Low MIN 4 us Figure 20. TEMPORARY SECTOR UNPROTECT WAVEFORMS Program or Erase Command Sequence Disable CEx Enable WE# Tvhhwl RY/BY# Vhv 10V RESET# 0 or Vih Vil or Vih Trpvhh Trpvhh P/N:PM1289 REV. 1.1, JAN. 06, 2009 49 MX29LA641D H/L Figure 21. TEMPORARY SECTOR UNPROTECT FLOWCHART Start Apply Reset# pin Vhv Volt Enter Program or Erase Mode Mode Operation Completed (1) Remove Vhv Volt from Reset# (2) RESET# = Vih Completed Temporary Sector Unprotected Mode Notes: 1. Temporary unprotect all protected sectors Vhv=9.5~10.5V. 2. After leaving temporary unprotect mode, the previously protected sectors are again protected. P/N:PM1289 REV. 1.1, JAN. 06, 2009 50 MX29LA641D H/L Figure 22. SILICON ID READ TIMING WAVEFORM VCC 3V Vhv Vih Vil ADD A9 ADD A0 Vih Vil Taa A1 Taa Taa Taa Vih Vil A2 Vih Vil Vih ADD Vil Disable CEx Enable WE# Tce Vih Vil Vih Toe OE# Tdf Vil Toh Toh Toh Toh Vih DATA Q0-Q15 DATA OUT DATA OUT DATA OUT DATA OUT Manufacturer ID Device ID Cycle 1 Device ID Cycle 2 Device ID Cycle 3 Vil P/N:PM1289 REV. 1.1, JAN. 06, 2009 51 MX29LA641D H/L WRITE OPERATION STATUS Figure 23. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) Tce CEx Disable Enable Tch WE# Toe OE# Toeh Tdf Trc Address VA VA Taa Toh Q7 Status Data Complement True Valid Data Q0-Q6 Status Data Status Data True Valid Data High Z High Z Tbusy RY/BY# P/N:PM1289 REV. 1.1, JAN. 06, 2009 52 MX29LA641D H/L Figure 24. DATA# POLLING ALGORITHM Start Read Q7~Q0 at valid address (Note 1) No Q7 = Data# ? Yes No Q5 = 1 ? Yes Read Q7~Q0 at valid address Q7 = Data# ? (Note 2) No Yes FAIL Pass Notes: 1. For programming, valid address means program address. For erasing, valid address means erase sectors address. 2. Q7 should be rechecked even Q5="1" because Q7 may change simultaneously with Q5. P/N:PM1289 REV. 1.1, JAN. 06, 2009 53 MX29LA641D H/L Figure 25. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) Tce CEx Disable Enable Tch WE# Toe OE# Toeh Tdf Trc Address VA VA VA VA Taa Toh Q6/Q2 Valid Status Valid Data (second read) (stops toggling) Valid Status (first read) Valid Data Tbusy RY/BY# VA : Valid Address P/N:PM1289 REV. 1.1, JAN. 06, 2009 54 MX29LA641D H/L Figure 26. TOGGLE BIT ALGORITHM Start Read Q7-Q0 Twice (Note 1) NO Q6 Toggle ? YES NO Q5 = 1? YES Read Q7~Q0 Twice NO Q6 Toggle ? YES PGM/ERS fail Write Reset CMD PGM/ERS Complete Note: 1. Read toggle bit twice to determine whether or not it is toggling. 2. Recheck toggle bit because it may stop toggling as Q5 changes to "1". P/N:PM1289 REV. 1.1, JAN. 06, 2009 55 MX29LA641D H/L Figure 27. Q6 versus Q2 Enter Embedded Erasing Erase Suspend Erase WE# Enter Erase Suspend Program Erase Suspend Read Erase Resume Erase Suspend Program Erase Suspend Read Erase Erase Complete Q2 Q6 NOTES: The system can use OE# or CEx to toggle Q2/Q6, Q2 toggles only when read at an address within an erase-suspended P/N:PM1289 REV. 1.1, JAN. 06, 2009 56 MX29LA641D H/L RECOMMENDED OPERATING CONDITIONS At Device Power-Up AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly. Vcc(min) Vcc GND Tvr Tvcs Tf CEx Tce Tr Disable Enable Vih WE# Vil Tf Toe Tr Vih OE# Vil Tr or Tf Vih ADDRESS Tr or Tf Valid Address Vil Voh DATA Taa High Z Valid Ouput Vol Vih WP#/ACC Vil Figure A. AC Timing at Device Power-Up Symbol Parameter Min. Max. Unit Tvr Vcc Rise Time 80 500000 us/V Tr Input Signal Rise Time 20 us/V Tf Input Signal Fall Time 20 us/V Tvcs Vcc Setup Time 200 P/N:PM1289 us REV. 1.1, JAN. 06, 2009 57 MX29LA641D H/L ERASE AND PROGRAMMING PERFORMANCE LIMITS PARAMETER MIN. TYP.(2) MAX. UNITS Sector Erase Time 0.7 2 sec Chip Erase Time 45 65 sec Word Programming Time 11 360 us Byte Programming Time 9 300 us Accelerated Byte/Word Program Time 7 210 us Chip Programming Time Byte mode 50 160 sec Word mode 45 140 sec Erase/Program Cycles 100,000 Cycles Notes: 1. Typical program and erase times assume the following conditions: 25° C, 3.0V VCC. Programming specifications assume checkboard data pattern. 2. Maximum values are measured at VCC = 3.0 V, worst case temperature. Maximum values are valid up to and including 100,000 program/erase cycles. 3. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 4. Erase/Program cycles comply with JEDEC JESD-47E & A117A standard. LATCH-UP CHARACTERISTICS MIN. MAX. Input Voltage voltage difference with GND on WP#/ACC, A9, OE#, RESET# pins -1.0V 10.5V Input Voltage voltage difference with GND on all I/O pins -1.0V 1.5 x Vcc -100mA +100mA Vcc current pulse Includes all pins except Vcc. Test conditions: Vcc = 3.0V, one pin at a time. PIN CAPACITANCE Parameter Symbol Parameter Description Test Set TYP MAX UNIT CIN Input Capacitance VIN=0 6 7.5 pF COUT Output Capacitance VOUT=0 8.5 12 pF CIN2 Control Pin Capacitance VIN=0 7.5 9 pF Notes: 1. Test conditions TA=25° C, f=1.0MHz. P/N:PM1289 REV. 1.1, JAN. 06, 2009 58 MX29LA641D H/L ORDERING INFORMATION Please contact Macronix sales for specific information regarding 64-ball BGA (10x13mm) ordering information. P/N:PM1289 REV. 1.1, JAN. 06, 2009 59 MX29LA641D H/L PART NAME DESCRIPTION Please contact Macronix sales for specific information regarding 64-ball BGA (10x13mm) part name description. P/N:PM1289 REV. 1.1, JAN. 06, 2009 60 MX29LA641D H/L PACKAGE INFORMATION P/N:PM1289 REV. 1.1, JAN. 06, 2009 61 MX29LA641D H/L REVISION HISTORY Revision No. Description 1.0 1. Format changed 2. Corrected WP# function description 3. Revised Sector Erase Time 4. Changed Vhv spec as 9.5V~10.5V 5. Removed "Advanced Information" 6. Revised GENERAL DESCRIPTION 7. Revised AUTOMATIC SELECT OPERATION 8. Revised SOFTWARE COMMAND DEFINITIONS 1.1 1. Modified table 2-2. 2nd cycle from 1Dh to 13h P/N:PM1289 Page Date All AUG/29/2008 P10,11,14 P29,58 P39 P1 P2 P16 P17 P11 JAN/06/2008 REV. 1.1, JAN. 06, 2009 62 MX29LA641D H/L Macronix's products are not designed, manufactured, or intended for use for any high risk applications in which the failure of a single component could cause death, personal injury, severe physical damage, or other substantial harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft and military application. Macronix and its suppliers will not be liable to you and/or any third party for any claims, injuries or damages that may be incurred due to use of Macronix's products in the prohibited applications. MACRONIX INTERNATIONAL CO., LTD. Macronix Offices : Taiwan Macronix Offices : Japan Headquarters, FAB2 Macronix, International Co., Ltd. Macronix Asia Limited. NKF Bldg. 5F, 1-2 Higashida-cho, Kawasaki-ku Kawasaki-shi, Kanagawa Pref. 210-0005, Japan Tel: +81-44-246-9100 Fax: +81-44-246-9105 16, Li-Hsin Road, Science Park, Hsinchu, Taiwan, R.O.C. Tel: +886-3-5786688 Fax: +886-3-5632888 Macronix Offices : Korea Taipei Office Macronix, International Co., Ltd. Macronix Asia Limited. 19F, 4, Min-Chuan E. Road, Sec. 3, Taipei, Taiwan, R.O.C. Tel: +886-2-2509-3300 Fax: +886-2-2509-2200 #906, 9F, Kangnam Bldg., 1321-4, Seocho-Dong, Seocho-Ku, 135-070, Seoul, Korea Tel: +82-02-588-6887 Fax: +82-02-588-6828 Macronix Offices : China Macronix Offices : Singapore Macronix (Hong Kong) Co., Limited. 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Tel: +1-408-262-8887 Fax: +1-408-262-8810 http : //www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 63