SN74LVC2G02-EP DUAL 2-INPUT POSITIVE-NOR GATE www.ti.com SGDS034A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 FEATURES 1 • • • • • • • • • (1) Controlled Baseline – One Assembly Site – One Test Site – One Fabrication Site Extended Temperature Performance of –55°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product Change Notification Qualification Pedigree (1) Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 5.9 ns at 3.3 V Low Power Consumption, 10 μA Max ICC • • ±24 mA Output Drive at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 1000-V Charged-Device Model (C101) • • • • Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. DCU PACKAGE (TOP VIEW) 1A 1B 2Y GND 1 8 VCC 2 7 3 6 4 5 1Y 2B 2A See mechanical drawings for dimensions. DESCRIPTION/ORDERING INFORMATION This dual 2-input positive-NOR gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC2G02 performs the Boolean function Y = A + B or Y = A • B in positive logic. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION (1) PACKAGE (2) TA –55°C to 125°C (1) (2) VSSOP – DCU ORDERABLE PART NUMBER Reel of 3000 SN74LVC2G02MDCUREP TOP-SIDE MARKING SBMM For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated SN74LVC2G02-EP DUAL 2-INPUT POSITIVE-NOR GATE www.ti.com SGDS034A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 FUNCTION TABLE (EACH GATE) INPUTS B OUTPUT Y H X L X H L L L H A LOGIC DIAGRAM (POSITIVE LOGIC) 1 7 1A 1B 2 1Y 5 3 2A 2B 2Y 6 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V –0.5 6.5 V –0.5 VCC + 0.5 (2) UNIT VO Voltage range applied to any output in the high-impedance or power-off state VO Voltage range applied to any output in the high or low state (2) (3) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through VCC or GND θJA Package thermal impedance (4) Tstg Storage temperature range (1) (2) (3) (4) 2 V 227 –65 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): SN74LVC2G02-EP SN74LVC2G02-EP DUAL 2-INPUT POSITIVE-NOR GATE www.ti.com SGDS034A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 RECOMMENDED OPERATING CONDITIONS (1) VCC Supply voltage Operating Data retention only High-level input voltage MAX 1.65 5.5 1.5 VCC = 2.3 V to 2.7 V 1.7 VCC = 3 V to 3.6 V 0.7 × VCC 0.35 × VCC VCC = 1.65 V to 1.95 V Low-level input voltage V V 2 VCC = 4.5 V to 5.5 V VIL UNIT 0.65 × VCC VCC = 1.65 V to 1.95 V VIH MIN VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 V 0.3 × VCC VCC = 4.5 V to 5.5 V VI Input voltage 0 5.5 V VO Output voltage 0 VCC V VCC = 1.65 V IOH High-level output current –4 VCC = 2.3 V –8 –16 VCC = 3 V –24 VCC = 1.65 V IOL Low-level output current 4 VCC = 2.3 V 8 16 VCC = 3 V Δt/Δv Input transition rise or fall rate VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20 VCC = 3.3 V ± 0.3 V 10 (1) Operating free-air temperature mA 24 VCC = 5 V ± 0.5 V TA mA ns/V 5 –55 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): SN74LVC2G02-EP 3 SN74LVC2G02-EP DUAL 2-INPUT POSITIVE-NOR GATE www.ti.com SGDS034A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 μA VOH 1.65 V to 5.5 V 1.65 V 1.2 IOH = –8 mA 2.3 V 1.9 IOL = 100 μA A or B inputs 0.1 1.65 V 0.45 IOL = 8 mA 2.3 V 0.3 VI = 5.5 V or GND VI or VO = 5.5 V ICC VI = 5.5 V or GND, IO = 0 ΔICC One input at VCC – 0.6 V, Other inputs at VCC or GND Ci VI = VCC or GND V 0.4 3V Ioff (1) 2.3 1.65 V to 5.5 V IOL = 24 mA II V IOL = 4 mA IOL = 16 mA UNIT 2.4 3V IOH = –24 mA MAX VCC – 0.1 IOH = –4 mA IOH = –16 mA VOL MIN TYP (1) VCC 0.55 0 to 5.5 V ±5 μA 0 ±10 μA 1.65 V to 5.5 V 10 μA 3 V to 5.5 V 500 μA 3.3 V 5 pF All typical values are at VCC = 3.3 V, TA = 25°C. SWITCHING CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A or B Y VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V UNIT MIN MAX MIN MAX 1 5.9 1 5.4 ns OPERATING CHARACTERISTICS TA = 25°C PARAMETER Cpd 4 Power dissipation capacitance TEST CONDITIONS f = 10 MHz Submit Documentation Feedback VCC = 3.3 V VCC = 5 V TYP TYP 19 22 UNIT pF Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): SN74LVC2G02-EP SN74LVC2G02-EP DUAL 2-INPUT POSITIVE-NOR GATE www.ti.com SGDS034A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf 3V VCC £2.5 ns £2.5 ns VM VLOAD CL RL VD 1.5 V VCC/2 6V 2 × VCC 50 pF 50 pF 500 W 500 W 0.3 V 0.3 V VI Timing Input VM 0V tW tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH VM VOL tPHL 0V VLOAD/2 VM tPZH VM VM VM tPLZ Output Waveform 1 S1 at VLOAD (see Note B) tPLH VOH Output VM tPZL tPHL VM Output VI Output Control VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + VD VOL tPHZ VM VOH – VD VOH »0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): SN74LVC2G02-EP 5 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LVC2G02MDCUREP ACTIVE US8 DCU 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/07637-01XE ACTIVE US8 DCU 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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