MOSA MS6821GU

MOSA
MS6821
4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control
4 Stereo Inputs, 2W BTL Stereo Output
16-bit Stereo DAC and Volume Control
FEATURES
‧Operation range: 2.4V ~ 6.5V
‧Volume control range
Gain: 0 to 21dB, 3dB/step
Attenuation: 0 to –77.5dB, 1.25dB/step
‧4 stereo inputs (mixed with an audio DAC)
‧Output mode : Speaker( BTL)/Headphone(SE)
‧BTL Output power, THD+N=1%, Stereo Input
RL=4Ω, 2W at 5V, 0.8W at 3.3V, 360mW at 2.4V
RL=8Ω, 1.3W at 5V, 0.53W at 3.3V, 250mW at 2.4V
‧BTL Output power, DAC Input
RL=4Ω, 1.6W at 5V, 0.70W at 3.3V, 340mW at 2.4V
RL=8Ω, 0.83W at 5V, 0.35W at 3.3V, 170mW at 2.4V
‧Built-in 16-bit Audio DAC
‧Audio format : I2S, Right justified, Left justified
‧Control interface : I2C
‧Excellent Power Supply Rejection Ratio(PSRR)
‧Flexibility power management
‧Component less
‧Reduce pop noise circuit
‧ Housed in SOP28, TSSOP28 package, enhanced
thermal PAD
APPLICATIONS
Multimedia system, Portable Digital Audio.
DESCRIPTION
The MS6821 is a 16-bits voltage-output Digital-to-Analog Converter (DAC) integrated class AB stereo headphone
driver and stereo speaker power amplifier. It can drive 2W of continuous average power into a dual 4Ω bridged-tied
(BTL) speaker or 2 * 90mW into stereo 32Ω single ended (SE) headphone. The 16-bit DAC supports general and
popular formats as I2S, Right justified. The volume control offers wide range of gain and attenuation for 4-set stereo
input. All of the functions are set by I2C interface.
The MS6821 has good feature for portable equipment, including wide voltage operation 2.4V ~ 6.5V, low power
consumption, flexible power management, component less and small package TSSOP28, make the MS6821 ideally
suitable for use in the portable digital audio equipments.
BLOCK DIAGRAM
REV 3
1/29
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MOSA
MS6821
4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control
PIN CONFIGURATION
Symbol
Pin
Description
WS
1
Audio word select input
BCK
2
Audio bit clock input
CAP
3
Capacitor connected
RIN1
4
Right channel input 1
RIN2
5
Right channel input 2
RIN3
6
Right channel input 3
RIN4
7
Right channel input 4
VSS
8
PVDDR
9
OUTR-
10
OUTR+
11
Negative supply voltage
Positive supply voltage for right
channel of power amplifier
SE right channel output or negative
output of BTL right channel
Positive output of BTL right channel
GND
12
PVSSR
13
DACR
14
DACL
15
PVSSL
16
GND
17
OUTL+
18
OUTL-
19
PVDDL
20
VDD
21
Positive output of BTL left channel
SE left channel output or negative
output of BTL left channel
Positive supply voltage for left channel
of power amplifier
Positive supply voltage
LIN4
22
Left channel input 4
LIN3
23
Left channel input 3
LIN2
24
Left channel input 2
LIN1
25
Left channel input 1
SDA
26
I2C data input
SCL
27
I2C clock input
DATA
28
Audio data input
WS 1
Connected to ground
Negative supply voltage for right
channel of power amplifier
DAC right channel output
BCK 2
27 SCL
CAP 3
26 SDA
RIN1 4
25 LIN1
RIN2 5
24 LIN2
RIN3 6
23 LIN3
RIN4 7
22 LIN4
VSS 8
DAC Left channel output
Negative supply voltage for left channel
of power amplifier
Connected to ground
28 DATA
21 VDD
PVDDR 9
20 PVDDL
OUTR- 10
19 OUTL-
OUTR+ 11
18 OUTL+
GND 12
17 GND
PVSSR 13
16 PVSSL
DACR 14
15 DACL
Note: 1. SE: Single Ended. BTL: Bridged-Tied Load
REV 3
2/29
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MOSA
MS6821
4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control
ORDERING INFORMATION
Package
Part number
Packaging Marking
Transport Media
28Pin SOP (lead free)
MS6821GTR
MS6821G
1k Units Tape and Reel
28Pin SOP (lead free)
MS6821GU
MS6821G
25 Units Tube
28Pin TSSOP (lead free)
MS6821TGTR
MS6821G
2.5k Units Tape and Reel
28Pin TSSOP (lead free)
RoHS Compliance
MS6821TGU
MS6821G
50 Units Tube
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Rating
Unit
6.5
V
2000
VDD
Supply voltage
VESD
Electrostatic handling
TSTG
Storage temperature range
-65 to 150
V
℃
TA
Operating ambient temperature range
-40 to 85
℃
TJ
Maximum junction temperature
150
℃
TS
Soldering temperature, 10 seconds
Thermal resistance from junction to ambient in free air
SOP28
TSSOP28 (enhance thermal pad)
260
℃
210
51
℃/W
RTHJA
OPERATING RATINGS
Symbol
VDD
REV 3
Parameter
Supply voltage
3/29
Min
Typ
Max
Unit
2.4
5
6.5
V
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MOSA
MS6821
4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control
5V ELECTRICAL CHARACTERISTICS
(Ta=25℃, VDD=5V, VSS=0V, f=1kHz; unless otherwise specified)
Symbol
Parameter
Conditions
Min
All devices are active, BTL
0.5VDD
-0.05
0.5VDD
-0.05
-
Typ
Max
Unit
DC Characteristics
VCAP
Voltage at CAP
VDC
Output DC level
IQ
Quiescent current
13.0
0.5VDD
+0.05
0.5VDD
+0.05
-
0.5VDD
0.5VDD
All devices are active, SE
-
9.8
-
DAC PD, BTL
-
9.9
-
DAC PD, SE
L-ch (R-ch) PD, BTL
DAC active
L-ch (R-ch) PD, SE
DAC active
Only DAC is active
-
6.7
-
-
8.2
-
-
6.6
-
-
3.2
-
-
-
0.3
All devices power down
All devices power down,
except CAP=1/2 VDD
V
V
mA
IPD
Power down current
ATT
Mute attenuation
GARAN
Gain/Attenuation range
0
dB
GSTEP
Gain step
-
3
-
dB
ASTEP
Attenuation step
-
1.25
-
dB
EGA
Gain/Attenuation step error
-
0.3
-
dB
VI2CH
Serial interface high input level
2
VI2CL
Serial interface low input level
Gain
0
Attenuation
uA
12
-
-77.5
-90
dB
21
dB
V
0.8
V
AC Characteristics (Stereo input)
PSRR
CS
THD+N
S/N
Po
Power supply rejection ratio
Channel separation
Total harmonic distortion plus
Noise
Signal-to-noise ratio
Maximum output power
BTL Mode , RL=8Ω
CAP=1uF, f=200Hz
SE Mode , RL=32Ω
CAP=1uF, f=200Hz
BTL Mode, RL=8Ω
Po=1W
SE Mode, RL=32Ω
Po=60mW
SE mode, RL=32Ω, 60mW
SE mode, A-weighting,
75mW
BTL Mode, RL = 4Ω
THD+N = 1%
BTL Mode, RL = 8Ω
THD+N = 1%
SE Mode, RL = 32Ω
THD+N = 0.1%
-
61
-
dB
-
65
-
dB
-
78
-
dB
-
81
-
dB
-
-65
-
dB
-
0.0562
-
%
-
93
-
dB
-
2
-
W
-
1.3
-
W
-
93m
-
W
PD: Power Down
REV 3
4/29
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MOSA
Symbol
MS6821
4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control
Parameter
Audio DAC Characteristics
Min
Typ
Max
Unit
-
-
16
bits
VFS-1.5%
VFS
VFS+1.5%
V
CAP=1uF (200Hz)
66
-
CAP=10uF (200Hz)
67
-
(sampling rate=4fs, fs= 44.1kHz, f=1kHz)
Res
Resolution
VFSDAC
Full scale output voltage of DAC
PSRR
Power supply rejection ratio
CS
Channel separation
THD+N
Total harmonic distortion plus
noise
S/N
Signal-to-noise ratio
DACPo
Conditions
Maximum output power
using DAC
VFS=0.72 * VDD
88
dB
dB
-
-67
-62
dB
-
0.0447
0.079
%
86
90
-
dB
1.44
1.6
-
W
0.75
0.83
-
W
41.4m
46m
-
W
Conditions
Min
Typ
Max
Unit
All devices are active, BTL
-
11.5
-
All devices are active, SE
-
8.5
-
DAC PD, BTL
-
9
-
DAC PD, SE
L-ch (R-ch) PD, BTL
DAC active
L-ch (R-ch) PD, SE
DAC active
Only DAC is active
-
6
-
-
7.1
-
-
5.6
-
-
2.6
-
-
-67
60
dB
-
0.0447
0.1
%
-
0.8
-
W
-
0.53
-
W
-
35m
-
W
-
-66
60
dB
-
0.05
0.1
%
0.63
0.70
-
W
0.32
0.35
-
W
18m
20m
-
W
DAC output, RL=1kΩ, VFS
DAC output, RL=1kΩ, VFS
A-weighting
BTL Mode, RL = 4Ω
THD+N = 0.33%
BTL Mode, RL = 8Ω
THD+N = 0.15 %
SE Mode, RL = 32Ω
THD+N = 0.042%
3.3V ELECTRICAL CHARACTERISTICS
(Ta=25℃, VDD=3.3V, VSS=0V, f=1kHz; unless otherwise specified)
Symbol
Parameter
DC Characteristics
IQ
Quiescent current
mA
AC Characteristics (Stereo input)
THD+N
Total harmonic distortion plus
Noise
SE mode, RL=32Ω, 35mW
BTL Mode, RL = 4Ω
THD+N = 1%
BTL Mode, RL = 8Ω
Po
Maximum output power
THD+N = 1%
SE Mode, RL = 32Ω
THD+N = 0.1%
Audio DAC Characteristics (sampling rate=4fs, fs= 44.1kHz, f=1kHz)
THD+N
DACPo
REV 3
Total harmonic distortion plus
noise
DAC output, RL=1kΩ, VFS
Maximum output power
using DAC
BTL Mode, RL = 4Ω
THD+N = 0.25%
BTL Mode, RL = 8Ω
THD+N = 0.14 %
SE Mode, RL = 32Ω
THD+N = 0.052%
5/29
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MOSA
MS6821
4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control
2.4V ELECTRICAL CHARACTERISTICS
(Ta=25℃, VDD=2.4V, VSS=0V, f=1kHz; unless otherwise specified)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
All devices are active, BTL
-
9.9
-
All devices are active, SE
-
7.1
-
DAC PD, BTL
-
7.8
-
DAC PD, SE
L-ch (R-ch) PD, BTL
DAC active
L-ch (R-ch) PD, SE
DAC active
Only DAC is active
-
5.1
-
-
6
-
-
4.7
-
-
2.2
-
-
-65
-60
dB
-
0.0562
0.1
%
-
0.36
-
W
-
0.25
-
W
-
15m
-
W
-
-63
-58
dB
-
0.071
0.126
%
0.31
0.34
-
W
0.15
0.17
-
W
9m
10m
-
W
DC Characteristics
IQ
Quiescent current
mA
AC Characteristics (Stereo input)
THD+N
Total harmonic distortion plus
Noise
SE mode, RL=32Ω, 15mW
BTL Mode, RL = 4Ω
THD+N = 1%
BTL Mode, RL = 8Ω
Po
Maximum output power
THD+N = 1%
SE Mode, RL = 32Ω
THD+N = 0.1%
Audio DAC Characteristics (sampling rate=4fs, fs= 44.1kHz, f=1kHz)
THD+N
DACPo
REV 3
Total harmonic distortion plus
noise
DAC output, RL=1kΩ, VFS
Maximum output power
using DAC
BTL Mode, RL = 4Ω
THD+N = 0.85%
BTL Mode, RL = 8Ω
THD+N = 0.17 %
SE Mode, RL = 32Ω
THD+N = 0.07%
6/29
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MOSA
MS6821
4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control
TYPICAL PERFORMANCE CHARACTERISTICS
(Ta=25℃; unless otherwise specified)
All Devices activate.
BTL
SE
All Devices activate except DAC
QUIESCENT CURRENT (mA)
SE
QUIESCENT CURRENT (mA)
QUIESCENT CURRENT (mA)
BTL
BTL
SE
LPD or RPD
DAC activates.
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Quiescent current vs. supply voltage
Quiescent current vs. supply voltage
QUIESCENT CURRENT (mA)
SUPPLY VOLTAGE (V)
Quiescent current vs. supply voltage
DAC activates only
SUPPLY VOLTAGE (V)
Quiescent current vs. supply voltage
REV 3
7/29
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MOSA
MS6821
4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control
VDD=5V, Po=2W
BTL mode, RL=4Ω
VDD=3.3V, Po=0.8W
BTL mode, RL=4Ω
VDD=2.4V, Po=330mW
BTL mode, RL=4Ω
FREQUENCY (Hz)
THD+N vs. frequency
THD+N (%)
THD+N (%)
FREQUENCY (Hz)
THD+N vs. frequency
THD+N (%)
FREQUENCY (Hz)
THD+N vs. frequency
VDD=5V, Po=1.2W
BTL mode, RL=8Ω
VDD=3.3V, Po=0.53W
BTL mode, RL=8Ω
VDD=2.4V, Po=250mW
BTL mode, RL=8Ω
FREQUENCY (Hz)
THD+N vs. frequency
THD+N (%)
THD+N (%)
FREQUENCY (Hz)
THD+N vs. frequency
THD+N (%)
FREQUENCY (Hz)
THD+N vs. frequency
VDD=5V, Po=90mW
SE mode, RL=32Ω
REV 3
THD+N (%)
THD+N (%)
THD+N (%)
Stereo inputs signal
(Ta=25℃, stereo inputs signal, f=1kHz, DAC is Power Down mode; unless otherwise specified)
VDD=3.3V, Po=35mW
SE mode, RL=32Ω
VDD=2.4, Po=15mW
SE mode, RL=32Ω
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
THD+N vs. frequency
THD+N vs. frequency
THD+N vs. frequency
8/29
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MOSA
MS6821
4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control
f=20kHz
f=20kHz
f=1kHz
f=1kHz
THD+N (%)
THD+N (%)
THD+N (%)
f=20kHz
f=1kHz
f=20Hz
f=20Hz
f=20Hz
VDD=3.3V
BTL mode
RL=4Ω
VDD=5V
BTL mode
RL=4Ω
VDD=2.4V
BTL mode
RL=4Ω
OUTPUT POWER (W)
OUTPUT POWER (W)
OUTPUT POWER (W)
THD+N vs. output power
THD+N vs. output power
THD+N vs. output power
f=20kHz
f=20kHz
f=1kHz
f=1kHz
f=1kHz
f=20Hz
THD+N (%)
THD+N (%)
THD+N (%)
f=20kHz
f=20Hz
f=20Hz
VDD=5V
BTL mode
RL=8Ω
VDD=3.3V
BTL mode
RL=8Ω
VDD=2.4V
BTL mode
RL=8Ω
OUTPUT POWER (W)
OUTPUT POWER (W)
OUTPUT POWER (W)
THD+N vs. output power
THD+N vs. output power
THD+N vs. output power
f=20kHz
f=20kHz
f=1kHz
VDD=5V
SE mode
RL=32Ω
REV 3
f=20Hz
f=1kHz
VDD=3.3V
SE mode
RL=32Ω
THD+N (%)
f=20Hz
THD+N (%)
THD+N (%)
f=20kHz
f=20Hz
f=1kHz
VDD=2.4V
SE mode
RL=32Ω
OUTPUT POWER (W)
OUTPUT POWER (W)
OUTPUT POWER (W)
THD+N vs. output power
THD+N vs. output power
THD+N vs. output power
9/29
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VDD=5V, Po=1W
BTL, RL=8Ω
MS6821
4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control
CHANNEL SEPARATION (dB)
CHANNEL SEPARATION (dB)
MOSA
VDD=5V, Po=60mW
SE, RL=32Ω
FREQUENCY (Hz)
FREQUENCY (Hz)
Channel separation vs. frequency
Channel separation vs. frequency
CAP=10uF
CAP=10uF
CAP=1uF
PSRR (dB)
PSRR (dB)
CAP=1uF
VDD=5V,
VRR=200mVrms,
BTL RL=8Ω
REV 3
VDD=5V,
VRR=200mVrms,
SE RL=32Ω
FREQUENCY (Hz)
FREQUENCY (Hz)
PSRR vs. frequency
PSRR vs. frequency
10/29
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MOSA
MS6821
4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control
VDD=5V
DAC VFS
THD+N (%)
THD+N (%)
THD+N (%)
DAC inputs signal
(Ta=25℃, sampling rate=4fs, fs= 44.1kHz, f=1kHz, PA is Power Down mode; unless otherwise specified)
VDD=3.3V, VFS
DAC VFS
VDD=2.4V, VFS
DAC VFS
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
THD+N vs. frequency
THD+N vs. frequency
THD+N vs. frequency
CHANNEL SEPARATION (dB)
CAP=10uF
PSRR (dB)
CAP=1uF
VDD=5V
DAC VFS
VDD=5V
VRR=0.2Vrms
SUPPLY VOLTAGE (V)
FREQUENCY (Hz)
Channel separation vs. supply voltage
PSRR vs. frequency
REV 3
11/29
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MOSA
MS6821
4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control
AUDIO TIMING AND FORMAT
The MS6821 accepts input serial data formats of 16-bit word length. Left and right data words are time multiplexed.
The MSB must always be first.
LEFT
WS
RIGHT
tr
tHB
tf
tLB
tHW
tSW
BCK
tcr
DATA
tSD
LSB
Audio data format (BCK, WS, DATA)
Symbol
Parameter
tHD
MSB
Conditions
Min
Typ
Max
Unit
VIL
Input LOW level
2
-
-
V
VIH
Input HIGH level
-
-
0.8
V
f BCK
Input Clock Frequency
-
-
18.4
MHz
BR
Bit Rate Data Input
-
-
18.4
Mbits/s
fWS
Word Select Input
-
-
384
kHz
tr
tf
t Cr
t HB
t LB
t SD
t HD
t HW
t SW
Rise Time
-
-
12
ns
Fall Time
-
-
12
ns
Bit Clock Cycle Time
54
-
-
ns
Bit Clock High Time
15
-
-
ns
Bit Clock Low Time
15
-
-
ns
Data Set-up Time
12
-
-
ns
Data Hold Time to Bit Clock
2
-
-
ns
Word Select Hold Time
2
-
-
ns
Word Select Set-up Time
12
-
-
ns
REV 3
12/29
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MOSA
MS6821
4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control
Right justified format
LEFT
WS
RIGHT
BCK
DATA 2
1
0
15
14
13
2
1
MSB
0
15
LSB
MSB
14
13
2
1
0
LSB
Left justified format
LEFT
WS
RIGHT
BCK
DATA
15
14
13
2
MSB
1
0
15
LSB
MSB
14
13
2
1
0
15
LSB
MSB
I2S format
WS
LEFT
RIGHT
BCK
1 BCK
DATA
15
MSB
REV 3
14
1 BCK
13
2
1
0
15
LSB
MSB
13/29
14
13
2
1
0
LSB
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MOSA
MS6821
4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control
I2C BUS DESCRIPTION
Start and Stop Conditions
A start condition is activated when the SCL is set to HIGH and SDA shifts from HIGH to LOW state. The stop
condition is activated when SCL is set to HIGH and SDA shifts from LOW to HIGH state. Please refer to the timing
diagram below.
SCL
SDA
Stop
Start
SCL : Serial Clock Line, SDA : Serial Data Line
Data Validity
A data on the SDA line is considered valid and stable only when the SCL signal is in HIGH state. The HIGH and
LOW states of the SDA line can only change when the SCL signal is LOW. Please refer to the figure below.
SDA
SCL
Data line
stable,
Data valid
Data
change
allowed
Byte Format
Every byte transmitted to the SDA line consists of 8 bits. Each byte must be followed by an acknowledge bit.
The MSB is transmitted first.
Acknowledge
During the Acknowledge clock pulse, the master (up) put a resistive HIGH level on the SDA line. The peripheral
(audio processor) that acknowledges has to pull-down (LOW) the SDA line during the Acknowledge clock pulse so that
the SDA line is in a stable LOW state during this clock pulse. Please refer to the diagram below.
SCL
1
2
3
7
8
9
SDA
MSB
Acknowledge
Start
The audio processor that has been addressed has to generate an Acknowledge after receiving each byte, otherwise,
the SDA line will remain at the HIGH level during the ninth (9th) clock pulse. In this case, the master transmitter can
generate the STOP information in order to abort the transfer.
REV 3
14/29
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MOSA
MS6821
4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control
Timing of SDA and SCL Bus Lines
SDA
tf
tLOW
SCL
S
tHD;STA
tSU;DAT
tr
tHD;DAT
Standard Mode
Symbol
fSCL
tHD;STA
tf
tSU;STA
tHIGH
Parameter
Sr
tSP
tBUF
tr
tSU;STO
P
S
Min
Max
Unit
0
100
kHz
4.0
-
us
tLOW
SCL clock frequency
Hold time (repeated) START condition.
After this period, the first clock pulse is generated
LOW period of the SCL clock
4.7
-
us
tHIGH
HIGH period of the SCL clock
4.0
-
us
tSU:STA
4.7
-
us
0
3.45
us
tSU:DAT
Set-up time for a repeated START condition
Data hold time:
For I2C-bus devices
Data-set-up time
250
-
ns
tr
Rise time of both SDA and SCL signals
-
1000
ns
tf
Fall time of both SDA and SCL signals
-
300
ns
tSU:STO
Set-up time for STOP condition
4.0
-
us
tBUF
Bus free time between a STOP and START condition
4.7
-
us
Cb
Capacitive load for each bus line
-
400
pF
VnL
Noise margin at the LOW level for each connected device (including
0.1VDD
hysteresis)
-
V
VnH
Noise margin at the HIGH level for each connected device (including
0.2VDD
hysteresis)
-
V
tHD:STA
tHD:DAT
REV 3
15/29
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MOSA
MS6821
4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control
BUS INTERFACE
Data are transmitted to and from the MCU to the MS6821 via the SDA and SCL. The SDA and SCL make up the
BUS interface. It should be noted that pull-up resistors must be connected to the positive supply voltage.
VDD
Rp
Rp
Pull up resistors
SDA (Serial Data Line)
SCL (Serial Clock Line)
MCU
MS6821
I2C interface protocol
The format consists of the following:
‧A START condition
‧A chip address byte including the chip address. (7bits)
‧The 8th bit of the byte must be “0”.(write=0, read=1)
‧The chip must always acknowledge the end of each transmitted byte.
‧A data sequence (N-bytes + Acknowledge)
‧A STOP condition
SDA
SCL
1-7
8
9
1-7
8
9
1-7
8
9
S
P
START
CONDITION
STOP
CONDITION
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK
I2C chip address
88H
1
0
0
0
1
7 bits address
REV 3
0
0
0
W
16/29
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MOSA
MS6821
4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control
I2C data bytes description
MSB
LSB
Function
0
0
B2
B1
B0
A2
A1
A0
L-ch, Attenuation and Mute
0
1
B2
B1
B0
A2
A1
A0
R-ch, Attenuation and Mute
1
0
0
G2
G1
G0
S1
S0
L-ch, Input Gain and line Selection
1
0
1
G1
G0
S1
1
0
RPD
LPD
PDPR
S0
CAP
PD
R-ch, Input Gain and line Selection
1
G2
DAC
PD
1
1
1
MixL
MixR
AF1
S/B
AF0
Power Down Mode
Output mode (SE/BTL), Mixer control
and Audio format
Where Ax = 1.25dB/step; Bx = 10dB/step; Gx = 3dB/step
Attenuation and Mute
MSB
LSB
0
0
0
1
B2
B1
B0
L-ch, Attenuation and Mute
A2
A1
A0
0
0
0
0 dB
R-ch, Attenuation and Mute
0
0
1
-1.25 dB
0
1
0
-2.5 dB
0
1
1
-3.75 dB
1
0
0
-5 dB
1
0
1
-6.25 dB
1
1
0
-7.5 dB
1
1
1
-8.75 dB
0
0
0
0 dB
0
0
1
-10 dB
0
1
0
-20 dB
0
1
1
-30 dB
1
0
0
-40 dB
1
0
1
-50 dB
1
1
0
-60 dB
1
1
1
-70 dB
1
1
1
1
Initial state: Both L-ch and R-ch are mute-on.
REV 3
Function
1
1
17/29
Mute
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MOSA
MS6821
4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control
Input Selector and Input Gain
MSB
LSB
1
0
0
1
0
1
G2
G1
G0
Function
L-ch, Input Gain and line Selection
S1
S0
0
0
Line 1 (L-ch or R-ch)
0
1
Line 2 (L-ch or R-ch)
1
0
Line 3 (L-ch or R-ch)
1
1
Line 4 (L-ch or R-ch)
R-ch, Input Gain and line Selection
0
0
0
0 dB
0
0
1
3 dB
0
1
0
6 dB
0
1
1
9 dB
1
0
0
12 dB
1
0
1
15 dB
1
1
0
18 dB
1
1
1
Initial state: L-ch1, R-ch1, Input gain is 0dB.
21 dB
Power Down Mode
MSB
1
1
0
DAC
PD
0
RPD
LSB
CAP
LPD PDPR
PD
Function
Power mode selection and power management
DAC is active mode
1
DAC is power down mode
0
R-ch PA output is active mode
1
R-ch PA output is power down mode
0
L-ch PA output is active mode
1
L-ch PA output is power down mode
0
Disable preparation for power off
1
Enable preparation for power off
0
Set the voltage of CAP to middle of supply voltage
1
Pull down CAP pin to ground
Initial state: All are the power down modes.
Enable the power down preparation before the chip will be shut down.
REV 3
18/29
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MOSA
MS6821
4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control
Output mode (SE/BTL), Mixer control and Audio format
MSB
LSB
1
1
1
S/B
MixL
MixR
AF1
AF0
Function
Output mode, mixer control and audio format
0
Output mode is BTL
1
Output mode is SE
0
L-ch of input selector is the only signal
1
Mix L-ch of input selector and L-ch of DAC
0
R-ch of input selector is the only signal
1
Mix R-ch of input selector and R-ch of DAC
0
0
Right justified format
1
0
Left justified format
0
1
I2S format
1
1
Initial state: Output mode is BTL mode, unmixed mode and Right justified format
I2C Initial code and status
MSB
LSB
Function
Initial status
0
0
1
1
1
1
1
1
L-ch, Attenuation and Mute
Mute On
0
1
1
1
1
1
1
1
R-ch, Attenuation and Mute
Mute On
1
0
0
0
0
0
0
0
L-ch, Input Gain and line Selection
Line1, 0dB
1
0
1
0
0
0
0
0
R-ch, Input Gain and line Selection
1
1
0
1
1
1
1
1
Power Down Mode
1
1
1
0
0
0
0
0
Output mode (SE/BTL), Mixer control
and Audio format
Line1, 0dB
All devices
power down
BTL, Unmixed,
Right justified
REV 3
19/29
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MOSA
MS6821
4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control
I2C CODE EXAMPLE
Input selector and input gain
Set left channel to be line-4 and input gain to be 3dB. Set right channel to be line-4 and input gain to be 3dB.
Gain
Start
MS6821 Address
ACK
1
0
0
0
0
Line
1
1
1
ACK
1
L-ch = Line4, G = 3dB
0
1
0
0
1
1
1
ACK
Stop
ACK
Stop
R-ch = Line4, G = 3dB
The left and right input channel are independent.
Volume control
Set left channel to be -15dB and right channel to be 30dB.
Gain
Start
MS6821 Address
ACK
1
0
0
0
0
Line
1
1
1
ACK
L-ch = Line4, G = 3dB
1
0
1
0
0
1
1
1
R-ch = Line4, G = 3dB
Power down mode
Set built-in DAC to be power down mode.
DACPD
Start
MS6821 Address
ACK
1
1
0
1
0
0
0
0
ACK
Stop
DAC power down
Output mode, mixer control and audio format
Set output mode to be SE mode, audio format is I2S, and both input channel to be mixed.
Output mode
Start
MS6821 Address
ACK
1
1
1
Mixer
1
1
1
Audio format
0
1
ACK
Stop
SE mode, All mix, I2S
REV 3
20/29
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MOSA
MS6821
4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control
OPERATION PROCEDURE
The sequence of operation: power on→ activating → power down → activating → power off. The basic flowcharts are
as follows:
For HP mode and HP/BTL mode
REV 3
21/29
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MOSA
MS6821
4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control
For BTL mode only
Power On
Activating
Power Down
(Shut Down)
Power Off
All the Digital Interface Signals
Pull Low
Setting Input Gain Is Fixed
Volume Down To Mute
Input Channels Mute On
Volume Down To Mute
Input Channels Mute On
I2C pull low
Audio inputs pull low
(BCK, WS, DATA)
VDD = GND
[ Input Gain ]
Code: Lch 100xxx00
Rch 101xxx00
[ Attenuation and Mute ]
Code: Lch 00111111 (3Fh)
Rch 01111111 (7Fh)
Disable Power Down
Power On
VDD = Supply voltage
Pull Down CAP Pin To Ground
[ Power Down Mode ]
Code: 11000000 (C0h)
Wait 0.5 sec
[ Power Down Mode ]
Code: 11000001 (C1h)
Wait 0.1 sec
[ Attenuation and Mute ]
Code: Lch 00111111 (3Fh)
Rch 01111111 (7Fh)
Pull Down CAP Pin To Ground
[ Power Down Mode ]
Code: 11000001 (C1h)
Wait 0.1 sec
Default Status
[Attenuation & Mute]
Mute on (max attenuation)
[ Input Selector & Input Gain ]
L-ch1, R-ch1
0dB
Mute Off And Volume Up/Down
Step By Step
[ Attenuation and Mute ]
Code: Lch 00xxxxxx
Rch 01xxxxxx
Power Down All The Devices
[ Power Down Mode ]
Code: 11011111 (DFh)
Power Down All The Devices
[ Power Down Mode ]
Code: 11011111 (DFh)
[ Power Down Mode ]
All power down status
Keep All The Digital Interface
Signals Unchanged
[ Output Mode & Mixer & Format ]
BTL mode
Inputs not mixed with DAC signal
RJF format
All the Digital Interface Signals
Pull Low
I2C pull low
Audio inputs pull low
(BCK, WS, DATA)
Power Off
Disconnect VDD
VDD will be fell down to 0V
REV 3
22/29
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MOSA
MS6821
4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control
APPLICATION INFORMATION
A base application circuit
MCU
VDD
HP_sense
100k
100k
10uF
10uF
10uF
10uF
1uF
RIN1
RIN2
RIN3
Attenuation
&
Mute
RIN4
Mixer
-1
OUTR-
Input selector
&
Gain control
10uF
10uF
10uF
10uF
OUTR+
LIN1
LIN2
LIN3
LIN4
Attenuation
&
Mute
Mixer
Headphone Jack
-1
OUTL-
100uF
OUTL+
16-bit DAC
1k
RL
8Ω
-1
WS
1k
RL
8Ω
-1
BCK
Audio
Decoder
100uF
DATA
I2C
Interface
Supply
VDD Vss
2.4 ~ 6.5V
1uF
Supply
CAP
DACR
DACL
SCL
SDA
1uF
Power Amplifier
Supply
PVDDL PVSSL PVDDR PVSSR
1uF
1uF
MCU
2.4 ~ 6.5V
Power Amplifier Supply
0.1uF
MCU
VDD
HP_sense
100k
10uF
10uF
10uF
10uF
1uF
RIN1
RIN2
RIN3
Attenuation
&
Mute
RIN4
Mixer
off
-1
Input selector
&
Gain control
10uF
10uF
10uF
10uF
LIN1
LIN2
LIN3
LIN4
WS
OUTR-
-1
Attenuation
&
Mute
Mixer
off
-1
BCK
Audio
Decoder
100k
OUTR+
OUTL-
-1
16-bit DAC
OUTL+
100uF
1k
RL
8Ω
Headphone Jack
100uF
1k
RL
8Ω
DATA
I2C
Interface
Supply
VDD Vss
2.4 ~ 6.5V
1uF
Supply
CAP
DACL
DACR
SCL
SDA
1uF
1k
1k
Power Amplifier
Supply
PVDDL PVSSL PVDDR PVSSR
1uF
1uF
MCU
2.4 ~ 6.5V
Power Amplifier Supply
0.1uF
10nF
REV 3
10nF
23/29
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MOSA
MS6821
4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control
Output mode operation -- SE mode and BTL mode
The output mode has two modes, SE mode and BTL mode. The mode is selected by I2C code via a MCU.
In BTL mode, the outputs of A1(B1) and A2(B2) are then used to drive the bridged-tied load
A1
OUTR-
-1
RL
4Ω / 8Ω
A2
-1
OUTR+
B1
OUTL-
-1
RL
4Ω / 8Ω
B2
-1
OUTL+
I2C
Interface
SCL SDA
In the SE mode, the amplifiers A2 and B2 are shutdown, and then the amplifiers will be a high output impedance state.
A1
OUTR-
-1
100uF
1k
Headphone
Jack
RL
16Ω / 32Ω
A2
-1
Shutdown
B1
OUTL-
-1
100uF
1k
B2
-1
Shutdown
I2 C
Interface
SCL SDA
Headphone sense
The output mode is SE or BTL that is decided by a headphone. It has to be set SE mode when a headphone is plug-in
status. The output mode is selected by I2C command code by a MCU. Please note that the MS6821 don’t detect a
headphone automatically. Thus a detect function is executed via a MCU. An operation diagram is as follows:
The HP_sense pin is high when a headphone is plug-in.
The HP_sense pin is low when a headphone is not plug-in.
REV 3
24/29
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MOSA
MS6821
4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control
EXTERNAL DIMENSIONS
SOP28 (300mil)
D
Detail A
E H
h x45
C
A
e
B
A1
0.25mm
θ
Detail A
Symbol
Dimension in inch
Min
Max
Min
Max
A
2.35
2.65
0.0926
0.1043
A1
0.10
0.30
0.0040
0.0118
B
0.33
0.51
0.013
0.020
C
0.23
0.32
0.0091
0.0125
e
REV 3
Dimension in mm
1.27 BASIC
0.050 BASIC
E
7.40
7.60
0.2914
0.2992
H
10.00
10.65
0.394
0.419
L
0.40
1.27
0.016
0.050
D
17.70
18.10
0.6969
0.7125
h
θ
0.25
0.75
0.010
0.029
0
o
8
L
o
25/29
0
o
8
o
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MOSA
MS6821
4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control
TSSOP28 (Thermal Pad)
D
D2
Detail A
E2
E1 E
C
A2
A
θ
A1
B
Symbol
REV 3
e
Dimension in mm
Min
Nom
L
y
Max
L1
Dimension in inches
Min
Nom
Max
A
-
-
1.15
-
-
0.045
A1
0.00
-
0.10
0.000
-
0.004
A2
0.80
1.00
1.05
0.031
0.039
0.041
b
0.19
-
0.30
0.007
-
0.012
0.008
C
0.09
-
0.20
0.004
-
D
9.60
9.70
9.80
0.378
0.382
0.386
D2
3.70
3.80
3.90
0.146
0.150
0.154
E
6.20
6.40
6.60
0.244
0.252
0.260
E1
4.30
4.40
4.50
0.169
0.173
0.177
E2
2.70
2.80
2.90
0.106
0.110
0.114
e
-
0.65
-
-
0.026
-
L
0.45
0.60
0.75
0.018
0.024
0.030
L1
0.90
1.00
1.10
0.035
0.039
0.043
θ
0o
-
8o
0o
-
8o
y
-
-
0.10
-
-
0.004
26/29
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MOSA
MS6821
4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control
DEMO BOARD
1
2
3
8
4
7
5
6
Function description
Label 1: Supply Input
Supply voltage range is 2.4V to 6.5V.
Label 2: Headphone Jack
Used 3.5mm diameter of headphone with 32ohm
Label 3: DAC output
Connected to a post-power-amplifier, as active speaker.
In addition, using volume control for DAC, this output can connected to input section (label 6) as feedback.
Label 4: Speaker Output
Connected to speaker with 8ohm or 4 ohm
Label 5: Digital Signal Input
Connected to digital audio formats as I2S, Right Justified and Left Justified.
Label 6: Signal Input
There are four stereo inputs in the section. Please input stereo audio signal, as music or sine wave.
Label 7: Reset
All I/O pins are reset to default values.
Label 8: LED Indicator
The LEDs indicate the chip status and IR received status. It keeps on a light state when the MS6821 is active. The other
hand, keeps on a dark state when the MS6821 is power-off. It is red-dark blink once when the MCU has received the
function code correctly.
REV 3
27/29
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MOSA
MS6821
4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control
SE mode and BTL mode operation
The headphone controls operational mode. System enters SE mode when headphone jack is empty.
When a set of headphone plugged into the jack, the system switched to BTL mode.
IR Controller
Power ON/OFF : The power key.
Press the key once to set power-on or power-off for MS6821.
IN1~IN4 : Analog input channel.
Press the key once to select input channel.
The default state is IN1.
VOL+, VOL- : The volume control keys.
The volume control in 1.25dB/step as the switch is pressed once, the range is –77.5dB to 0dB.
The default value is -20dB.
Gain+, Gain- : The gain control keys.
The gain control in 3dB/step as the switch is pressed once, the range is 0dB to 21dB.
The initial value is 0dB.
Mute : The mute key
Press the key once to set mute-on or mute-off.
The default state is mute-off.
PD/Active : The power down key.
Press the key once to set power-down or activation for MS6821.
Mix_LR ON/OFF : The mixing DAC signal keys.
Mix_L ON, mixed the left channel of DAC with the left channel of input signal.
Mix_R OFF, unmixed the right channel of DAC with the right channel of input signal.
I2S, LJF, RJF: The digital input format keys.
There are three formats can be selected that is I2S, Left justified and Right justified.
REV 3
28/29
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MOSA
MS6821
4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control
Circuit
J1
DVDD
R1
1
2
+
+
DVDD
C3
0.1u
S1
C4
1u
J13
10K
C6
20P
C7
20P
+
1
2
3
2
LCD
Q2
C8
0.1u
J3
R5
R6
R7
1
2
3
4
1K
1K
C15
SP1
10u
C16
10u
SPK_R
1K
1K
C20
10u
C22
C19 100u
+
+
R14
R15
1K
1K
C23
WS
BCK
REF
R1
R2
R3
R4
Vss
PVDDR
-OUTR
+OUTR
GND
PVSSR
DAC_R
DATA
SCL
SDA
L1
L2
L3
L4
VDD
PVDDL
-OUTL
+OUTL
GND
PVSSL
DAC_L
28
27
26
25
24
23
22
21
20
19
18
17
16
15
C25
10u
SCL
SDA
AVCC
SP2
+
C17
1u
SPK_L
+
C18
100u
+
R9
1K
1
2
3
4
5
6
HP-IN
HP-R
R
HP-L
L
G
HEADPHONE
J9
1
2
3
OUT
1
R
2
L
3
G
DAC_OUT
Jumper
REV 3
DGND
J12
W1
AGND
U2
C24
10u
R8 J10
1K
1
2
3
DAC_OUT
AGND
+ C5
470P
+
10u
+
R16
R17
IR
IR
MS6821
C21
1u
10u
+
1
2
3
10u
+
IN4
R
L
G
10u
+
J8
1
2
3
C13
+
IN3
R
L
G
1K
1K
+
J6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
10u
C14
R12
R13
GND
R4
100K
C11
R10
R11
IN1
D1
IN2
D2
IN3
D3
IN4
D4
VS
3
1K
1K
1K
+
IN2
R
L
G
1
2
3
2
1u
+
J5
47u
R22 100K
C10 1u
1
2
3
1
+
+
IN1
R
L
G
C12
Q1
C1 +
C9
1u
DAC_IN
J4
1
R2
10K
IR_IN
20
19
18
17
16
15
14
13
12
11
Vcc
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
P3.7
AT89C4051
2
+
+
AVCC
RST
P3.0
P3.1
XTAL2
XTAL1
P3.2
P3.3
P3.4
P3.5
GND
NMOS
AVCC
1
2
1
2
RX
3
TX
4
5
IR_IN 6
SCL
7
SDA
8
HP_IN 9
10
3
+
DGND
J2
1
Y1
24M
W2
JUMP
R18 R19 R20 R21
1K 1K 1K 1K
U1
RST
R3
RX
TX
+ C2
10u
220
DGND
29/29
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