OKI Semiconductor ML7055 FEDL7055-02 Issue Date: Apr. 8, 2003 Bluetooth Baseband Controller IC GENERAL DESCRIPTION The ML7055 is a CMOS digital IC for use in 2.4 GHz band Bluetooth™ systems. This IC incorporates the ARM7TDMI as the CPU core, features a highly expandable architecture, and supports the interfaces for a variety of applications. Since the ML7055 has Oki’s Bluetooth protocol stack software installed, when the IC is used in conjunction with the Bluetooth RF transceiver IC, data/voice communications are possible while maintaining interconnectivity with other Bluetooth systems. FEATURES • Conforms to Bluetooth Specification (Ver1.1) • Designed for connection with the RF-LSI interface, such as the OKI RF-LSI interface (ML7050), the SKYWORKS RF-LSI interface (CX72303), or the BROADCOM RF-LSI interface (BCM2002X) that functions as the Bluetooth RF-LSI interface • The high-speed, low-power ARM7TDMITM is installed as the CPU core • PCM-CVSD transcoder that provides high quality voice using the noise filter is installed • Low power consumption in flexible power management modes according to operating modes of Bluetooth • DETACH signal provides control of change to power-saving mode (STOP) and return request to normal mode. • UART interface corresponding to baud rates up to 921.6 kbps • I2C bus interface provides accesses to EEPROM or PCM-Codec • Selactable 12 MHz or 13 MHz for the system clock • Selectable 32 kHz or 32.768 kHz for the LPO clock • Built-in programmed ROM eliminates external ROM/FLASH • The packages are available in three types: 63-pin WCSP for ML7055HB 64-pin BGA for ML7055LA 84-pin BGA for ML7055LP ARM, ARM7TDMI and Thumb are registered trademarks of ARM Ltd., UK. BLUETOOTH is a trademark owned by Bluetooth SIG, Inc. and licensed to Oki Electric Industry. The information contained herein can change without notice owing to the product being under development. 1/30 FEDL7055-02 OKI Semiconductor ML7055 SPECIFICATIONS Process Package 0.16 µm CMOS (5-layer metal wire) 63-pin WCSP (P-VFLGA63-4.90×4.72-0.50-W) (Dimensions: 4.90 mm × 4.72 mm × 0.48 mm; pin pitch: 0.50 mm) 64-pin BGA (P-TFBGA64-0707-0.65) (Dimensions: 7 mm × 7 mm × 1.2 mm; pin pitch: 0.65 mm) 84-pin BGA (P-LFBGA84-0909-0.80) (Dimensions: 9 mm × 9 mm × 1.5 mm; pin pitch: 0.80 mm) Supply current 22 mA (24 MHz operation) Operating voltage ranges 2.70 to 3.6 V for input-output, 1.65 to 1.95 V for internal circuits Operating frequency 24 MHz Built-in ROM size 176 KB (for ARM program) Built-in RAM size 24 KB Input clocks 12 MHz or 13 MHz (system clock) 32 kHz or 32.768 kHz (LPO clock) RF-LSI interface OKI RF-LSI interface (ML7050) SKYWORKS RF-LSI interface (CX72303) Timers BROADCOM RF-LSI interface (BCM2002X) UART interface (up to 921.6 Kbps) General-purpose I/O interface (used as a pin for I2C bus interface depending on software installed) PCM interface (PCM Linear/A-law/µ-law can be selected) DETACH interface 16-bit auto reload timer (1ch) Interrupt controller 11 causes Installed interfaces 18-bit auto reload timer (1ch) Clock control circuit Crystal oscillator circuit (12 MHz or 13 MHz, 32 kHz or 32.768 kHz) Internal PLL 2/30 FEDL7055-02 OKI Semiconductor ML7055 PIN PLACEMENT ML7055HB: 63-pin WCSP (P-VFLGA63-4.90 × 4.72-0.50-W) RSSI_ TX_POW CLK VDD GND GND VDD PLL_ DATA GND SOUT Core VDD GND GND PLL _CLK GND PCM OUT Core VDD PCM SYNC PCM CLK GND SCL PCMIN LVDD GND 8 PLL _PS PLL _POW GND TXD RX_ POW PLL _OFF Core VDD RSSI RXD PLL_LE VDD PLL SFRQ LOCK SEL 7 6 5 SIN RFSEL1 SDA 4 XC32KN SCLK SEL RESET AGND0 RFSEL0 CTS CLKOUT VDD 3 Core XC32KP AVDD1 AGND1 VDD VDD DETACH RTS GND 2 GND AVDD0 GND SCLKN SCLKP GND Core VDD RFSEL2 1 A B C D E F G H TOP VIEW 3/30 FEDL7055-02 OKI Semiconductor ML7055 ML055LA: 64-pin BGA (P-TFBGA64-0707-0.65) GND AGND1 AGND0 Core SCLKN RESET VDD GND RFSEL1 Core VDD RFSEL2 10 XC32KP AVDD1 AVDD0 GND SCLKP VDD DETACH RFSEL0 RTS CTS 9 XC32KN VDD CLKOUT GND 8 SCLK SEL SFRQ SEL SDA SCL Core VDD PLL LOCK VDD Core VDD RSSI RXD PCMIN GND GND TXD PCM SYNC PCM CLK PCMOUT Core VDD 7 6 5 4 PLL_PS PLL_LE 3 RX_ POW TX_ POW PLL_ DATA LVDD GND VDD GND GND GND GND PLL_ POW PLL_ OFF RSSI_ CLK PLL_ CLK GND SOUT SIN Core VDD GND VDD 2 1 A B C D E F G H J K TOP VIEW 4/30 FEDL7055-02 OKI Semiconductor ML7055 ML7055LP: 84-pin BGA (P-LFBGA84-0909-0.80) GND Core AVDD1 AGND1 AVDD0 AGND0 SCLKN RESET RFSEL0 VDD RFSEL2 10 XC32KP AVDD1 AGND1 AGND0 GND VDD GND NC CTS RTS 9 VDD XC32KN NC AVDD0 Core VDD SCLKP DETACH RFSEL1 GND CLKOUT 8 SFRQ SEL SCLK SEL NC SCL NC SDA Core VDD NC NC NC NC VDD RXD PLL LOCK RSSI TXD GND NC 7 6 PCMIN GND Core VDD PCM OUT PCM SYNC 5 PCMCLK 4 PLL_LE PLL_PS NC NC GND VDD GND NC GND Core VDD PLL_ CLK GND SOUT SIN NC GND GND LVDD NC NC Core VDD GND GND VDD E F 3 TX_ POW RX_ RSSI_ POW CLK 2 PLL_ POW PLL_ OFF PLL_ DATA B C 1 A D G H J K TOP VIEW 5/30 FEDL7055-02 OKI Semiconductor ML7055 PIN DESCRIPTIONS RF I/F Pin Name Direction [*0] Internal Pull Up/ Down, Schmitt TXD O — RXD I — PLL_DATA O — PLL_CLK O — Initial Value L L L — — — X H L L L L Pin Placement ML7055 HB ML7055 LA ML7055 LP B6 B4 A4 C5 B5 A5 C7 C2 C1 E6 D1 D2 D5 B3 A3 B5 A5 C5 B8 C1 C2 B7 A1 A1 L PLL_LE O — H L RSSI I Pull down — — — L RSSI_CLK O — L X H PLL_POW O — L H H TX_POW O — L A8 B2 A2 C6 A2 B2 A7 A3 B3 L H RX_POW O — L L L Description ML7050: Transmit data output CX72303: Transmit data output BCM2002X: Transmit data output ML7050: Receive data input CX72303: Receive data input BCM2002X: Receive data input ML7050: Serial write data CX72303: Serial write data BCM2002X: Transmit enable ML7050: Serial clock CX72303: Serial clock BCM2002X: Serial clock ML7050: Serial road enable 0: Negate, 1: Assert CX72303: Serial enable 0: Assert, 1: Negate BCM2002X: RF-LSI synthesizer on 0: Negate, 1: Assert ML7050: Receive field strength data input CX72303: Serial read data BCM2002X: Serial read data ML7050: Receive field strength data clock CX72303: RF-LSI receiving characteristic control BCM2002X: System clock request ML7050: Local PLL power control 0: Assert, 1: Negate CX72303: PA Power control 0: Negate, 1: Assert BCM2002X: Select serial transmit mode ML7050: Transmit enable 0: Assert, 1: Negate CX72303: Transmit enable 0: Negate, 1: Assert BCM2002X: Serial write data ML7050: Receive enable 0: Assert, 1: Negate CX72303: Receive enable 0: Negate, 1: Assert BCM2002X: Receive enable ML7050: ”L” CX72303: Power on reset PLL_PS O — X L [*0] 0: Assert (reset) 1: Negate BCM2002X: RF-LSI receiving characteristic control “I” = Input, “O” = Output, “I/O” = Input/Output 6/30 FEDL7055-02 OKI Semiconductor ML7055 RF I/F Pin Name Direction [*0] Internal Pull Up/ Down, Schmitt PLLLOCK I Pull down Initial Value Pin Placement ML7055 HB ML7055 LA ML7055 LP B4 B6 B5 — PLL_OFF O — — Description ML7050: — CX72303: — — BCM2002X: 1MHz clock H ML7050: PLL loop control — D6 B1 B1 L 0: Open loop 1: Closed loop CX72303: Diversity output BCM2002X: PA Power control PCM I/F Pin Name Direction Internal Pull Up/ Down, Schmitt Initial Value PCMOUT O — PCMIN I PCMSYNC PCMCLK Pin Placement L ML7055 HB G6 ML7055 LA J3 ML7055 LP J4 Pull up — H4 J5 H5 I/O Pull down — F5 J4 K4 I/O Pull down — G5 K4 H4 Description PCM data output PCM data input PCM sync signal (8 kHz), Initial setting: input (can be switched by an internal register) PCM clock (64 kHz/128 kHz) Initial setting: input (can be switched by an internal register) Note: The PCM sync signal (8 kHz) must be guaranteed at the accuracy of ±50 ppm if the PCMSYNC pin is configured as an input. UART I/F Internal Pull Up/ Down, Schmitt Pin Name Direction SOUT O — SIN I Schmitt RTS O CTS I Initial Value Pin Placement Description H ML7055 HB E7 ML7055 LA F1 ML7055 LP F2 ACE transmit serial data — D4 G1 G2 ACE receive serial data — — G2 J9 K9 ACE transmit data ready — H F3 K9 J9 ACE transmit ready 7/30 FEDL7055-02 OKI Semiconductor ML7055 CLK and Configuration Pin Name Direction Internal Pull Up/ Down, Schmitt Initial Value SCLKP I — Pin Placement ML7055 HB ML7055 LA ML7055 LP — E1 E9 F8 Description System clock (12/13 MHz) pins (Power level: CMOS level) SCLKN O — — D1 E10 F10 XC32KP I — — A2 A9 A9 XC32KN O — — A3 A8 B8 SCLKSEL I Pull down — B3 A7 B7 SFRQSEL I Pull down — C4 B7 A7 RFSEL0– 2 I — — [*1] [*2] [*3] RESET I Schmitt — C3 F10 G10 DETACH I Schmitt — F2 G9 G8 Sleep pin (Sleep = L) SCL O — L G4 K7 H7 I2C serial clock SDA I/O — H F4 J7 K7 I2C serial data CLKOUT O — — G3 J8 K8 System clock (12/13 MHz) output pins [*1] [*2] [*3] Subclock pins (for oscillator) System clock frequency select pin L: Select CLK divided by internal PLL H: Select subclock System clock frequency select pin L: 13 MHz H: 12 MHz RF-LSI select pins RFSEL[2:0] 001: ML7050 (OKI) 010: CX72303 (SKYWORKS) 101: BCM2002X (BROADCOM) Others: Unused Hardware reset pin (Reset = L) RFSEL0: E3; RFSEL1: E4; RFSEL2: H1 RFSEL0: H9; RFSEL1: H10; RFSEL2: K10 RFSEL0: H10; RFSEL1: H8; RFSEL2: K10 8/30 FEDL7055-02 OKI Semiconductor ML7055 NC Pin Name Direction Internal Pull Up/ Down, Schmitt Initial Value NC [*4] Pin Placement ML7055 HB ML7055 LA ML7055 LP — — [*4] Description No connection B6, C3, C4, C6, C7, C8, D3, E1, F1, H2, H3, H6, H9, J6, J7 Note: Do not wire under the NC pin. Power, GND Pin Name Direction Internal Pull Up/ Down, Schmitt Initial Value VDD — — CoreVDD — LVDD Pin Placement ML7055 HB ML7055 LA ML7055 LP — [*5] [*6] [*7] — — [*8] [*9] [*10] — — — C8 D2 D1 Description I/O power supply pin 2.70 to 3.6 V Power supply pin for internal circuit 1.65 to 1.95 V RF-I/O power suply pin (Same voltage to the VDD for RF-LSI) GND — — — [*11] [*12] [*13] Digital block ground pin AVDD0 — — — B1 C9 [*14] AVDD1 — — — B2 B9 [*15] Analog block power supply pin 1.65 to 1.95 V AGND0 — — — D3 C10 [*16] AGND1 — — — C2 B10 [*17] [*5] [*6] [*7] [*8] [*9] [*10] [*11] [*12] [*13] [*14] [*15] [*16] [*17] Analog block ground pin VDD: A4, E2, E8, H3, H8 VDD: B8, F2, K1, J6, F9 VDD: A8, F3, K1, K6, F9 Core VDD: A5, D2, F7, G1, H6 Core VDD: A6, H1, K3, K6, J10, D10 Core VDD: A6, G1, K3, K5, J10, E8 GND: A1, A6, C1, D7, D8, F1, F6, F8, G7, G8, H2, H5, H7 GND: A4, A10, D9, E1, E2, G2, G10, H2, J1, J2, K2, K5, K8 GND: A10, B4, E2, E3, E9, G3, G9, H1, J1, J2, J3, J5, J8, K2 AVDD0: D8, D10 AVDD1: B9, B10 AGND0: E10, D9 AGND1: C9, C10 9/30 RFLSI Clock Default Slave TIC DETACH IF UART GPIO GPIO I/F SCL SDA PCM/ CVSD BT-BB Core PCM Codec I/F ARM7 TDMI I/F AMBA APB AHB Ctl APB Ctl I/F Arbiter AMBA AHB System Control IRAMC 24kB RAM I/F Timer (1ch) IROMC 176kB ROM I/F CTL/ WDT Processor Bus UART I/F I/F IRC Timer AMBA APB DETACH I/F I/F APB Ctl I/F Default Slave CLK GEN FEDL7055-02 OKI Semiconductor ML7055 BLOCK DIAGRAM ML7055 10/30 FEDL7055-02 OKI Semiconductor ML7055 DESCRIPTION OF INTERNAL BLOCKS CLKGEN Block • Generates a clock that is supplied to each block through SCLKP (12/13 MHz) • STOP/HALT function CTL/WDT Block • • • • • Control of the frequency division function of the internal main clock Control of clock supplied to each peripheral Control of reset of each peripheral STOP/HALT control Watchdog timer function (interrupt/reset) Timer Block • • • • 1 channel 18-bit timer counter Interrupt by compare function One shot, interval, or free-run mode Base band Core Block RF LSI Tx SCO Buffer Audio I/F Tx ACL Buffer Security APB TXD Packet Composer Codec Timing FHCNT RF CNT CNT ARM I/F Rx SCO Buffer Packet Decomposer Rx ACL Buffer RXD • RF Controller - RF power supply control (PLL, TX, RX) - Local PLL frequency division ratio setting - Receive clock regeneration function - Synchronization detection (synchronizing within the permissable error limit of SyncWord) - Receive clock re-timing function • FH Controller hopping - Sequence control - Frequency hopping selection function - CRC computation's initial value selection function 11/30 FEDL7055-02 OKI Semiconductor ML7055 • Timing Generator - Bluetooth clock generation - Operation interrupts depend on mode (slot, scan, sniff, hold, park) - Sync detection timing generation (sync window ±10 µs) - PLL setting timing generation - Transmit/Receive timing generation - Multi-master timing management function • Packet Composer - Access code generation (SyncWord generation, appending PR*TRAILER) - Packet header generation (HEC generation, scrambling, FEC encoding) - Payload generation (CRC generation, encryption, scrambling, FEC encoding) - Packet synthesis • Packet Decomposer - Packet decomposition (separating the packet header and the payload) - Packet header processing (FEC decoding, descrambling, HEC error detection, header information separation) - Payload processing (FEC decoding, descrambling, encryption decoding, CRC judgement, payload separation) • Security - Various key generation functions (initialization, link key, encryption key) - Certification function - Encryption function 12/30 FEDL7055-02 OKI Semiconductor ML7055 UART Block • • • • • • • • • • Full-duplex buffering method All status reporting function Built-in 64-byte transmit/receive FIFO Modem control based on CTS Programmable serial interface 5-, 6-, 7-, 8-bit characters Generation and verification of odd parity, even parity, or no parity 1, 1.5, or 2 stop bits Programmable Baud Rate Generator (9600 bps to 921.6 kbps) Error servicing for parity, overrun, and framing errors • Configuration of 1 Data Frame during Reception SIN Start 5 data bits to 8 data bits Parity Stop SAMPLE CLK • Configuration of 1 Data Frame during Transmission SOUT Start 5 data bits to 8 data bits Parity Stop 13/30 FEDL7055-02 OKI Semiconductor ML7055 PCM-CVSD Transcoder Block • Application side I/O: - PCM Codec • Application-side format: - PCM linear (8, 14, 16 bits/sample, 8 kHz sampling frequency)/A-law/µ-law • Bluetooth-side format: - CVSD/A-law/µ-law • All combinations of the above conversions are supported • PCMSYNC/PCMCLK I/O can be switched (initial setting: input) • Timing in Short Mode and in PCMCLK and PCMSYNC Output Mode (For PCM data of 14 bits/sample, lower 2 bits of 16 bits are invalid.) 8 bits or 16 bits PCMCLK(O) 64k/128kHz PCMOUT LSB MSB DATA DATA DATA LSB MSB DATA DATA LSB MSB DATA DATA LSB MSB DATA DATA LSB MSB DATA Data is output on the rising edge of CLK. PCMIN LSB MSB DATA DATA Data is shifted in on the falling edge of CLK PCMSYNC(O) 125µs (8kHz) • Timing in Short Mode and in PCMCLK and PCMSYNC Input Mode. (For PCM data of 14 bits/sample, lower 2 bits of 16 bits are invalid.) 8 bits or 16 bits PCMCLK(I) 64k/128kHz PCMOUT LSB MSB DATA DATA Data is output on the rising edge of CLK. PCMIN LSB MSB DATA DATA Data is shifted in on the falling edge of CLK PCMSYNC(I) 125µs (8kHz) 14/30 FEDL7055-02 OKI Semiconductor ML7055 • Timing in Long Mode and in PCMCLK and PCMSYNC Output mode (For PCM data of 14 bits/sample, lower 2 bits of 16 bits are invalid.) 8 bits or 16 bits PCMCLK(O) 64k/128kHz PCMOUT MSB DATA DATA DATA Data is output on the rising edge of CLK PCMIN MSB DATA DATA DATA LSB MSB DATA LSB MSB DATA LSB MSB DATA MSB DATA Data is shifted in on the falling edge of CLK DATA DATA PCMSYNC(O) PCMCLK period × 3 125µs (8kHz) • Timing in Long Mode and in PCMCLK and PCMSYNC Input Mode. (For PCM data of 14 bits/sample, lower 2 bits of 16 bits are invalid.) 8 bits or 16 bits PCMCLK(I) 64k/128kHz PCMOUT MSB DATA DATA DATA Data is output on the rising edge of CLK. PCMIN MSB DATA DATA DATA DATA Data is shifted in on the falling edge of CLK. DATA LSB ≥ PCMCLK period (Min.) or ≤ 62.5 µs (Max.) 125µs (8kHz) DETACH Interface Block • Generation of the request for change to (from) the stop mode by detection of the rising (falling) edge of the DETACH signal 15/30 FEDL7055-02 OKI Semiconductor ML7055 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Conditions Rating Unit VDD/LVDD — –0.3 to +4.5 V CoreVDD/AVDD — –0.3 to +2.5 V Input voltage VI — –0.3 to +4.5 V Allowable power dissipation Pd — 0.62 W Storage temperature Tstg — –55 to 150 °C I/O power supply voltage Core power supply voltage RECOMMENDED OPERATING CONDITIONS Parameter I/O power supply voltage Core power supply voltage Symbol Conditions Min. Typ. Max. Unit VDD/LVDD — 2.7 3.3 3.6 V CoreVDD/AVDD — 1.65 1.8 1.95 V “H” level input voltage Vih — 2.2 — VDD V “L” level input voltage Vil — 0 — 0.8 V Operating temperature Ta — –40 — 85 °C ELECTRICAL CHARACTERISTICS DC Characteristics (VDD = 2.7 to 3.6 V, CoreVDD = 1.65 to 1.95 V, Ta = –40 to +85°C) Parameter “H” level output voltage “L” level output voltage Symbol Voh Vol Conditions Min. Typ. Max. 3.0V≤Vdd≤3.6V 2.4 — — 2.7V≤Vdd<3.0V 2.2 — — Iol = 2 mA — — 0.4 Vi = GND to 3.6 V –10 — 10 10 66 200 –200 –66 –10 –10 — 10 10 66 200 Ioh = –2 mA Vi = VDD Input leakage current Ii 50 kΩ Pull-down Vi = GND 50 kΩ Pull-up Vo = GND to VDD Output leakage current Io Vo = VDD 50 kΩ Pull-down Power supply current (during operation) Power supply current (during stand-by) Unit V V µA µA Iddo During 24 MHz operation 0 22 32 mA Idds CLK stopped — 10 100 µA 16/30 FEDL7055-02 OKI Semiconductor ML7055 Power Supply Current (IDDO) Characteristics by Power Saving Mode (VDD = 2.7 V to 3.6V, CoreVDD = 1.65 V to 1.95V, Ta = -40 to 85°C) Operating mode STOP mode (DETACH = "L") Page Scan operating mode Poll Interval operating mod Conditions — Interval:1.28sec Window:11.25msec Interval:40slot Interval:2000slot Attempt:4frame Interval:4000slot Sniff operating mode Hold operating mode DH1/DM1 RX:DH3/DM3 TX:DH1/DM1 RX:DH5/DM5 TX:DH1/DM1 ACL operating mode Min. Typ. Max. — 0.03 — — 2.5 — — 3.5 — — 2.5 — — 0.05 — — 22.0 — — 22.0 — — 22.0 — Unit mA AC Characteristics ~ System clock (SCLKP) SCLKP Tmc0 Parameter Tmc0 Tmc1 Tmc1 (VDD = 2.7 to 3.6V, CoreVDD = 1.65 to 1.95V, Ta = -40 to 85°C) Description Min Typ Max Unit Duty in SCLKP “H” duration 40 50 60 % Duty in SCLKP “L” duration 40 50 60 % ~ Sub-clock (XC32KP) XC32KP Tmp0 Parameter Tmp0 Tmp1 Tmp1 (VDD = 2.7 to 3.6V, CoreVDD = 1.65 to 1.95V, Ta = -40 to 85°C) Description Min Typ Max Unit Duty in XC32KP “H” duration 40 50 60 % Duty in XC32KP “L” duration 40 50 60 % 17/30 FEDL7055-02 OKI Semiconductor ML7055 ~ Reset Power supply stable period Vdd/LVdd CoreVdd/AVdd TRESW RESET Parameter TRESW Reset pulse width (VDD = 2.7 to 3.6V, CoreVDD = 1.65 to 1.95V, Ta = -40 to 85°C) Description Min Typ Max Unit 10 — — µs Note : Apply "L" to the RESET pin for 10 µsec or more after the power supply has been settled. 18/30 FEDL7055-02 OKI Semiconductor ML7055 ~ PCM interface PCMCLK(I) PCMIN Tpc0 Tpc1 PCMOUT Tpc2 Tpc2 PCMSYNC(I) Tpc3 Tpc4 Tpc3 Tpc4 PCMCLK(O) PCMIN Tpc5 Tpc6 PCMOUT Tpc 7 Tpc7 PCMSYNC(O) Tpc 8 Parameter Tpc0 Tpc1 Tpc2 Tpc3 Tpc4 Tpc5 Tpc6 Tpc7 Tpc8 (Vdd = 2.7 to 3.6V, CoreVdd = 1.65 to 1.95V, Ta = -40 to 85°C) Description Min Typ Max Unit PCMIN setup time relative to PCMCLK (input) falling edge 100 ns — — PCMIN hold time relative to PCMCLK (input) falling edge 100 ns — — PCMOUT delay time relative to PCMCLK (input) rising edge 250 ns — — PCMSYNC (input) setup time relative to PCMCLK (input) — — 100 ns rising edge PCMSYNC (input) hold time relative to PCMCLK (input) — — ns 100 rising edge PCMIN setup time relative to PCMCLK (output) falling edge 100 ns — — PCMIN hold time relative to PCMCLK (output) falling edge 100 ns — — PCMOUT delay time relative to PCMCLK (output) rising — 250 ns — edge Delay time from PCMCLK (output) rising edge to PCMSYNC 150 ns — — (output) ~ AC Characteristic Measuring Points VDD 0V 0.8VDD 0.8VDD 0.2VDD 0.2VDD 19/30 FEDL7055-02 OKI Semiconductor ML7055 REFERENCE FOR VOLTAGE SUPPLY CIRCUIT ML7055 AVDD0 0.1µF AGND0 AVDD1 0.1µF AGND1 CoreVDD LVDD 10 to 47µF 0.1µF 0.1µF 10 to 47µF 0.1µF 0.1µF 10 to 47µF 0.1µF 0.1µF CoreVDD VDD VDD GND GND Capacitors should locate close to LSI pins. Feed lines should be separated from LSI pins. Example of ML7055 voltage supply circuit • Insert appropriate bypass capacitors between the VDD and GND lines. Note 1: Precautions to insert the bypass capacitors - Use traces of VDD and GND lines wider than those of the other signal lines. - Keep the length of traces between the bypass capacitors and the VDD line and between the bypass capacitors and the GND line as short as possible. - Keep the length of traces between the bypass capacitors and the VDD line and between the bypass capacitors and the GND line as equal as possible. The circuit is subject to change according to the specific LSI board design. Please contact Oki Electric Industry Co., Ltd. for detailed information. 20/30 FEDL7055-02 OKI Semiconductor ML7055 REFERENCE FOR OSCILLATOR CIUCUIT SCLKN SCLKP XC32KP XC32KN ML7055 R0 R2 R1 C0 X’tal 1 C1 R3 C2 X’tal 2 C3 Connect this oscillator circuit only when connecting the OKI RF-LSI ML7050. Example of oscillator circuit Note 1: The values of C0 and C1, and R0 and R1 should be determined according to the specifications for the external crystal X’tal 1 (32 or 32.768 kHz). The values of C2 and C3, and R2 and R3 should be determined according to the specifications for the external crystal X’tal 2 (13 or 12 MHz). Note 2: The crystal oscillator circuit should be connected to pins SCLKP and SCLKN only when the OKI RF-LSI (ML7050) is connected. In other cases, the system clock should be input from the RF-LSI to pin SCLKP. Note 3: In the case of 13 MHz or 12 MHz system clock (SCLKP) input, make sure the crystal frequency tolerance is ±20 ppm for temperature, supply voltage, and aging. In the case of 32 kHz or 32.768 kHz sub-clock (XC32KP) input, make sure the crystal frequency tolerance is ±250 ppm for temperature, supply voltage, and aging. Note 4: Precautions to build a crystal oscillator circuit - Keep length of wire traces as short as possible. - Do not cross the crystal oscillator circuit wires over other signal line wires. - Do not keep signal line wires through which high current flows close to the crystal oscillator circuit. - Keep the grounding point of the capacitors in the oscillator circuit at the potential equal to GND. And do not connect the capacitors to the GND or GND lines through which high current flows. - Do not output signals from the oscillator circuit. The circuit is subject to change according to the specific LSI board design. Please contact Oki Electric Industry Co., Ltd. for detailed information. It is recommended to determine the final circuit values including the capacitance of the circuit board designed by the user. 21/30 FEDL7055-02 OKI Semiconductor ML7055 APPLICATION NOTES Clock Selection • The system clock frequency is selected according to external pin SFRQSEL. SFRQSEL = 0 : SFRQSEL = 1 : A 13 MHz clock is input to external pins SCLKP. A 12 MHz clock is input to external pins SCLKP. • The CPU clock supply source is selected according to external pin SCLKSEL. SCLKSEL = 0 : SCLKSEL = 1 : Use the clock that was divided down from the internal PLL output of 192 MHz that was generated from external pins SCLKP. (Dividing ratios are selectable in the range of 1/6 to 1/16. Initial value is 1/8 (24 MHz).) Use external pins XC32KP. Note: The clock supply source can be set by the CLKCNTL register in the CTL/WDT block once the LSI is powered up. • The frequency of CPU clock is selectable from the high speed (24 MHz) and low speed (16 MHz). This can be performed by the Vendor Specific Command. Setting the Reset • Apply a “L” level to the RESET pin for more than 10 µs after power voltage is stabilized. When the system clock oscillator circuit is stable and the RESET pin is at a “H” level, the internal reset is released and operation starts after the internal reset is held for 1.9 ms for the input clock of 13 MHz or 2.0 ms for the input clock of 12 MHz. Setting the UART Baud Rate • It is possible to set the UART baud rate using the Vendor Specific Commands. Available baud rate settings: 9600/19.2k/38.4k/56k/57.6k/115.2k/230.4k/345.6k/460.8k/921.6k (Initial value is 115.2 kbps.) Setting the PCM-CVSD Transcoder • It is possible to set the PCM-CVSD transcoders using the Vendor Specific Commands. For command details, contact Oki Electric Industry Co., Ltd. • It is possible to set the following parameters using the VCCTL command: - PCMSYNC/PCMCLK mode (initial setting: input) - Mute reception (initial setting: OFF) - Mute transmission (initial setting: OFF) - Air coding CVSD (initial setting)/µ-law/A-law - Interface coding Linear (initial setting)/µ-law/A-law - PCM format (data width of one PCM Linear sample) 8-bit (initial setting)/14-bit/16-bit - Serial interface format Short frame (initial setting)/long frame 22/30 FEDL7055-02 OKI Semiconductor ML7055 - Application interface mode PCM Codec I/F (initial setting)/APB I/F XTAL Input Frequency of BCM2002X • If the system clock is supplied from BCM2002X, the XTAL input frequency of BCM2002X must be 13 MHz. 12, 19.2, 19.68, or 19.8 MHz should not be applied. XTAL Input Frequency of CX72303 • If the system clock is supplied from CX72303, the XTAL input frequency of CX72303 must be 13 MHz. 10 MHz should not be applied. Required processes when interface pins are unused • The following tables show the processes that should be performed when interface pins are not used. • The pins that are not included in the following table should be left open. RF I/F Pin Name Process When Pin Not Used RXD GND RSSI Open or GND PLLLOCK Open or GND Comments UART I/F Pin Name Process When Pin Not Used SIN VDD CTS GND Comments PCM I/F Pin Name Process When Pin Not Used PCMIN Open or VDD PCMSYNC Open or GND PCMCLK Open or GND Comments Processes of Other Pins TEST I/F etc. Pin Name Process When Pin Not Used DETACH Pull up or VDD Comments 23/30 RESET RFVDD VDD ML7055 LVDD 0.1 µ 47 µ ML7050 ANT VDD_D 0.1 µ 68kΩ Poewr on reset Hardware reset PCMIN PCMOUT RSYNC XSYNC BCLK Microphone Voice input/ output peripherals Speaker PCMOUT PCMIN PCMSYNC PCMCLK MSM7702-01 GND RXD PLL_LE PLL_DATA PLL_CLK PLL_OFF TXD PLL_POW RX_POW TX_POW RSSI RSSI_CLK PLL_PS PLLLOCK RXD PLL_LE PLL_DATA PLL_CLK PLL_OFF TXD PLL_POW RX_POW TX_POW OKI Semiconductor System Configuration Example ML7055/ML7050 VDD MCLK CLKOUT SCLKN SCLKSEL SFRQSEL VDD RFSEL2 RFSEL1 RFSEL0 VDD 68kΩ GND DETACH AVDD0 0.1 µ AGND0 Separate, as far as possible, the wiring from the board pins. 13MHz ± 20ppm SCLKP GND XC32KN XC32KP 32kHz or 32.768kHz ± 250ppm GND SOUT RTS SIN CTS T1IN T1OUT T2IN T2OUT T3IN R1OUT R1IN R2OUT R2IN AVDD1 0.1 µ AGND1 GND CoreVDD UART I/F TD RTS 1 2 3 4 5 6 7 8 9 RD CTS MAX3245 DSUB9PIN GND VDD CoreVDD VDD GND 0.1 µ 0.1 µ 47 µ 0.1 µ 0.1 µ 47 µ The capacitors should be as close to the LSI pins as possible. VDD GND 47kΩ VDD SDA SDA GND SCL SCL NC Vcc GND AT24C02 GND FEDL7055-02 ML7055 24/30 FEDL7055-02 OKI Semiconductor ML7055 PACKAGE DIMENSIONS ML7055HB - 63pinWCSP (P-VFLGA63-4.90 × 4.72-0.50-W) (Unit: mm) P-VFLGA63-4.90×4.72-0.50-W 5 Package material Terminal material Package weight (g) Rev. No./Last Revised Epoxy resin Sn/Pb 0.03 TYP. 1/May 27, 2002 Note: A lead-free package is available. Please contact Oki Sales Office/Distributors for more information. 25/30 FEDL7055-02 OKI Semiconductor ML7055 ML7055LA - 64pinBGA (P-TFBGA64-0707-0.65) (Unit: mm) P-TFBGA64-0707-0.65 5 Package material Ball material Package weight (g) Rev. No./Last Revised Epoxy resin Sn/Pb 0.10 TYP. 1/July 5, 2002 Note: A lead-free package is available. Please contact Oki Sales Office/Distributors for more information. 26/30 FEDL7055-02 OKI Semiconductor ML7055 ML7055LP - 84pinBGA (P-LFBGA84-0909-0.80) (Unit: mm) P-LFBGA84-0909-0.80 5 Package material Ball material Package weight (g) Rev. No./Last Revised Epoxy resin Sn/Pb 0.20 TYP. 1/May 15, 2000 Note: A lead-free package is available. Please contact Oki Sales Office/Distributors for more information. Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 27/30 FEDL7055-02 OKI Semiconductor ML7055 REVISION HISTORY Document No. PEDL7055-01 Date Aug.23, 2002 Page Previous Current Edition Edition Description –- –- Preliminary edition 1 1 1 The contents of the “FEATURES” Section have been fully changed. –- 2 Added the “SPECIFICATIONS” Section. 2 3 3 4 5 6 The contents of the table in the “ABSOLUTE MAXIMUM RATINGS” Section have been partially changed. The voltage values of “Core VDD” have been added on the table in the “DC Characteristics” Section. The pin name has been changed from LPO_CLK to TCK. Eliminated the “LPO_CLK” row in the table of the “RF/IF” Section. Eliminated “Note” on the bottom side of the table of the “RF/IF” Section. PEDL7055-02 FEDL7055-01 6 7 The “Description” column of Pin name “TCK” in the table of the “JTAG I/F” Section has been partially changed. 8 9 Added “REFERENCE CIRCUIT” Section. 11 13 “DETACH signal” has been changed to “DETECH signal” in the content of the “DETACH Interface Block” Section. 12 14 Eliminated the “RESET signal input” Section and added the “Setting the Reset” Section. –- 15 The “XTAL Input Frequency of BCM2002X” and “XTAL Input Frequency of CX72303” Sections have been added. 13 15 Eliminated the “LPO_CLK” row of the “Pin name” column in the table of the “RF/IF” Section.. 14-16 16-18 1 1 2 2 13 13 13 14 Nov. 25, 2002 Dec. 17, 2002 FOR OSCILLATOR Changed the System Configuration Examples. Partially changed the contents of “FEATURES” Section. Changed the contents of “Package” row in the table. Partially added the contents of “UART Block” Section. Partially added the contents of “PCM-CVSD” Section. 28/30 FEDL7055-02 OKI Semiconductor Document No. FEDL7055-01 FEDL7055-02 ML7055 Date Page Previous Current Edition Edition Description 13 15 Partially eliminated the contents of “DETACH Interface Block” Section. –- 17-19 Added “Power Supply Current Characteristics by Power Saving Mode” and “AC Characteristics” Sections. 9 19 Partially added the contents of “REFERENCE FOR VOLTAGE SUPPLY CIRCUIT” Section. 10 20 Partially added the contents of “REFERENCE FOR OSCILLATOR CIRCUIT” Section. 14 22 Partially added the contents of “Clock Selection” Section. 16 24 Partially changed the contents of “System Configuration Example” Section. 6 6 Partially added the contents of “RF I/F” Section. 16 16 Partially added the Characteristics” Section. 18 18 Partially eliminated the contents of “Reset” Section. 23 23 Eliminated the “RESET” row in the table of the “TEST I/F ” Section. Dec. 17, 2002 contents of “DC Apr. 8, 2003 29/30 FEDL7055-02 OKI Semiconductor ML7055 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2003 Oki Electric Industry Co., Ltd. 30/30