TECHNICAL DATA SL74LV244 OCTAL BUFFER/LINE DRIVE; 3-STATE The SL74LV244 is a low-voltage Si-gate CMOS device and is pin and function compatible with SL74HC/HCT244. The SL74LV244 is an octal non-inverting buffer/line driver with 3state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH on nOE causes the outputs to assume a high impedance OFF-state. The SL74LV244 is identical to the SL74LV240 but has non-inverting outputs. • • • • • N SUFFIX PLASTIC DIP 20 1 DW SUFFIX SO 20 1 Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 1.2 to 3.6 V Low Input Current: 1.0 µA, 0.1 µÀ at Ò = 25 °Ñ Output Current: 8 mA at VCC = 3.0 V High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION SL74LV244N SL74LV244DW Plastic DIP SOIC TA = -40° to 125° C for all packages LOGIC DIAGRAM PIN ASSIGNMENT 1A0 1A1 1A2 1A3 DATA INPUTS 2A0 2A1 OUTPUT ENABLES 2 18 1Y0 4 16 1Y1 6 14 1Y2 8 12 11 9 2Y0 13 7 2Y1 1Y3 2A0 15 5 2Y0 2A1 17 3 2Y1 1OE 2OE NONINVERTING OUTPUTS 1OE 1 20 VCC 1A0 2 19 2OE 2Y3 3 18 1Y 0 1A1 4 17 2A 3 2Y2 5 16 1Y 1 1A2 6 15 2A2 2Y1 7 14 1Y 2 1A3 8 13 2A 1 2Y0 9 12 1Y 3 10 11 2A 0 GND FUNCTION TABLE 1 19 Input PIN 20=VCC PIN 10 = GND Output nOE nAn nYn L L L L H H H X Z H= high level L = low level X = don’t care Z = high impedance SLS System Logic Semiconductor 1 SL74LV244 MAXIMUM RATINGS * Symbol VCC IIK * Value Unit -0.5 to +5.0 V DC Input diode current ±20 mA DC Output diode current ±50 mA DC Output source or sink current ±35 mA DC VCC current ±70 mA ±70 mA DC supply voltage 1 IOK * 2 IO * Parameter 3 ICC IGND DC GND current PD Power dissipation per package: * Plastic DIP SO Tstg 4 mW 750 500 Storage Temperature TL -65 to +150 °C 260 °C Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO Package) from Case for 4 Seconds * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. * 1 VI < -0.5 V or VI > VCC + 0.5 V. * 2 VO < -0.5 V or VO > VCC + 0.5 V. * 3 -0.5 V < VO < VCC + 0.5 V. * 4 Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C SO Package: : - 8 mW/°C from 70° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit 1.2 3.6 V VCC DC Supply Voltage VI Input Voltage 0 VCC V VO Output Voltage 0 VCC V TA Operating Temperature, All Package Types -40 +125 °C tr, t f Input Rise and Fall Time (Figure 1) 0 0 0 0 1000 700 500 400 ns VCC =1.2 V VCC =2.0 V VCC =3.0 V VCC =3.6 V This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. SLS System Logic Semiconductor 2 SL74LV244 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Test VCC conditions V Guaranteed Limit 25°C -40°C to 85°C 125°C Unit min max min max min max VIH HIGH level input voltage 1.2 2.0 3.0 3.6 0.9 1.4 2.1 2.5 - 0.9 1.4 2.1 2.5 - 0.9 1.4 2.1 2.5 - V VIL LOW level input voltage 1.2 2.0 3.0 3.6 - 0.3 0.6 0.9 1.1 - 0.3 0.6 0.9 1.1 - 0.3 0.6 0.9 1.1 V VOH HIGH level output voltage VI = VIH or VIL IO = -50 µÀ 1.2 2.0 3.0 3.6 1.1 1.92 2.92 3.52 - 1.0 1.9 2.9 3.5 - 1.0 1.9 2.9 3.5 - V VI = VIH or VIL IO = -8 mÀ 3.0 2.48 - 2.34 - 2.20 - V VI = VIH or VIL IO = 50 µÀ 1.2 2.0 3.0 3.6 - 0.09 0.09 0.09 0.09 - 0.1 0.1 0.1 0.1 - 0.1 0.1 0.1 0.1 V VI = VIH or VIL IO = 8 mÀ 3.0 - 0.33 - 0.4 - 0.5 V VI = VCC or 0 V * - ±0.1 - ±1.0 - ±1.0 µÀ 1.2 * - ±0.5 - ±5 - ±10 µÀ * - 8.0 - 80 - 160 µÀ VOL II LOW level output voltage Input current IOZ Three state leakage 3-state outputs current VI (01,19) = VIH VO =VCC or 0 V ICC Supply current VI =VCC or 0 V IO = 0 µÀ * VCC = 3.3 ± 0.3 V SLS System Logic Semiconductor 3 SL74LV244 AC ELECTRICAL CHARACTERISTICS (CL=50 pF, t r=t f=6.0 ns) Symbol Parameter tPHL, tPLH Propagation delay , 1An to 1Yn, 2An to 2Yn Test VCC conditions V Guaranteed Limit 25°C -40°C to 85°C 125°C min max min max min max Unit VI = 0 V or VCC Figure 1 and 3 1.2 2.0 * - 100 24 15 - 125 30 19 - 150 36 23 ns tPHZ tPLZ Propagation delay, 1OE to VI = 0 V or VCC 1Yn, 2OE to 2Yn Figure 2 and 4 1.2 2.0 * - 140 30 20 - 175 35 24 - 210 41 28 ns tPZH tPZL Propagation delay, 1OE to VI = 0 V or VCC 1Yn, 2OE to 2Yn Figure 2 and 4 1.2 2.0 * - 140 32 20 - 175 40 25 - 210 48 30 ns 1.2 2.0 * - 60 16 10 - 75 20 13 - 90 24 15 ns 3.0 - 7.0 - 7.0 - 7.0 pF - 50 - - - - pF tTHL, tTLH Output Transition Time, Any Output CI VI = 0 V or VCC Figure 1 and 3 Input capacitance CPD Power dissipation capacitance (per one channel) VI = 0 V or VCC * VCC = 3.3 ± 0.3 V tr 1Anor 2An 10% VCC tf VCC 90% 50% GND t PZL t PLZ GND tPLH tPHL 1Yn or 2Yn 50% 1OE or 2OE 50% 10% 90% VCC 50% 1Ynor 2Y n t PZH tTLH tTHL VOL t PHZ VOH 1Ynor 2Y n 50% GND Figure 1. Switching Waveforms Figure 2. Switching Waveforms TEST POINT TEST POINT Connect to V C C when DEVICE OUTPUT DEVICE UNDER TEST CL * OUTPUT 1 k UNDER TEST testing tP LZ and tP Z L Connect to GND when * CL testing tP HZ and tP Z H * Includes all probe and jig capacitance * Includes all probe and jig capacitance Figure 3. Test Circuit Figure 4. Test Circuit SLS System Logic Semiconductor 4