LM20154 www.ti.com SNVS531G – OCTOBER 2007 – REVISED MARCH 2013 LM20154/LM20154-Q1 4A, 1MHz Synchronous Buck Regulator with SYNCOUT Check for Samples: LM20154 FEATURES DESCRIPTION • The LM20154 is a full featured 1 MHz synchronous buck regulator capable of delivering up to 4A of continuous output current. The current mode control loop can be compensated to be stable with virtually any type of output capacitor. For most cases, compensating the device only requires two external components, providing maximum flexibility and ease of use. The device is optimized to work over the input voltage range of 2.95V to 5.5V making it suited for a wide variety of low voltage systems. 1 2 • • • • • • • • • • • • • LM20154-Q1 is AEC-Q100 Qualified and Manufactured on an Automotive Grade Flow Input Voltage Range 2.95V to 5.5V Accurate Current Limit Minimizes Inductor Size 96% Peak Efficiency at 1.0 MHz Switching Frequency Frequency Synchronization Output 32 mΩ Integrated FET Switches Starts up into Pre-Biased Loads Output Voltage Tracking Peak Current Mode Control Adjustable Output Voltage Down to 0.8V Adjustable Soft-Start with External Capacitor Precision Enable Pin with Hysteresis Integrated OVP, UVLO, Power Good and Thermal Shutdown HTSSOP Exposed Pad Package The device features internal over voltage protection (OVP) and over current protection (OCP) circuits for increased system reliability. A precision enable pin and integrated UVLO allows the turn on of the device to be tightly controlled and sequenced. Start-up inrush currents are limited by both an internally fixed and externally adjustable Soft-Start circuit. Fault detection and supply sequencing is possible with the integrated power good circuit. The LM20154 features an open drain SYNCOUT pin which provides an external clock that matches the switching frequency of the device but is shifted by 180 degrees. APPLICATIONS • • • The LM20154 is designed to work well in multi-rail power supply architectures. The output voltage of the device can be configured to track a higher voltage rail using the SS/TRK pin. If the output of the LM20154 is pre-biased at startup it will not sink current to pull the output low until the internal soft-start ramp exceeds the voltage at the feedback pin. Simple to Design, High Efficiency Point of Load Regulation from a 5V or 3.3V Bus High Performance DSPs, FPGAs, ASICs and Microprocessors Broadband, Networking and Optical Communications Infrastructure The LM20154 is offered in an exposed pad 16-pin HTSSOP package that can be soldered to the PCB, eliminating the need for bulky heatsinks. Typical Application Circuit L LM20154 PVIN VIN CIN RF RFB1 EN RS VOUT SW FB COUT AVIN RFB2 PGOOD CF SYNCOUT VCC COMP SYNCOUT RC1 CC1 SS/TRK PGND AGND CVCC CSS (optional) 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2013, Texas Instruments Incorporated LM20154 SNVS531G – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com Connection Diagram SS/TRK 1 16 SYNCOUT FB 2 15 AGND PGOOD 3 14 AVIN COMP 4 13 VCC NC 5 12 EN PVIN 6 11 PGND PVIN 7 10 PGND SW 8 9 EP SW Figure 1. Top View HTSSOP Package PIN DESCRIPTIONS 2 Pin # Name Description 1 SS/TRK Soft-Start or Tracking control input. An internal 5 µA current source charges an external capacitor to set the Soft-Start ramp rate. If driven by a external source less than 800 mV, this pin overrides the internal reference that sets the output voltage. If left open, an internal 1ms Soft-Start ramp is activated. 2 FB Feedback input to the error amplifier from the regulated output. This pin is connected to the inverting input of the internal transconductance error amplifier. An 800 mV reference connected to the non-inverting input of the error amplifier sets the closed loop regulation voltage at the FB pin. 3 PGOOD 4 COMP 5 NC 6,7 PVIN 8,9 SW 10,11 PGND 12 EN Power good output signal. Open drain output indicating the output voltage is regulating within tolerance. A pull-up resistor of 10 to 100 kΩ is recommend for most applications. External compensation pin. Connect a resistor and capacitor to this pin to compensate the device. These pins must be connected to GND to ensure proper operation. Input voltage to the power switches inside the device. These pins should be connected together at the device. A low ESR capacitor should be placed near these pins to stabilize the input voltage. Switch pin. The PWM output of the internal power switches. Power ground pin for the internal power switches. Precision enable input for the device. An external voltage divider can be used to set the device turn-on threshold. If not used the EN pin should be connected to PVIN. 13 VCC Internal 2.7V sub-regulator. This pin should be bypassed with a 1 µF ceramic capacitor. 14 AVIN Analog input supply that generates the internal bias. Must be connected to VIN through a low pass RC filter. 15 AGND Quiet analog ground for the internal bias circuitry. 16 SYNCOUT Frequency synchronization output. This NMOS open drain output provides a signal that has the same frequency as the internal oscillator, but is shifted by 180 degrees. EP Exposed Pad Exposed metal pad on the underside of the package with a weak electrical connection to ground. It is recommended to connect this pad to the PC board ground plane in order to improve heat dissipation. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20154 LM20154 www.ti.com SNVS531G – OCTOBER 2007 – REVISED MARCH 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) Voltages from the indicated pins to GND AVIN, PVIN, EN, PGOOD, SS/TRK, COMP, FB, SYNCOUT -0.3V to +6V Storage Temperature -65°C to 150°C Junction Temperature 150°C Power Dissipation (2) 2.6W Lead Temperature (Soldering, 10 sec) 260°C Minimum ESD Rating (3) (1) (2) (3) ±2kV Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The maximum allowable power dissipation is a function of the maximum junction temperature, TJ_MAX, the junctions-to-ambient thermal resistance, θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using: PD_MAX = (TJ_MAX – TA)/θJA. The maximum power dissipations of 2.6W is determined using TA = 25°C, θJA = 38°C/W, and TJ_MAX = 125°C. The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor to each pin. OPERATING RATINGS PVIN, AVIN to GND 2.95V to 5.5V −40°C to + 125°C Junction Temperature Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20154 3 LM20154 SNVS531G – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com ELECTRICAL CHARACTERISTICS Unless otherwise stated, the following conditions apply: AVIN = PVIN = VIN = 5V. Limits in standard type are for TJ = 25°C only, limits in bold face type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Symbol VFB ΔVOUT/ΔIOUT ICL Parameter Conditions Feedback pin voltage VIN = 2.95V to 5.5V Load Regulation IOUT = 100 mA to 4A Min Typ Max 0.788 0.8 0.812 0.08 5.4 Unit V %/A Switch Current Limit Threshold VIN = 3.3V 6.0 6.6 A RDS_ON High-Side Switch On Resistance ISW = 3.5A 36 55 mΩ RDS_ON Low-Side Switch On Resistance ISW = 3.5A 32 52 mΩ IQ Operating Quiescent Current Non-switching, VFB = VCOMP 3.5 6 mA ISD Shutdown Quiescent current VEN = 0V 90 180 µA VUVLO VIN Under Voltage Lockout Rising VIN 2.7 2.95 V VIN Under Voltage Lockout Hysteresis Falling VIN 45 100 mV VUVLO_HYS VVCC 2.45 VCC Voltage IVCC = 0 µA 2.45 2.7 2.95 V ISS Soft-Start Pin Source Current VSS/TRK = 0V 2 4.5 7 µA VTRACK SS/TRK Accuracy, VSS - VFB VSS/TRK = 0.4V -10 3 15 mV 850 1000 1150 kHz Oscillator FOSC Oscillator Frequency DCMAX Maximum Duty Cycle TON_TIME Minimum On Time TCL_BLANK Current Sense Blanking Time FSYNCOUT SYNCOUT Frequency PSYNCOUT ILOAD = 0A After Rising VSW 85 % 100 ns 80 850 SYNCOUT Phase Shift Relative to High-Side Turn-On IOLSYNC SYNCOUT Low Sink Current VSYNCOUT = 0.8V IOHSYNC SYNCOUT High Leakage Current VSYNCOUT = 5V 1000 ns 1150 kHz 1.8 2.4 mA 10 150 nA 1 100 nA 180 1.3 ° Error Amplifier and Modulator Feedback pin bias current VFB = 0.8V ICOMP_SRC IFB COMP Output Source Current VFB = VCOMP = 0.6V 80 100 µA ICOMP_SNK COMP Output Sink Current VFB = 1.0V, VCOMP = 0.6V 80 100 µA Error Amplifier Transconductance ICOMP = ± 50 µA 450 gm AVOL Error Amplifier Voltage Gain 510 600 2000 µmho V/V Power Good VOVP VOVP_HYS Over Voltage Protection Rising Threshold With respect to VFB 105 Over Voltage Protection Hysteresis With respect to VFB 111 % 2 3 % 94 96 % 3 VPGTH PGOOD Rising Threshold VPGHYS PGOOD Falling Hysteresis 2 TPGOOD PGOOD deglitch time 16 IOL PGOOD Low Sink Current VPGOOD = 0.4V IOH PGOOD High Leakage Current VPGOOD = 5V EN Pin Turn on Threshold VEN Rising 92 108 0.6 % µs 1 mA 5 100 1.18 1.28 nA Enable VIH_EN VEN_HYS 1.08 V EN Pin Hysteresis 66 mV Thermal Shutdown 160 °C Thermal Shutdown Hysteresis 10 °C Junction to Ambient 38 °C/W Thermal Shutdown TSD TSD_HYS Thermal Resistance θJA 4 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20154 LM20154 www.ti.com SNVS531G – OCTOBER 2007 – REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise specified: CIN = COUT = 100 µF, L = 1.0 µH (Coilcraft MSS1038), VIN = 5V, VOUT = 1.2V, RLOAD = 1.2Ω, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Efficiency vs. Load Current (VIN = 5V) Efficiency vs. Load Current (VIN = 3.3V) Figure 2. Figure 3. High-Side FET Resistance vs. Temperature Low-Side FET Resistance vs. Temperature Figure 4. Figure 5. Error Amplifier Gain vs. Frequency Line Regulation Figure 6. Figure 7. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20154 5 LM20154 SNVS531G – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: CIN = COUT = 100 µF, L = 1.0 µH (Coilcraft MSS1038), VIN = 5V, VOUT = 1.2V, RLOAD = 1.2Ω, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. 6 Load Regulation Feedback Pin Voltage vs. Temperature Figure 8. Figure 9. Switching Frequency vs. Temperature Synchronization Output Figure 10. Figure 11. Quiescent Current vs. VIN (Not Switching) Shutdown Current vs. Temperature Figure 12. Figure 13. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20154 LM20154 www.ti.com SNVS531G – OCTOBER 2007 – REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: CIN = COUT = 100 µF, L = 1.0 µH (Coilcraft MSS1038), VIN = 5V, VOUT = 1.2V, RLOAD = 1.2Ω, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Enable Threshold vs. Temperature UVLO Threshold vs. Temperature Figure 14. Figure 15. Peak Current Limit vs. Temperature Peak Current Limit vs. VOUT Figure 16. Figure 17. Peak Current Limit vs. VIN Load Transient Response Figure 18. Figure 19. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20154 7 LM20154 SNVS531G – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: CIN = COUT = 100 µF, L = 1.0 µH (Coilcraft MSS1038), VIN = 5V, VOUT = 1.2V, RLOAD = 1.2Ω, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. 8 Line Transient Response Start-Up (Soft-Start) Figure 20. Figure 21. Start-Up (Tracking) Power Down Figure 22. Figure 23. Short Circuit Input Current vs. VIN PGOOD vs. IPGOOD Figure 24. Figure 25. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20154 LM20154 www.ti.com SNVS531G – OCTOBER 2007 – REVISED MARCH 2013 BLOCK DIAGRAM +2.7V REGULATOR AVIN + - 2.7V VCC UVLO SLOPE COMP PVIN COMP 2.7V CURRENT SENSE + 5 PA DISCHARGE (50 Ps) SS/TRK ERROR AMP gm = 510 Pmho + + FB + - 6.0A VREF 800 mV DISCHARGE CURRENT LIMIT + - PVIN + PWM COMPARATOR 864 mV 752 mV + - OVERVOLTAGE + - UNDERVOLTAGE DIODE EMULATION PG-L CONTROL LOGIC THERMAL PROTECTION EN 1.18V + - SW PVIN + OSCILLATOR PGND SYNCOUT 180° PHASE SHIFT PG-L PGOOD AGND Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20154 9 LM20154 SNVS531G – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com OPERATION DESCRIPTION GENERAL The LM20154 switching regulator features all of the functions necessary to implement an efficient low voltage buck regulator using a minimum number of external components. This easy to use regulator features two integrated switches and is capable of supplying up to 4A of continuous output current. The regulator utilizes peak current mode control with nonlinear slope compensation to optimize stability and transient response over the entire output voltage range. Peak current mode control also provides inherent line feed-forward, cycle-by-cycle current limiting and easy loop compensation. The fixed 1 MHz operating frequency minimizes the inductor size while still achieving efficiencies up to 96%. The precision internal voltage reference allows the output to be set as low as 0.8V. Fault protection features include: current limiting, thermal shutdown, over voltage protection, and shutdown capability. The device is available in the HTSSOP package featuring an exposed pad to aid thermal dissipation. The LM20154 can be used in numerous applications to efficiently step-down from a 5V or 3.3V bus. The typical application circuit for the LM20154 is shown in Figure 27 in the design guide. PRECISION ENABLE The enable (EN) pin allows the output of the device to be enabled or disabled with an external control signal. This pin is a precision analog input that enables the device when the voltage exceeds 1.18V (typical). The EN pin has 66 mV of hysteresis and will disable the output when the enable voltage falls below 1.11V (typical). If the EN pin is not used, it should be connected to VIN. Since the enable pin has a precise turn on threshold it can be used along with an external resistor divider network from VIN to configure the device to turn on at a precise input voltage. The precision enable circuitry will remain active even when the device is disabled. CLOCK SYNCHRONIZATION OUTPUT The SYNCOUT pin is an open drain output that provides a signal that is the same frequency as the internal oscillator but is 180 degrees out of phase with the switch voltage. The SYNCOUT pin requires an external pull-up resistor to set the high level. For most applications a 2.94 kΩ pull-up connected to the input voltage should be sufficient. Since the SYNCOUT is out of phase with the switch voltage it can be used with other devices with a synchronization input such as the LM20134 to run multiple convertors out of phase. Running multiple converters out of phase reduces the RMS current requirements for the input capacitor, value of the input capacitor, and conducted EMI back through the input bus. PEAK CURRENT MODE CONTROL In most cases, the peak current mode control architecture used in the LM20154 only requires two external components to achieve a stable design. The compensation can be selected to accommodate any capacitor type or value. The external compensation also allows the user to set the crossover frequency and optimize the transient performance of the device. For duty cycles above 50% all current mode control buck converters require the addition of an artificial ramp to avoid sub-harmonic oscillation. This artificial linear ramp is commonly referred to as slope compensation. What makes the LM20154 unique is the amount of slope compensation will change depending on the output voltage. When operating at high output voltages the device will have more slope compensation than when operating at lower output voltages. This is accomplished in the LM20154 by using a non-linear parabolic ramp for the slope compensation. The parabolic slope compensation of the LM20154 is much better than the traditional linear slope compensation because it optimizes the stability of the device over the entire output voltage range. CURRENT LIMIT The precise current limit of the LM20154 is set at the factory to be within 10% over the entire operating temperature range. This enables the device to operate with smaller inductors that have lower saturation currents. When the peak inductor current reaches the current limit threshold, an over current event is triggered and the internal high-side FET turns off and the low-side FET turns on allowing the inductor current to ramp down until the next switching cycle. For each sequential over-current event, the reference voltage is decremented and PWM pulses are skipped resulting in a current limit that does not aggressively fold back for brief over-current events, while at the same time providing frequency and voltage foldback protection during hard short circuit conditions. 10 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20154 LM20154 www.ti.com SNVS531G – OCTOBER 2007 – REVISED MARCH 2013 SOFT-START AND VOLTAGE TRACKING The SS/TRK pin is a dual function pin that can be used to set the start up time or track an external voltage source. The start up or Soft-Start time can be adjusted by connecting a capacitor from the SS/TRK pin to ground. The Soft-Start feature allows the regulator output to gradually reach the steady state operating point, thus reducing stresses on the input supply and controlling start up current. If no Soft-Start capacitor is used the device defaults to the internal Soft-Start circuitry resulting in a start up time of approximately 1 ms. For applications that require a monotonic start up or utilize the PGOOD pin, an external Soft-Start capacitor is recommended. The SS/TRK pin can also be set to track an external voltage source. The tracking behavior can be adjusted by two external resistors connected to the SS/TRK pin as shown in Figure 32 in the design guide. PRE-BIAS START UP CAPABILITY The LM20154 is in a pre-biased state when the device starts up with an output voltage greater than zero. This often occurs in many multi-rail applications such as when powering an FPGA, ASIC, or DSP. In these applications the output can be pre-biased through parasitic conduction paths from one supply rail to another. Even though the LM20154 is a synchronous converter it will not pull the output low when a prebias condition exists. During start up the LM20154 will not sink current until the Soft-Start voltage exceeds the voltage on the FB pin. Since the device can not sink current it protects the load from damage that might otherwise occur if current is conducted through the parasitic paths of the load. POWER GOOD AND OVER VOLTAGE FAULT HANDLING The LM20154 has built in under and over voltage comparators that control the power switches. Whenever there is an excursion in output voltage above the set OVP threshold, the part will terminate the present on-pulse, turn on the low-side FET, and pull the PGOOD pin low. The low-side FET will remain on until either the FB voltage falls back into regulation or the zero cross detection is triggered which in turn tri-states the FETs. If the output reaches the UVP threshold the part will continue switching and the PGOOD pin will be asserted and go low. Typical values for the PGOOD resistor are on the order of 100 kΩ or less. To avoid false tripping during transient glitches the PGOOD pin has 16 µs of built in deglitch time to both rising and falling edges. UVLO The LM20154 has a built-in under-voltage lockout protection circuit that keeps the device from switching until the input voltage reaches 2.7V (typical). The UVLO threshold has 45 mV of hysteresis that keeps the device from responding to power-on glitches during start up. If desired the turn on point of the supply can be changed by using the precision enable pin and a resistor divider network connected to VIN as shown in Figure 31 in the design guide. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20154 11 LM20154 SNVS531G – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com THERMAL PROTECTION Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. When activated, typically at 160°C, the LM20154 tri-states the power FETs and resets soft start. After the junction cools to approximately 150°C, the part starts up using the normal start up routine. This feature is provided to prevent catastrophic failures from accidental device overheating. LIGHT LOAD OPERATION The LM20154 offers increased efficiency when operating at light loads. Whenever the load current is reduced to a point where the peak to peak inductor ripple current is greater than two times the load current, the part will enter the diode emulation mode preventing significant negative inductor current. The point at which this occurs is the critical conduction boundary and can be calculated by Equation 1: IBOUNDARY = (VIN ± VOUT) x D 2 x L x fSW (1) Several diagrams are shown in Figure 26 illustrating continuous conduction mode (CCM), discontinuous conduction mode, and the boundary condition. It can be seen that in diode emulation mode, whenever the inductor current reaches zero the SW node will become high impedance. Ringing will occur on this pin as a result of the LC tank circuit formed by the inductor and the parasitic capacitance at the node. If this ringing is of concern an additional RC snubber circuit can be added from the switch node to ground. At very light loads, usually below 100 mA, several pulses may be skipped in between switching cycles, effectively reducing the switching frequency and further improving light-load efficiency. 12 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20154 LM20154 SNVS531G – OCTOBER 2007 – REVISED MARCH 2013 Switchnode Voltage www.ti.com Continuous Conduction Mode (CCM) VIN Time (s) Inductor Current Continuous Conduction Mode (CCM) IAVERAGE Inductor Current Time (s) DCM - CCM Boundary IAVERAGE Switchnode Voltage Time (s) Discontinuous Conduction Mode (DCM) VIN Inductor Current Time (s) Discontinuous Conduction Mode (DCM) IPeak Time (s) Figure 26. Modes of Operation for LM20154 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20154 13 LM20154 SNVS531G – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com DESIGN GUIDE This section walks the designer through the steps necessary to select the external components to build a fully functional power supply. As with any DC-DC converter numerous trade-offs are possible to optimize the design for efficiency, size, or performance. These will be taken into account and highlighted throughout this discussion. To facilitate component selection discussions the circuit shown in Figure 27 below may be used as a reference. Unless otherwise indicated all formulas assume units of amps (A) for current, farads (F) for capacitance, henries (H) for inductance and volts (V) for voltages. L LM20154 VIN PVIN CIN SW VOUT EN RF AVIN RFB1 COUT FB VIN CF VIN RPG RS SYNCOUT COMP VSYNCOUT RC1 CC1 RFB2 PGOOD VCC SS/TRK PGND GND VPG CVCC CSS Figure 27. Typical Application Circuit The first equation to calculate for any buck converter is duty-cycle. Ignoring conduction losses associated with the FETs and parasitic resistances it can be approximated by Equation 2: D= VOUT VIN (2) INDUCTOR SELECTION (L) The inductor value is determined based on the operating frequency, load current, ripple current, and duty cycle. The inductor selected should have a saturation current rating greater than the peak current limit of the device. Keep in mind the specified current limit does not account for delay of the current limit comparator, therefore the current limit in the application may be higher than the specified value. To optimize the performance and prevent the device from entering current limit at maximum load, the inductance is typically selected such that the ripple current, ΔiL, is less than 30% of the rated output current. Figure 28, shown below illustrates the switch and inductor ripple current waveforms. Once the input voltage, output voltage, operating frequency, and desired ripple current are known, the minimum value for the inductor can be calculated by the formula shown below: LMIN = (VIN - VOUT) x D 'iL x fSW (3) VSW VIN Time IL IL AVG = IOUT 'IL Time Figure 28. Switch and Inductor Current Waveforms 14 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20154 LM20154 www.ti.com SNVS531G – OCTOBER 2007 – REVISED MARCH 2013 If needed, slightly smaller value inductors can be used, however, the peak inductor current, IOUT + ΔiL/2, should be kept below the peak current limit of the device. In general, the inductor ripple current, ΔiL, should be greater than 10% of the rated output current to provide adequate current sense information for the current mode control loop. If the ripple current in the inductor is too low, the control loop will not have sufficient current sense information and can be prone to instability. OUTPUT CAPACITOR SELECTION (COUT) The output capacitor, COUT, filters the inductor ripple current and provides a source of charge for transient load conditions. A wide range of output capacitors may be used with the LM20154 that provide excellent performance. The best performance is typically obtained using ceramic, SP, or OSCON type chemistries. Typical trade-offs are that the ceramic capacitor provides extremely low ESR to reduce the output ripple voltage and noise spikes, while the SP and OSCON capacitors provide a large bulk capacitance in a small volume for transient loading conditions. When selecting the value for the output capacitor the two performance characteristics to consider are the output voltage ripple and transient response. The output voltage ripple can be approximated by using the formula shown below. 'VOUT = 'iL x RESR + 1 8 x fSW x COUT (4) Where, ΔVOUT (V) is the amount of peak to peak voltage ripple at the power supply output, RESR (Ω) is the series resistance of the output capacitor, fSW(Hz) is the switching frequency, and COUT (F) is the output capacitance used in the design. The amount of output ripple that can be tolerated is application specific; however a general recommendation is to keep the output ripple less than 1% of the rated output voltage. Keep in mind ceramic capacitors are sometimes preferred because they have very low ESR; however, depending on package and voltage rating of the capacitor the value of the capacitance can drop significantly with applied voltage. The output capacitor selection will also affect the output voltage droop during a load transient. The peak droop on the output voltage during a load transient is dependent on many factors; however, an approximation of the transient droop ignoring loop bandwidth can be obtained using Equation 5. VDROOP = 'IOUTSTEP x RESR + L x 'IOUTSTEP2 COUT x (VIN - VOUT) (5) Where, COUT (F) is the minimum required output capacitance, L (H) is the value of the inductor, VDROOP (V) is the output voltage drop ignoring loop bandwidth considerations, ΔIOUTSTEP (A) is the load step change, RESR (Ω) is the output capacitor ESR, VIN (V) is the input voltage, and VOUT (V) is the set regulator output voltage. Both the tolerance and voltage coefficient of the capacitor needs to be examined when designing for a specific output ripple or transient drop target. INPUT CAPACITOR SELECTION (CIN) Good quality input capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current during the on-time. In general it is recommended to use a ceramic capacitor for the input as they provide both a low impedance and small footprint. One important note is to use a good dielectric for the ceramic capacitor such as X5R or X7R. These provide better over temperature performance and also minimize the DC voltage derating that occurs on Y5V capacitors. For most applications, a 22 µF, X5R, 6.3V input capacitor is sufficient; however, additional capacitance may be required if the connection to the input supply is far from the PVIN of the device. The input capacitor should be placed as close as possible PVIN and PGND pins of the device. Non-ceramic input capacitors should be selected for RMS current rating and minimum ripple voltage. A good approximation for the required ripple current rating is given by the relationship: IIN-RMS = IOUT D(1 - D) (6) As indicated by the RMS ripple current equation, highest requirement for RMS current rating occurs at 50% duty cycle. For this case, the RMS ripple current rating of the input capacitor should be greater than half the output current. For best performance, low ESR ceramic capacitors should be placed in parallel with higher capacitance capacitors to provide the best input filtering for the device. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20154 15 LM20154 SNVS531G – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com SETTING THE OUTPUT VOLTAGE (RFB1, RFB2) The resistors RFB1 and RFB2 are selected to set the output voltage for the device. Table 1, shown below, provides suggestions for RFB1 and RFB2 for common output voltages. Table 1. Suggested Values for RFB1 and RFB2 RFB1(kΩ) RFB2(kΩ) VOUT short open 0.8 4.99 10 1.2 8.87 10.2 1.5 12.7 10.2 1.8 21.5 10.2 2.5 31.6 10.2 3.3 If different output voltages are required, RFB2 should be selected to be between 4.99 kΩ to 49.9 kΩ and RFB1 can be calculated using Equation 7. RFB1 = VOUT 0.8 - 1 x RFB2 (7) LOOP COMPENSATION (RC1, CC1) The purpose of loop compensation is to meet static and dynamic performance requirements while maintaining adequate stability. Optimal loop compensation depends on the output capacitor, inductor, load, and the device itself. Table 2 gives values for the compensation network that will result in a stable system when using a 100 µF, 6.3V ceramic X5R output capacitor and 1 µH inductor. Table 2. Recommended Compensation for COUT = 100 µF and L = 1 µH 16 VIN VOUT CC1 (nF) RC1 (kΩ) 5.00 3.30 3.3 14.3 5.00 2.50 3.3 11 5.00 1.80 3.3 7.32 5.00 1.50 3.3 6.34 5.00 1.20 3.3 4.42 5.00 0.80 4.7 1.21 3.30 2.50 3.3 12.7 3.30 1.80 3.3 8.87 3.30 1.50 3.3 5.76 3.30 1.20 3.3 3.16 3.30 0.80 4.7 1.62 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20154 LM20154 www.ti.com SNVS531G – OCTOBER 2007 – REVISED MARCH 2013 Output Filter Pole, fP(FIL) AM 0 dB Output Filter Zero, fZ(FIL) Complex Double Pole, fP(MOD) Modulator and Output Filter Transfer Function If the desired solution differs from Table 2 the loop transfer function should be analyzed to optimize the loop compensation. The overall loop transfer function is the product of the power stage and the feedback network transfer functions. For stability purposes, the objective is to have a loop gain slope that is -20db/decade from a very low frequency to beyond the crossover frequency. Figure 29, shown below, shows the transfer functions for power stage, feedback/compensation network, and the resulting closed loop system for the LM20154. Pole, fP2(EA) 0 dB Error Amp Zero, fZ(EA) AEA + AM Error Amp Pole, fP(EA) 0 dB Complex Double Pole, fP(MOD) fC Error Amplifier Transfer Function Optional Error Amp Compensated Closed Loop Transfer Function GAIN (dB) Error Amp Pole, fP1(EA) AEA fSW/2 FREQUENCY (Hz) Figure 29. LM20154 Loop Compensation The power stage transfer function is dictated by the modulator, output LC filter, and load; while the feedback transfer function is set by the feedback resistor ratio, error amp gain, and external compensation network. To achieve a -20dB/decade slope, the error amplifier zero, located at fZ(EA), should positioned to cancel the output filter pole (fP(FIL)). An additional error amp pole, located at fP2(EA), can be added to cancel the output filter zero at fZ(FIL). Cancellation of the output filter zero is recommended if larger value, non-ceramic output capacitors are used. Compensation of the LM20154 is achieved by adding an RC network as shown in Figure 30 below. LM20154 COMP RC1 CC2 (optional) CC1 Figure 30. Compensation Network for LM20154 A good starting value for CC1 for most applications is 4.7 nF. Once the value of CC1 is chosen the value of RC should be calculated using Equation 8 to cancel the output filter pole (fP(FIL)) as shown in Figure 29. 18 x D CC1 IOUT 1-D x + + RC1 = VIN f x L COUT VOUT SW -1 (8) Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20154 17 LM20154 SNVS531G – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com A higher crossover frequency can be obtained, usually at the expense of phase margin, by lowering the value of CC1 and recalculating the value of RC1. Likewise, increasing CC1 and recalculating RC1 will provide additional phase margin at a lower crossover frequency. As with any attempt to compensate the LM20154 the stability of the system should be verified for desired transient droop and settling time. If the output filter zero, fZ(FIL) approaches the crossover frequency (FC), an additional capacitor (CC2) should be placed at the COMP pin to ground. This capacitor adds a pole to cancel the output filter zero assuring the crossover frequency will occur before the double pole at fSW/2 degrades the phase margin. The output filter zero is set by the output capacitor value and ESR as shown in Equation 9. fZ(FIL) = 1 2 x S x COUT x RESR (9) If needed, the value for CC2 should be calculated using Equation 10. CC2 = COUT x RESR RC1 (10) Where RESR is the output capacitor series resistance and RC1 is the calculated compensation resistance. AVIN FILTERING COMPONENTS (CF and RF) To prevent high frequency noise spikes from disturbing the sensitive analog circuitry connected to the AVIN and AGND pins, a high frequency RC filter is required between PVIN and AVIN. These components are shown in Figure 27 as CF and RF. The required value for RF is 1Ω. CF must be used. Recommended value of CF is 1.0 µF. The filter capacitor, CF should be placed as close to the IC as possible with a direct connection from AVIN to AGND. A good quality X5R or X7R ceramic capacitor should be used for CF. SUB-REGULATOR BYPASS CAPACITOR (CVCC) The capacitor at the VCC pin provides noise filtering and stability for the internal sub-regulator. The recommended value of CVCC should be no smaller than 1 µF and no greater than 10 µF. The capacitor should be a good quality ceramic X5R or X7R capacitor. In general, a 1 µF ceramic capacitor is recommended for most applications. SETTING THE START UP TIME (CSS) The addition of a capacitor connected from the SS pin to ground sets the time at which the output voltage will reach the final regulated value. Larger values for CSS will result in longer start up times. Table 3, shown below provides a list of soft start capacitors and the corresponding typical start up times. Table 3. Start Up Times for Different Soft-Start Capacitors Start Up Time (ms) CSS (nF) 1 none 5 33 10 68 15 100 20 120 If different start up times are needed Equation 11 can be used to calculate the start up time. 0.8V x CSS tSS = ISS (11) As shown above, the start up time is influenced by the value of the Soft-Start capacitor CSS(F) and the 5 µA SoftStart pin current ISS(A). that may be found in the Electrical Characteristics table. 18 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20154 LM20154 www.ti.com SNVS531G – OCTOBER 2007 – REVISED MARCH 2013 While the Soft-Start capacitor can be sized to meet many start up requirements, there are limitations to its size. The Soft-Start time can never be faster than 1ms due to the internal default 1 ms start up time. When the device is enabled there is an approximate time interval of 50 µs when the Soft-Start capacitor will be discharged just prior to the Soft-Start ramp. If the enable pin is rapidly pulsed or the Soft-Start capacitor is large there may not be enough time for CSS to completely discharge resulting in start up times less than predicted. To aid in discharging of Soft-Start capacitor during long disable periods an external 1 MΩ resistor from SS/TRK to ground can be used without greatly affecting the start-up time. SYNCOUT PULL UP RESISTANCE (RS) In applications where timing is critical, the value of RS should be selected to be as small as possible to avoid timing delays due to parasitic capacitive loading. In this case, the size of the resistor should be selected based on the desired pull down voltage and minimum rated pull down current. The SYNCOUT pin is specified to pull down to 0.8V while sinking at least 1.3 mA of current, which equates to an on resistance of approximately 615Ω. To insure a specific logic low level is met the pull-up resistor should be selected using the formula below. RS = (VPULLUP ± VOL) x 615: VOL (12) Where, VPULLUP is the high pull up voltage for the resistor RS and VOL is the logic low level needed on the SYNCOUT pin. For most applications the SYNCOUT pin will be pulled up to the input voltage. USING PRECISION ENABLE AND POWER GOOD The precision enable (EN) and power good (PGOOD) pins of the LM20154 can be used to address many sequencing requirements. The turn-on of the LM20154 can be controlled with the precision enable pin by using two external resistors as shown in Figure 31 External Power Supply VOUT1 RA LM20154 VOUT2 EN RB Figure 31. Sequencing LM20154 with Precision Enable The value for resistor RB can be selected by the user to control the current through the divider. Typically this resistor will be selected to be between 10 kΩ and 1 MΩ. Once the value for RB is chosen the resistor RA can be solved using Equation 13 to set the desired turn on voltage. RA = VTO VIH_EN - 1 x RB (13) When designing for a specific turn-on threshold (VTO) the tolerance on the input supply, enable threshold (VIH_EN), and external resistors needs to be considered to insure proper turn on of the device. The LM20154 features an open drain power good (PGOOD) pin to sequence external supplies or loads and to provide fault detection. This pin requires an external resistor (RPG) to pull PGOOD high while when the output is within the PGOOD tolerance window. Typical values for this resistor range from 10 kΩ to 100 kΩ. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20154 19 LM20154 SNVS531G – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com TRACKING AN EXTERNAL SUPPLY By using a properly chosen resistor divider network connected to the SS/TRK pin, as shown in Figure 32, the output of the LM20154 can be configured to track an external voltage source to obtain a simultaneous or ratiometric start up. External Power Supply VOUT1 LM20154 R1 EN VOUT2 SS/TRK R2 Figure 32. Tracking an External Supply Since the Soft-Start charging current ISS is always present on the SS/TRK pin, the size of R2 should be less than 10 kΩ to minimize the errors in the tracking output. Once a value for R2 is selected the value for R1 can be calculated using appropriate equation in Figure 33, to give the desired start up. Figure 33 shows two common start up sequences; the top waveform shows a simultaneous start up while the waveform at the bottom illustrates a ratiometric start up. SIMULTANEOUS START UP VOLTAGE VOUT1 VOUT2 §VOUT2 · -1¸¸ x R2 R1 = ¨¨ © 0.8V ¹ VEN VOUT2 < 0.8 x VOUT1 TIME RATIOMETRIC START UP VOUT1 VOLTAGE VOUT2 R1 = ( VOUT1 -1) x R2 VEN TIME Figure 33. Common Start Up Sequences 20 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20154 LM20154 www.ti.com SNVS531G – OCTOBER 2007 – REVISED MARCH 2013 A simultaneous start up is preferred when powering most FPGAs, DSPs, or other microprocessors. In these systems the higher voltage, VOUT1, usually powers the I/O, and the lower voltage, VOUT2, powers the core. A simultaneous start up provides a more robust power up for these applications since it avoids turning on any parasitic conduction paths that may exist between the core and the I/O pins of the processor. The second most common power on behavior is known as a ratiometric start up. This start up is preferred in applications where both supplies need to be at the final value at the same time. Similar to the Soft-Start function, the fastest start up possible is 1 ms regardless of the rise time of the tracking voltage. When using the track feature the final voltage seen by the SS/TRACK pin should exceed 1V to provide sufficient overdrive and transient immunity. THERMAL CONSIDERATIONS The thermal characteristics of the LM20154 are specified using the parameter θJA, which relates the junction temperature to the ambient temperature. Although the value of θJA is dependant on many variables, it still can be used to approximate the operating junction temperature of the device. To obtain an estimate of the device junction temperature, one may use the following relationship: TJ = PDθJA + TA (14) PD = PIN x (1 - Efficiency) - 1.1 x IOUT2 x DCR (15) and Where: TJ is the junction temperature in °C. PIN is the input power in Watts (PIN = VIN x IIN). θJA is the junction to ambient thermal resistance for the LM20154. TA is the ambient temperature in °C. IOUT is the output load current. DCR is the inductor series resistance. It is important to always keep the operating junction temperature (TJ) below 125°C for reliable operation. If the junction temperature exceeds 160°C the device will cycle in and out of thermal shutdown. If thermal shutdown occurs it is a sign of inadequate heatsinking or excessive power dissipation in the device. Figure 34, shown below, provides a better approximation of the θJA for a given PCB copper area. The PCB heatsink area consists of 2oz. copper located on the bottom layer of the PCB directly under the HTSSOP exposed pad. The bottom copper area is connected to the HTSSOP exposed pad by means of a 4 x 4 array of 12 mil thermal vias. Figure 34. Thermal Resistance vs PCB Area Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20154 21 LM20154 SNVS531G – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com PCB LAYOUT CONSIDERATIONS PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability. Good layout can be implemented by following a few simple design rules. 1. Minimize area of switched current loops. In a buck regulator there are two loops where currents are switched very fast. The first loop starts from the input capacitor, to the regulator VIN pin, to the regulator SW pin, to the inductor then out to the output capacitor and load. The second loop starts from the output capacitor ground, to the regulator PGND pins, to the inductor and then out to the load (see Figure 35). To minimize both loop areas the input capacitor should be placed as close as possible to the PVIN pin. Grounding for both the input and output capacitor should consist of a small localized top side plane that connects to PGND and the die attach pad (DAP). The inductor should be placed as close as possible to the SW pin and output capacitor. 2. Minimize the copper area of the switch node. Since the LM20154 has the SW pins on opposite sides of the package it is recommended to via these pins down to the bottom or internal layer with 2 to 4 vias on each SW pin. The SW pins should be directly connected with a trace that runs across the bottom of the package. To minimize IR losses this trace should be no smaller that 50 mils wide, but no larger than 100 mils wide to keep the copper area to a minimum. In general the SW pins should not be connected on the top layer since it could block the ground return path for the power ground. The inductor should be placed as close as possible to one of the SW pins to further minimize the copper area of the switch node. 3. Have a single point ground for all device analog grounds located under the DAP. The ground connections for the compensation, feedback, and Soft-Start components should be connected together then routed to the AGND pin of the device. The AGND pin should connect to PGND under the DAP. This prevents any switched or load currents from flowing in the analog ground plane. If not properly handled poor grounding can result in degraded load regulation or erratic switching behavior. 4. Minimize trace length to the FB pin. Since the feedback node can be high impedance the trace from the output resistor divider to FB pin should be as short as possible. This is most important when high value resistors are used to set the output voltage. The feedback trace should be routed away from the SW pin and inductor to avoid contaminating the feedback signal with switch noise. 5. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or output of the converter and can improve efficiency. If voltage accuracy at the load is important make sure feedback voltage sense is made at the load. Doing so will correct for voltage drops at the load and provide the best output accuracy. 6. Provide adequate device heatsinking. Use as many vias as is possible to connect the DAP to the power plane heatsink. For best results use a 4x4 via array with a minimum via diameter of 12 mils. See the Thermal Considerations section to insure enough copper heatsinking area is used to keep the junction temperature below 125°C. LM20154 PVIN L SW VOUT CIN COUT PGND LOOP1 LOOP2 Figure 35. Schematic of LM20154 Highlighting Layout Sensitive Nodes 22 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20154 LM20154 www.ti.com SNVS531G – OCTOBER 2007 – REVISED MARCH 2013 Typical Application Circuits This section provides several application solutions with a bill of materials. All bill of materials reference Figure 36. The compensation for these solutions were optimized to work over a wide range of input and output voltages; if a faster transient response is needed reduce the value of CC1 and calculate the new value for RC1 as outline in the design guide. L LM20154 CIN RF RFB1 EN RS VOUT SW PVIN VIN FB COUT AVIN RFB2 PGOOD CF SYNCOUT VCC COMP SYNCOUT RC1 SS/TRK PGND AGND CC1 CVCC CSS (optional) Figure 36. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20154 23 LM20154 SNVS531G – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com Bill of Materials (VIN = 5V, VOUT = 3.3V, IOUTMAX = 4A) Designator Description Part Number Manufacturer Qty U1 Synchronous Buck Regulator LM20154 Texas Instruments 1 CIN 100 µF, 1210, X5R, 6.3V GRM32ER60J107ME20 Murata 1 COUT 100 µF, 1210, X5R, 6.3V GRM32ER60J107ME20 Murata 1 L 1 µH, 6 mΩ MSS1038-102NL Coilcraft 1 RF 1Ω, 0603 CRCW06031R0J-e3 Vishay-Dale 1 CF 100 nF, 0603, X7R, 16V GRM188R71C104KA01 Murata 1 CVCC 1 µF, 0603, X5R, 6.3V GRM188R60J105KA01 Murata 1 RC1 7.87 kΩ, 0603 CRCW06037871F-e3 Vishay-Dale 1 CC1 2.2 nF, 0603, X7R, 25V VJ0603Y242KXXA Vishay-Vitramon 1 CSS 33 nF, 0603, X7R, 25V VJ0603Y333KXXA Vishay-Vitramon 1 RFB1 31.6 kΩ, 0603 CRCW06033162F-e3 Vishay-Dale 1 RFB2 10.2 kΩ, 0603 CRCW06031022F-e3 Vishay-Dale 1 RS 3.24 kΩ, 0603 CRCW06033241F-e3 Vishay-Dale 1 Bill of Materials (VIN = 3.3V to 5V, VOUT = 1.2V, IOUTMAX = 4A) 24 Designator Description Part Number Manufacturer Qty U1 Synchronous Buck Regulator LM20154 Texas Instruments 1 CIN 100 µF, 1210, X5R, 6.3V GRM32ER60J107ME20 Murata 1 COUT 100 µF, 1210, X5R, 6.3V GRM32ER60J107ME20 Murata 1 L 1 µH, 6 mΩ MSS1038-102NL Coilcraft 1 RF 1Ω, 0603 CRCW06031R0J-e3 Vishay-Dale 1 CF 100 nF, 0603, X7R, 16V GRM188R71C104KA01 Murata 1 CVCC 1 µF, 0603, X5R, 6.3V GRM188R60J105KA01 Murata 1 RC1 3.57 kΩ, 0603 CRCW06033571F-e3 Vishay-Dale 1 CC1 3.3 nF, 0603, X7R, 25V VJ0603Y332KXXA Vishay-Vitramon 1 CSS 33 nF, 0603, X7R, 25V VJ0603Y333KXXA Vishay-Vitramon 1 RFB1 4.99 kΩ, 0603 CRCW06034991F-e3 Vishay-Dale 1 RFB2 10 kΩ, 0603 CRCW06031002F-e3 Vishay-Dale 1 RS 3.24 kΩ, 0603 CRCW06033241F-e3 Vishay-Dale 1 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20154 LM20154 www.ti.com SNVS531G – OCTOBER 2007 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision F (March 2013) to Revision G • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 24 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20154 25 PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) LM20154MH/NOPB ACTIVE HTSSOP PWP 16 92 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 20154 MH LM20154MHE/NOPB ACTIVE HTSSOP PWP 16 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 20154 MH LM20154MHX/NOPB ACTIVE HTSSOP PWP 16 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 20154 MH (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 29-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LM20154MHE/NOPB HTSSOP PWP 16 250 178.0 12.4 LM20154MHX/NOPB HTSSOP PWP 16 2500 330.0 12.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.95 8.3 1.6 8.0 12.0 Q1 6.95 8.3 1.6 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 29-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM20154MHE/NOPB HTSSOP PWP LM20154MHX/NOPB HTSSOP PWP 16 250 210.0 185.0 35.0 16 2500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA PWP0016A MXA16A (Rev A) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2013, Texas Instruments Incorporated