DAC8531 SBAS192B – MARCH 2001 – REVISED JUNE 2003 Low-Power, Rail-to-Rail Output, 16-Bit Serial Input DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION ● microPower OPERATION: 250µA at 5V ● POWER-ON RESET TO ZERO ● POWER SUPPLY: +2.7V to +5.5V ● ENSURED MONOTONIC BY DESIGN ● SETTLING TIME: 10µs to ±0.003 FSR ● LOW-POWER SERIAL INTERFACE WITH SCHMITT-TRIGGERED INPUTS ● ON-CHIP OUTPUT BUFFER AMPLIFIER, RAIL-TO-RAIL OPERATION ● SYNC INTERRUPT FACILITY ● PACKAGES: MSOP-8 and 3x3 SON-8 (same size as QFN) The DAC8531 is a low-power, single, 16-bit buffered voltage output Digital-to-Analog Converter (DAC). Its on-chip precision output amplifier allows rail-to-rail output swing to be achieved. The DAC8531 uses a versatile three-wire serial interface that operates at clock rates up to 30MHz and is compatible with standard SPI™, QSPI™, Microwire™, and Digital Signal Processor (DSP) interfaces. The DAC8531 requires an external reference voltage to set the output range of the DAC. The DAC8531 incorporates a power-on reset circuit that ensures that the DAC output powers up at 0V and remains there until a valid write takes place to the device. The DAC8531 contains a power-down feature, accessed over the serial interface, that reduces the current consumption of the device to 200nA at 5V. The low power consumption of this part in normal operation makes it ideally suited to portable battery-operated equipment. The power consumption is 2mW at 5V reducing to 1µW in power-down mode. APPLICATIONS ● ● ● ● ● ● PROCESS CONTROL DATA ACQUISITION SYSTEMS CLOSED-LOOP SERVO-CONTROL PC PERIPHERALS PORTABLE INSTRUMENTATION PROGRAMMABLE ATTENUATION The DAC8531 is available in both MSOP-8 and 3x3 SON-8 (same size as QFN) packages. VDD VFB VREF Ref (+) VOUT 16-Bit DAC 16 DAC Register 16 SYNC SCLK DIN Shift Register Power-Down Control Logic Resistor Network GND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2001-2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC DISCHARGE SENSITIVITY VDD to GND ........................................................................... –0.3V to +6V Digital Input Voltage to GND ................................. –0.3V to +VDD + 0.3V VOUT to GND .......................................................... –0.3V to +VDD + 0.3V Operating Temperature Range ...................................... –40°C to +105°C Storage Temperature Range ......................................... –65°C to +150°C Junction Temperature Range (TJ max) ........................................ +150°C Power Dissipation ........................................................ (TJ max — TA)/θJA θJA Thermal Impedance ......................................................... 206°C/W θJC Thermal Impedance .......................................................... 44°C/W Lead Temperature, Soldering: Vapor Phase (60s) ............................................................... +215°C Infrared (15s) ........................................................................ +220°C This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PACKAGE/ORDERING INFORMATION PRODUCT MINIMUM RELATIVE ACCURACY (LSB) DIFFERENTIAL NONLINEARITY (LSB) DAC8531E ±64 " " DAC8531I DAC8531I PACKAGE-LEAD PACKAGE DESIGNATOR(1) SPECIFICATION TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ±1 MSOP-8 DGK –40°C to +105°C D31 " " " " " DAC8531E/250 DAC8531E/2K5 Tape and Reel, 250 Tape and Reel, 2500 ±64 ±1 SON-8 DRB –40°C to +105°C D31 " " " " " " DAC8531IDRBT DAC8531IDRBR Tape and Reel, 250 Tape and Reel, 2500 NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. ELECTRICAL CHARACTERISTICS VDD = +2.7V to +5.5V. –40°C to +105°C, unless otherwise specified. DAC8531E PARAMETER STATIC PERFORMANCE (1) Resolution Relative Accuracy Differential Nonlinearity Zero Code Error Full-Scale Error Gain Error Zero Code Error Drift Gain Temperature Coefficient OUTPUT CHARACTERISTICS (2) Output Voltage Range Output Voltage Settling Time Slew Rate Capacitive Load Stability Code Change Glitch Impulse Digital Feedthrough DC Output Impedance Short-Circuit Current Power-Up Time REFERENCE INPUT Reference Current CONDITIONS MIN TYP MAX 16 Ensured Monotonic by Design All Zeroes Loaded to DAC Register All Ones Loaded to DAC Register +5 –0.15 ±20 ±5 0 To ±0.003% FSR 0200H to FD00H RL = 2kΩ; 0pF < CL < 200pF RL = 2kΩ; CL = 500pF 8 RL = ∞ RL = 2kΩ 1LSB Change Around Major Carry VDD = +5V VDD = +3V Coming Out of Power-Down Mode VDD = +5V Coming Out of Power-Down Mode VDD = +3V VREF = VDD = +5V VREF = VDD = +3.6V Reference Input Range Reference Input Impedance ±0.098 ±1 +20 –1.25 ±1.25 UNITS Bits % of FSR LSB mV % of FSR % of FSR µV/°C ppm of FSR/°C VREF V 10 µs 12 1 470 1000 20 0.5 1 50 20 µs V/µs pF pF nV-s nV-s Ω mA mA 2.5 µs 5 µs 35 20 0 150 45 30 VDD µA µA V kΩ NOTES: (1) Linearity calculated using a reduced code range of 485 to 64714; output unloaded. (2) Ensured by design and characterization, not production tested. 2 DAC8531 www.ti.com SBAS192B ELECTRICAL CHARACTERISTICS (Cont.) VDD = +2.7V to +5.5V. –40°C to +105°C, unless otherwise specified. DAC8531E PARAMETER CONDITIONS LOGIC INPUTS (2) Input Current VINL, Input LOW Voltage VINL, Input LOW Voltage VINH, Input HIGH Voltage VINH, Input HIGH Voltage Pin Capacitance VDD VDD VDD VDD POWER REQUIREMENTS VDD IDD (normal mode) VDD = +3.6V to +5.5V VDD = +2.7V to +3.6V IDD (all power-down modes) VDD = +3.6V to +5.5V VDD = +2.7V to +3.6V = = = = MIN +5V +3V +5V +3V 2.7 VOUT 0.2 0.05 1 1 µA µA ILOAD = 2mA, VDD = +5V 89 GND 7 DIN 3 6 SCLK 4 5 SYNC DAC8531 NAME 8 GND 7 DIN 3 6 SCLK 4 5 SYNC 2 VFB VOUT +105 °C DAC8531 DESCRIPTION 1 VDD Power-Supply Input, +2.7V to +5.5V. 2 VREF Reference Voltage Input 3 VFB Feedback connection for the output amplifier. 4 VOUT Analog output voltage from DAC. The output amplifier has rail-to-rail operation. 5 SYNC Level-triggered control input (active LOW). This is the frame sychronization signal for the input data. When SYNC goes LOW, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is updated following the 24th clock cycle unless SYNC is taken HIGH before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC8531. 6 SCLK Serial Clock Input. Data can be transferred at rates up to 30MHz. 7 DIN Serial Data Input. Data is clocked into the 24-bit input shift register on the falling edge of the serial clock input. 8 GND Ground reference point for all circuitry on the part. MSOP-8 VREF % PIN DESCRIPTION 8 1 V VIH = VDD and VIL = GND VIH = VDD and VIL = GND –40 VDD 5.5 µA µA PIN VFB 3 µA V V V V pF 400 390 Top View 2 ±1 0.8 0.6 250 240 PIN CONFIGURATIONS VREF UNITS 2.4 2.1 TEMPERATURE RANGE Specified Performance 1 MAX DAC Active and Excluding Load Current VIH = VDD and VIL = GND VIH = VDD and VIL = GND POWER EFFICIENCY IOUT/IDD VDD TYP SON-8 DAC8531 SBAS192B www.ti.com 3 TIMING CHARACTERISTICS(1, 2) VDD = +2.7V to +5.5V; all specifications –40°C to +105°C unless otherwise noted. DAC8531E PARAMETER t1 (3) t2 t3 t4 t5 t6 t7 t8 DESCRIPTION CONDITIONS MIN TYP MAX UNITS VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 50 33 ns ns VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 13 13 ns ns VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 22.5 13 ns ns VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 0 0 ns ns VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 5 5 ns ns VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 4.5 4.5 ns ns VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 0 0 ns ns VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 50 33 ns ns SCLK Cycle Time SCLK HIGH Time SCLK LOW Time SYNC to SCLK Rising Edge Setup Time Data Setup Time Data Hold Time SCLK Falling Edge to SYNC Rising Edge Minimum SYNC HIGH Time NOTES: (1) All input signals are specified with tR = tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. (2) See Serial Write Operation timing diagram, below. (3) Maximum SCLK frequency is 30MHz at VDD = +3.6V to +5.5V and 20MHz at VDD = +2.7V to +3.6V. SERIAL WRITE OPERATION t1 SCLK t8 t3 t4 t2 t7 SYNC t6 t5 DIN 4 DB23 DB0 DAC8531 www.ti.com SBAS192B TYPICAL CHARACTERISTICS: VDD = 5V At TA = +25°C, VDD = 5V, unless otherwise noted. NOTE: All references to IDD include IREF current. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C) LE (LSB) 64 48 32 16 0 –16 –32 –48 –64 2.0 1.5 1.0 0.5 0.0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (–40°C) 64 48 32 16 0 –16 –32 –48 –64 2.0 1.5 1.0 0.5 0.0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code DLE (LSB) ZERO-SCALE ERROR vs TEMPERATURE 20 64 48 32 16 0 –16 –32 –48 –64 15 10 2.0 1.5 1.0 0.5 0.0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Error (mV) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+105°C) 5 0 –5 –10 –15 –20 –40 0 40 80 120 Temperature (°C) Digital Input Code FULL-SCALE ERROR vs TEMPERATURE IDD HISTOGRAM 20 2000 15 1500 5 Frequency Error (mV) 10 0 –5 –10 1000 500 –15 –20 –40 0 0 40 80 120 100 130 Temperature (°C) IDD (µA) DAC8531 SBAS192B 160 190 220 250 280 310 340 370 400 www.ti.com 5 TYPICAL CHARACTERISTICS: VDD = 5V (Cont.) At TA = +25°C, VDD = 5V, unless otherwise noted. NOTE: All references to IDD include IREF current. SOURCE AND SINK CURRENT CAPABILITY SUPPLY CURRENT vs DIGITAL INPUT CODE 5 500 DAC Loaded with FFFFH 400 3 IDD (µA) VOUT (V) 4 2 1 300 200 100 DAC Loaded with 0000H 0 0 0 5 10 15 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH ISOURCE/SINK (mA) Digital Input Code POWER-SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs SUPPLY VOLTAGE 350 350 300 300 250 250 200 200 IDD (µA) Quiescent Current (µA) VREF tied to VDD. 150 150 100 100 50 50 0 –40 0 40 80 0 120 2.7 3.2 3.7 4.2 Temperature (°C) 4.7 5.2 5.7 VDD (V) POWER-DOWN CURRENT vs SUPPLY VOLTAGE SUPPLY CURRENT vs LOGIC INPUT VOLTAGE 100 700 90 600 80 500 60 IDD (µA) IDD (nA) 70 +105°C 50 –40°C 40 400 300 30 20 200 +25°C 10 0 100 2.7 3.2 3.7 4.2 4.7 5.2 5.7 VDD (V) 6 0 1 2 3 4 5 VLOGIC (V) DAC8531 www.ti.com SBAS192B TYPICAL CHARACTERISTICS: VDD = 5V (Cont.) At TA = +25°C, VDD = 5V, unless otherwise noted. FULL-SCALE SETTLING TIME FULL-SCALE SETTLING TIME Scope Trigger (5.0V/div) Scope Trigger (5.0V/div) Large-Signal Output (1.0V/div) Small-Signal Error (1mV/div) Small-Signal Error (1mV/div) Full-Scale Code Change FFFFH to 0000H Output Loaded with 2kΩ and 200pF to GND Full-Scale Code Change 0000H to FFFFH Output Loaded with 2kΩ and 200pF to GND Large-Signal Output (1.0V/div) Time (2µs/div) Time (2µs/div) HALF-SCALE SETTLING TIME HALF-SCALE SETTLING TIME Scope Trigger (5.0V/div) Scope Trigger (5.0V/div) Large-Signal Output (1.0V/div) Small-Signal Error (1mV/div) Small-Signal Error (1mV/div) Large-Signal Output (1V/div) Half-Scale Code Change 4000H to C000H Output Loaded with 2kΩ and 200pF to GND Half-Scale Code Change C000H to 4000H Output Loaded with 2kΩ and 200pF to GND Time (2µs/div) Time (2µs/div) EXITING POWER-DOWN (8000H Loaded) POWER-ON RESET TO 0V Loaded with 2kΩ to VDD. Scope Trigger (5.0V/div) VDD (2V/div) Output (1.0V/div) VOUT (1V/div) Time (2µs/div) Time (50µs/div) DAC8531 SBAS192B www.ti.com 7 TYPICAL CHARACTERISTICS: VDD = 5V (Cont.) At TA = +25°C, VDD = 5V, unless otherwise noted. VOUT (50mV/div) CODE CHANGE GLITCH Glitch Waveform (50mV/div) Time (2µs/div) TYPICAL CHARACTERISTICS: VDD = 2.7V At TA = +25°C, VDD = 2.7V, unless otherwise noted. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C) LE (LSB) 64 48 32 16 0 –16 –32 –48 –64 2.0 1.5 1.0 0.5 0.0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (–40°C) 64 48 32 16 0 –16 –32 –48 –64 2.0 1.5 1.0 0.5 0.0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code DLE (LSB) ZERO-SCALE ERROR vs TEMPERATURE 20 64 48 32 16 0 –16 –32 –48 –64 15 10 2.0 1.5 1.0 0.5 0.0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Error (mV) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+105°C) 0 –5 –10 –15 –20 –40 0 40 80 120 Temperature (°C) Digital Input Code 8 5 DAC8531 www.ti.com SBAS192B TYPICAL CHARACTERISTICS: VDD = 2.7V At TA = +25°C, VDD = 2.7V, unless otherwise noted. NOTE: All references to IDD include IREF current. FULL-SCALE ERROR vs TEMPERATURE IDD HISTOGRAM 20 2000 15 1500 5 Frequency Error (mV) 10 0 –5 –10 1000 500 –15 0 –20 –40 0 40 80 120 100 130 160 190 220 250 280 310 340 370 400 Temperature (°C) IDD (µA) SUPPLY CURRENT vs DIGITAL INPUT CODE SOURCE AND SINK CURRENT CAPABILITY 500 3.0 2.5 400 DAC Loaded with FFFFH IDD (µA) VOUT (V) 2.0 1.5 300 200 1.0 100 0.5 DAC Loaded with 0000H 0 0.0 0 5 10 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH 15 Digital Input Code ISOURCE/SINK (mA) SUPPLY CURRENT vs LOGIC INPUT VOLTAGE 200 300 180 250 160 IDD (µA) Quiescent Current (µA) POWER SUPPLY CURRENT vs TEMPERATURE 350 200 150 140 120 100 100 50 80 0 –40 0 40 80 120 0 DAC8531 SBAS192B 0.5 1 1.5 2 2.5 3 VLOGIC (V) Temperature (°C) www.ti.com 9 TYPICAL CHARACTERISTICS: VDD = 2.7V (Cont.) At TA = +25°C, VDD = 2.7V, unless otherwise noted. FULL-SCALE SETTLING TIME FULL-SCALE SETTLING TIME Scope Trigger (5.0V/div) Scope Trigger (5.0V/div) Large-Signal Output (1.0V/div) Small-Signal Error (1mV/div) Small-Signal Error (1mV/div) Large-Signal Output (1.0V/div) Full-Scale Code Change 0000H to FFFFH Output Loaded with 2kΩ and 200pF to GND Full-Scale Code Change FFFFH to 0000H Output Loaded with 2kΩ and 200pF to GND Time (2µs/div) Time (2µs/div) HALF-SCALE SETTLING TIME HALF-SCALE SETTLING TIME Scope Trigger (5.0V/div) Scope Trigger (5.0V/div) Large-Signal Output (1.0V/div) Small-Signal Error (1mV/div) Small-Signal Error (1mV/div) Large-Signal Output (1.0V/div) Half-Scale Code Change 4000H to C000H Output Loaded with 2kΩ and 200pF to GND Half-Scale Code Change C000H to 4000H Output Loaded with 2kΩ and 200pF to GND Time (2µs/div) Time (2µs/div) POWER-ON RESET to 0V EXITING POWER-DOWN (8000H Loaded) Loaded with 2kΩ to VDD. Scope Trigger (5.0V/div) VDD (1V/div) Output (1.0V/div) VOUT (1V/div) Time (50µs/div) 10 Time (2µs/div) DAC8531 www.ti.com SBAS192B TYPICAL CHARACTERISTICS: VDD = 2.7V (Cont.) At TA = +25°C, VDD = 2.7V, unless otherwise noted. VOUT (20mV/div) CODE CHANGE GLITCH Glitch Waveform (20mV/div) Time (2µs/div) RESISTOR STRING THEORY OF OPERATION DAC SECTION The architecture consists of a string DAC followed by an output buffer amplifier. Figure 1 shows a block diagram of the DAC architecture. Figure 2 shows the resistor string section. It is simply a string of resistors, each of value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the amplifier. It is ensured monotonic because it is a string of resistors. VDD DAC Register VFB R VOUT REF (+) Resistor String REF(–) Output Amplifier R GND R To Output Amplifier FIGURE 1. DAC8531 Architecture. The input coding to the DAC8531 is straight binary, so the ideal output voltage is given by: VOUT = VREF • D 65536 R where D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 65535. R FIGURE 2. Resistor String. DAC8531 SBAS192B www.ti.com 11 OUTPUT AMPLIFIER The output buffer amplifier is capable of generating rail-to-rail voltages on its output which gives an output range of 0V to VDD. It is capable of driving a load of 2kΩ in parallel with 1000pF to GND. The source and sink capabilities of the output amplifier can be seen in the typical curves. The slew rate is 1V/µs with a full-scale settling time of 8µs with the output unloaded. The inverting input of the output amplifier is brought out to the VFB pin. This allows for better accuracy in critical applications by tying the VFB point and the amplifier output together directly at the load. Other signal conditioning circuitry may also be connected between these points for specific applications. SERIAL INTERFACE SYNC buffer draws more current when the SYNC signal is HIGH than it does when it is LOW, SYNC should be idled LOW between write sequences for lowest power operation of the part. As mentioned above, it must be brought HIGH again just before the next write sequence. INPUT SHIFT REGISTER The input shift register is 24 bits wide, as shown in Figure 3. The first six bits are “don’t cares”. The next two bits (PD1 and PD0) are control bits that control which mode of operation the part is in (normal mode or any one of three power-down modes). There is a more complete description of the various modes in the Power-Down Modes section. The next 16 bits are the data bits. These are transferred to the DAC register on the 24th falling edge of SCLK. SYNC INTERRUPT The DAC8531 has a three-wire serial interface (SYNC, SCLK, and DIN), which is compatible with SPI, QSPI, and Microwire interface standards as well as most DSPs. See the Serial Write Operation timing diagram for an example of a typical write sequence. The write sequence begins by bringing the SYNC line LOW. Data from the DIN line is clocked into the 24-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high as 30MHz, making the DAC8531 compatible with high-speed (DSPs). On the 24th falling edge of the serial clock, the last data bit is clocked in and the programmed function is executed (i.e., a change in DAC register contents and/or a change in the mode of operation). At this point, the SYNC line may be kept LOW or brought HIGH. In either case, it must be brought HIGH for a minimum of 33ns before the next write sequence so that a falling edge of SYNC can initiate the next write sequence. Since the In a normal write sequence, the SYNC line is kept LOW for at least 24 falling edges of SCLK and the DAC is updated on the 24th falling edge. However, if SYNC is brought HIGH before the 24th falling edge, this acts as an interrupt to the write sequence. The shift register is reset and the write sequence is seen as invalid. Neither an update of the DAC register contents or a change in the operating mode occurs, as shown in Figure 4. POWER-ON RESET The DAC8531 contains a power-on reset circuit that controls the output voltage during power-up. On power-up, the DAC register is filled with zeros and the output voltage is 0V; it remains there until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the output of the DAC while it is in the process of powering up. DB23 X DB0 X X X X X PD1 PD0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FIGURE 3. Data Input Register. 24th Falling Edge 24th Falling Edge CLK SYNC DIN DB23 DB0 DB23 Invalid Write Sequence: SYNC HIGH before 24th Falling Edge DB0 Valid Write Sequence: Output Updates on the 24th Falling Edge FIGURE 4. SYNC Interrupt Facility. 12 DAC8531 www.ti.com SBAS192B POWER-DOWN MODES The DAC8531 supports four separate modes of operation. These modes are programmable by setting two bits (PD1 and PD0) in the control register. Table I shows how the state of the bits corresponds to the mode of operation of the device. PD1 (DB17) PD0 (DB16) 0 0 OPERATING MODE Normal Operation — — Power-Down Modes 0 1 Output 1kΩ to GND 1 0 Output 100kΩ to GND 1 1 High-Z TABLE I. Modes of Operation for the DAC8531. When both bits are set to 0, the part works normally with its typical current consumption of 250µA at 5V. However, for the three power-down modes, the supply current falls to 200nA at 5V (50nA at 3V). Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the part is known while the part is in power-down mode. There are three different options. The output is connected internally to GND through a 1kΩ resistor, a 100kΩ resistor, or it is left opencircuited (High-Z). The output stage is illustrated in Figure 5. MICROPROCESSOR INTERFACING DAC8531 TO 8051 INTERFACE Figure 6 shows a serial interface between the DAC8531 and a typical 8051-type microcontroller. The setup for the interface is as follows: TXD of the 8051 drives SCLK of the DAC8531, while RXD drives the serial data line of the part. The SYNC signal is derived from a bit-programmable pin on the port. In this case, port line P3.3 is used. When data is to be transmitted to the DAC8531, P3.3 is taken LOW. The 8051 transmits data only in 8-bit bytes; thus only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left LOW after the first eight bits are transmitted and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken HIGH following the completion of the third write cycle. The 8051 outputs the serial data in a format which has the LSB first. The DAC8531 requires its data with the MSB as the first bit received. The 8051 transmit routine must therefore take this into account, and “mirror” the data as needed. 80C51/80L51(1) DAC8531(1) P3.3 SYNC TXD SCLK RXD DIN NOTE: (1) Additional pins omitted for clarity. VFB Resistor String DAC Amplifier FIGURE 6. DAC8531 to 80C51/80L51 Interface. VOUT DAC8531 TO Microwire INTERFACE Power-Down Circuitry Figure 7 shows an interface between the DAC8531 and any Microwire compatible device. Serial data is shifted out on the falling edge of the serial clock and is clocked into the DAC8531 on the rising edge of the SK signal. Resistor Network FIGURE 5. Output Stage During Power-Down. MicrowireTM All linear circuitry is shut down when the power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically 2.5µs for VDD = 5V, and 5µs for VDD = 3V. See the Typical Characteristics for more information. DAC8531(1) CS SYNC SK SCLK SO DIN NOTE: (1) Additional pins omitted for clarity. Microwire is a registered trademark of National Semiconductor. FIGURE 7. DAC8531 to Microwire Interface. DAC8531 SBAS192B www.ti.com 13 DAC8531 TO 68HC11 INTERFACE Figure 8 shows a serial interface between the DAC8531 and the 68HC11 microcontroller. SCK of the 68HC11 drives the SCLK of the DAC8531, while the MOSI output drives the serial data line of the DAC. The SYNC signal is derived from a port line (PC7), similar to what was done for the 8051. power supply is quite noisy or if the system supply voltages are at some value other than 5V. The REF02 will output a steady supply voltage for the DAC8531. If the REF02 is used, the typical current it needs to supply to the DAC8531 is 250µA. This is with no load on the output of the DAC. When the DAC output is loaded, the REF02 also needs to supply the current to the load. The total current required (with a 5kΩ load on the DAC output) is: 250µA + (5V/ 5kΩ) = 1.29mA DAC8531(1) 68HC11(1) PC7 SYNC SCK SCLK MOSI The load regulation of the REF02 is typically 0.005%/mA, which results in an error of 322µV for the 1.29mA current drawn from it. This corresponds to a 4.2LSB error. DIN NOTE: (1) Additional pins omitted for clarity. BIPOLAR OPERATION USING THE DAC8531 FIGURE 8. DAC8531 to 68HC11 Interface. The 68HC11 should be configured so that its CPOL bit is a 0 and its CPHA bit is a 1. This configuration causes data appearing on the MOSI output to be valid on the falling edge of SCK. When data is being transmitted to the DAC, the SYNC line is taken LOW (PC7). Serial data from the 68HC11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. In order to load data to the DAC8531, PC7 is left LOW after the first eight bits are transferred, then a second and third serial write operation is performed to the DAC and PC7 is taken HIGH at the end of this procedure. The output voltage for any input code can be calculated as follows: R2 D R1 + R 2 VO = VREF • • – VREF • R 65536 R1 1 where D represents the input code in decimal (0–65535). With VREF = 5V, R1 = R2 = 10kΩ: 10 • D VO = – 5V 65536 APPLICATIONS USING REF02 AS A POWER SUPPLY FOR THE DAC8531 Due to the extremely low supply current required by the DAC8531, an alternative option is to use a REF02 +5V precision voltage reference to supply the required voltage to the part, as shown in Figure 9. This is especially useful if the This is an output voltage range of ±5V with 0000H corresponding to a –5V output and FFFFH corresponding to a +5V output. Similarly, using VREF = 2.5V, ±2.5V output voltage raw can be achieved. LAYOUT A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. +15 As the DAC8531 offers single-supply operation, it will often be used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it will be to keep digital noise from appearing at the output. +5V REF02 285µA SYNC Three-Wire Serial Interface The DAC8531 has been designed for single-supply operation but a bipolar output range is also possible using the circuit in Figure 10. The circuit shown will give an output voltage range of ±VREF. Rail-to-rail operation at the amplifier output is achievable using an OPA703 as the output amplifier. SCLK DAC8531 VOUT = 0V to 5V DIN Due to the single ground pin of the DAC8531, all return currents, including digital and analog return currents, must flow through the GND pin. Ideally, GND would be connected directly to an analog ground plane. This plane would be separate from the ground connection for the digital components until they were connected at the power-entry point of the system. FIGURE 9. REF02 as a Power Supply to the DAC8531. 14 DAC8531 www.ti.com SBAS192B As with the GND connection, VDD should be connected to a +5V power-supply plane or trace that is separate from the connection for digital logic until they are connected at the power-entry point. In addition, the 1µF to 10µF and 0.1µF bypass capacitors are strongly recommended. In some situations, additional bypassing may be required, such as a 100µF electrolytic capacitor or even a “Pi” filter made up of inductors and capacitors—all designed to essentially lowpass filter the +5V supply, removing the high-frequency noise. The power applied to VDD should be well regulated and low noise. Switching power supplies and DC/DC converters will often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes as their internal logic switches states. This noise can easily couple into the DAC output voltage through various paths between the power connections and analog output. R2 10kΩ VREF +5V R1 10kΩ OPA703 VFB VREF 10µF DAC8531 0.1µF ±5V VOUT –5V Three-Wire Serial Interface FIGURE 10. Bipolar Operation with the DAC8531. DAC8531 SBAS192B www.ti.com 15 PACKAGE DRAWINGS DGK (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE 0,38 0,25 0,65 8 0,08 M 5 0,15 NOM 3,05 2,95 4,98 4,78 Gage Plane 0,25 1 0°– 6° 4 3,05 2,95 0,69 0,41 Seating Plane 1,07 MAX 0,15 0,05 0,10 4073329/C 08/01 NOTES: A. B. C. D. 16 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-187 DAC8531 www.ti.com SBAS192B PACKAGE DRAWINGS (Cont.) DAC8531 SBAS192B www.ti.com 17 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) DAC8531E/250 ACTIVE VSSOP DGK 8 250 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) -40 to 105 D31 DAC8531E/250G4 ACTIVE VSSOP DGK 8 250 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) -40 to 105 D31 DAC8531E/2K5 ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) -40 to 105 D31 DAC8531E/2K5G4 ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) -40 to 105 D31 DAC8531IDRBR ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 105 D31 DAC8531IDRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 105 D31 DAC8531IDRBT ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 105 D31 DAC8531IDRBTG4 ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 105 D31 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DAC8531E/250 VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 DAC8531E/2K5 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 DAC8531IDRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 DAC8531IDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC8531E/250 VSSOP DGK 8 250 210.0 185.0 35.0 DAC8531E/2K5 VSSOP DGK 8 2500 367.0 367.0 35.0 DAC8531IDRBR SON DRB 8 3000 367.0 367.0 35.0 DAC8531IDRBT SON DRB 8 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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