SLLA255 – APRIL 2006
TSB83AA22A IEEE Std 1394b-2002 Phy and OHCI Link Device
Fully Supports Provisions of IEEE Std
1394b-2002 Revision 1.33+ at 1-Gigabit
Signaling Rates
Fully Supports Provisions of IEEE Std
1394a-2000 and IEEE Std 1394-1995
Standards for High-Performance Serial Bus
Fully Interoperable With Firewire™, i.LINK™,
and SB1394 Implementations of IEEE Std
Provides Two Fully Backward-Compatible,
IEEE Std 1394a-2000 Fully Compliant)
Bilingual IEEE Std 1394b-2002 Cable Ports at
up to 800 Megabits per Second (Mbps)
Full IEEE Std 1394a-2000 Support Includes:
– Connection Debounce
– Arbitrated Short Reset
– Multispeed Concatenation
– Arbitration Acceleration
– Fly-By Concatenation
– Port Disable/Suspend/Resume
Extended Resume Signaling for Compatibility
With Legacy DV Devices
Power-Down Features to Conserve Energy in
Battery-Powered Applications
Low-Power Sleep Mode
Fully Compliant With Open Host Controller
Interface (OHCI) Requirements
Cable Power Presence Monitoring
Cable Ports Monitor Line Conditions for
Active Connection to Remote Node
Register Bits Give Software Control of
Contender Bit, Power-Class Bits, Link Active
Control Bit, and IEEE Std 1394a-2000
Interoperable With Other 1394 Physical
Layers (Phy) Using 1.8-V, 3.3-V, and 5-V
Low-Jitter, External Crystal Oscillator
Provides Transmit and Receive Data at
100/200/400/800 Mbps and Link-Layer
Controller Clock at 49.152 MHz and 98.304
Separate Bias (TPBIAS) for Each Port
Software Device Reset (SWR)
Fail-Safe Circuitry Senses Sudden Loss of
Power to the Device and Disables the Ports
Ensure That the TSB83AA22A Does Not Load
the TPBIAS of Any Connected Device and
Blocks any Leakage From the Port Back to
Power Plane.
The TSB83AA22A Has an IEEE Std
1394a-2000-Compliant Common-Mode Noise
Filter on Incoming Bias Detect Circuit to Filter
Out Cross-Talk Noise.
The TSB83AA22A Is Port Programmable to
Force IEEE Std 1394a-2000 Mode to Allow
Use of IEEE Std 1394a-2000 Connectors
(IEEE Std 1394b-2002 Signaling Must Not Be
Put Across IEEE Std 1394a-2000 Connectors
or Cables).
3.3-V and 5-V PCI Signaling Environments
Serial-Bus Data Rates of 100 Mbps, 200
Mbps, 400 Mbps, and 800 Mbps
Physical Write Posting of up to Three
Outstanding Transactions
Serial ROM or Boot ROM Interface Supports
2-wire Serial EEPROM Devices
33-MHz/32-Bit PCI Interface
Multifunction Terminal (MFUNC Terminal 1):
– PCI_CLKRUN Protocol per the PCI Mobile
Design Guide
– General-Purpose I/O
– CYCLEIN/CYCLEOUT for External Cycle
Timer Control for Customized
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Firewire is a trademark of Apple Computer, Inc..
i.LINK is a trademark of Sony Kabushiki Kaisha TA Sony Corporation..
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
SLLA255 – APRIL 2006
PCI Burst Transfers and Deep FIFOs to
Tolerate Large Host Latency:
– Transmit FIFO—5K Asynchronous
– Transmit FIFO—2K Isochronous
– Receive FIFO—2K Asynchronous
– Receive FIFO—2K Isochronous
D0, D1, D2, and D3 Power States and PME
Events per the PCI Bus Power Management
Interface Specification
Programmable Asynchronous Transmit
Isochronous Receive Dual-Buffer Mode
Out-of-Order Pipelining for Asynchronous
Transmit Requests
Initial-Bandwidth-Available and
Initial-Channels-Available Registers
Digital Video and Audio Performance
The TSB83AA22A is an IEEE Std 1394b-2002 link-layer design and Phy design combined in a single package to
meet the demanding requirements of today’s 1394 bus applications. The TSB83AA22A device is capable of
exceptional 800-Mbps performance; thus, providing the throughput and bandwidth to move data efficiently and
quickly between the PCI and 1394 buses. The TSB83AA22A device also provides outstanding ultralow-power
operation and intelligent power management capabilities. The device provides the IEEE 1394 LLC function and
Phy function and is compatible with 100 Mbps, 200 Mbps, 400 Mbps, and 800 Mbps serial-bus data rates.
The TSB83AA22A operates as the interface between 33-MHz/32-bit PCI local bus and an IEEE Std 1394a-2000
or IEEE Std 1394b-2002 serial bus interface. It is capable of supporting serial data rates at 98.304, 196.608,
393.216, 491.52, or 786.432 Mbps (referred to as S100, S200, S400, S400B, or S800 speeds, respectively).
When acting as a PCI bus master, the TSB83AA22A device is capable of multiple cacheline bursts of data,
which can transfer at 132M bytes/s for 32-bit transfers after connecting to the memory controller.
Due to the high throughput potential of the TSB83AA22A device, it possible to encounter large PCI and legacy
1394 bus latencies, which can cause the 1394 data to be overrun. To overcome this potential problem, the
TSB83AA22A implements deep transmit and receive FIFOs (see Section 1.1, Features, for FIFO size
information) to buffer the 1394 data, thus preventing possible problems due to bus latency. This also ensures
that the device can transmit and receive sustained maximum-size isochronous or asynchronous data payloads
at S800.
The TSB83AA22A LLC section implements other performance enhancements to improve overall performance of
the device, such as: a highly tuned physical data path for enhanced SBP-2 performance, physical post writing
buffers, multiple isochronous contexts, and advanced internal arbitration.
The TSB83AA22A LLC section also implements hardware enhancements to better support digital video (DV)
and MPEG data stream reception and transmission. These enhancements are enabled through the isochronous
receive digital video enhancements register at TI extension offset A80h (see Section 6.3.4, Isochronous Receive
Digital Video Enhancements Register). These enhancements include automatic time stamp insertion for
transmitted DV and MPEG-formatted streams and common isochronous packet (CIP) header stripping for
received DV streams.
The CIP format is defined by the IEC 61883-1:1998 specification. The enhancements to the isochronous data
contexts are implemented as hardware support for the synchronization timestamp for both DV and audio/video
CIP formats. The TSB83AA22A device supports modification of the synchronization timestamp field to ensure
that the value inserted via software is not stale — that is, less than the current cycle timer when the packet is
The TSB83AA22A performance and enhanced throughput make it an excellent choice for today’s 1394 PC
market; however, the portable, mobile, and even today’s desktop PCs power management schemes continue to
require devices to use less and less power, and Texas Instrument’s 1394 product line has continued to raise the
bar by providing the lowest-power 1394 devices in the industry. The TSB83AA22A device represents the next
evolution of Texas Instruments commitment to meet the challenge of power-sensitive applications. The
TSB83AA22A device has ultralow operational power requirements and intelligent power management
capabilities that allow it to conserve power autonomously based on the device usage. The TSB83AA22A LLC
section fully supports D0, D1, D2, and D3hot/cold power states as specified in the PC 2001 Design Guide
requirements and the PCI Power Management Specification. PME wake event support is subject to operating
system support and implementation.
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As required by the 1394 Open Host Controller Interface Specification (OHCI) and IEEE Std 1394a-2000, internal
control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through
configuration cycles as specified by the PCI Local Bus Specification, and provides plug-and-play (PnP)
compatibility. Furthermore, the TSB83AA22A LLC section is fully compliant with the latest PCI Local Bus
Specification, PCI Bus Power Management Interface Specification, IEEE Std 1394b-2002, IEEE Std
1394a-2000, and 1394 Open Host Controller Interface Specification.
The TSB83AA22A Phy section provides the digital and analog transceiver functions needed to implement a
two-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line
transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining
connection status, for initialization and arbitration, and for packet reception and transmission.
The TSB83AA22A is powered by multiple voltage supplies, 3.3-V supplies for I/O and the LLC section, and a
core voltage supply for the Phy section. The core voltage supply is supplied to the PLLVDD_CORE and
DVDD_CORE terminals in accordance with the requirements in the recommended operating conditions. The
PLLVDD_CORE terminals must be separated from the DVDD_CORE terminals, the PLLVDD_CORE terminals
are decoupled with 1-µF and smaller decoupling capacitors, and the DVDD_CORE terminals separately
decoupled with 1-µF and smaller decoupling capacitors. The separation between DVDD_CORE and
PLLVDD_CORE can be implemented by separate power supply rails, or by a single power supply rail, where the
DVDD_CORE and PLLVDD_CORE are separated by a filter network to keep noise from the PLLVDD_CORE
supply. In addition, REG_EN must be asserted low to enable the internal voltage regulator for the LLC section. If
REG_EN is not pulled low, the a 1.8-V power rail must be applied to the REG18 pins.
The TSB83AA22A requires an external 98.304-MHz crystal oscillator to generate a reference clock. The external
clock drives an internal phase-locked loop (PLL), which generates the required reference signal. This reference
signal provides the clock signals that control transmission of the outbound encoded information. The
power-down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL.
Data bits to be transmitted through the cable ports are latched internally, combined serially, encoded, and
transmitted at 98.304, 196.608, 393.216, 491.52, or 983.04 Mbps (referred to as S100, S200, S400, S400B, or
S800 speed, respectively) as the outbound information stream.
To ensure that the TSB83AA22A conforms to the IEEE Std 1394b-2002 standard, the BMODE terminal must be
The BMODE terminal does not select the cable-interface mode of operation. The
BMODE terminal selects the internal Phy section–LLC section interface mode of
operation and affects the arbitration modes on the cable. BMODE must be pulled
high during normal operation.
The cable interface can follow either the IEEE Std 1394a-2000 protocol or the IEEE Std 1394b-2002 protocol on
both ports. The mode of operation is determined by the interface capabilities of the ports being connected. When
either of the ports is connected to an IEEE Std 1394a-2000-compliant device, the cable interface on that port
operates in the IEEE Std 1394a-2000 data-strobe mode at a compatible S100, S200, or S400 speed. When a
bilingual port is connected to an IEEE Std 1394b-2002-compliant node, the cable interface on that port operates
per the IEEE Std 1394b-2002 standard at S400B or S800 speed. The TSB83AA22A automatically determines
the correct cable interface connection method for the bilingual ports.
To operate a port as an IEEE Std 1394b-2002 bilingual port, the data-strobe-only terminal for the port (DS0 or
DS1) must be pulled to ground through a 1- kΩ resistor. The port must be operated in the IEEE Std 1394b-2002
bilingual mode whenever an IEEE Std 1394b-2002 bilingual or an IEEE Std 1394b-2002 Beta-only connector is
connected to the port. To operate the port as an IEEE Std 1394a-2000-only port, the data-strobe-only terminal
(DS0 or DS1) must be pulled to 3.3-V VCC through a 1-kΩ resistor. The only time the port must be forced to the
data-strobe-only mode is if the port is connected to an IEEE Std 1394a-2000 connector (either 6-pin, which is
recommended, or 4-pin). This mode is provided to ensure that IEEE Std 1394b-2002 signaling is never sent
across an IEEE Std 1394a-2000 cable.
During packet reception, the serial data bits are split into 2-, 4-, or 8-bit parallel streams by the Phy section and
sent to the link-layer controller (LLC) section. The received data is also transmitted (repeated) on the other
connected and active cable ports.
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Both the twisted pair A (TPA) and the twisted pair B (TPB) cable interfaces incorporate differential comparators
to monitor the line states during initialization and arbitration when connected to an IEEE Std
1394a-2000-compliant device. The outputs of these comparators are used by the internal logic to determine the
arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this
common-mode voltage is used during IEEE Std 1394a-2000-mode arbitration and sets the speed of the next
packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage on the
TPB pair for the presence of the remotely supplied twisted pair bias (TPBIAS) voltage.
When connected to an IEEE Std 1394a-2000-compliant node, the TSB83AA22A Phy section provides a 1.86-V
nominal bias voltage at the TPBIAS terminal for port termination. The Phy section contains two independent
TPBIAS circuits (one for each port). This bias voltage, when seen through a cable by a remote receiver,
indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter
capacitor of 1 µF.
The line drivers in the TSB83AA22A Phy section are designed to work with external 112-Ω termination resistor
networks in order to match the 110-Ω cable impedance. One termination network is required at each end of a
twisted-pair cable. Each network is composed of a pair of series-connected 56-Ω resistors. The midpoint of the
pair of resistors that is connected to the TPA terminals is connected to its corresponding TPBIAS voltage
terminal. The midpoint of the pair of resistors that is directly connected to the TPB terminals is coupled to ground
through a parallel RC network with recommended values of 5 kΩ and 270 pF. The values of the external
line-termination resistors are selected to meet the standard specifications when connected in parallel with the
internal receiver circuits. A precision external resistor connected between the R0 and R1 terminals sets the
driver output current, along with other internal operating currents.
When the power supply of the TSB83AA22A is off while the twisted-pair cables are connected, the
TSB83AA22A transmitter and receiver circuitry present to the cable a high-impedance signal that does not load
the device at the other end of the cable.
When the TSB83AA22A Phy section is used without one or more of the ports brought out to a connector, the
twisted-pair terminals of the unused ports must be terminated for reliable operation. For each unused port, the
port must be forced to the IEEE Std 1394a-2000-only mode (data-strobe-only mode), after which the TPB+ and
TPB– terminals can be tied together and then pulled to ground; or the TPB+ and TPB– terminals can be
connected to the suggested normal termination network. The TPA+ and TPA– terminals of an unused port can
be left unconnected. The TPBIAS terminal can be connected through a 1-µF capacitor to ground or left
The TESTM, TESTW, SE, and SM terminals are used to set up various manufacturing test conditions. For
normal operation, the TESTM and TESTW terminals must be connected to VDD through a 1-kΩ resistor. The
SE and SM terminals must be tied to ground through a 1-kΩ resistor.
Three package terminals are used as inputs to set the default value for three configuration status bits in the
self-ID packet. They can be pulled high through a 1-kΩ resistor or hardwired low as a function of the equipment
design. The PC0, PC1, and PC2 terminals indicate the default power class status for the node (the need for
power from the cable or the ability to supply power to the cable). The contender bit in the Phy register set
indicates that the node is a contender either for the isochronous resource manager (IRM) or for the bus
manager (BM). On the TSB83AA22A, this bit can only be set by a write to the Phy register set. If a node is to be
a contender for IRM or BM, then the node software must set this bit in the Phy register set.
The LPS (link power status) terminal of the Phy section works with the LKON terminal to manage the power
usage in the node. The PHY_LPS signal from the LLC section is used in conjunction with the LCtrl bit (see Table
1 and Table 2 in the APPLICATION INFORMATION section) to indicate the active/power status of the LLC
section. The LPS signal also resets, disables, and initializes the Phy section–LLC section interface (the state of
the PHY section–LLC section interface is controlled solely by the LPS input regardless of the state of the LCtrl
bit). The LPS terminal of the Phy section must be connected to the PHY_LPS terminal of the LLC section during
normal operation.
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The LPS input is considered inactive if it remains low for more than the LPS_RESET time (see the LPS terminal
definition) and is considered active otherwise. When the Phy section detects that the LPS input is inactive, the
PHY section–LLC section interface is placed into a low-power reset state in which the CTL and D outputs are
held in the logic 0 state and the LREQ input is ignored; however, the PCLK output remains active. If the LPS
input remains low for more than the LPS_DISABLE time (see the LPS terminal definition), then the Phy
section–LLC section interface is put into a low-power disabled state in which the PCLK output is also held
inactive. The TSB83AA22A continues the necessary Phy repeater functions required for normal network
operation regardless of the state of the Phy section–LLC section interface. When the interface is in the reset or
disabled state and the LPS input is again observed active, the Phy section initializes the interface and returns to
normal operation. The Phy section–LLC section interface is also held in the disabled state during hardware
reset. When the LPS terminal is returned to an active state after being sensed as having entered the
LPS_DISABLE time, the TSB83AA22A issues a bus reset. This broadcasts the node self-ID packet, which
contains the updated L bit state (the Phy section and LLC section now being accessible).
The Phy section uses the LKON terminal to notify the LLC section to power up and become active. When
activated, the output LKON signal is a square wave. The Phy section activates the LKON output when the LLC
section is inactive and a wake-up event occurs. The LLC section is considered inactive when either the LPS
input is inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on Phy
packet addressed to this node is received, or conditionally when a Phy interrupt occurs. The Phy section
deasserts the LKON output when the LLC section becomes active (both LPS sensed as active and the LCtrl bit
set to 1). The Phy section also deasserts the LKON output when a bus reset occurs, unless a Phy interrupt
condition exists which would otherwise cause LKON to be active. If the TSB83AA22A is power cycled and the
power class is 0 through 4, then the Phy section asserts LKON for approximately 167 µs or until both the LPS is
active and the LCtrl bit is 1.
Special Note: This product is for high-volume PC applications only. Contact [email protected] for more
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