CERAMIC SMD CRYSTAL CLOCK OSCILLATOR APV SERIES : PRELIMINARY FEATURES: • Low Power ( 2.5, 3.3V ) • Low Jitter • CMOS, PECL or LVDS Output 5.0 x 7.0 x 1.8mm | | | | | | | | | | | | | | | • Sub 1pS ( 12kHz - 20MHz ) APPLICATIONS: • SONET, Fiber Channel, SERDES HDTV, OBSAI, CPRI, PCI Express, 1394 STANDARD SPECIFICATIONS: PARAMETERS Frequency Range Operating Temperature Storage Temperature Overall Frequency Stability Supply Voltage (Vdd) Phase Jitter RMS (12KHz-20MHz) Period Jitter (peak to peak) Tri-State Function PECL Supply Current (IDD) Symmetry (Duty Cycle) Output Logic High Output Logic Low Rise time Fall time CMOS Supply Current Symmetry (Duty Cycle) Rise/ Fall Time 38 MHz to 640 MHz 0°C to + 70°C (see options) -55°C to +125°C ± 50 ppm max. (see options) 2.25V to 3.63V (2.5V to 3.3V ± 10%) 0.5pS Typ, 1pS Max 20pS typ., 30pS max up to 320 MHz; 50pS typ., 70pS max 321MHz to 640MHz For CMOS and LVDS = "1" (VIH ³ 0.7* Vdd) or open: Oscillation; "0" (VIL < 0.3* Vdd): No oscillation/Hi Z For PECL See TriState Pin Operation table P Option Standard PECL OE "0" (VIL < 0.3* Vdd): or Open: Oscillation; "1" (VIH ³ 0.7* Vdd): No oscillation/Hi Z P Option = "1" (VIH ³ 0.7* Vdd) or open: Oscillation; "0" (VIL < 0.3* Vdd): No oscillation/Hi Z 65mA max (for 38MHz<Fo<320MHz), 90mA max (320MHz<Fo<640MHz) 45% min, 50% typical, 55% max. VDD -1.025V min, VDD -0.880V max. VDD -1.810V min, VDD -1.620V max. 1.5ns max, 0.6nSec typical 1.5ns max, 0.6nSec typical 30mA max (38MHz<Fo<320MHz) 45% min, 50% typ, 55% max, (0.3V ~ 3.0V w/15 pF load) 0.7nS Typ.; (20%-80% w/50Ω Load) 0.3nS Typ. ABRACON IS ISO 9001 / QS 9000 CERTIFIED rev3.1-8/06 LVDS 45mA max(for 38MHz<Fo<320MHz), 70mA max (320MHz<Fo<640MHz) Supply Current (IDD) Output Clock Duty Cycle @ 1.25V 45% min, 50% typical, 55% max Output Differential Voltage (VOD) 247mV min, 355mV typical, 454mV max VDD Magnitude Change (∆VOD) -50mV min, 50mV max Output High Voltage VOH = 1.6V max, 1.4V typical Output Low Voltage VOL = 0.9V min, 1.1V typical Offset Voltage [RL = 100Ω] VOS = 1.125V min, 1.2V typical, 1.375V max Offset Magnitude Voltage[RL = 100Ω] ∆VOS = 0mV min, 3mV typical, 25mV max Power-off Leakage (IOXD) [Vout=VDD or GND, VDD=0V] ±10µA max, ±1µA typical Differential Clock Rise Time (tr) [RL=100Ω, CL=10pF] 0.7ns typical, 1.0ns max, 0.2nS min Differential Clock Fall Time (tf) [RL=100Ω, CL=10pF] 0.7ns typical, 1.0ns max, 0.2nS min 30332 Esperanza, Rancho Santa Margarita, California 92688 tel 949-546-8000 | fax 949-546-8001 | www.abracon.com CERAMIC SMD CRYSTAL CLOCK OSCILLATOR APV SERIES : PRELIMINARY 5.0 x 7.0 x 1.8mm | | | | | | | | | | | | | | | MARKING: PIN ASSIGNMENTS: PIN # 1 2 3 4 5 6 NAME Tri-state NC GND Q Q VDD - TUH DESCRIPTION Tri-state No Connect Ground PECL, LVDS Complimentary PECL, LVDS VDD Connection - APV ZYX Frequency T=First “ten” digit of frequency, U=First “unit” of frequency, H=First “tenth” digit of freq, Ex: 100 for 10.0MHz; 143 for 14.31818 MHz) (Z: Month, A to L; Y: Year, 5 for 2005; X: Traceability Code) TRI-STATE PIN OPERATION: OUTPUT TYPE OPTION P PECL P1 PECL1 V LVDS C CMOS PIN 1 LOGIC LEVEL* 0 (Default) 1 1 0 0 1 (Default) 0 1 (Default) OUTPUT STATE Enabled Tri-state Enabled Tri-state Tri-state Enabled Tri-state Enabled *Connect to VDD from logic level "1", connect to ground for logic level "0". OPTIONS AND PART IDENTIFICATION (Left blank if standard): APVX - Frequency - Temperature - Frequency Stability - Output - Packaging Vdd options: Blank (3.3Vdc±10%V) 1 (2.5Vdc±10%V) Temperature: E for -20°C to +70°C L for -40°C to +85°C Stability options: R for ± 25 ppm max S for ± 20 ppm max Packaging option: T for Tape and Reel (1,000pcs/reel) PECL & LVDS DRAWING: ABRACON IS ISO 9001 / QS 9000 CERTIFIED rev3.1-8/06 Dimensions: inch (mm) Output options: P = PECL P1 = PECL1 V = LVDS C = CMOS CMOS DRAWING: PIN # 1 2 3 4 NAME Tri-state GND/Case Output Vdd Dimensions: inch (mm) 30332 Esperanza, Rancho Santa Margarita, California 92688 tel 949-546-8000 | fax 949-546-8001 | www.abracon.com