SDZS011 − APRIL 1990 • • • • • • OR NT PACKAGE 100K Compatible (T0P VIEW) Open-Collector Outputs Drive Bus Lines or Buffer Memory Address Registers Y1 Y2 Y3 Y4 1 24 2 23 3 22 4 21 VCC GND GND GND Y5 Y6 Y7 Y8 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 ECL and TTL Control Inputs Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC, VEE, and GND Configurations Minimize High-Speed Switching Noise Package Options Include “Small Outline” Packages and Standard Plastic 300-mil DIPs description A1 A2 A3 A4 OE2 (TTL) VEE GND OE1 (ECL) A5 A6 A7 A8 logic symbol† This octal ECL-to-TTL translator is designed to provide efficient translation between a 100K signal environment and a TTL signal environment. This device is designed specifically to improve the performance and density of ECL-to-TTL CPU/bus oriented functions such as memory address drivers, clock drivers, and bus-oriented receivers and transmitters while eliminating the need for three-state overlap protection. OE1 OE2 A1 A2 A3 Two output enables, OE1 and OE2, are provided. These enable inputs are ANDed together with OE1 being ECL-compatible and OE2 being TTL-compatible. This offers the choice of controlling the outputs of the device from either a TTL or ECL signal environment. A4 A5 A6 A7 A8 The SN100KT5538 is characterized for operation from 0°C to 85°C. 17 & ECL/TTL EN 20 24 1 ECL/TTL 23 2 22 3 21 4 16 9 15 10 14 11 13 12 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. FUNCTION TABLE OUTPUT ENABLE DATA INPUT OUTPUT (TTL) OE1 OE2 A Y H X X H X H X H L L L H L L H L Copyright 1990, Texas Instruments Incorporated ! "#$ ! %#&'" ($) (#"! " !%$""! %$ *$ $! $+! !#$! !(( ,-) (#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!) • DALLAS, TEXAS 75265 • HOUSTON, TEXAS 77251−1443 POST OFFICE BOX 655303 POST OFFICE BOX 1443 1 SDZS011 − APRIL 1990 logic diagram (positive logic) A1 24 ECL/TTL 1 ECL/TTL 2 ECL/TTL 3 ECL/TTL 4 Y1 23 A2 Y2 22 A3 Y3 21 A4 Y4 17 ECL/TTL OE1 (ECL) 20 OE2 (TTL) 16 A5 ECL/TTL 9 ECL/TTL 10 ECL/TTL 11 ECL/TTL 12 Y5 15 A6 Y6 14 A7 Y7 13 A8 Y8 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Supply voltage range, VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −8 V to 0 V Input voltage range (TTL) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −1.2 V to 7 V Input voltage range (ECL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VEE to 0 V Input current range (TTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −30 mA to 5 mA Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA Voltage applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC Operating temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The TTL input voltage ratings may be exceeded provided the input current ratings are observed. 2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • SDZS011 − APRIL 1990 recommended operating conditions VCC VEE MIN NOM MAX TTL supply voltage 4.5 5 5.5 V ECL supply voltage −4.2 −4.5 −4.8 V −1150 −840 mV −1810 −1490 TTL 2 UNIT V VIH High-level input voltage VIL Low-level input voltage VOH IOL TTL high-level output voltage 5.5 V TTL low-level output current 48 mA IIK TA TTL input clamp current −18 mA 85 °C ECL (see Note 2) TTL 0.8 ECL (see Note 2) Operating free-air temperature 0 V mV NOTE 2: The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for logic levels only. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOL OE2 only II OE2 only TEST CONDITIONS MIN VCC = 4.5 V, VCC = 4.5 V, VEE = − 4.2 V, VEE = − 4.5 V ± 0.3 V, II = − 18 mA IOL = 48 mA VCC = 5.5 V, VCC = 5.5 V, VEE = − 4.8 V, VEE = − 4.8 V, VCC = 5.5 V, VCC = 5.5 V, TYP† UNIT −1.2 V 0.55 V VI = 7 V VI = 2.7 V 0.1 mA VEE = − 4.8 V, VEE = − 4.8 V, VI = − 840 mV VI = 0.5 V 350 µA −0.5 mA VCC = 5.5 V, VCC = 4.5 V, VEE = − 4.8 V, VEE = − 4.2 V, VI = − 1810 mV VOH = 5.5 V ICCH ICCL VCC = 5.5 V, VCC = 5.5 V, VEE = − 4.8 V VEE = − 4.8 V IEE Ci VCC = 5.5 V, VCC = 5.5 V, Co VCC = 5.5 V, OE2 only IIH A inputs and OE1 OE2 only IIL IOH A inputs and OE1 0.38 MAX 20 µA 0.5 250 µA 66 95 mA 79.5 114 mA VEE = − 4.2 V VEE = − 4.5 V −23 −33 mA 5 pF VEE = − 4.5 V 5 pF switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) CL = 50 pF, PARAMETER FROM TO (INPUT) (OUTPUT) R1 = 500 Ω, R2 = 500 Ω TYP† MAX UNIT MIN tPLH tPHL tPLH tPHL Any A Y OE1 (ECL) Y tPLH tPHL Y OE2 (TTL) † All typical values are at VCC = 5 V, VEE = − 4.5 V, TA = 25°C. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 6.4 9.1 2.7 4.9 11.7 7.2 7 10.1 13.3 3.6 6.2 8.8 6.5 9.1 11.6 2.8 5.3 7.9 ns ns ns 3 SDZS011 − APRIL 1990 PARAMETER MEASUREMENT INFORMATION 7V R1 From Output Under Test Test Point R2 CL (See Note A) LOAD CIRCUIT tf tr 3V Input (See Note B) 1.5 V Input (See Note C) 1.5 V 20% 0 tPHL tPLH In-Phase Output 1.5 V Out-of-Phase Output 1.5 V 80% 50% tPLH VOH 1.5 V VOL −950 mV 20% −1690 mV tPHL VOH In-Phase Output 1.5 V 1.5 V VOL tPLH tPHL 80% 50% tPLH tPHL VOH 1.5 V Out-of-Phase Output VOH 1.5 V 1.5 V VOL VOL VOLTAGE WAVEFORMS TTL-INPUT PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ECL-INPUT PROPAGATION DELAY TIMES NOTES: A. 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