ASIX
AX88850
100BASE-TX/FX Repeater Controller
ASIX AX88850
100BASE-TX/FX
Repeater Controller
Data Sheet(11/03/’97)
DOCUMENT NO. : AX850D2.DOC
This data sheets contain new products information. ASIX ELECTRONICS reserves the rights to modify the products
specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent
accompany the sale of the product.
ASIX ELECTRONICS CORPORATION
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500
FAX: 886-3-579-9558
AX88850
PRELIMINARY
CONTENTS
1.0 AX88850 OVERVIEW ......................................................................................................................................... 5
1.1 GENERAL DESCRIPTION ....................................................................................................................................... 5
1.2 FEATURES ............................................................................................................................................................ 6
1.3 BLOCK DIAGRAM................................................................................................................................................. 7
1.4 PIN CONNECTION DIAGRAM FOR AX88851 (16MII + 2MII MODE) .................................................................... 8
1.5 PIN CONNECTION DIAGRAM FOR AX88852 (8MII + 2MII MODE) ...................................................................... 9
1.6 PIN CONNECTION DIAGRAM FOR AX88853 (8PCS + 2MII MODE) ................................................................... 10
1.7 PIN CONNECTION DIAGRAM FOR AX88854 (MANAGEMENT MODE).................................................................. 11
2.0 PIN DESCRIPTION........................................................................................................................................... 12
2.1A PCS INTERFACE ............................................................................................................................................. 12
2.1B MII INTERFACE (SHARE BUS MII GROUP 0 PORT & MII GROUP 1 PORT) ........................................................ 13
2.2 MII INTERFACE ( TWO INDIVIDUAL MII PORTS ) ............................................................................................... 14
2.3 STATION MANAGEMENT INTERFACE.................................................................................................................. 15
2.4 MANAGEMENT INFORMATION BASE (MIB) INTERFACE ..................................................................................... 15
2.5 EXPANSION BUS INTERFACE .............................................................................................................................. 16
2.7 MISCELLANEOUS ............................................................................................................................................... 19
3.0 FUNCTIONAL DESCRIPTION ...................................................................................................................... 20
3.1 PCS INTERFACE LOGIC ...................................................................................................................................... 20
3.2 CARRIER INTEGRITY MONITOR STATE MACHINE ( AX88853 PCS MODE ONLY ).............................................. 20
3.3 REPEATER STATE MACHINE .............................................................................................................................. 20
3.4 JABBER STATE MACHINE ................................................................................................................................... 21
3.5 PARTITION STATE MACHINE .............................................................................................................................. 21
3.6 EXPANSION LOGIC(CASCADE INTERFACE)......................................................................................................... 22
3.7 MANAGEMENT LOGIC ........................................................................................................................................ 22
3.8 MANAGEMENT COUNTERS ................................................................................................................................. 23
3.9 STATION MANAGEMENT ACCESS INTERFACE .................................................................................................... 23
3.10 RID RECEIVE-TRANSMIT INTERFACE(DAISY CHAIN LOGIC) ........................................................................... 23
3.11 LED INTERFACE .............................................................................................................................................. 25
3.11.1 LED Status Driver wave-form for AX88851 ............................................................................................ 25
3.11.2 LED Status Driver wave-form for AX88852 ............................................................................................ 26
3.11.3 LED Status Driver wave-form for AX88853 ............................................................................................ 26
3.11.4 LED Status Driver wave-form for AX88854 ............................................................................................ 27
3.12 POWER ON CONFIGURATION(INITIAL SETTING) ............................................................................................... 27
4.0 REGISTERS........................................................................................................................................................ 28
4.1 PAGE 0 REGISTER MAP..................................................................................................................................... 28
4.2 PAGE 1 REGISTER MAP ..................................................................................................................................... 29
4.3 PAGE 2 REGISTER MAP..................................................................................................................................... 29
4.4 PAGE 3 REGISTER MAP..................................................................................................................................... 29
4.5 CONFIGURATION REGISTER (CONFIG) ............................................................................................................. 30
4.6 PAGE REGISTER (PAGE) ................................................................................................................................... 30
4.7 PARTITION STATUS REGISTER (PARTITION) ................................................................................................... 31
4.8 JABBER STATUS REGISTER (JABBER) .............................................................................................................. 31
4.9 ADMINISTRATION REGISTER (ADMIN) ............................................................................................................. 31
4.10 DEVICE ID REGISTER (DEVICEID) ................................................................................................................ 32
4.11 SILICON REVISION REGISTER ........................................................................................................................... 32
4.12 PORT MANAGEMENT COUNTER REGISTERS ..................................................................................................... 33
4.12.1 Short Event Counter Registers................................................................................................................. 33
4.12.2 Late Event Counter Registers .................................................................................................................. 33
4.12.3 Collision Counter Registers ..................................................................................................................... 33
4.12.4 Auto-Partition Counter Registers ............................................................................................................ 33
4.12.5 False Carrier Counter Registers.............................................................................................................. 33
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ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
5.0 ELECTRICAL SPECIFICATION AND TIMING ......................................................................................... 34
5.1 ABSOLUTE MAXIMUM RATINGS ........................................................................................................................ 34
5.2 GENERAL OPERATION CONDITIONS ................................................................................................................... 34
5.3 DC CHARACTERISTICS ...................................................................................................................................... 34
5.4 AC SPECIFICATIONS ........................................................................................................................................... 35
5.4.1 MII Interface Timing Tx & Rx................................................................................................................... 35
5.4.2 Station Management ................................................................................................................................. 36
5.4.3 PCS Interface Timing................................................................................................................................. 37
5.4.4 LED DISPLAY ........................................................................................................................................... 37
5.4.5 LED Display After Reset ........................................................................................................................... 38
5.4.6 Repeater ID Daisy Chain........................................................................................................................... 38
5.4.7 Expansion Bus............................................................................................................................................ 39
6.0 PACKAGE INFORMATION............................................................................................................................ 40
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ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
FIGURES
FIG - 1 CHIP BLOCK DIAGRAM (PCS MODE CONFIGURATION -- 8 PCS + 2 MII)..................................................................... 7
FIG - 2 CHIP BLOCK DIAGRAM(MII MODE CONFIGURATION -- 16 MII + 2 MII) ..................................................................... 7
FIG - 3 PIN CONNECTION DIAGRAM FOR 16MII MODE ............................................................................................................ 8
FIG - 4 PIN CONNECTION DIAGRAM FOR 8MII MODE .............................................................................................................. 9
FIG - 5 PIN CONNECTION DIAGRAM FOR 8PCS MODE .......................................................................................................... 10
FIG - 6 PIN CONNECTION DIAGRAM FOR MANAGEMENT MODE............................................................................................. 11
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ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
1.0 AX88850 Overview
The AX88850 series 100Mbps Repeater Controllers are designed for both low cost
dumb HUB and high performance intelligent HUB applications. The AX88850 series
product support up-to ten 100Mbps links with its 8 PCS (Physical coding sub-layer , also
called Symbol Interface) interfaces and 2 dedicated MII interfaces or supports up-to eighteen
100Mbps links with 2 shared 8 ports MII interfaces and 2 dedicated MII interfaces.
Maximum up-to 144 ports can be constructed when using expansion bus cascades 8
AX88850s. The AX88850 is designed base on IEEE 802.3u clause 27 “ Repeater for
100Mb/s base-band networks” . It is fully compatible with IEEE 802.3u standard.
1.1 General Description
The AX88850 Repeater Controller is a subset of a repeater set containing all the
repeater-specific components and functions, exclusive of PHY components and functions.
The AX88850 family has two kind of interfaces to connect to PHY devices. There are
Physical coding sub-layer (PCS) interface and Media Independent Interface (MII).
The AX88850 supports 8 PCS ports interface or 2 shared bus (8 ports/per bus) MII
interfaces, 2 dedicated MII ports interface, an expansion port interface, a management
information base IC interface, a repeater ID daisy chain interface, a serial register interface
and LED display interface.
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ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
1.2 Features
•
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IEEE 802.3u repeater compatible
Supports 10 or 18 network connections optional configuration.
8 PCS interfaces direct interface to PHY chip with PCS interface ( ie.LUC3X04,
KS8761, QSI6611, NWK914 ) to save user cost
16 MII interfaces to double the network connections.
2 dedicated MII interfaces can also support 100BASE-T4/FX PHY interfaces
The 2 dedicated MII interfaces can also easily connect to MII interface of 100BASE
MAC controller for network management purpose or other bridging devices.
Up-to 8 repeater chips can be cascaded for large HUB application
Low latency design supports Class II repeater implementation with large port number.
All ports can be separately isolated or partitioned in response to fault condition
Separate jabber and partition state machines for each port
Separate carrier integrity monitor state machines for each port to protect network from
some transient fault conditions (AX88853 PCS mode only)
Management interface for AX88856 (MIB IC) allows all repeater MIBs to be maintained
Large per-port management counters to reduce CPU overhead
External pins setup or automatic daisy chain channel setup repeater ID.
Per-port LED display for Jabber, Partition, Link/Activity. Global utilization and
collision (%) presentation.
Power on LED diagnosis. All the LED display will follow the “ON-OFF-ON-OFFNormal” operation procedure during/after power on reset.
Dedicated collision LED display
208-pin PQFP
The AX88850 Family has the following members:
AX88851
AX88852
AX88853
AX88854
AX88856
16 shared MII ports + 2 dedicated MII ports
8 shared MII ports + 2 dedicated MII ports
8 PCS (Symbol) Interface ports + 2 dedicated MII ports
AX88851 + AX88853 + management function
MIB co-processor for intelligent Hub applications
Function availability list
Parts Number 16MII + 2MII
4
AX88851
AX88852
AX88853
4
AX88854
8MII + 2MII
8PCS + 2MII Management I/F
4
4
4
4
6
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ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
1.3 Block Diagram
sym
I /F
Q -P H Y
4 B /5 B
P er p o rt J a b b er ctl,
a u t o - p a r t it i o n S M &
C o d in g /
D ec o d in g
P e r p o r t C o ll is io n ,
P a r t it i o n c o u n t e r s .
R eg iste rs
M I B I /F
&
S rr a m b ler/
D escr a m b le r
P ort 7 )
Q -P H Y
M II
PHY
I /F
........
(P o rt 1 -
MUX
R e c o n c ili a tio n
C ascad e
A r b it r a t io n
L o g ic
R e p e a t e r S ta t e
M a c h in e
E l a s t i c it y B u f f e r
C o ll is io n H a n d l in g L o g ic
P ort 8 P ort 9
PHY
Fig - 1 Chip Block Diagram (PCS mode configuration -- 8 PCS + 2 MII)
M II
I /F
M II
in te r fa c e
R e c o n c ilia tio n la y e r
Q -P H Y
Q -P H Y
P e r p o r t J a b b e r c tl,
a u to -p a r titio n S M &
R e g is te r s
M I B I /F
P e r p o r t C o llis io n ,
P a r titio n c o u n te r s .
P ort 0 P ort 7
M II
I /F
M II
in te r fa c e
R e c o n c ilia tio n la y e r
P ort 10 P ort 17
Q -P H Y
PHY
M II
I /F
M II
P ort 8
........
Q -P H Y
R e p e a te r S ta te
M a c h in e
MUX
E la stic ity B u ffe r
C ascad e
A r b itr a tio n
L o g ic
C o llis io n H a n d lin g L o g ic
P ort 9
PHY
Fig - 2 Chip Block Diagram(MII mode configuration -- 16 MII + 2 MII)
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ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
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VDD
MD
IRD_ODIR
VSS
/IR_ACTO<7>
/IR_ACTO<6>
/IR_ACTO<5>
/IR_ACTO<4>
/IR_ACTO<3>
/IR_ACTO<2>
/IR_ACTO<1>
/IR_ACTO<0>
VSS
/IR_ACTI<7>
/IR_ACTI<6>
/IR_ACTI<5>
/IR_ACTI<4>
/IR_ACTI<3>
/IR_ACTI<2>
/IR_ACTI<1>
/IR_ACTI<0>
RST_DLY
DAISY_OUT
DAISY_IN
VDD1
VSS1
MEDIA
OPTION
VDD
/COLLED
LED_SYN
LED<7>
LED<6>
LED<5>
LED<4>
VSS
LED<3>
LED<2>
LED<1>
LED<0>
NC
NC
NC
VSS
NC
NC
NC
MTX_RDY
OPT1
CRS<1>
RX_DV<1>
RX_CLK<1>
1.4 Pin Connection Diagram for AX88851 (16MII + 2MII mode)
RID<0>
RID<1>
RID<2>
RID<3>
RID<4>
/DIS_DAISY
/TO_ID_CLR
/IR_ACT_EN
104
103
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AX 88851
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(16 MII Mode)
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RX_ER<1>
VDD
RXD<1><3>
RXD<1><2>
RXD<1><1>
RXD<1><0>
TX_EN<1>
TXD<3>
TXD<2>
TXD<1>
TXD<0>
VSS
TX_ER
COL
CRS<0>
RX_DV<0>
RX_CLK<0>
RX_ER<0>
RXD<0><3>
RXD<0><2>
RXD<0><1>
RXD<0><0>
TX_EN<0>
OPT0
VDD1
VSS1
M1_RXEN7
M1_RXEN6
M1_RXEN5
M1_RXEN4
M1_TXEN7
VDD
NC
NC
NC
NC
NC
NC
NC
M1_TXEN6
M1_TXEN5
M1_TXEN4
M1_RXEN3
M1_RXEN2
VSS
M1_RXEN1
NC
NC
M1_CRS7
M1_CRS6
M1_CRS5
M1_CRS4
VDD
NC
M0_TXEN6
M0_TXEN7
M0_RXEN4
M0_RXEN5
M0_RXEN6
M0_RXEN7
VSS
M0_RXD0
M0_RXD1
M0_RXD2
M0_RXD3
M0_RXER
M0_RX_CLK
M0_RXDV
VDD
M0_TXD0
M0_TXD1
M0_TXD2
M0_TXD3
M0_TXER
VSS
M1_RXD0
M1_RXD1
M1_RXD2
VDD1
VSS1
M1_RXD3
M1_RXER
M1_RXCLK
M1_RXDV
VDD
M1_TXD0
M1_TXD1
M1_TXD2
M1_TXD3
M1_TXER
VSS
M1_CRS0
M1_CRS1
M1_CRS2
M1_CRS3
NC
NC
NC
M1_TXEN0
M1_TXEN1
M1_TXEN2
M1_TXEN3
M1_RXEN0
VDD
157
158
159
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96
IRD_CK
/IRD_V
/IRD_ER
VSS
IRD<0>
IRD<1>
IRD<2>
IRD<3>
/RST
TEST
VSS
LCLK
NC
NC
VDD
GEP<0>
GEP<1>
GEP<2>
GEP<3>
VSS
NC
NC
NC
NC
NC
NC
NC
VDD1
VSS1
M0_TXEN0
M0_TXEN1
M0_TXEN2
M0_TXEN3
M0_RXEN0
M0_CRS0
M0_CRS1
M0_CRS2
M0_CRS3
NC
NC
NC
VSS
M0_RXEN1
M0_RXEN2
M0_RXEN3
M0_TXEN4
M0_TXEN5
M0_CRS4
M0_CRS5
M0_CRS6
M0_CRS7
NC
Fig - 3 Pin Connection Diagram for 16MII Mode
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RID<0> 143
RID<1> 142
RID<2> 141
RID<3> 140
RID<4> 139
/DIS_DAISY 138
137
/TO_ID_CLR
/IR_ACT_EN 136
135
134
133
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IRD_CK
/IRD_V
/IRD_ER
VSS
IRD<0>
IRD<1>
IRD<2>
IRD<3>
/RST
TEST
VSS
LCLK
NC
NC
VDD
GEP<0>
GEP<1>
GEP<2>
GEP<3>
VSS
NC
NC
NC
NC
NC
NC
NC
VDD1
VSS1
M0_TXEN0
M0_TXEN1
M0_TXEN2
M0_TXEN3
M0_RXEN0
M0_CRS0
M0_CRS1
M0_CRS2
M0_CRS3
NC
NC
NC
VSS
M0_RXEN1
M0_RXEN2
M0_RXEN3
NC
NC
NC
NC
NC
NC
NC
VDD
NC
NC
NC
NC
NC
NC
NC
VSS
M0_RXD0
M0_RXD1
M0_RXD2
M0_RXD3
M0_RXER
M0_RX_CLK
M0_RXDV
VDD
M0_TXD0
M0_TXD1
M0_TXD2
M0_TXD3
M0_TXER
VSS
M1_RXD0
M1_RXD1
M1_RXD2
VDD1
VSS1
M1_RXD3
M1_RXER
M1_RXCLK
M1_RXDV
VDD
M1_TXD0
M1_TXD1
M1_TXD2
M1_TXD3
M1_TXER
VSS
M1_CRS0
M1_CRS1
M1_CRS2
M1_CRS3
NC
NC
NC
M1_TXEN0
M1_TXEN1
M1_TXEN2
M1_TXEN3
M1_RXEN0
VDD
VDD
MD
IRD_ODIR
VSS
/IR_ACTO<7>
/IR_ACTO<6>
/IR_ACTO<5>
/IR_ACTO<4>
/IR_ACTO<3>
/IR_ACTO<2>
/IR_ACTO<1>
/IR_ACTO<0>
VSS
/IR_ACTI<7>
/IR_ACTI<6>
/IR_ACTI<5>
/IR_ACTI<4>
/IR_ACTI<3>
/IR_ACTI<2>
/IR_ACTI<1>
/IR_ACTI<0>
RST_DLY
DAISY_OUT
DAISY_IN
VDD1
VSS1
MEDIA
OPTION
VDD
/COLLED
LED_SYN
LED<7>
LED<6>
LED<5>
LED<4>
VSS
LED<3>
LED<2>
LED<1>
LED<0>
NC
NC
NC
VSS
NC
NC
NC
MTX_RDY
OPT1
CRS<1>
RX_DV<1>
RX_CLK<1>
AX88850
PRELIMINARY
1.5 Pin Connection Diagram for AX88852 (8MII + 2MII mode)
ASIX
AX 88852
(8 MII Mode)
9
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RX_ER<1>
VDD
RXD<1><3>
RXD<1><2>
RXD<1><1>
RXD<1><0>
TX_EN<1>
TXD<3>
TXD<2>
TXD<1>
TXD<0>
VSS
TX_ER
COL
CRS<0>
RX_DV<0>
RX_CLK<0>
RX_ER<0>
RXD<0><3>
RXD<0><2>
RXD<0><1>
RXD<0><0>
TX_EN<0>
OPT0
VDD1
VSS1
NC
NC
NC
NC
NC
VDD
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
M1_RXEN3
M1_RXEN2
VSS
M1_RXEN1
NC
NC
NC
NC
NC
NC
Fig - 4 Pin Connection Diagram for 8MII Mode
ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
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VDD
MD
IRD_ODIR
VSS
/IR_ACTO<7>
/IR_ACTO<6>
/IR_ACTO<5>
/IR_ACTO<4>
/IR_ACTO<3>
/IR_ACTO<2>
/IR_ACTO<1>
/IR_ACTO<0>
VSS
/IR_ACTI<7>
/IR_ACTI<6>
/IR_ACTI<5>
/IR_ACTI<4>
/IR_ACTI<3>
/IR_ACTI<2>
/IR_ACTI<1>
/IR_ACTI<0>
RST_DLY
DAISY_OUT
DAISY_IN
VDD1
VSS1
MEDIA
OPTION
VDD
/COLLED
LED_SYN
LED<7>
LED<6>
LED<5>
LED<4>
VSS
LED<3>
LED<2>
LED<1>
LED<0>
NC
NC
NC
VSS
NC
NC
NC
MTX_RDY
OPT1
CRS<1>
RX_DV<1>
RX_CLK<1>
1.6 Pin Connection Diagram for AX88853 (8PCS + 2MII mode)
RID<0>
RID<1>
RID<2>
RID<3>
RID<4>
/DIS_DAISY
/TO_ID_CLR
/IR_ACT_EN
104
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AX88853
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11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
(PCS Mode)
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
RX_ER<1>
VDD
RXD<1><3>
RXD<1><2>
RXD<1><1>
RXD<1><0>
TX_EN<1>
TXD<3>
TXD<2>
TXD<1>
TXD<0>
VSS
TX_ER
COL
CRS<0>
RX_DV<0>
RX_CLK<0>
RX_ER<0>
RXD<0><3>
RXD<0><2>
RXD<0><1>
RXD<0><0>
TX_EN<0>
OPT0
VDD1
VSS1
TDATA<7><4>
TDATA<7><3>
TDATA<7><2>
TDATA<7><1>
TDATA<7><0>
VDD
RSD<7>
RSCLK<7>
RDATA<7><4>
RDATA<7><3>
RDATA<7><2>
RDATA<7><1>
RDATA<7><0>
TDATA<6><4>
TDATA<6><3>
TDATA<6><2>
TDATA<6><1>
TDATA<6><0>
VSS
RSD<6>
RSCLK<6>
RDATA<6><4>
RDATA<6><3>
RDATA<6><2>
RDATA<6><1>
RDATA<6><0>
VDD
RSCLK<2>
RSD<2>
TDATA<2><0>
TDATA<2><1>
TDATA<2><2>
TDATA<2><3>
TDATA<2><4>
VSS
RDATA<3><0>
RDATA<3><1>
RDATA<3><2>
RDATA<3><3>
RDATA<3><4>
RSCLK<3>
RSD<3>
VDD
TDATA<3><0>
TDATA<3><1>
TDATA<3><2>
TDATA<3><3>
TDATA<3><4>
VSS
RDATA<4><0>
RDATA<4><1>
RDATA<4><2>
VDD1
VSS1
RDATA<4><3>
RDATA<4><4>
RSCLK<4>
RSD<4>
VDD
TDATA<4><0>
TDATA<4><1>
TDATA<4><2>
TDATA<4><3>
TDATA<4><4>
VSS
RDATA<5><0>
RDATA<5><1>
RDATA<5><2>
RDATA<5><3>
RDATA<5><4>
RSCLK<5>
RSD<5>
TDATA<5><0>
TDATA<5><1>
TDATA<5><2>
TDATA<5><3>
TDATA<5><4>
VDD
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
96
IRD_CK
/IRD_V
/IRD_ER
VSS
IRD<0>
IRD<1>
IRD<2>
IRD<3>
/RST
TEST
VSS
LCLK
NC
NC
VDD
GEP<0>
GEP<1>
GEP<2>
GEP<3>
VSS
RDATA<0><0>
RDATA<0><1>
RDATA<0><2>
RDATA<0><3>
RDATA<0><4>
RSCLK<0>
RSD<0>
VDD1
VSS1
TDATA<0><0>
TDATA<0><1>
TDATA<0><2>
TDATA<0><3>
TDATA<0><4>
RDATA<1><0>
RDATA<1><1>
RDATA<1><2>
RDATA<1><3>
RDATA<1><4>
RSCLK<1>
RSD<1>
VSS
TDATA<1><0>
TDATA<1><1>
TDATA<1><2>
TDATA<1><3>
TDATA<1><4>
RDATA<2><0>
RDATA<2><1>
RDATA<2><2>
RDATA<2><3>
RDATA<2><4>
Fig - 5 Pin Connection Diagram for 8PCS Mode
10
ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
VDD
MD
IRD_ODIR
VSS
/IR_ACTO<7>
/IR_ACTO<6>
/IR_ACTO<5>
/IR_ACTO<4>
/IR_ACTO<3>
/IR_ACTO<2>
/IR_ACTO<1>
/IR_ACTO<0>
VSS
/IR_ACTI<7>
/IR_ACTI<6>
/IR_ACTI<5>
/IR_ACTI<4>
/IR_ACTI<3>
/IR_ACTI<2>
/IR_ACTI<1>
/IR_ACTI<0>
RST_DLY
DAISY_OUT
DAISY_IN
VDD1
VSS1
MEDIA
OPTION
VDD
/COLLED
LED_SYN
LED<7>
LED<6>
LED<5>
LED<4>
VSS
LED<3>
LED<2>
LED<1>
LED<0>
SMDC
SMDIO
/SMDV
VSS
BSMDC
BSMDIO
SMDIR
MTX_RDY
OPT1
CRS<1>
RX_DV<1>
RX_CLK<1>
1.7 Pin Connection Diagram for AX88854 (Management mode)
RID<0>
RID<1>
RID<2>
RID<3>
RID<4>
/DIS_DAISY
/TO_ID_CLR
/IR_ACT_EN
104
103
102
101
100
99
98
97
ASIX
AX 88854
M0_TXEN0
M0_TXEN1
M0_TXEN2
M0_TXEN3
M0_RXEN0
M0_CRS0
M0_CRS1
M0_CRS2
M0_CRS3
M1_RXEN7
M1_RXEN6
M1_RXEN5
M1_RXEN4
M1_TXEN7
(Management Mode)
M1_TXEN6
M1_TXEN5
M1_TXEN4
M1_RXEN3
M1_RXEN2
M0_RXEN1
M0_RXEN2
M0_RXEN3
M0_TXEN4
M0_TXEN5
M0_CRS4
M0_CRS5
M0_CRS6
M0_CRS7
M1_RXEN1
VDD
RSCLK<2>
RSD<2>
TDATA<2><0>
TDATA<2><1>
TDATA<2><2>
TDATA<2><3>
TDATA<2><4>
VSS
M0_RXD0 RDATA<3><0>
M0_RXD1 RDATA<3><1>
M0_RXD2 RDATA<3><2>
M0_RXD3 RDATA<3><3>
M0_RXER RDATA<3><4>
M0_RX_CLK
RSCLK<3>
RSD<3>
M0_RXDV
VDD
TDATA<3><0>
M0_TXD0
TDATA<3><1>
M0_TXD1
TDATA<3><2>
M0_TXD2
TDATA<3><3>
M0_TXD3
M0_TXER TDATA<3><4>
VSS
M1_RXD0 RDATA<4><0>
RDATA<4><1>
M1_RXD1
M1_RXD2 RDATA<4><2>
VDD1
VSS1
M1_RXD3 RDATA<4><3>
RDATA<4><4>
M1_RXER
RSCLK<4>
M1_RXCLK
RSD<4>
M1_RXDV
VDD
TDATA<4><0>
M1_TXD0
TDATA<4><1>
M1_TXD1
M1_TXD2
TDATA<4><2>
M1_TXD3
TDATA<4><3>
M1_TXER
TDATA<4><4>
VSS
RDATA<5><0>
M1_CRS0
RDATA<5><1>
M1_CRS1
RDATA<5><2>
M1_CRS2
RDATA<5><3>
M1_CRS3
RDATA<5><4>
RSCLK<5>
RSD<5>
TDATA<5><0>
M1_TXEN0
TDATA<5><1>
M1_TXEN1
TDATA<5><2>
M1_TXEN2
TDATA<5><3>
M1_TXEN3
M1_RXEN0
TDATA<5><4>
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
M1_CRS7
M1_CRS6
M1_CRS5
M1_CRS4
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
RX_ER<1>
VDD
RXD<1><3>
RXD<1><2>
RXD<1><1>
RXD<1><0>
TX_EN<1>
TXD<3>
TXD<2>
TXD<1>
TXD<0>
VSS
TX_ER
COL
CRS<0>
RX_DV<0>
RX_CLK<0>
RX_ER<0>
RXD<0><3>
RXD<0><2>
RXD<0><1>
RXD<0><0>
TX_EN<0>
OPT0
VDD1
VSS1
TDATA<7><4>
TDATA<7><3>
TDATA<7><2>
TDATA<7><1>
TDATA<7><0>
VDD
RSD<7>
RSCLK<7>
RDATA<7><4>
RDATA<7><3>
RDATA<7><2>
RDATA<7><1>
RDATA<7><0>
TDATA<6><4>
TDATA<6><3>
TDATA<6><2>
TDATA<6><1>
TDATA<6><0>
VSS
RSD<6>
RSCLK<6>
RDATA<6><4>
RDATA<6><3>
RDATA<6><2>
RDATA<6><1>
RDATA<6><0>
M0_TXEN6
M0_TXEN7
M0_RXEN4
M0_RXEN5
M0_RXEN6
M0_RXEN7
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
96
IRD_CK
/IRD_V
/IRD_ER
VSS
IRD<0>
IRD<1>
IRD<2>
IRD<3>
/RST
TEST
VSS
LCLK
NC
NC
VDD
GEP<0>
GEP<1>
GEP<2>
GEP<3>
VSS
RDATA<0><0>
RDATA<0><1>
RDATA<0><2>
RDATA<0><3>
RDATA<0><4>
RSCLK<0>
RSD<0>
VDD1
VSS1
TDATA<0><0>
TDATA<0><1>
TDATA<0><2>
TDATA<0><3>
TDATA<0><4>
RDATA<1><0>
RDATA<1><1>
RDATA<1><2>
RDATA<1><3>
RDATA<1><4>
RSCLK<1>
RSD<1>
VSS
TDATA<1><0>
TDATA<1><1>
TDATA<1><2>
TDATA<1><3>
TDATA<1><4>
RDATA<2><0>
RDATA<2><1>
RDATA<2><2>
RDATA<2><3>
RDATA<2><4>
Fig - 6 Pin Connection Diagram for Management Mode
11
ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
2.0 Pin Description
2.1A PCS interface
Signal Name
Type Pin No.
Description
RDATA[0][4:0]
RDATA[1][4:0]
RDATA[2][4:0]
RDATA[3][4:0]
RDATA[4][4:0]
I/PU 181-177, Receive Symbol Data : Data is input synchronously with the rising edge of
I/PD* 195-191 RSCLK
I/PD* 208-204
I/PD*
14-10
I/PD* 30,29,2624
RDATA[5][4:0]
I/PD*
44-40
RDATA[6][4:0]
I/PD*
57-53
RDATA[7][4:0]
I/PU
70-66
RSCLK[0]
I
182
Receive Symbol Clock : This 25Mhz input signal is phase-locked to the
RSCLK[1]
I
196
incoming signal at PHY. RSCLK is used to clock in received data from the
RSCLK[2]
I
2
RDATA[4:0] data bus.
RSCLK[3]
I
15
RSCLK[4]
I
31
RSCLK[5]
I
45
RSCLK[6]
I
58
RSCLK[7]
I
71
Receive Signal Detect : This asynchronous input signal indicates that the
183
I /PD
RSD[0]
receive signal is above the detection threshold and will be used for link test
197
I/PD
RSD[1]
state machine.
3
I/PD
RSD[2]
16
I/PD
RSD[3]
32
I/PD
RSD[4]
46
I/PD
RSD[5]
59
I/PD
RSD[6]
72
I/PD
RSD[7]
O/L 190-186 Transmit Symbol Data : These signals are 4B/5B encoded transmit data
TDATA[0][4:0]
O/L 203-199 symbol, driven at the rising edge of local 25Mhz clock. LCLK
TDATA[1][4:0]
8-4
O/L
TDATA[2][4:0]
O/H** 22-18
TDATA[3][4:0]
O/H** 38-34
TDATA[4][4:0]
O/L
51-47
TDATA[5][4:0]
65-61
TDATA[6][4:0]
O/L
78-74
TDATA[7][4:0]
O/L
* RDATA[1:6][4] are pull up.
** TDATA[3][4] and TDATA[4][4] drive capability are MH
Note : “Type” has the following attributes
I : Input
O : Output
I/O : Bi-direction
PU : Pull Up
PD : Pull Down
H : Driving High Current 16mA
MH : Driving Middle High Current 12mA
ML : Driving Middle Low Current 8mA
L : Driving Low Current 4mA
12
ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
2.1B MII interface (share bus MII group 0 port & MII group 1 port)
M0 -- MII group 0 ; M1 -- MII group 1
Signal Name
M0_TX_ER
M1_TX_ER
M0_TXD[3:0]
M1_TXD[3:0]
Type Pin No.
O/ML
O/ML
O/H
O/H
M0_TX_EN[7:0]
O/L
M1_TX_EN[7:0]
O/L
M0_RXD[3:0]
M1_RXD[3:0]
M0_RX_ER
M1_RX_ER
I/PU
I/PU
I/PD
I/PD
M0_RX_CLK
M1_RX_CLK
I
I
M0_RX_DV
M1_RX_DV
M0_CRS[7:0]
I/PD
I/PD
I/PD
M1_CRS[7:0]
I/PD
M0_RX_EN[7:0]
O/L
M1_RX_EN[7:0]
O/L
Description
22
38
21-18
37-34
Transmit Error : TX_ER is transition synchronously with respect to the rising
edge of TX_CLK . Asserted high when a code violation is request to be send
Transmit Data : TXD[3:0] is transition synchronously with respect to the
rising edge of TX_CLK. For each TX_CLK period in which TX_EN is
asserted, TXD[3:0] are accepted for transmission by the PHY.
4,3,203, Transmit Enable : TX_EN is transition synchronously with respect to the
202, rising edge of TX_CLK. TX_EN indicates that the port is presenting nibbles
189-186 on TXD [3:0] for transmission.
74,65-63,
50-47
13-10 Receive Data : RXD [3:0] is driven by the PHY synchronously with respect to
29,26-24 RX_CLK.
14
Receive Error : RX_ER ,is driven by PHY and synchronous to RX_CLK, is
30
asserted for one or more RX_CLK periods to indicate to the port that an error
has detected.
15
Receive Clock : RX_CLK is a continuous clock that provides the timing
31
reference for the transfer of the RX_DV,RXD [3:0] and RX_ER signals from
the PHY to the MII port of the repeater.
16
Receive Data Valid : RX_DV is driven by the PHY synchronously with
32
respect to RX_CLK. Asserted high when valid data is present on RXD [3:1].
207-204, Carrier Sense : Asynchronous signal CRS is asserted by the PHY when either
194-191 the transmit or receive medium is non-idle.
56-53,
43-40
8-4, Receive Enable : Assert high to the respective PHY chip to enable its receive
201-199, data.
190
78-75,
62,61,59,
51
13
ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
2.2 MII interface ( two individual MII ports )
Signal Name
Type Pin No.
TX_ER
(share)
TXD[3:0]
(share)
O/ML
TX_EN[0]
TX_EN[1]
O/L
O/L
RXD[0][3:0]
RXD[1][3:0]
RX_ER[0]
RX_ER[1]
I/PU
I/PU
I/PD
I/PD
RX_CLK[0]
RX_CLK[1]
I
I
RX_DV[0]
RX_DV[1]
CRS[0]
CRS[1]
COL
(share)
I/PD
I/PD
I/PD
I/PD
O/ML
OPT0
OPT1
O/ML
I/PU
I/PU
Description
92
Transmit Error : TX_ER is transition synchronously with respect to the rising
edge of TX_CLK . Asserted high when a code violation is request to be send
97-94 Transmit Data : TXD[3:0] is transition synchronously with respect to the
rising edge of TX_CLK. For each TX_CLK period in which TX_EN is
asserted, TXD[3:0] are accepted for transmission by the PHY.
82
Transmit Enable : TX_EN is transition synchronously with respect to the
98
rising edge of TX_CLK. TX_EN indicates that the port is presenting nibbles
on TXD [3:0] for transmission.
86-83 Receive Data : RXD [3:0] is driven by the PHY synchronously with respect to
102-99 RX_CLK.
87
Receive Error : RX_ER ,is driven by PHY and synchronous to RX_CLK, is
104
asserted for one or more RX_CLK periods to indicate to the port that an error
has detected.
88
Receive Clock : RX_CLK is a continuous clock that provides the timing
105
reference for the transfer of the RX_DV,RXD [3:0] and RX_ER signals from
the PHY to the MII port of the repeater.
89
Receive Data Valid : RX_DV is driven by the PHY synchronously with
106
respect to RX_CLK. Asserted high when valid data is present on RXD [3:1].
90
Carrier Sense : Asynchronous signal CRS is asserted by the PHY when either
107
the transmit or receive medium is non-idle.
91
Collision Signal :This pin indicates collision(s) , that occurred at the collision
domain of the hub, to MII interface devices. Both the MII port use this signal
commonly.
81
108
Option for external device type : Default ‘high’ is for PHY type device.
Otherwise, ‘low’ for MAC type device.
14
ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
2.3 Station Management Interface
Signal Name
Type Pin No.
SMDC
I
116
SMDIO
I/O/L
/PU
115
/SMDV
I/PU
114
SMDIR
O/L
110
BSMDC
O/L
112
BSMDIO
I/O/L
/PU
111
Description
Station Management Data Clock : The timing reference for MDIO. All data
transfers on MDIO are synchronized to the rising edge of this clock. MDC is
limited to a maximum frequency of 2.5MHz.
Station Management Data Input / Output : Serial data input/output transfers
from/to the internal registers or PHYs . The transfer protocol conforms to the
IEEE 802.3u MII specification.
Station Management Data Valid : Asserted when a valid read/write command
is present.
Station Management Data Direction : Direction signal for an external bidirectional buffer on the MDIO signal.
0 = MDIO data flows into the AX88850
1 = MDIO data flows out of the AX88850
Defaults to 0 when no register access is present.
Buffered Station Management Data Clock : Buffered MDC signal. Allow
more devices to be chained on the MII serial bus.
Buffered Station Management Data Input /Output : Buffered MDIO signal.
When the “PHY_access” bit in the CONFIG register is set High, the MDIO
signal is passed through to BMDIO for accessing the physical device chips.
2.4 Management Information Base (MIB) Interface
Signal Name
MD
MTX_RDY
Type Pin No.
I/O/Z
/MH
/PU
O/L
155
109
Description
Management Data : Outputs management information for the AX88856 MIB
chip. This signal carries with RID_CH signal and port number of the incoming packet and is synchronous to IRD_CK signal.
Repeated Packet Ready : Repeated packet data ready to copy to MIB chip
indicator.
15
ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
2.5 Expansion Bus Interface
Signal Name
IRD[3:0]
/IRD_ER
/IRD_V
IRD_CK
IRD_ODIR
/IR_ACTO
[7:0]
/IR_ACTI[7:0]
Type Pin No.
I/O/Z
/MH
/PU
I/O/Z
/MH
/PU
I/O/Z
/MH
/PU
I/O/Z
/MH
O/L
Description
164-161 INTER REPEATER DATA : Nibble data input/output. Transfer data from
the “active” AX88850 to all other “inactive” AX88850s. The bus-master of
the IRD bus is determined by IR_VECT bus arbitration.
159
INTER REPEATER DATA ERROR: This signal reflect the RX_ER status
of the active port across the inter repeater bus. Used to track receive errors
from the PHY in real time.
158
INTER REPEATER DATA VALID : This signal reflect the RX_DV status
of the active port across the inter repeater bus. Used to frame good packets.
157
INTER REPEATER CLOCK VALID : All inter repeater signals are
synchronized to the rising edge of this clock.
154
INTER REPEATER DATA IN/OUT DIRECTION : This pin indicates the
direction of data for external transceiver.
“High” = IRD[3:0], /IRD_ER, /IRD_V , IRD_CK are Output.
“Low” = IRD[3:0], /IRD_ER, /IRD_V , IRD_CK are Input.
I/O/OC 152-145 INTER REPEATER ACTIVITY IN/OUT: Then the local repeater activity
/H
appearance, the signal of the related RID (Repeater ID) will be asserted and as
a output pin. All other pins serve as input pins but except the collision
conditions. When collision occurred all of the signal of related (RID-1) pins
will served as outputs and will active during local collision period. The
exception case is when RID = 0, then (RID-1) is replaced with (RID+1)=1.
I/PU 143-136 INTER REPEATER ACTIVITY IN: These pins perform the same function
as /IR_ACTO[7:0] when they serve as input function. Then the
/IR_ACTO[7:0] insert external buffers the input function must be replaced
with /IR_ACTI [7:0].
The /IR_ACTI[7:0] also serve as power-on configuration input:
or
140-136 Repeater Identification Number Parallel In RID[4:0]: When power on reset
these pin as inputs to setup the repeater ID of the chip. RID[2:0] indicate the
repeater ID from 0 to 7. RID[4:3] defines the group code in the cascade
system and must keep difference with PHY ID address definition.
RID[4:0]
/IR_ACTI[4:0]
I/PU
/DIS_DAISY
/IR_ACTI[5]
I/PU
141
Disable RID Daisy-chain Input. No matter what kind of data input from
DAISY_IN pin ,the repeater ID will never be changed from DAIST_IN.
/TO_ID_CLR
/IR_ACTI[6]
I/PU
142
Time Out to Clear repeater ID : Within the time out period, if no daisy chain
repeater ID input. The repeater ID will be clear to RID=0 . Otherwise, the
repeater ID will remain the previous value ( power on configured value ,
previous daisy chain reconfigured value or the configuration value written via
station management port).The tome out period is about 4 to 5 second.
/IR_ACT_EN
/IR_ACTI[7]
I/PU
143
/IR_ACTI[7:0] pins function is enable when IR_ACT_EN is pulled “low”
when power on. Otherwise , it is disable.
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PRELIMINARY
2.6 LED Display
Signal Name
LED[7:0]
Type Pin No.
O/L
Description
125-122, LED Display Information : Those signals indicate each port‘s Partition,
120-117 Jabber, Link/Activity, Utilization % (global), Collision % (global) in
sequence. For detail , see the LED timing specification
The Utilization % display define as following :
Group0 [ U4 :U0 ]
Utilization %
0
1
5
15
30
60
LED4
1
1
1
1
1
0
LED3
1
1
1
1
0
0
LED2
1
1
1
0
0
0
LED1
1
1
0
0
0
0
LED0
1
0
0
0
0
0
LED3
1
1
1
1
0
0
LED2
1
1
1
0
0
0
LED1
1
1
0
0
0
0
LED0
1
0
0
0
0
0
Group1 [ UU4 :UU0 ]
Utilization %
0
2
10
20
40
80
LED4
1
1
1
1
1
0
The Collision % display define as following :
Group0 [ C4 :C0 ]
Collision %
0
1
2
5
10
15
LED4
1
1
1
1
1
0
LED3
1
1
1
1
0
0
LED2
1
1
1
0
0
0
LED1
1
1
0
0
0
0
LED0
1
0
0
0
0
0
LED3
1
1
1
1
0
0
LED2
1
1
1
0
0
0
LED1
1
1
0
0
0
0
LED0
1
0
0
0
0
0
Group1 [ CC4 :CC0 ]
Collision %
0
4
8
20
30
60
LED_SYN
O/L
126
/COLLED
O/MH
127
LED4
1
1
1
1
1
0
LED status synchronous signal : The signal is a LED_CK period width signal
and repeated every 16 cycle. When high indicate the next cycle on the
LED[7:0] bus show the Partition status of port 8 to 0 respectively.
Collision LED Display : When Collision occur, the signal will
be “LOW” about 52.4 ms.
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PRELIMINARY
2.7 Miscellaneous
Signal Name
LCLK or
TX_CLK
/RST
RST_DLY
DAISY_IN
DAISY_OUT
TEST
GEP[3:0]
MEDIA
OPTION
VDD
VSS
Type Pin No.
I
168
I
O/L
165
135
Description
Local Clock : Must be run at 25Mhz . Used for transmit data to PHY devices,
Reset : The chip is reset when this signal is asserted Low.
Reset Delay : The signal is active high when reset and delay /RST signal
about 2 LCLK cycle. It is useful for power on configuration setup control of
/IR_ACTI[7:0].
I/PU
133
Repeater Identification Number Daisy-Chain In : This pin is a daisy chain
serial input for Repeater ID. A state machine always monitor the input if a
correct data (RID) present at the pin, the (RID+1) will be written to RID
register and override the power on setup RID for the chip.
O/L
134
Repeater Identification Number Daisy-Chain Out : This pin is periodically
shift out the RID of itself to the next chained chip to inform that this ID has
already been occupied. The RID is shift out periodically every about 200us.
I/PD
166
Test Pin : The pin is just for test mode setting purpose only. Must be pull low
when normal operation. When in test mode , GEP pins will be force to test
input signals.
I/O/L 175-172 General Purpose I/O Pins : Those pins just for system application usage. I.e.
/PU
for output control or input status report.
When reset the default function is for inputs.
I/PD
130
Media selection :
External pull-down for AX88853 with 4.7K ohm resister.
External pull-up for AX88851, AX88852 and AX88854 with 4.7K ohm
resister.
I/PU
129
Option : Option for repeater state machine. User must pull this pin up.
I
1,17,27, POWER : +5V +/-5%
33,52,73,
80,103,
128,132,
156,171,
184
I
9,23,28, POWER: 0V
39,60,79,
93,113,
121,131,
144,153,
160,167,
176,185,
198
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AX88850
PRELIMINARY
3.0 Functional Description
3.1 PCS interface logic
The PCS logic performs PCS / MII receiving / transmitting interface. When it receives, first deciphers the signals from
RDATA<4:0>, then do symbol alignment after detecting /J/K/ codes, then data is aligned to do 5B/4B decoding.
When it transmits, first do 4B/5B encoding to convert MII signals to PCS signals, then enciphers and send to
TDATA<4:0>.
When RSD is high from low, then link fail counter will count for 330u sec, then the port can receive packet normally.
During 330u sec that link fail counter counts, then receiving packet will be ignored. Cipher / No-cipher is selected by
station management access logic.
3.2 Carrier Integrity Monitor State Machine ( AX88853 PCS mode only )
For 100BASE-X systems, it is necessary that the repeater set protect the network from some transient fault conditions
that would disrupt network communications. Potential likely causes of such conditions are DTE and repeater powerup and power-down transients, cable disconnects, and faulty wiring.
The AX88853 support CIM state machine with self-interrupt capability to prevent a segment’s spurious carrier
activity from reaching the repeater unit and hence propagating through the network.
3.3 Repeater State Machine
The repeater state machine is used to control repeater behavior, generates right signal in corresponding states. The
repeater state machine is in Idle state when there is no carrier . When there is carrier , the repeater state machine
goes to Data Forwarding State to ensure correct data forwarding. If collision happens anytime, The repeater state
machine detects collision then send jam pattern until collision ceases.
idle State
The idle state happens when these conditions exists:
a. /RST is low.
b. Reset emitted by station management access logic(RST_RSM).
c. There is no any carrier in M0_CRS[7:0], M1_CRS[7:0], and CRS{1:0] in MII mode. Or
receive IDLE code in PCS mode. If in cascade application, repeater receive no inter repeater
active signal.
In this state,M0_RXEN[7:0],M1_RXEN[7:0],M0_TXEN[7:0],M1_TXEN[7:0] are all low in MII
mode.
Data Forwarding State
When there is only one carrier in M0_CRS[7:0], M1_CRS[7:0]or CRS[0], CRS[1] in MII mode, or
only one of eight ports receives /J/K/ codes in PCS mode ,or only one of IR_ACTO[7:0] become low,
The repeater state machine stores receiving packet and transmits to all other ports. Exception for
a. The port is jabbered.
b. The port is partitioned.
c. There exists collision.
In this state, only one of M0_RXEN[7:0] and M1_RXEN[7:0] is high, or M0_RXEN[7:0] or
M1_RXEN[7:0] are all low because either packet is from two dedicated MII port or from inter-repeater
cascade interface in MII mode.
The repeater send packet from receiving port to all ports exclusive of the receiving that is
M0_TXEN[7:0] and M1_TXEN[7:0] all becomes high, and one may be low if that port is the receiving
port in MII mode. The repeater forwards data to TDATA[7:0] except for the receiving RDATA port in
PCS mode.
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PRELIMINARY
Collision State
The Collision State happens when these conditions exists:
a. There are two or more signals high among M0_CRS[7:0],M1_CRS[7:0],CRS[1:0]. Or receive
collision messages from /IR_ACTO[7:0] in MII mode.
b. At least two ports of PCS ports receive /J/K/ code group or receive collision message from
/IR_ACTO[7:0] in PCS mode.
c. Only one carrier exists but RXDV still low exceeds 5 clock cycles. The repeater sends collision
pattern to all ports, that is, M0_TXEN[7:0] and M1_TXEN[7:0] all become high during collision
state.
3.4 Jabber State Machine
To prevent an illegally long reception of data from reaching the repeater unit, each port has its own jabber timer. If a
reception exceeds this duration(64K bit times for AX88850), the jabber condition will be detected. In this condition,
repeater unit will disable receive and transmit packets for the jabbered port and the other ports remain the normal
operation.
When the carrier is no longer detected for the jabbered port or reset the repeater, the jabber function will be clear and
re-enable reception and transmission.
3.5 Partition State Machine
The partition state machine is used to protect network from be upset by a port suffering continuous collision, each port
uses a partition state machine to detect and prevent this condition. When a port is suffering from continuous 32 or
64 times of collisions by CCLimits. Then it goes to Partition State. The port entering Partition State will be released
until a packet without collision more than 512 bit times or after power-on reset.
Partition function is enabled by default, and CCLimits is 64 by default. Enable/Disable partition function
(DIS_PART) and option of CCLimits to be 64 or 32 (COL_LIMIT32) are selected by station management access
logic.
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PRELIMINARY
3.6 Expansion Logic(Cascade Interface)
The expansion logic is used to stack numerous repeaters. The expansion logic can be divided into two types:
Expansion Logic with Buffer (maximum mode
In this mode, use /IR_ACTO[7:0] and /IR_ACTI[7:0] to cascade repeaters. Buffers are used both in
/IR_ACTO[7:0] and /IR_ACTI[7:0]. This mode is supposed to cascade repeaters on difference boards via cables.
There is a configuration bit /IR_ACT_EN to decide cascade signals are judges by /IR_ACTI[7:0](/IR_ACT_EN
= 0) or /IR_ACTO[7:0](/IR_ACT_EN = 1).
Expansion Logic without Buffer (minimum mode)
In this mode, use /IR_ACTO[7:0] to cascade repeaters. Just connect /IR_ACTO[7:0] without using buffer in this
part. This mode is supposed to cascade repeaters on the same board.
RPTR_ID<2:0>
0
1
2
3
4
5
6
7
Idle
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
/IR_ACTO<7:0>
Active
FEh
FDh
FBh
F7h
EFh
DFh
BFh
7Fh
Collision
FBh
FCh
F9h
F3h
E7h
CFh
9Fh
3Fh
In this table:
a. All /IR_ACTO[7:0] will be in open-drain state when repeater chip is idle. These signals are all high via
external pull high resister.
b. One signal of /IR_ACTO[7:0] is low in data forwarding state corresponding to different RPTR_ID[2:0].
c. Two signals of /IR_ACTO[7:0] are low in collision state corresponding to different RPTR_ID[2:0].
3.7 Management Logic
AX88850 provides the required management information associated with a packet for management chip which
statistics processed on a per packet basis. Transmit ready signal TX_RDY is used as a framing signal for management
data MD. Then management chip uses this data to determine the source of the current packet. MD data is synchronized
to the rising edge of IRD_CK. When collision occur, MD will be tri-state and becomes invalid.
MD frame format
idle
start bit
data0
data1
data2
data3
data4
1
0
PID[0]
PID[1]
PID[2]
PID[3]
PID[4]
Notes:
a. PID[4:0] is the number of the receiving port.
b. RID_CH indicates change in RID.
c. PARITY = 1 when sum of 1‘s among PID[4:0] and RID_CH is even
PARITY = xnor (PID[4],PID[3],PID[2],PID[1],PID[0],RID_CH)
21
data5
RID_CH
data6
PARITY
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AX88850
PRELIMINARY
3.8 Management Counters
There are four management counters in each port. These 16-bit-wide management counters keep track of the
following events:
Collision Event Counter
It indicates the number of times that collision occurrences on a port.
Partition Event Counter
It indicates the number of times that a port has been partition.
Short Event Counter
It indicates the number of packets that is shorter than 76 BT.
Late Event Counter
It indicates the number of collision occurrences time after 512 BT when carrier presents.
Fault Carrier Event Counter (AX88853 only)
It indicates the number of times that fault carrier occurrences on a port.
These counters can be read out by MIB serial access interface and will be clear after read operation.
3.9 Station Management Access Interface
The AX88850 provides 128 registers held in 4 pages of 32(Page 0 ~ 3 Register).These registers are 16 bits wide. Only
one register of one page can be access at the same time through the MII serial management bus. After power on
reset, Page 0 Register is the default setting. Change the value of PAGE REGISTER which exists in all pages, then
switches to any page. For example: Page 3 Register can be accessed by writing 03h to the PAGE REGISTER.
AX88850 can thus be managed through SMDC and SMDIO pins. The SMDC clock with maximum 2.5M Hz is used
to sample data train on SMDIO. The interface follows the serial management protocol defined by IEEE 802.3u clause
22.
READ
WRITE
Management frame format
PREAM START OPCODE DEV_AD REG_AD TA
1.......1
01
10
AAAAA RRRRR
Z0
1.......1
01
01
AAAAA
RRRRR
10
DATA
DDDDDDDDDDDDDDDD
IDLE
Z
DDDDDDDDDDDDDDDD
Z
For the protocol to work, all serial data must be “synchronized” to incoming data. To ensure data locked, a preamble
of 32 consecutive 1‘s present before the start code, then the receive logic know the beginning of the data frame.
With the setting of PHY_ACCESS = 1(stored in CONFIGURATION REGISTER), the target access device may be
physical layer devices. In this mode, SMDIO is gated to BSMDIO. SMDIO and BSMDIO must turn on in the
appropriate direction for read/write access. In the cascade system, only one repeater chip has the set of
PHY_ACCESS at a time to avoid contention problems.
3.10 RID Receive-Transmit Interface(Daisy Chain Logic)
In the cascade system, repeater ID of each chip will be re-arranged by serial in/out daisy chain logic. The DAISY_IN
pin always monitor RID of the previous chained chip, and the value of (RID+1) will override the original RID of the
current chip. Then the DAISY_OUT pin will periodically (about 200us) send out the exact RID of current chip to
inform the next chained chip. By this way, each repeater chip in 8 AX88850 hub (maximum application) will keep
unique ID of itself. The RID is used in inter repeater bus arbitration and uniquely identify station management
accesses.
Note that only RID[2:0] can be changed and RID[4:3] must be the same value for all repeaters in the cascade system.
In this way, repeater ID won‘t be confused with PHY device ID during station management access.
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AX88850
PRELIMINARY
DAISY_IN/OUT frame format
idle
start bit
data0
data1
1
0
RID[0]
RID[1]
Notes: PARITY = 1 when sum of 1‘s in RID[2:0] is even
data2
RID[2]
data3
PARITY
There are two flag : /DIS_DAISY and /TO_ID_CLR which control daisy-chain access. If disable daisy-chain input
(/DIS_DAISY = 0), the RID of current chip can‘t be override and don‘t care the present data on DAISY_IN. If no
daisy-chain input, the RID of current chip can be clear to 0 during time out period with the setting of /TO_ID_CLR =
0. The timer is done about 4sec.
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PRELIMINARY
3.11 LED Interface
AX88850 provides per-port LED status indication for partition, jabber, link/activity and support rate-based LED for
global utilization (%) and global collision frequency (%). Detail function is described on previous pin description
(LED interface). LED[7:0] are all active low.
3.11.1 LED Status Driver wave-form for AX88851
LED_SYN
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10 ~ D15
D0
D1
D2
D3
LED[0]
P0
J0
A0
C4
C0
P10
J10
A10
RID0
CC0
no useful phase
P0
J0
A0
C4
LED[1]
P1
J1
A1
U4
C1
P11
J11
A11
RID1
CC1
no useful phase
P1
J1
A1
U4
LED[2]
P2
J2
A2
A8
C2
P12
J12
A12
RID2
CC2
no useful phase
P2
J2
A2
A8
LED[3]
P3
J3
A3
A9
C3
P13
J13
A13
RID3
CC3
no useful phase
P3
J3
A3
A9
LED[4]
P4
J4
A4
J8
U0
P14
J14
A14
RID4
UU0
no useful phase
P4
J4
A4
J8
LED[5]
P5
J5
A5
J9
U1
P15
J15
A15
"0"
UU1
no useful phase
P5
J5
A5
J9
LED[6]
P6
J6
A6
P8
U2
P16
J16
A16
CC4
UU2
no useful phase
P6
J6
A6
P8
LED[7]
P7
J7
A7
P9
U3
P17
J17
A17
UU4
UU3
no useful phase
P7
J7
A7
P9
Note 1 :
a.
b.
c.
d.
e.
f.
g.
P17~0 indicates partition status for each port
J17~0 indicates jabber status for each port
L17~0 indicates link status for each port
A17~0 indicates activity status for each port
RID4~0 is the ID number of repeater chip
The LED display support two estimations:C4~0 and CC4~0 which indicate global collision rate for
each 104.8ms sampling period. Users can choose any one presentation.
The LED display support two estimations:U4~0 and UU4~0 which indicate global utilization rate for
each 104.8ms sampling period. Users can choose any one presentation.
Note 2 : Reference port map as following table (Using per port Carrier Sense / Receive Signal Detect to identify port
number).
AX88851
Port[7:0] == M0_CRS[7:0]
Port[9:8] == CRS[1:0]
Port[17:10] == M1_CRS[7:0]
AX88852
Port[3:0] == M0_CRS[3:0]
Port[9:8] == CRS[1:0]
Port[7:4] == M1_CRS[3:0]
AX88853
Port[7:0] == RSD[7:0]
Port[9:8] == CRS[1:0]
AX88854
Reference to AX88851/AX88853 depended on MEDIA setting.
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PRELIMINARY
3.11.2 LED Status Driver wave-form for AX88852
LED_SYN
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10 ~ D15
D0
D1
D2
D3
LED[0]
P0
J0
A0
C4
C0
P4
J4
A4
RID0
CC0
no useful phase
P0
J0
A0
C4
LED[1]
P1
J1
A1
U4
C1
P5
J5
A5
RID1
CC1
no useful phase
P1
J1
A1
U4
LED[2]
P2
J2
A2
A8
C2
P6
J6
A6
RID2
CC2
no useful phase
P2
J2
A2
A8
LED[3]
P3
J3
A3
A9
C3
P7
J7
A7
CC3
no useful phase
P3
J3
A3
A9
LED[4]
J8
U0
RID4
UU0
no useful phase
J8
LED[5]
J9
U1
"0"
UU1
no useful phase
J9
LED[6]
P8
U2
CC4
UU2
no useful phase
P8
LED[7]
P9
U3
UU4
UU3
no useful phase
P9
UU1
3.11.3 LED Status Driver wave-form for AX88853
LED_SYN
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10 ~ D15
D0
D1
D2
D3
LED[0]
P0
J0
L0/
A0
C4
C0
RID0
CC0
no useful phase
P0
J0
L0/
A0
C4
LED[1]
P1
J1
L1/
A1
U4
C1
RID1
CC1
no useful phase
P1
J1
L1/
A1
U4
LED[2]
P2
J2
L2/
A2
A8
C2
RID2
CC2
no useful phase
P2
J2
L2/
A2
A8
LED[3]
P3
J3
L3/
A3
A9
C3
UU1
CC3
no useful phase
P3
J3
L3/
A3
A9
LED[4]
P4
J4
L4/
A4
J8
U0
RID4
UU0
no useful phase
P4
J4
L4/
A4
J8
LED[5]
P5
J5
L5/
A5
J9
U1
"0"
UU1
no useful phase
P5
J5
L5/
A5
J9
LED[6]
P6
J6
L6/
A6
P8
U2
CC4
UU2
no useful phase
P6
J6
L6/
A6
P8
LED[7]
P7
J7
L7/
A7
P9
U3
UU4
UU3
no useful phase
P7
J7
L7/
A7
P9
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PRELIMINARY
3.11.4 LED Status Driver wave-form for AX88854
LED_SYN
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10 ~ D15
D0
D1
D2
D3
LED[0]
P0
J0
L0/
A0
C4
C0
P10
J10
A10
RID0
CC0
no useful phase
P0
J0
L0/
A0
C4
LED[1]
P1
J1
L1/
A1
U4
C1
P11
J11
A11
RID1
CC1
no useful phase
P1
J1
L1/
A1
U4
LED[2]
P2
J2
L2/
A2
L8/
A8
C2
P12
J12
A12
RID2
CC2
no useful phase
P2
J2
L2/
A2
L8/
A8
LED[3]
P3
J3
L3/
A3
L9/
A9
C3
P13
J13
A13
CC3
no useful phase
P3
J3
L3/
A3
L9/
A9
LED[4]
P4
J4
L4/
A4
J8
U0
P14
J14
A14
RID4
UU0
no useful phase
P4
J4
L4/
A4
J8
LED[5]
P5
J5
L5/
A5
J9
U1
P15
J15
A15
"0"
UU1
no useful phase
P5
J5
L5/
A5
J9
LED[6]
P6
J6
L6/
A6
P8
U2
P16
J16
A16
CC4
UU2
no useful phase
P6
J6
L6/
A6
P8
LED[7]
P7
J7
L7/
A7
P9
U3
P17
J17
A17
UU4
UU3
no useful phase
P7
J7
L7/
A7
P9
UU1
3.12 Power on Configuration(Initial Setting)
During power-on reset, /IR_ACTI[[7:0] are used as some configuration setting. These include inter repeater active
input pin enable/disable (/IR_ACT_EN); time out to clear repeater ID(/TO_ID_CLR); daisy-chain input
disable/enable (/DIS_DAISY); and repeater ID(RPTR_ID[4:0]). Detail function is described on previous pin
description (expansion bus interface). After reset, these setting are stored in DEVICE ID REGISTER which can be
modified by station management write commands.
Default setting
Function
/IR_ACT_EN pull high
DISABLE inter repeater active in
/TO_ID_CLR pull high
DISABLE time out to clear repeater ID
/DIS_DAISY
pull high
ENABLE daisy-chain input
RPTR_ID
pull high
RPTR_ID = 11111
26
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AX88850
PRELIMINARY
4.0 REGISTERS
The AX88850 has 128 16-bit registers which are separated into four pages with each page 32 words. At
power-on or reset , the default value is page 0 registers. The register page can be changed by writing to the register
address 1 on all the four pages .
4.1 Page 0 Register MAP
Address (hex)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
10-13
14-17
18-1B
1C-1F
Name
CONFIG
PAGE
PARTITION
JABBER
ADMIN
DEVICE-ID
P8-SE
P8-LE
P8-COL
P8-PART
P9-SE
P9-LE
P9-COL
P9-PART
P0-SE …
P0-PART
P1-SE …
P1-PART
P2-SE …
P2-PART
P3-SE …
P3-PART
Access
R/W
R/W
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Set AX88850 configuration
Selects register from page 0 to page 3.
Indicates Auto-Partitioning status.(port0 - port9)
Indicates Jabber status. (port0 - port9)
Port enable / disable, administration control/status(port0 - port9)
Accesses 1) the AX88850 ID number configured externally on the
RID[4:0] pins. 2) the last receiving port number.
The device number of AX88850 may be overwritten after it has been
latched at the end of reset.
Reserved
Reserved
Port 8 : 16-bit ShortEvent Counter (dedicated MII port 0)
Port 8 : 16-bit LateEvent Counter
Port 8 : 16-bit Collision Counter
Port 8 : 16-bit Auto-partition Counter
Port 9 : 16-bit ShortEvent Counter (dedicated MII port 1)
Port 9 : 16-bit LateEvent Counter
Port 9 : 16-bit Collision Counter
Port 9 : 16-bit Auto-partition Counter
Port 0 management counters ( as per ports 8,9 as above )
R/W Port 1 management counters ( as per ports 8,9 as above )
R/W Port 2 management counters ( as per ports 8,9 as above )
R/W Port 3 management counters ( as per ports 8,9 as above )
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4.2 Page 1 Register MAP
Address (hex)
0
1
2
3
4
5
6-7
8-F
10-13
14-17
18-1B
1C-1F
Name
CONFIG
PAGE
PARTITION
JABBER
ADMIN
SI_REV
P0-FCRS …
P7-FCRS
P4-SE …
P4-PART
P5-SE …
P5-PART
P6-SE …
P6-PART
P7-SE …
P7-PART
Access
R/W
R/W
RO
RO
R/W
RO
Description
Set AX88850 configuration ( same as page 0 )
Selects register from page 0 to page 3. ( same as page 1 )
Indicates Auto-Partitioning status.(port10 - port17)
Indicates Jabber status. (port10 - port17)
Port enable / disable, administration control/status(port10 - port17)
Silicon revision code.
Reserved
R/W Port 0 false carrier counters (address 8) to
Port 7 false carrier counters (address F)
Those counters are valid just for PCS mode port 0 to port 7.
As for MII mode , the false carrier counter will be available on PHY, but
some PHY chip manufacturer not support those functions.
R/W Port 4 management counters ( as per ports 8,9 as above )
R/W Port 5 management counters ( as per ports 8,9 as above )
R/W Port 6 management counters ( as per ports 8,9 as above )
R/W Port 7 management counters ( as per ports 8,9 as above )
4.3 Page 2 Register MAP
Address (hex)
Name
0
CONFIG
1
PAGE
2-F
10-13
P10-SE …
P10-PART
14-17
P11-SE …
P11-PART
18-1B
P12-SE …
P12-PART
1C-1F
P13-SE …
P13-PART
Access
Description
R/W Set AX88850 configuration
R/W Selects register from page 0 to page 3.
Reserved
R/W Port 10 management counters ( as per ports 8,9 as above )
R/W Port 11 management counters ( as per ports 8,9 as above )
R/W Port 12 management counters ( as per ports 8,9 as above )
R/W Port 13 management counters ( as per ports 8,9 as above )
4.4 Page 3 Register MAP
Address (hex)
Name
0
CONFIG
1
PAGE
2-F
10-13
P14-SE …
P14-PART
14-17
P15-SE …
P15-PART
18-1B
P16-SE …
P16-PART
1C-1F
P17-SE …
P17-PART
Access
Description
R/W Set AX88850 configuration ( same as page 0 )
R/W Selects register from page 0 to page 3.. ( same as page 1 )
Reserved
R/W Port 14 management counters ( as per ports 8,9 as above )
R/W Port 15 management counters ( as per ports 8,9 as above )
R/W Port 16 management counters ( as per ports 8,9 as above )
R/W Port 17 management counters ( as per ports 8,9 as above )
28
ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
4.5 Configuration Register (CONFIG)
Page 0 to Page 3 Address 0h
Bit
D15-D8
Bit Name
Reserved
Access
D7
RST_FLAG
RO
D6
RID_CH
RO
D5
DIS_CIPHER
R/W
D4
MGTEN
R/W
D3
COL_LIMIT32
R/W
D2
DIS_PART
R/W
D1
PHY_ACCESS
R/W
D0
RST_RSM
R/W
Bit Description
Written as “0” for future compatibility concern.
Undefined by read.
Reset Flag : The bit is set when power on reset and is clear after read
CONFIG register.
Repeater ID Changed : The bit is set when Daisy-Chain RID input
override the current RID or after power on reset. When read CONFIG
register will clear the bit.
Disable Cipher Function : Then set the bit at PCS mode, the 5bit symbol
scramble and descrambler function are disable. Default is enable.
Management Enable : This bit enable all the management counters.
0 : Management Counters disabled. (default)
1 : Management Counters enabled.
Collision limit : This bit configures the collision limit for AutoPartitioning.
0 : Consecutive Collision limit set to 64 (default). A port will
be partitioned on the 65th consecutive collision.
1 : Consecutive Collision limit set to 32 . A port will
be partitioned on the 33rd consecutive collision.
Disable Auto-Partition : Set this bit disable the Auto-Partition
algorithm.
0 : Auto-Partition is not disabled (default)
1 : Auto-Partition is disabled .
PHY access enable : This bit enable to access PHY register via MII serial
protocol.
0 : PHY access disabled (default)
1 : PHY access enabled .
Reset Repeater State Machines : Setting the bit holds the RSM in reset.
The management event flags and counters are unaffected by this bit.
Setting this bit while a reception is in progress may truncate the packet.
0 : AX88850 in normal operation (default)
1 : AX88850 held in reset .
4.6 Page Register (PAGE)
Page 0 to Page 3 Address 1h
Bit
D15-D8
Bit Name
GEP[3:0]
D7-D2
Reserved
D1-D0
PAGE[1:0]
Access
Bit Description
R/W D11-D8 : GEP I/O control. Default = 0h for input mode. Otherwise, =1h,
enable output.
D15-D12 : GEP Data . Default = 0h.
When write, D15-D12 value present to GEP[3:0] if enabled.
When read, D15-D12 reflect the GEP[3:0] value.
Written as “0” for future compatibility concern.
undefined by read.
R/W Those bits setting the register page to be accessed.
PAGE[1:0]
PAGE
0h
0
(default)
1h
1
2h
2
3h
3
29
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AX88850
PRELIMINARY
4.7 Partition Status Register (PARTITION)
Page 0 Address 2h
Bit
D15-D10
D9-D0
Bit Name
Reserved
PART[9: 0]
Access
RO
Bit Description
undefined when read.
The respective port‘s PART bit is set to “1” when Partitioning is sensed
on that port. After reset, these bits are cleared to “0”.
Page 1 Address 2h
Bit
D15-D8
D7-D0
Bit Name
Reserved
PART[17: 10]
Access
RO
Bit Description
undefined when read.
The respective port‘s PART bit is set to “1” when Partitioning is sensed
on that port. After reset, these bits are cleared to “0”.
4.8 Jabber Status Register (JABBER)
Page 0 Address 3h
Bit
D15-D10
D9-D0
Bit Name
Reserved
JAB[9: 0]
Access
RO
Bit Description
undefined when read.
The respective port‘s JAB bit is set to “1” when Jabber condition is
detected on that port. After reset, these bits are cleared to “0”.
Page 1 Address 3h
Bit
D15-D8
D7-D0
Bit Name
Reserved
JAB[17: 10]
Access
RO
Bit Description
undefined when read.
The respective port‘s JAB bit is set to “1” when Jabber condition is
detected on that port. After reset, these bits are cleared to “0”.
4.9 Administration Register (ADMIN)
Page 0 Address 4h
Bit
D15-D10
Bit Name
Reserved
D9-D0
ADMIN[9: 0]
Access
Bit Description
Written as “0” for future compatibility concern.
undefined by read.
R/W Administration Disable : Setting these bits to “0” enable the respective
port (TX and RX). Writing a 1 to any bit will disable that port. After reset,
these bits default to “0” ( all ports enable ). Note that port enable/disable
action will occur at the next network idle period.
Page 1 Address 4h
Bit
D15-D8
Bit Name
Reserved
D7-D0
ADMIN[17: 10]
Access
Bit Description
Written as “0” for future compatibility concern.
undefined by read.
R/W Administration Disable : Setting these bits to “0” enable the respective
port (TX and RX). Writing a 1 to any bit will disable that port. After reset,
these bits default to “0” ( all ports enable ). Note that port enable/disable
action will occur at the next network idle period.
30
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AX88850
PRELIMINARY
4.10 Device ID Register (DEVICEID)
Page 0 Address 5h
Bit
D15-D13
D12-D8
D7
Bit Name
Temp
PORT_NUM
/IR_ACT_EN
D6
/TO_ID_CLR
D5
/DIS_DAISY
D4-D0
Access
Bit Description
R/W Temporary Registers : reserved for system programer used.
*R/W Port Number : These bit indicate the last or current receiving port number.
*R/W Inter Repeater Active Input Pin Enable : This bit active low to enable
/IR_ACTI[7:0] pin as inter-repeater carrier sense detection input.
Otherwise, /IR_ACTI[7:0] pins is disable and only perform power-on
configuration inputs.
R/W Time Out to Clear repeater ID : Within the time out period, if no daisy
chain repeater ID input. The repeater ID will be clear to RID=0 .
Otherwise, the repeater ID will remain the previous value ( power on
configured value or previous daisy chain reconfigured value).The tome
out period is about 4 to 5 second.
R/W Disable RID Daisy-chain Input: No matter what kind of data input from
DAISY_IN pin the RPTR_ID can’t be override.
RPTR_ID
R/W Repeater ID : At the rising edge of /RST , the value of RID[4:0] are
latched in this register as D[4:0]. The setting of RID[2:0]can be override
according to the data from serial daisy-chain DAISY_IN pin input except
/DIS_DAISY is configured to “low” .
Note that in system application, the maximum of 8 devices can be
cascade. Therefore only RID[2:0] can be variation and the RID[4:3] must
be keep the same value in the same system and avoid conflicted with PHY
device ID.
* Note : Host can’t override these signals.
4.11 Silicon Revision Register
Page 1 Address 5h
Bit
D15-D0
Bit Name
SI_REV[15:0]
Access
Bit Description
RO Silicon Reversion : Currently reads all 1‘s
31
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AX88850
PRELIMINARY
4.12 Port Management Counter Registers
Each of the 18 ports of the AX88850 has a set of 4 event counters whose values can be read or pre-set (written)
through the Port Management Counter Registers. When PCS (symbol) mode is selected, there is a set of false carrier
counter / per port build-in on the chip. As for MII mode , the false carrier counter will be available on PHY, note that
some PHY chip manufacturer not support those functions.
4.12.1 Short Event Counter Registers
Per port (“n” =port number) counters that indicate the number of Carrier Events that were active for less than the
ShortEventMaxTime, which is defined as between 74 and 82 (76 nominal) bit times.
Bit
Bit Name
Access
Bit Description
D15-D0
P“n”_SE[15:0]
R/W P“n”_SE[15:0]
4.12.2 Late Event Counter Registers
Per port (“n”= port number) counters that indicate the number of collision that occurred after the
LateEventThreshold, , which is defined as between 480 and 565 (512 nominal) bit times. Both the Late Event and
collisions will be incremented when this event occurs.
Bit
Bit Name
Access
Bit Description
D15-D0
P“n”_LE[15:0]
R/W P“n”_LE[15:0]
4.12.3 Collision Counter Registers
Per port (“n”= port number) counters that indicate the number of collisions (COL asserted) .
Bit
Bit Name
Access
Bit Description
D15-D0
P“n”_CO[15:0]
R/W P“n”_CO[15:0]
4.12.4 Auto-Partition Counter Registers
Per port (“n”= port number) counters that indicate the number of times the port was auto-partitioned.
Bit
Bit Name
Access
Bit Description
D15-D0
P“n”_PART[15: R/W P“n”_PART[15:0]
0]
4.12.5 False Carrier Counter Registers
Per port (“n”= port number) counters that indicate the number of times the port was false carrier occurred.
Those counters are valid just for PCS mode port 0 to port 7. As for MII mode , the false carrier counter will be
available on PHY, but some PHY chip manufacturer not support those functions.
Bit
Bit Name
Access
Bit Description
D15-D0
P“n”_FCRS[15: R/W P“n”_FCRS[15:0]
0]
32
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AX88850
PRELIMINARY
5.0 ELECTRICAL SPECIFICATION AND TIMING
5.1 Absolute Maximum Ratings
Description
SYM
Min
Max
Units
Operating Temperature
Ta
0
+70
°C
Storage Temperature
Ts
-55
+150
°C
Supply Voltage
Vcc
-0.5
+7
V
Input Voltage
Vin
Vss-0.5
Vdd+0.5
V
Output Voltage
Vout
Vss-0.5
Vdd+0.5
V
Lead Temperature (soldering 10 seconds maximum)
Tl
-55
+250
°C
Note : Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
Exposure to Absolute Maximum Ratings conditions for extended period, adversely affect device life and reliability
5.2 General Operation Conditions
Description
Operating Temperature
Supply Voltage
SYM
Min
0
+4.75
Max
+70
+5.25
Units
°C
V
SYM
Min
Vss-0.5
2
Max
0.8
Vdd+0.5
0.4
Units
V
V
V
V
uA
uA
uA
Ta
Vdd
5.3 DC Characteristics
(Vdd=4.75V to 5.25V, Vss=0V, Ta=0°C to 70°C)
Description
Low Input Voltage
High Input Voltage
Low Output Voltage
High Output Voltage
Input Leakage Current 1 (Note 1)
Input Leakage Current 2 (Note 2)
Output Leakage Current
Vil
Vih
Vol
Voh
Iil1
Iil1
Iol
2.4
10
500
10
Note :
1.
All the input pins without pull low or pull high.
2.
Those pins had been pull low or pull high.
33
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PRELIMINARY
5.4 AC specifications
5.4.1 MII Interface Timing Tx & Rx
T0
T1
LCLK
T2
T2
T3
T3
TX_EN
(MTX_RDY)
TX_ER
TXD
Symbol
T0
T1
T2
T3
Description
Local Clock Cycle Time
Local Clock High Time
TX_EN or MTX_RDY Delay from LCLK High
TX_ER or TXD Delay from LCLK High
T4
Min
39.996
14
4
4
Typ.
40
20
14
14
Max
40.004
26
19
19
Units
ns
ns
ns
ns
T5
RX_CLK
CRS
T6
T7
RXE
T8
RXDV
T9
RXD
RXER
34
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AX88850
Symbol
T4
T5
T6
T7
T8
T9
PRELIMINARY
Description
RX_CLK Clock Cycle Time
RX_CLK Clock High Time
CRS to RXE Assertion Delay
CRS to RXE De-assertion Delay
CRS to RXDV Delay Requirement
RXD or RXDV setup to RX_CLK rise time
Min
39.996
14
Typ.
40
20
120
40
10
Max
40.004
26
20
200
160
-
Units
ns
ns
ns
ns
ns
ns
5.4.2 Station Management
T1
T2
SMDC
T3 T4
T5
SMDIO
Write
Write
T6
T7
/SMDV
Read
SMDIR
Write
T8
BSMDC
BSMDIO
Symbol
T1
T2
T3
T4
T5
T6
T7
T8
Description
SMDC Period
SMDC High Time
SMDIO Setup Time to SMDC High(Write)
SMDIO Hold Time to SMDC High(Write)
SMDIO Valid from SMDC High(Read)
/SMDV Setup Time to SMDC High
/SMDV Hold Time to SMDC High
BSMDIO Buffer Delay Time
Min
400
40
10
10
10
10
35
Typ.
Max
50
20
Units
ns
ns
ns
ns
ns
ns
ns
ns
ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
5.4.3 PCS Interface Timing
TX
LCLK
T0
TDATA
RX
T1
T2
RSCLK
T3
T4
RDATA
Symbol
T0
T1
T2
T3
T4
Description
TDATA Valid From LCLK High
RSCLK Clock Cycle Time
RSCLK Clock High Time
RDATA Setup Time
RDATA Hold Time
Min
12
39.996
14
13
10
Typ.
40
20
Max
35
40.004
26
-
Units
ns
ns
ns
ns
ns
5.4.4 LED DISPLAY
LCLK
T1
LED[7:0
D15
T3
T2
D0
D1
D2
D3
D4
D15
D0
T4
LED-SYN
T5
Symbol
T1
T2
T3
T4
T5
Description
LED Valid from LCLK Low
LED Data Width
LED_SYN Valid from LCLK Low
LED-SYN Pulse Width
LED-SYN Cycle Time
Min
7
Typ.
Max
24
40
6
13
40
640
36
Units
ns
ns
ns
ns
ns
ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
5.4.5 LED Display After Reset
/Reset
T1
T2
T2
T2
T3
LED[7:0]
T4
LED_SYN
…………………………………
Symbol
Description
T1
Repeater reset time
T2
LED Blink Time After Reset
T3
LED Dark Time Before Normal Display
………………
Min
1000
Typ.
Max
838.4
419.2
Units
ns
ms
ms
5.4.6 Repeater ID Daisy Chain
T1
T2 T2
Daisy-Out
ID0
ID1
ID2
ID0
ID1
ID2
T3
Daisy-In
ID0
ID1 ID2
ID0 ID1
ID2
Symbol
Description
Min
Typ.
Max
Units
T1
Daisy Chain One Burst period
204.8
us
T2
Start Bit Period or Data Width
12.8
us
T3
Daisy Chain Data In Time-out *
3.8
s
Note : Daisy-Chain Data-In Time-out stands for no input data (always high level) for the specific time.
37
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AX88850
PRELIMINARY
5.4.7 Expansion Bus
CRS
T1
T2
IRD-ODIR
IRD_CK
T3
IRD[3:0]
T4
/IRD_ER
T5
T6
/IRD_V
MD
ID0
ID1
T7
Symbol
T1
T2
T3
T4
T5
T6
T7
T8
Description
CRS Assertion to IRD-ODIR Assertion
CRS De-Assertion to IRD-ODIR De-Assertion
IRD[3:0] Setup Time to IRD-CK High
/IRD_ER Setup Time to IRD-CK High
/IRD_V Setup Time to IRD-CK High
/IRD_V Hold Time from IRD-CK High
MD Setup Time to IRD-CK High
MD Hold Time from IRD-CK High
38
ID2
T8
Min
160
10
10
5
5
3
3
Max
42
240
13
13
Units
ns
ns
ns
ns
ns
ns
ns
ns
ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
6.0 PACKAGE INFORMATION
He
A2
A1
L
L1
D
Hd
E
pin 1
e
b
θ
SYMBOL
MILIMETER
MIN.
NOM
MAX
A1
0.05
0.25
0.5
A2
3.17
3.32
3.47
b
0.10
0.20
0.30
D
27.90
28.00
28.10
E
27.90
28.00
28.10
e
0.50
Hd
30.35
30.60
30.85
He
30.35
30.60
30.85
L
0.45
0.60
0.75
L1
θ
1.30
0
10
39
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