CADEKA CDK2307CILP64

Data Sheet
A m p l i fy t h e H u m a n E x p e r i e n c e
CDK2307
Dual, 20/40/65/80MSPS, 12/13-bit
Analog-to-Digital Converters
13-bit resolution
n
20/40/65/80MSPS maximum sampling rate
n
Ultra-low power dissipation: 30/55/85/102mW
n
SNR 72dB at 80MSPS and 8MHz FIN
n
Internal reference circuitry
n
1.8V core supply voltage
n
1.7V – 3.6V I/O supply voltage
n
Parallel CMOS output
64-pin QFN package
(TQFP-64 package option also available)
n
n
Dual channel
n
Pin compatible with CDK2308
APPLICATIONS
Handheld Communication, PMR, SDR
n
Medical Imaging
n
Portable Test Equipment
n
Digital Oscilloscopes
n
Baseband / IF Communication
n
Video Digitizing
n
CCD Digitizing
Several idle modes with fast startup times exist. Each channel can be independently powered down and the entire chip can either be put in Standby
Mode or Power Down mode. The different modes are optimized to allow the
user to select the mode resulting in the smallest possible energy consumption
during idle mode and startup.
The CDK2307 has a highly linear THA optimized for frequencies up to 70MHz.
The differential clock interface is optimized for low jitter clock sources and
supports LVDS, LVPECL, sine wave and CMOS clock inputs.
Functional Block Diagram
CLKP
n
The CDK2307 is a high performance, low power dual Analog-to-Digital Converter (ADC). The ADC employs internal reference circuitry, a CMOS control
interface and CMOS output data, and is based on a proprietary structure.
Digital error correction is employed to ensure no missing codes in the complete full scale range.
CLKN
n
CLK_EXT
Ordering Information (QFN-6 Package)
Speed
Package
Pb-Free
RoHS Compliant
Operating Temperature Range
Packaging Method
CDK2307AILP64
20MSPS
QFN-64
Yes
Yes
-40°C to +85°C
Tray
CDK2307AILP64X
20MSPS
QFN-64
Yes
Yes
-40°C to +85°C
Tape & Reel
CDK2307BILP64
40MSPS
QFN-64
Yes
Yes
-40°C to +85°C
Tray
CDK2307BILP64X
40MSPS
QFN-64
Yes
Yes
-40°C to +85°C
Tape & Reel
CDK2307CILP64
65MSPS
QFN-64
Yes
Yes
-40°C to +85°C
Tray
CDK2307CILP64X
65MSPS
QFN-64
Yes
Yes
-40°C to +85°C
Tape & Reel
CDK2307DILP64
80MSPS
QFN-64
Yes
Yes
-40°C to +85°C
Tray
CDK2307DILP64X
80MSPS
QFN-64
Yes
Yes
-40°C to +85°C
Tape & Reel
Moisture sensitivity level for all parts is MSL-2A.
©2009 CADEKA Microcircuits LLC www.cadeka.com
Rev 2A
Part Number
CDK2307 Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters
General Description
FEATURES
Data Sheet
Ordering Information (TQFP-64 Package)
Speed
Package
Pb-Free
RoHS Compliant
Operating Temperature Range
Packaging Method
CDK2307AITQ64
20MSPS
TQFP-64
Yes
Yes
-40°C to +85°C
Tray
CDK2307AITQ64X
20MSPS
TQFP-64
Yes
Yes
-40°C to +85°C
Tape & Reel
CDK2307BITQ64
40MSPS
TQFP-64
Yes
Yes
-40°C to +85°C
Tray
CDK2307BITQ64X
40MSPS
TQFP-64
Yes
Yes
-40°C to +85°C
Tape & Reel
CDK2307CITQ64
65MSPS
TQFP-64
Yes
Yes
-40°C to +85°C
Tray
CDK2307CITQ64X
65MSPS
TQFP-64
Yes
Yes
-40°C to +85°C
Tape & Reel
CDK2307DITQ64
80MSPS
TQFP-64
Yes
Yes
-40°C to +85°C
Tray
CDK2307DITQ64X
80MSPS
TQFP-64
Yes
Yes
-40°C to +85°C
Tape & Reel
CDK2307 Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters
Part Number
Moisture sensitivity level for all parts is MSL-2A.
Pin Configuration
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
QFN-64, TQFP-64
1
48
2
47
3
46
4
45
5
44
6
43
CDK2307
7
42
QFN-64, TQFP-64
8
32
31
CLK_EXT_EN
30
33
29
16
28
34
CLKN
27
15
26
35
CLKP
25
14
24
36
DVDDCLK
23
13
22
37
DVSSCLK
21
38
12
20
39
11
19
40
18
9
10
17
CLK_EXT
41
Pin Assignments
Pin No.
Pin Name
Description
DVDD
2
CM_EXT
Digital and I/O-ring pre driver supply voltage, 1.8V
3, 9, 12
AVDD
Analog supply voltage, 1.8V
4, 5, 8
AVSS
Analog ground
Common Mode voltage output
6, 7
IP0, IN0
Analog input Channel 0 (non-inverting, inverting)
10, 11
IP1, IN1
Analog input Channel 1 (non-inverting, inverting)
13
DVSSCLK
Clock circuitry ground
14
DVDDCLK
Clock circuitry supply voltage, 1.8V
15
CLKP
Clock input, non-inverting (Format: LVDS, PECL, CMOS/TTL, Sine Wave)
16
CLKN
Clock input, inverting. For CMOS input on CLKP, connect CLKN to ground
17, 64
DVSS
Digital circuitry ground
©2009 CADEKA Microcircuits LLC Rev 2A
1, 18, 23
www.cadeka.com
2
Data Sheet
Pin Assignments (Continued)
Pin Name
Description
19
CLK_EXT_EN
CLK_EXT signal enabled when low (zero). Tristate when high.
20
DFRMT
Data format selection. 0: Offset Binary, 1: Two's Complement
21
PD_N
22
OE_N_1
24, 41, 58
OVDD
I/O ring post-driver supply voltage. Voltage range 1.7V to 3.6V.
25, 40, 57
OVSS
Ground for I/O ring
26
D1_0
Output Data Channel 1 (LSB, 13-bit output or 1Vpp full scale range )
27
D1_1
Output Data Channel 1 (LSB, 12-bit output 2Vpp full scale range)
28
D1_2
Output Data Channel 1
29
D1_3
Output Data Channel 1
30
D1_4
Output Data Channel 1
31
D1_5
Output Data Channel 1
32
D1_6
Output Data Channel 1
33
D1_7
Output Data Channel 1
34
D1_8
Output Data Channel 1
35
D1_9
Output Data Channel 1
36
D1_10
Output Data Channel 1
37
D1_11
Output Data Channel 1 (MSB for 1Vpp full scale range, see Reference Voltages section)
38
D1_12
Output Data Channel 1 (MSB for 2Vpp full scale range)
Full chip Power Down mode when Low. All digital outputs reset to zero. After chip power up,
always apply Power Down mode before using Active Mode to reset chip.
Output Enable Channel 0. Tristate when high.
ORNG_1
Out of Range flag Channel 1. High when input signal is out of range
42
CLK_EXT
Output clock signal for data synchronization. CMOS levels.
43
D0_0
Output Data Channel 0 (LSB, 13 bit output or 1Vpp full scale range)
44
D0_1
Output Data Channel 0 (LSB, 12 bit output 2Vpp full scale range)
45
D0_2
Output Data Channel 0
46
D0_3
Output Data Channel 0
47
D0_4
Output Data Channel 0
48
D0_5
Output Data Channel 0
49
D0_6
Output Data Channel 0
50
D0_7
Output Data Channel 0
51
D0_8
Output Data Channel 0
52
D0_9
Output Data Channel 0
53
D0_10
Output Data Channel 0
54
D0_11
Output Data Channel 0 (MSB for 1Vpp full scale range, see Reference Voltages section)
55
D0_12
Output Data Channel 0 (MSB for 2Vpp full scale range)
56
ORNG_0
Out of Range flag Channel 0. High when input signal is out of range.
59
OE_N_0
Output Enable Channel 0. Tristate when low.
60, 61
CM_EXTBC_1,
CM_EXTBC_0
62, 63
SLP_N_1,
SLP_N_0
Rev 2A
39
©2009 CADEKA Microcircuits LLC CDK2307 Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters
Pin No.
Bias control bits for the buffer driving pin CM_EXT
00: Off
10: 50uA
10: 500uA
11: 1mA
Sleep Mode
00: Sleep Mode
10: Channel 1 active
01: Channel 0 active
11: Both channels active
www.cadeka.com
3
Data Sheet
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device
should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper device
function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the
operating conditions noted on the tables and plots.
Min
Max
Unit
AVDD, AVSS
DVDD, DVSS
AVSS, DVSSCLK, DVSS, OVSS
OVDD, OVSS
CKP, CKN, DVSSCLK
Analog inputs and outpts (IPx, INx, AVSS)
Digital inputs
Digital outputs
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
+2.3
+2.3
+0.3
+3.9
+3.9
+2.3
+3.9
+3.9
V
V
V
V
V
V
V
V
CDK2307 Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters
Parameter
Reliability Information
Parameter
Min
Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10s)
-40
-60
Typ
Max
Unit
85
+150
°C
°C
°C
J-STD-020
ESD Protection
Product
Human Body Model (HBM)
QFN-64
TQFP-64
TBD
2kV
Recommended Operating Conditions
Parameter
Min
Operating Temperature Range
-40
Typ
Max
Unit
+85
°C
Rev 2A
©2009 CADEKA Microcircuits LLC www.cadeka.com
4
Data Sheet
Electrical Characteristics
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20/40/65/80MSPS clock, 50% clock duty cycle,
-1dBFS 8MHz input signal, 13-bit output, unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DC Accuracy
Guaranteed
Offset Error
Midscale offset
1
Gain Error
Full scale range deviation from typical
Gain Matching
Gain matching between channels. ±3 sigma
value at worst case conditions.
±0.5
%FS
DNL
Differential Non-Linearity
12-bit level
±0.2
LSB
INL
Integral Non-Linearity
12-bit level
±0.6
LSB
VCMO
Common Mode Voltage Output
VAVDD/2
V
-6
LSB
6
%FS
Analog Input
VCMI
Input Common Mode
Analog input common mode voltage
Full Scale Range, Normal
Differential input voltage range,
2.0
Vpp
Full Scale Range, Option
Differential input voltage range, 1V
(see section Reference Voltages)
1.0
Vpp
Input Capacitance
Differential input capacitance
Bandwidth
Input bandwidth, full power
500
AVDD, DVDD
Core Supply Voltage
Supply voltage to all 1.8V domain pins.
See Pin Configuration and Description
1.7
1.8
2.0
V
2.5
3.6
V
I/O Supply Voltage
Output driver supply voltage (OVDD).
Must be higher than or equal to Core Supply
Voltage (VOVDD ≥ VDVDD)
1.7
OVDD
VFSR
VCM -0.1
VCM +0.2
V
2.0
pF
MHz
Power Supply
CDK2307 Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters
No Missing Codes
Rev 2A
©2009 CADEKA Microcircuits LLC www.cadeka.com
5
Data Sheet
Electrical Characteristics - CDK2307A
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20MSPS clock, 50% clock duty cycle,
-1dBFS 8MHz input signal, 13-bit output, unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Performance
SNR
SINAD
Signal to Noise Ratio
Signal to Noise and Distortion Ratio
72.5
dBFS
72.2
dBFS
FIN ≃ FS/2
72.1
dBFS
FIN = 20MHz
71.6
dBFS
FIN = 2MHz
72.4
dBFS
FIN = 8MHz
FIN = 8MHz
71.5
72
dBFS
FIN ≃ FS/2
71
71.7
dBFS
FIN = 20MHz
71.3
dBFS
87
dBc
85
dBc
80
dBc
FIN = 20MHz
80
dBc
FIN = 2MHz
-90
dBc
-95
dBc
FIN ≃ FS/2
-95
dBc
FIN = 20MHz
-95
dBc
FIN = 2MHz
-87
dBc
-85
dBc
FIN ≃ FS/2
-80
dBc
FIN = 20MHz
-80
dBc
11.7
bits
FIN = 8MHz
11.7
bits
FIN ≃ FS/2
11.6
bits
FIN = 20MHz
11.6
bits
Signal crosstalk between channels, FIN1 =
8MHz, FIN0 = 9.9MHz
-105
dB
FIN = 2MHz
SFDR
HD2
HD3
Spurious Free Dynamic Range
Second order Harmonic Distortion
Third order Harmonic Distortion
FIN = 8MHz
FIN ≃ FS/2
FIN = 8MHz
FIN = 8MHz
FIN = 2MHz
ENOB
XTALK
Effective number of Bits
Crosstalk
75
-85
-75
11.5
Power Supply
AIDD
Analog Supply Current
DIDD
Digital Supply Current
OIDD
Output Driver Supply
11.6
mA
Digital core supply
1.8
mA
2.5V output driver supply, sine wave input,
FIN = 1MHz
2.9
mA
2.5V output driver supply, sine wave input,
FIN = 1MHz, CLK_EXT disabled
2.4
mA
Analog Power Dissipation
mW
Digital Power Dissipation
9.2
mW
Total Power Dissipation
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
30.1
mW
9.9
µW
Sleep Mode 1
Power Dissipation, Sleep mode one channel
20.5
mW
Sleep Mode 2
Power Dissipation, Sleep mode both channels
9.2
mW
Power Down Dissipation
Rev 2A
20.9
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
Clock Inputs
Max. Conversion Rate
Min. Conversion Rate
©2009 CADEKA Microcircuits LLC 20
MSPS
15
MSPS
www.cadeka.com
CDK2307 Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters
FIN = 2MHz
6
Data Sheet
Electrical Characteristics - CDK2307B
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 40MSPS clock, 50% clock duty cycle,
-1dBFS 8MHz input signal, 13-bit output, unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Performance
SNR
SINAD
Signal to Noise Ratio
Signal to Noise and Distortion Ratio
FIN = 8MHz
71.9
FIN ≃ FS/2
HD2
HD3
ENOB
XTALK
Spurious Free Dynamic Range
Second order Harmonic Distortion
Third order Harmonic Distortion
Effective number of Bits
Crosstalk
dBFS
72.7
dBFS
72
dBFS
FIN = 30MHz
70.8
dBFS
FIN = 2MHz
71.7
dBFS
FIN = 8MHz
72.1
dBFS
FIN ≃ FS/2
71
71.5
dBFS
FIN = 30MHz
71.2
dBFS
81
dBc
81
dBc
80
dBc
FIN = 30MHz
80
dBc
FIN = 2MHz
-90
dBc
-95
dBc
FIN ≃ FS/2
-95
dBc
FIN = 30MHz
-90
dBc
FIN = 2MHz
-81
dBc
-81
dBc
FIN ≃ FS/2
-80
dBc
FIN = 30MHz
-80
dBc
FIN = 2MHz
11.6
bits
FIN = 2MHz
SFDR
72.5
FIN = 8MHz
75
FIN ≃ FS/2
FIN = 8MHz
FIN = 8MHz
FIN = 8MHz
-85
-75
11.7
bits
FIN ≃ FS/2
11.5
11.6
bits
FIN = 30MHz
11.5
bits
Signal crosstalk between channels, FIN1 =
8MHz, FIN0 = 9.9MHz
-102
dB
Power Supply
AIDD
Analog Supply Current
DIDD
Digital Supply Current
OIDD
Output Driver Supply
21.1
mA
Digital core supply
3.3
mA
2.5V output driver supply, sine wave input,
FIN = 1MHz
5.3
mA
2.5V output driver supply, sine wave input,
FIN = 1MHz, CLK_EXT disabled
4.4
mA
Analog Power Dissipation
mW
Digital Power Dissipation
16.9
mW
Total Power Dissipation
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
54.9
mW
9.7
µW
Sleep Mode 1
Power Dissipation, Sleep mode one channel
36.1
mW
Sleep Mode 2
Power Dissipation, Sleep mode both channels
14.2
mW
Power Down Dissipation
Rev 2A
38.0
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
Clock Inputs
Max. Conversion Rate
Min. Conversion Rate
©2009 CADEKA Microcircuits LLC 40
MSPS
20
MSPS
www.cadeka.com
CDK2307 Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters
FIN = 2MHz
7
Data Sheet
Electrical Characteristics - CDK2307C
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 65MSPS clock, 50% clock duty cycle,
-1dBFS 8MHz input signal, 13-bit output, unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
FIN = 8MHz
71.6
Max
Units
Performance
Signal to Noise Ratio
dBFS
71.8
dBFS
FIN ≃ FS/2
71.5
dBFS
FIN = 40MHz
70.4
dBFS
71.7
dBFS
FIN = 20MHz
71.7
dBFS
FIN ≃ FS/2
71.7
dBFS
70
dBFS
FIN = 8MHz
SINAD
Signal to Noise and Distortion Ratio
70.5
FIN = 40MHz
FIN = 8MHz
SFDR
Spurious Free Dynamic Range
81
dBc
FIN = 20MHz
75
84
dBc
FIN ≃ FS/2
79
dBc
FIN = 40MHz
77
dBc
-95
dBc
FIN = 20MHz
-95
dBc
FIN ≃ FS/2
-95
dBc
FIN = 40MHz
-95
dBc
-81
dBc
FIN = 20MHz
-84
dBc
FIN ≃ FS/2
-79
dBc
FIN = 40MHz
-79
dBc
11.6
bits
FIN = 20MHz
11.6
bits
FIN ≃ FS/2
11.5
bits
FIN = 40MHz
11.3
bits
Signal crosstalk between channels, FIN1 =
8MHz, FIN0 = 9.9MHz
-97.0
dB
FIN = 8MHz
HD2
Second order Harmonic Distortion
FIN = 8MHz
HD3
Third order Harmonic Distortion
FIN = 8MHz
ENOB
XTALK
Effective number of Bits
Crosstalk
-85
-75
11.4
Power Supply
AIDD
Analog Supply Current
DIDD
Digital Supply Current
OIDD
Output Driver Supply
32.8
mA
Digital core supply
5.0
mA
2.5V output driver supply, sine wave input,
FIN = 1MHz
8.2
mA
2.5V output driver supply, sine wave input,
FIN = 1MHz, CLK_EXT disabled
6.6
mA
Analog Power Dissipation
mW
Digital Power Dissipation
25.5
mW
Total Power Dissipation
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
84.5
mW
9.3
µW
Sleep Mode 1
Power Dissipation, Sleep mode one channel
55.3
mW
Sleep Mode 2
Power Dissipation, Sleep mode both channels
20.4
mW
Power Down Dissipation
Rev 2A
59.0
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
Clock Inputs
Max. Conversion Rate
Min. Conversion Rate
©2009 CADEKA Microcircuits LLC 65
MSPS
40
MSPS
www.cadeka.com
CDK2307 Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters
SNR
72.6
FIN = 20MHz
8
Data Sheet
Electrical Characteristics - CDK2307D
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 80MSPS clock, 50% clock duty cycle,
-1dBFS 8MHz input signal, 13-bit output, unless otherwise noted)
Symbol
Parameter
Conditions
Min
FIN = 8MHz
70.4
Typ
Max
Units
Performance
Signal to Noise Ratio
dBFS
71.7
dBFS
FIN = 30MHz
71.2
dBFS
FIN ≃ FS/2
70.7
dBFS
70.5
dBFS
FIN = 20MHz
70.5
dBFS
FIN = 30MHz
70.4
dBFS
FIN ≃ FS/2
70.3
dBFS
FIN = 8MHz
SINAD
Signal to Noise and Distortion Ratio
FIN = 8MHz
SFDR
Spurious Free Dynamic Range
69.5
77
dBc
FIN = 20MHz
74
78
dBc
FIN = 30MHz
78
dBc
FIN ≃ FS/2
78
dBc
-95
dBc
-90
dBc
FIN = 30MHz
-90
dBc
FIN ≃ FS/2
-85
dBc
-77
dBc
-78
dBc
FIN = 30MHz
-78
dBc
FIN ≃ FS/2
-78
dBc
11.4
bits
FIN = 20MHz
11.4
bits
FIN = 30MHz
11.4
bits
FIN ≃ FS/2
11.4
bits
Signal crosstalk between channels, FIN1 =
8MHz, FIN0 = 9.9MHz
-95.0
dB
FIN = 8MHz
HD2
Second order Harmonic Distortion
FIN = 20MHz
FIN = 8MHz
HD3
Third order Harmonic Distortion
XTALK
Effective number of Bits
Crosstalk
-74
FIN = 20MHz
FIN = 8MHz
ENOB
-80
11.3
Power Supply
AIDD
Analog Supply Current
DIDD
Digital Supply Current
OIDD
Output Driver Supply
39.7
mA
Digital core supply
6.0
mA
2.5V output driver supply, sine wave input,
FIN = 1MHz
9.4
mA
2.5V output driver supply, sine wave input,
FIN = 1MHz, CLK_EXT disabled
7.7
mA
Analog Power Dissipation
mW
Digital Power Dissipation
30
mW
Total Power Dissipation
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
101.5
mW
9.1
µW
Sleep Mode 1
Power Dissipation, Sleep mode one channel
66.4
mW
Sleep Mode 2
Power Dissipation, Sleep mode both channels
24.1
mW
Power Down Dissipation
Rev 2A
71.5
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
Clock Inputs
Max. Conversion Rate
Min. Conversion Rate
©2009 CADEKA Microcircuits LLC 80
MSPS
65
MSPS
www.cadeka.com
CDK2307 Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters
SNR
72
FIN = 20MHz
9
Data Sheet
Digital and Timing Electrical Characteristics
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 50 MSPS clock, 50% clock duty cycle,
-1 dBFS input signal, 5pF capacitive load, unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
80
% high
Clock Inputs
20
Compliance
CMOS, LVDS, LVPECL, Sine Wave
Differential input swing
-200
200
mVpp
Differential input swing, sine wave clock input
-800
800
mVpp
Input Common Mode Voltage
Keep voltages within ground and voltage of OVDD
0.3
VOVDD -0.3
V
Input Resistance
Differential
TBD
kΩ
Input Capacitance
Differential
2
pF
TPD
Start Up Time Active Mode
From Power Down Mode to Active Mode
900
TSLP
Start Up Time Mode
From Sleep Mode to Active
20
TOVR
Out Of Range Recovery Time
TAP
Aperture Delay
0.8
ns
εRMS
Aperture Jitter
<0.5
psrms
TLAT
Pipeline Delay
12
clk cycles
TD
Output Delay (see timing diagram)
5pF load on output bits
3
10
ns
TDC
Output Delay (see timing diagram)
Relative to CLK_EXT
1
6
ns
VOVDD ≥ 3.0V
2
Input Range
Timing
1
clk cycles
µs
clk cycles
Logic Inputs
VHI
High Level Input Voltage
VOVDD = 1.7V – 3.0V
V
0.8 • VOVDD
V
VOVDD ≥ 3.0V
0
0.8
V
VOVDD = 1.7V – 3.0V
0
0.2 • VOVDD
V
VLI
Low Level Input Voltage
IHI
High Level Input Leakage Current
-10
10
µA
ILI
Low Level Input Leakage Current
-10
10
µA
CI
Input Capacitance
3
pF
Logic Outputs
VHO
High Level Output Voltage
VLO
Low Level Output Voltage
CL
Max Capacitive Load
VOVDD-0.1
V
Post-driver supply voltage equal to pre-driver
supply voltage VOVDD = VOVDD
Post-driver supply voltage above 2.25V (1)
0.1
V
5
pF
10
pF
Note:
(1) The outputs will be functional with higher loads. However, it is recommended to keep the load on output data bits as low as possible to keep dynamic currents
and resulting switching noise at a minimum.
CDK2307 Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters
Duty Cycle
Rev 2A
©2009 CADEKA Microcircuits LLC www.cadeka.com
10
Data Sheet
+F1
+F4
+F
+F2
+
+F0
CLK_EXT
Figure 1. Timing Diagram
Recommended Usage
DC-Coupling
Analog Input
Figure 3 shows a recommended configuration for DCcoupling. Note that the common mode input voltage must
be controlled according to specified values. Preferably, the
CM_EXT output should be used as a reference to set the
common mode voltage.
The analog input to the CDK2307 is done through a
switched capacitor track-and-hold amplifier optimized for
differential operation. Operation at mid supply common
mode voltage is recommended even if performance will
be good for the ranges specified. The CM_EXT pin provides a voltage suitable for a common mode voltage reference. The internal buffer for the CM_EXT voltage can be
switched off, and driving capabilities can be changed by
using the CM_EXTBC control input.
Ω
pF
Ω
Rev 2A
Figure 2 shows a simplified drawing of the input network.
The signal source must have sufficiently low output impedance to charge the sampling capacitors within one clock
cycle. A small external resistor (e.g. 22Ω) in series with
each input is recommended as it helps reducing transient
currents and dampens ringing behavior. A small differential
shunt capacitor at the chip side of the resistors may be
used to provide dynamic charging currents and may improve performance. The resistors form a low pass filter
with the capacitor, and values must therefore be determined by requirements for the application.
The input amplifier could be inside a companion chip or
it could be a dedicated amplifier. Several suitable single
ended to differential driver amplifiers exist in the market.
The system designer should make sure the specifications
of the selected amplifier is adequate for the total system,
and that driving capabilities comply with the CDK2307
input specifications.
Figure 3. DC-Coupled Input
Detailed configuration and usage instructions must be
found in the documentation of the selected driver.
AC-Coupling
Figure 2. Input Configuration
©2009 CADEKA Microcircuits LLC A signal transformer or series capacitors can be used to
make an AC-coupled input network. Figure 4 shows a
recommended configuration using a transformer. Make
sure that a transformer with sufficient linearity is selected,
www.cadeka.com
CDK2307 Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters
N-13
11
Data Sheet
If the input signal is traveling a long physical distance
from the signal source to the transformer (for example a
long cable), kick-backs from the ADC will also travel along
this distance. If these kick-backs are not terminated properly at the source side, they are reflected and will add to
the input signal at the ADC input. This could reduce the
ADC performance. To avoid this effect, the source must
effectively terminate the ADC kick-backs, or the traveling
distance should be very short. If this problem could not be
avoided, the circuit in Figure 6 can be used.
Note that startup time from Sleep Mode and Power Down
Mode will be affected by this filter as the time required
to charge the series capacitors is dependent on the filter
cut-off frequency.
If the input signal has a long traveling distance, and the
kick-backs from the ADC not are effectively terminated
at the signal source, the input network of Figure 6 can
be used. The configuration is designed to attenuate the
kickback from the ADC and to provide an input impedance
that looks as resistive as possible for frequencies below
Nyquist. Values of the series inductor will however depend
on board design and conversion rate. In some instances
a shunt capacitor in parallel with the termination resistor
(e.g. 33pF) may improve ADC performance further. This
capacitor attenuate the ADC kick-back even more, and
minimize the energy traveling towards the source. However, the impedance match seen into the transformer will
become worse.
120nH 33Ω
1:1
33Ω
optional
RT
47Ω
RT
68Ω
220Ω
pF
120nH
33Ω
33Ω
Figure 4. Transformer-Coupled Input
Ω
pF
Ω
Figure 5. AC-Coupled Input
©2009 CADEKA Microcircuits LLC Clock Input And Jitter Considerations
Typically high-speed ADCs use both clock edges to generate
internal timing signals. In the CDK2307 only the rising
edge of the clock is used. Hence, input clock duty cycles
between 20% and 80% are acceptable.
The input clock can be supplied in a variety of formats.
The clock pins are AC-coupled internally, and hence a
wide common mode voltage range is accepted. Differential clock sources such as LVDS, LVPECL or differential
sine wave can be connected directly to the input pins.
For CMOS inputs, the CLKN pin should be connected to
ground, and the CMOS clock signal should be connected
to CLKP. For differential sine wave clock input the amplitude must be at least ±800mVpp.
www.cadeka.com
12
Rev 2A
Figure 5 shows AC-coupling using capacitors. Resistors
from the CM_EXT output, RCM, should be used to bias the
differential input signals to the correct voltage. The series
capacitor, CI, form the high-pass pole with these resistors,
and the values must therefore be determined based on
the requirement to the high-pass cut-off frequency.
Figure 6. Alternative Input Network
CDK2307 Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters
and that the bandwidth of the transformer is appropriate.
The bandwidth should exceed the sampling rate of the
ADC with at least a factor of 10. It is also important to
keep phase mismatch between the differential ADC inputs
small for good HD2 performance. This type of transformer
coupled input is the preferred configuration for high frequency signals as most differential amplifiers do not have
adequate performance at high frequencies. Magnetic
coupling between the transformers and PCB traces may
impact channel crosstalk, and must hence be taken into
account during PCB layout.
Data Sheet
The quality of the input clock is extremely important for
high-speed, high-resolution ADCs. The contribution to SNR
from clock jitter with a full scale signal at a given frequency
is shown in equation 1.
•
π • FIN • εt)
where FIN is the signal frequency, and εt is the total rms
jitter measured in seconds. The rms jitter is the total of all
jitter sources including the clock generation circuitry, clock
distribution and internal ADC circuitry.
For applications where jitter may limit the obtainable performance, it is of utmost importance to limit the clock jitter. This can be obtained by using precise and stable clock
references (e.g. crystal oscillators with good jitter specifications) and make sure the clock distribution is well controlled. It might be advantageous to use analog power and
ground planes to ensure low noise on the supplies to all
circuitry in the clock distribution. It is of utmost importance
to avoid crosstalk between the ADC output bits and the
clock and between the analog input signal and the clock
since such crosstalk often results in harmonic distortion.
Note that the out of range flags (ORNG) will behave differently for 12-bit and 13-bit output. For 13-bit output ORNG
will be set when digital output data are all ones or all
zeros. For 12-bit output the ORNG flags will be set when
all twelve bits are zeros or ones and when the thirteenth
bit is equal to the rest of the bits.
The CDK2307 employs digital offset correction. This means
that the output code will be 4096 with the positive and
negative inputs shorted together(zero differential). However, small mismatches in parasitics at the input can cause
this to alter slightly. The offset correction also results in
possible loss of codes at the edges of the full scale range.
With “NO” offset correction, the ADC would clip in one
end before the other, in practice resulting in code loss at
the opposite end. With the output being centered digitally,
the output will clip, and the out of range flags will be set,
before max code is reached. When out of range flags are
set, the code is forced to all ones for over-range and all
zeros for under-range.
The jitter performance is improved with reduced rise and
fall times of the input clock. Hence, optimum jitter performance is obtained with LVDS or LVPECL clock with fast
edges. CMOS and sine wave clock inputs will result in
slightly degraded jitter performance.
Data Format Selection
If the clock is generated by other circuitry, it should be
retimed with a low jitter master clock as the last operation
before it is applied to the ADC clock input.
The data outputs can be used in three different configurations.
Digital Outputs
The timing is described in the Timing Diagram section.
Note that the load or equivalent delay on CLK_EXT always
should be lower than the load on data outputs to ensure
sufficient timing margins.
©2009 CADEKA Microcircuits LLC Normal mode:
All 13-bits are used. MSB is Dx_12 and LSB is Dx_0. This
mode gives optimum performance due to reduced quantization noise.
12-bit mode:
The LSB is left unconnected such that only 12 bits are used.
MSB is Dx_12 and LSB is Dx_1. This mode gives slightly
reduced performance, due to increased quantization noise.
Reduced full scale range mode:
The full scale range is reduced from 2Vpp to 1Vpp which is
equivalent to 6dB gain in the ADC frontend. MSB is Dx_11
and LSB is Dx_0. Note that the codes will wrap around
when exceeding the full scale range, and that out of range
bits should be used to clamp output data. See section
Reference Voltages for details. This mode gives slightly
reduced performance.
www.cadeka.com
13
Rev 2A
Digital output data are presented in a parallel CMOS form.
The voltage on the OVDD pin sets the levels of the CMOS
outputs. The output drivers are dimensioned to drive a
wide range of loads for OVDD above 2.25V, but it is recommended to minimize the load to ensure as low transient switching currents and resulting noise as possible. In
applications with a large fanout or large capacitive loads,
it is recommended to add external buffers located close to
the ADC chip.
The output data are presented on offset binary form
when DFRMT is low (connect to OVSS). Setting DFRMT
high (connect to OVDD) results in 2’s complement output
format. Details are shown in Table 1 on page 14.
CDK2307 Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters
SNRjitter = 20 • log (2
The digital outputs can be set in tristate mode by setting
the OE_N signal high.
Data Sheet
Table 1: Data Format Description for 2Vpp Full Scale Range
Output Data: Dx_12 : Dx_0
(DFRMT = 0, offset binary)
(DFRMT = 1, 2’s complement)
1.0 V
1 1111 1111 1111
0 1111 1111 1111
+0.24mV
1 0000 0000 0000
0 0000 0000 0000
-0.24mV
0 1111 1111 1111
1 1111 1111 1111
-1.0V
0 0000 0000 0000
1 0000 0000 0000
Reference Voltages
Operational Modes
The reference voltages are internally generated and buffered based on a bandgap voltage reference. No external
decoupling is necessary, and the reference voltages are
not available externally. This simplifies usage of the ADC
since two extremely sensitive pins, otherwise needed, are
removed from the interface.
The operational modes are controlled with the PD_N and
SLP_N pins. If PD_N is set low, all other control pins are
overridden and the chip is set in Power Down mode. In
this mode all circuitry is completely turned off and the
internal clock is disabled. Hence, only leakage current
contributes to the Power Down Dissipation. The startup
time from this mode is longer than for other idle modes
as all references need to settle to their final values before
normal operation can resume.
If a lower full scale range is required the 13-bit output
word provides sufficient resolution to perform digital scalingwith an equivalent impact on noise compared to adjusting
the reference voltages.
A simple way to obtain 1.0Vpp input range with a 12-bit
output word is shown in the table on page 10. Note that
only 2‘s complement output data are available in this
mode and that out of range conditions must be determined based on a two bit output. The output code will
wrap around when the code goes outside the full scale
range. The out of range bits should be used to clamp the
output data for overrange conditions.
The SLP_N bus can be used to power down each channel
independently, or to set the full chip in Sleep Mode. In this
mode internal clocking is disabled, but some low bandwidth circuitry is kept on to allow for a short startup time.
However, Sleep Mode represents a significant reduction in
supply current, and it can be used to save power even for
short idle periods.
The input clock could be kept running in all idle modes.
However, even lower power dissipation is possible in
Power Down mode if the input clock is stopped. In this
case it is important to start the input clock prior to enabling active mode.
Table 2: Data Format Description for 1Vpp Full Scale Range
Output data: Dx_11:
Dx_0 (DFRMT = 0)
> 0.5V
0111 1111 1111
0.5V
0111 1111 1111
0111 1111 1111
+0.24mV
0000 0000 0000
0000 0000 0000
-0.24mV
1111 1111 1111
1111 1111 1111
-0.5V
1000 0000 0000
1000 0000 0000
< -0.5V
1000 0000 0000
(2’s Complement)
©2009 CADEKA Microcircuits LLC Out of Range
(Use Logical AND Function for &)
Dx_12 = 1 & Dx_11 = 1
Dx_12 = 0 & Dx_11 = 0
Output Data: Dx_11:
Dx_0 (DFRMT = 1)
(2’s Complement)
0111 1111 1111
1000 0000 0000
Out of Range
(Use Logical AND Function for &)
D_12 = 0 & D_11 = 1
Rev 2A
Differential Input
Voltage
(IPx - INx)
Dx_12 = 1 & Dx_11 = 0
www.cadeka.com
CDK2307 Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters
Output data: Dx_12 : Dx_0
Differential Input Voltage (IPx - INx)
14
Data Sheet
Mechanical Dimensions
QFN-64 Package
aaa C A
A
ccc C
D1
aaa C B
A1
E
E1
Symbol
A
A1
A2
A3
b
D
D1
D2
E
E1
E2
L
e
θ1
R
aaa
bbb
ccc
Min
–
0.00
–
0.008
0.149
0.149
0.012
0°
0.004
Inches
Millimeters
Typ
Max
Min
Typ
–
0.035
–
–
0.0004
0.002
0.00
0.01
0.026
0.028
–
0.65
0.008 REF
0.2 REF
0.010
0.012
0.2
0.25
0.354 BSC
9.00 BSC
0.354 BSC
8.75 BSC
0.157
0.165
3.79
3.99
0.354 BSC
9.00 BSC
0.344 BSC
8.75 BSC
0.157
0.165
3.79
3.99
0.016
0.020
0.3
0.4
0.020 BSC
0.50 BSC
–
12°
0°
–
–
–
0.10
–
Tolerance of Form and Position
0.10
0.004
0.10
0.004
0.05
0.002
Max
0.9
0.05
0.7
0.30
4.19
4.19
0.5
12°
–
NOTES:
0.05 Dia. R
1. All dimensions are in millimeters.
2. Die thickness allowable is 0.305mm maximum (.012 inches maximum)
3. Dimensioning & tolerances conform to ASME y14.5m. -1994.
4. Dimension applies to plated terminal and is measured between 0.20 and 0.25mm from terminal tip.
B
C
bbb C A
1.14
5. The pin #1 identifier must be placed on the top surface of the package by using indentation mark
or other feature of package body.
6. Exact shape and size of this feature is optional.
7. Package warpage max 0.08mm.
8. Applied for exposed pad and terminals. Exclude embedding part of exposed pad from measuring.
9. Applied only to terminals.
TOP VIEW
Pin 1 ID
0.20 R
seating
plane
θ1
1.14
bbb C B
D2
0.45
SIDE VIEW
10. Package corners unless otherwise specipied are r0.175±0.025mm.
0.42
±0.18
R
0.42
±0.18
E2
L
e
b
0.10 M C A B
L
BOTTOM VIEW
CDK2307 Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters
A
A2
A3
D
Rev 2A
©2009 CADEKA Microcircuits LLC www.cadeka.com
15
Data Sheet
Mechanical Dimensions (Continued)
TQFP-64 Package
TOP VIEW
SIDE VIEW
Min
–
0.002
0.037
0.003
0.003
0°
0°
11°
11°
0.004
0.018
0.008
0.007
Inches
Typ
–
–
0.039
0.472 BSC
0.393 BSC
0.472 BSC
0.393 BSC
–
–
3.5°
–
12°
12°
–
0.24
0.039 REF
–
0.008
0.020 BSC
0.295
0.295
0.008
0.008
0.003
0.003
Max
0.047
0.006
0.041
Min
–
0.05
0.95
0.008
–
7°
–
13°
13°
0.008
0.030
0.08
0.08
0°
0°
11°
11°
0.09
0.45
–
0.011
0.20
0.17
Millimeters
Typ
–
–
1.00
12.00 BSC
10.00 BSC
12.00 BSC
10.00 BSC
–
–
3.5°
–
12°
12°
0.20
0.75
1.00 REF
–
0.20
0.520 BSC
7.50
7.50
0.20
0.20
0.08
0.08
Max
1.2
0.15
1.05
0.20
–
7°
–
13°
13°
–
0.27
NOTES:
1. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is
0.25mm per side. D1 and E1 are maxmum plastic body size dimensions
including mold mismatch.
2. Dimension b does not include dambar protrusion. Allowable dambar protrusion
shall not cause the lead width to exceed the maximum b dimension by more
than 0.08mm.
3. Dambar can not be located on the lower radius or the foot. Minimum space
between protrusion and an adjacent lead is 0.07mm for 0.4mm and 0.5mm
pitch packages.
DETAIL SIDE VIEW
CDK2307 Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters
Symbol
A
A1
A2
D
D1
E
E1
R2
R1
θ
θ1
θ2
θ3
c
L
L1
S
b
e
D2
E2
aaa
bbb
ccc
ddd
Rev 2A
For additional information regarding our products, please visit CADEKA at: cadeka.com
CADEKA Headquarters Loveland, Colorado
T: 970.663.5452
T: 877.663.5452 (toll free)
A m p l i fy t h e H u m a n E x p e r i e n c e
CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA
Microcircuits LLC. All other brand and product names may be trademarks of their respective companies.
CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any
responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in
writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties.
Copyright ©2009 by CADEKA Microcircuits LLC. All rights reserved. designed by