DAVICOM DM9000A_06

DM9000A
Ethernet Controller with General Processor Interface
DAVICOM Semiconductor, Inc.
DM9000A
Ethernet Controller
with General Processor Interface
DATA SHEET
Final
Version : DM9000A-DS-F01
May 10, 2006
Final
Version: DM9000A-17-DS-F01
May 10, 2006
1
DM9000A
Ethernet Controller with General Processor Interface
Content
1. General Description............................................................................................................................................................ 6
2. Block Diagram .................................................................................................................................................................... 6
3. Features ............................................................................................................................................................................... 7
4. Pin Configuration ............................................................................................................................................................... 8
4.1 (16-bit mode) ................................................................................................................................................................. 8
4.2 (8-bit mode) ................................................................................................................................................................... 9
5. Pin Description.................................................................................................................................................................. 10
5.1 Processor Interface ...................................................................................................................................................... 10
5.1.1 8-bit mode pins.......................................................................................................................................................... 10
5.2 EEPROM Interface .......................................................................................................................................................11
5.3 Clock Interface..............................................................................................................................................................11
5.4 LED Interface ...............................................................................................................................................................11
5.5 10/100 PHY/Fiber.........................................................................................................................................................11
5.6 Miscellaneous .............................................................................................................................................................. 12
5.7 Power Pins................................................................................................................................................................... 12
5.8 strap pins table ............................................................................................................................................................ 12
6. Vendor Control and Status Register Set ......................................................................................................................... 13
6.1 Network Control Register (00H).................................................................................................................................. 14
6.2 Network Status Register (01H) .................................................................................................................................... 15
6.3 TX Control Register (02H)........................................................................................................................................... 15
6.4 TX Status Register I ( 03H ) for packet index I ............................................................................................................ 15
6.5 TX Status Register II ( 04H ) for packet index I I......................................................................................................... 16
6.6 RX Control Register ( 05H ) ........................................................................................................................................ 16
6.7 RX Status Register ( 06H ) ........................................................................................................................................... 16
6.8 Receive Overflow Counter Register ( 07H ) ................................................................................................................ 17
6.9 Back Pressure Threshold Register (08H)..................................................................................................................... 17
6.10 Flow Control Threshold Register ( 09H ) .................................................................................................................. 17
6.11 RX/TX Flow Control Register ( 0AH ) ....................................................................................................................... 19
6.12 EEPROM & PHY Control Register ( 0BH )............................................................................................................... 19
6.13 EEPROM & PHY Address Register ( 0CH ) .............................................................................................................. 19
6.14 EEPROM & PHY Data Register (EE_PHY_L：0DH
Final
Version: DM9000A-17-DS-F01
May 10, 2006
EE_PHY_H：0EH).......................................................... 19
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DM9000A
Ethernet Controller with General Processor Interface
6.15 Wake Up Control Register ( 0FH ) (in 8-bit mode).................................................................................................... 20
6.16 Physical Address Register ( 10H~15H ) .................................................................................................................... 20
6.17 Multicast Address Register ( 16H~1DH ) .................................................................................................................. 20
6.18 General purpose control Register
( 1EH ) ( For
6.19 General purpose Register ( 1FH ) ( For
8 Bit mode only, For 16 bit mode, see reg . 34H) .................... 20
8 Bit mode only, For 16 bit mode, see reg . 34H) ................................... 22
6.20 TX SRAM Read Pointer Address Register (22H~23H) .............................................................................................. 22
6.21 RX SRAM Write Pointer Address Register (24H~25H).............................................................................................. 22
6.22 Vendor ID Register (28H~29H) ................................................................................................................................. 22
6.23 Product ID Register (2AH~2BH)............................................................................................................................... 22
6.24 Chip Revision Register (2CH) ................................................................................................................................... 22
6.25 Transmit Control Register 2 ( 2DH ) ......................................................................................................................... 22
6.26 Operation Test Control Register ( 2EH ) ................................................................................................................... 23
6.27 Special Mode Control Register ( 2FH ) ..................................................................................................................... 23
6.28 Early Transmit Control/Status Register ( 30H )......................................................................................................... 24
6.29 Check Sum Control Register ( 31H ).......................................................................................................................... 24
6.30 Receive Check Sum Status Register ( 32H )............................................................................................................... 24
6.31 MII PHY Address Register ( 33H )............................................................................................................................. 25
6.32 LED Pin Control Register ( 34H ) ............................................................................................................................. 25
6.33 Processor Bus Control Register ( 38H ) .................................................................................................................... 25
6.34 INT Pin Control Register ( 39H )............................................................................................................................... 26
6.35 System Clock Turn ON Control Register ( 50H ) ....................................................................................................... 26
6.36 Resume System Clock Control Register ( 51H )......................................................................................................... 26
6.37 Memory Data Pre-Fetch Read Command without Address Increment Register (F0H) ............................................. 26
6.38 Memory Data Read Command without Address Increment Register (F1H) .............................................................. 26
6.39 Memory Data Read Command with Address Increment Register (F2H) ................................................................... 26
6.40 Memory Data Read_address Register (F4H~F5H) ................................................................................................... 26
6.41 Memory Data Write Command without Address Increment Register (F6H).............................................................. 26
6.42 Memory data write command with address increment Register (F8H) ..................................................................... 27
6.43 Memory data write_address Register (FAH~FBH).................................................................................................... 27
6.44 TX Packet Length Register (FCH~FDH)................................................................................................................... 27
6.45 Interrupt Status Register (FEH)................................................................................................................................. 27
6.46 Interrupt Mask Register (FFH).................................................................................................................................. 27
7. EEPROM Format............................................................................................................................................................. 28
8. PHY Register Description ................................................................................................................................................ 29
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Version: DM9000A-17-DS-F01
May 10, 2006
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DM9000A
Ethernet Controller with General Processor Interface
8.1 Basic Mode Control Register (BMCR) - 00 ................................................................................................................. 30
8.2 Basic Mode Status Register (BMSR) - 01..................................................................................................................... 31
8.3 PHY ID Identifier Register #1 (PHYID1) - 02 ............................................................................................................. 33
8.4 PHY ID Identifier Register #2 (PHYID2) - 03 ............................................................................................................. 33
8.5 Auto-negotiation Advertisement Register (ANAR) - 04................................................................................................ 34
8.6 Auto-negotiation Link Partner Ability Register (ANLPAR) – 05.................................................................................. 35
8.7 Auto-negotiation Expansion Register (ANER)- 06....................................................................................................... 36
8.8 DAVICOM Specified Configuration Register (DSCR) - 16 ......................................................................................... 36
8.9 DAVICOM Specified Configuration and Status Register (DSCSR) - 17 ...................................................................... 38
8.10 10BASE-T Configuration/Status (10BTCSR) - 18...................................................................................................... 39
8.11 Power Down Control Register (PWDOR) - 19 .......................................................................................................... 40
8.12 (Specified config) Register – 20 ................................................................................................................................. 40
9. Functional Description ..................................................................................................................................................... 42
9.1 Host Interface .............................................................................................................................................................. 42
9.2 Direct Memory Access Control .................................................................................................................................... 42
9.3 Packet Transmission .................................................................................................................................................... 42
9.4 Packet Reception.......................................................................................................................................................... 42
9.5 100Base-TX Operation ................................................................................................................................................ 43
9.5.1 4B5B Encoder ...................................................................................................................................................... 43
9.5.2 Scrambler ............................................................................................................................................................. 43
9.5.3 Parallel to Serial Converter .................................................................................................................................. 43
9.5.4 NRZ to NRZI Encoder ......................................................................................................................................... 43
9.5.5 MLT-3 Converter.................................................................................................................................................. 43
9.5.6 MLT-3 Driver ....................................................................................................................................................... 43
9.5.7 4B5B Code Group................................................................................................................................................ 44
9.6 100Base-TX Receiver................................................................................................................................................... 45
9.6.1 Signal Detect ........................................................................................................................................................ 45
9.6.2 Adaptive Equalization .......................................................................................................................................... 45
9.6.3 MLT-3 to NRZI Decoder...................................................................................................................................... 45
9.6.4 Clock Recovery Module ...................................................................................................................................... 45
9.6.5 NRZI to NRZ ....................................................................................................................................................... 45
9.6.6 Serial to Parallel ................................................................................................................................................... 45
9.6.7 Descrambler ......................................................................................................................................................... 45
9.6.8 Code Group Alignment ........................................................................................................................................ 46
9.6.9 4B5B Decoder...................................................................................................................................................... 46
9.7 10Base-T Operation..................................................................................................................................................... 46
9.8 Collision Detection ...................................................................................................................................................... 46
9.9 Carrier Sense ............................................................................................................................................................... 46
9.10 Auto-Negotiation........................................................................................................................................................ 46
9.11 Power Reduced Mode ................................................................................................................................................ 47
9.11.1 Power Down Mode............................................................................................................................................. 47
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Version: DM9000A-17-DS-F01
May 10, 2006
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DM9000A
Ethernet Controller with General Processor Interface
9.11.2 Reduced Transmit Power Mode ......................................................................................................................... 47
10. DC and AC Electrical Characteristics .......................................................................................................................... 48
10.1 Absolute Maximum Ratings ( 25°C ).......................................................................................................................... 48
10.1.1 Operating Conditions ......................................................................................................................................... 48
10.2 DC Electrical Characteristics (VDD = 3.3V)............................................................................................................ 48
10.3 AC Electrical Characteristics & Timing Waveforms.................................................................................................. 49
10.3.1 TP Interface ........................................................................................................................................................ 49
10.3.2 Oscillator/Crystal Timing................................................................................................................................... 49
10.3.3 Processor I/O Read Timing ................................................................................................................................ 49
10.3.4 Processor I/O Write Timing ............................................................................................................................... 50
10.3.5 EEPROM Interface Timing................................................................................................................................ 51
11. Application Notes ............................................................................................................................................................ 52
11.1 Network Interface Signal Routing .............................................................................................................................. 52
11.2 10Base-T/100Base-TX Auto MDIX Application......................................................................................................... 52
11.3 10Base-T/100Base-TX ( Non Auto MDIX Transformer Application )........................................................................ 53
11.4 Power Decoupling Capacitors ................................................................................................................................... 54
11.5 Ground Plane Layout ................................................................................................................................................. 55
11.6 Power Plane Partitioning .......................................................................................................................................... 56
11.7 Magnetics Selection Guide......................................................................................................................................... 57
11.8 Crystal Selection Guide.............................................................................................................................................. 57
12. Package Information ...................................................................................................................................................... 58
13. Ordering Information .................................................................................................................................................... 59
Final
Version: DM9000A-17-DS-F01
May 10, 2006
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DM9000A
Ethernet Controller with General Processor Interface
1. General Description
The DM9000A is a fully integrated and cost-effective
low pin count single chip Fast Ethernet controller with
a general processor interface, a 10/100M PHY and 4K
Dword SRAM. It is designed with low power and high
performance process that support 3.3V with 5V IO
tolerance.
processors. The PHY of the DM9000A can interface to the
UTP3, 4, 5 in 10Base-T and UTP5 in 100Base-TX with
HP Auto-MDIX. It is fully compliant with the IEEE 802.3u
Spec. Its auto-negotiation function will automatically
configure the DM9000A to take the maximum advantage of
its abilities. The DM9000A also supports IEEE 802.3x fullduplex flow control..
The DM9000A supports 8-bit and 16-bit data
interfaces to internal memory accesses for various
2. Block Diagram
EEPROM
Interface
LED
MAC
PHYceiver
TX Machine
100 Base-TX
PCS
MII
TX+/AUTO-MDIX
10 Base-T
Tx/Rx
Control
&Status
Registers
Memory
Management
RX Machine
Processor
Interface
100 Base-TX
transceiver
RX+/Internal
SRAM
Autonegotiation
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Version: DM9000A-17-DS-F01
May 10, 2006
MII Management
Control
& MII Register
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DM9000A
Ethernet Controller with General Processor Interface
3. Features
■ 48-pin LQFP
■ Supports processor interface: byte/word of I/O
command to internal memory data operation
■ Integrated 10/100M transceiver
with HP Auto-MDIX
■
Supports back pressure mode for half-duplex
■
mode flow control
IEEE802.3x flow control for full-duplex mode
■
Supports wakeup frame, link status change and
magic packet events for remote wake up
Support 100M Fiber interface.
■
Integrated 16K Byte SRAM
■
Build in 3.3V to 2.5V regulator
■
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Version: DM9000A-17-DS-F01
May 10, 2006
■ Supports early Transmit
■
Supports IP/TCP/UDP checksum generation and
checking
■
Supports automatically load vendor ID and
product ID from EEPROM
■ Optional EEPROM configuration
■ Very low power consumption mode:
– Power reduced mode (cable detection)
– Power down mode
– Selectable TX drivers for 1:1 or 1.25:1
transformers for additional power reduction.
■ Compatible with 3.3V and 5.0V tolerant I/O
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DM9000A
Ethernet Controller with General Processor Interface
4. Pin Configuration
SD9
SD10
SD11
SD12
SD13
29
28
27
26
25
CMD
32
SD8
GND
33
VDD
INT
34
30
IOR#
35
31
IOW#
36
4.1 (16-bit mode)
CS#
37
24
SD14
LED2
38
23
VDD
LED1
39
22
SD15
PWRST#
40
21
EECS
TEST
41
20
EECK
VDD
42
19
EEDIO
X2
43
18
SD0
X1
44
17
SD1
GND
45
16
SD2
SD
46
15
GND
RXGND
47
14
SD3
BGGND
48
13
SD4
Final
Version: DM9000A-17-DS-F01
May 10, 2006
12
9
TXVDD25
11
8
TX-
SD6
SD5
7
10
6
TXGND
TX+
SD7
5
RX+
4
3
RXVDD25
RX-
2
RXGND
1
BGRES
DM9000A
(16-bit mode)
8
DM9000A
Ethernet Controller with General Processor Interface
IOR#
INT
GND
CMD
GP1
VDD
GP2
GP3
GP4
GP5
GP6
35
34
33
31
30
29
28
27
26
25
32
IOW#
36
4.2 (8-bit mode)
CS#
37
24
LED3
LED2
38
23
VDD
LED1
39
22
WAKE
PWRST#
40
21
EECS
TEST
41
20
EECK
VDD
42
19
EEDIO
X2
43
18
SD0
DM9000A
(8-bit mode)
X1
44
17
SD1
GND
45
16
SD2
Final
Version: DM9000A-17-DS-F01
May 10, 2006
TXVDD25
12
9
11
8
TX-
SD5
7
TX+
SD6
6
TXGND
10
5
RXGND
SD7
4
SD4
3
13
RX-
SD3
48
RX+
14
BGGND
2
GND
RXVDD25
15
47
1
46
BGRES
SD
RXGND
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DM9000A
Ethernet Controller with General Processor Interface
5. Pin Description
I = Input
O = Output
# = asserted low
I/O = Input/Output
O/D = Open Drain
P = Power
PD = internal pull-low about 60K
5.1 Processor Interface
Pin No.
Pin Name
Description
Type
Processor Read Command
This pin is low active at default, its polarity can be modified by EEPROM setting.
See the EEPROM content description for detail
Processor Write Command
This pin is low active at default, its polarity can be modified by EEPROM setting.
See the EEPROM content description for detail
Chip Select
A default low active signal used to select the DM9000A. Its polarity can be
modified by EEPROM setting. See the EEPROM content description for detail.
35
IOR#
I,PD
36
IOW#
I,PD
37
CS#
I,PD
32
CMD
34
INT
18,17,16,
14,13,12,
11,10
SD0~7
I/O,PD
SD8~15
Processor Data Bus bit 8~15
In 16-bit mode, these pins act as the processor data bus bit 8~15;
I/O,PD
When EECS pin is pulled high , they have other definitions. See 8-bit mode pin
description for details.
31,29,28,
27,26,25,
24,22
Command Type
When high, the access of this command cycle is DATA port
When low, the access of this command cycle is INDEX port
Interrupt Request
This pin is high active at default, its polarity can be modified by EEPROM
O,PD
setting or by strap pin EECK. See the EEPROM content description for
detail
I,PD
Processor Data Bus bit 0~7
5.1.1 8-bit mode pins
Pin No.
Pin Name
22
WAKE
24
LED3
25,26,27
GP6~4
28,29,31
GP3,GP2,GP1
Final
Version: DM9000A-17-DS-F01
May 10, 2006
Type
Description
O,PD Issue a wake up signal when wake up event happens
Full-duplex LED
In LED mode 1, Its low output indicates that the internal PHY is operated
in full-duplex mode, or it is floating for the half-duplex mode of the internal
O,PD PHY
In LED mode 0, Its low output indicates that the internal PHY is operated
in 10M mode, or it is floating for the 100M mode of the internal PHY
Note: LED mode is defined in EEPROM setting.
General Purpose output pins:
These pins are output only for general purpose that are configured by
register 1Fh.
O,PD
GP6 pin also act as trap pin for the INT output type.
When GP6 is pulled high, the INT is Open-Drain output type;
Otherwise it is force output type.
General I/O Ports
I/O
Registers GPCR and GPR can program these pins
10
DM9000A
Ethernet Controller with General Processor Interface
These pins are input ports at default.
5.2 EEPROM Interface
Description
Pin No.
Pin Name
19
EEDIO
I/O,PD IO Data to EEPROM
Clock to EEPROM
20
EECK
O,PD
EECS
Chip Select to EEPROM
This pin is also used as a strap pin to define the internal memory data bus
O,PD
width. When it is pulled high, the memory access bus is 8-bit; Otherwise it
is 16-bit.
21
Type
This pin is also used as the strap pin of the polarity of the INT pin
When this pin is pulled high, the INT pin is low active; otherwise the INT pin is
high active
5.3 Clock Interface
Description
Pin No.
Pin Name
Type
43
X2
O
Crystal 25MHz Out
44
X1
I
Crystal 25MHz In
5.4 LED Interface
Pin No.
Pin Name
Description
Type
39
LED1
O
38
LED2
O
Speed LED
Its low output indicates that the internal PHY is operated in 100M/S, or it
is floating for the 10M mode of the internal PHY.
This pin also acts as ISA bus IO16 defined in EEPROM setting in 16-bit
mode.
Link / Active LED
In LED mode 1, it is the combined LED of link and carrier sense signal of
the internal PHY
In LED mode 0, it is the LED of the carrier sense signal of the internal
PHY only
This pin also acts as ISA bus IOWAIT or WAKE defined in EEPROM
setting in 16-bit mode.
5.5 10/100 PHY/Fiber
Pin No.
Pin Name
Description
Type
Fiber-optic Signal Detect
PECL signal, which indicates whether or not the fiber-optic receive pair is
receiving valid levels
Bandgap Ground
46
SD
I
48
BGGND
P
1
BGRES
I/O
2
RXVDD25
P
2.5V power output for TP RX
9
TXVDD25
P
2.5V power output for TP TX
3
RX+
I/O
Final
Version: DM9000A-17-DS-F01
May 10, 2006
Bandgap Pin
TP RX Input
11
DM9000A
Ethernet Controller with General Processor Interface
4
RX-
I/O
TP RX Input
5,47
RXGND
P
RX Ground
6
TXGND
P
TX Ground
7
TX+
I/O
TP TX Output
8
TX-
I/O
TP TX Output
5.6 Miscellaneous
Pin No.
Pin Name
Type
41
TEST
I
40
PWRST#
I
Description
Operation Mode
Force to ground in normal application
Power on Reset
Active low signal to initiate the DM9000A
The DM9000A is ready after 5us when this pin deasserted
5.7 Power Pins
Pin No.
Pin Name
Type
23,30,42
VDD
P
15,33,45
GND
P
Description
Digital VDD
3.3V power input
Digital GND
5.8 strap pins table
1: pull-high 1K~10K, 0: floating (default)
Pin No.
Pin Name
20
EECK
21
EECS
22
WAKE
25
GP6
Final
Version: DM9000A-17-DS-F01
May 10, 2006
Description
Polarity of INT
1: INT pin low active;
0: INT pin high active
DATA Bus Width
1: 8-bit
0: 16-bit
Polarity of CS# in 8-bit mode
1: CS# pin active high
0: CS# pin active low
INT output type in 8-bit mode
1: Open-Drain
0: force mode
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DM9000A
Ethernet Controller with General Processor Interface
6. Vendor Control and Status Register Set
The DM9000A implements several control and status
registers, which can be accessed by the host. These CSRs
Register
NCR
NSR
TCR
TSR I
TSR II
RCR
RSR
ROCR
BPTR
FCTR
FCR
EPCR
EPAR
EPDRL
EPDRH
WCR
PAR
MAR
GPCR
GPR
TRPAL
TRPAH
RWPAL
RWPAH
VID
PID
CHIPR
TCR2
OCR
SMCR
ETXCSR
TCSCR
RCSCSR
MPAR
LEDCR
BUSCR
INTCR
SCCR
are byte aligned. All CSRs are set to their default values by
hardware or software reset unless they are specified
Description
Offset
Network Control Register
Network Status Register
TX Control Register
TX Status Register I
TX Status Register II
RX Control Register
RX Status Register
Receive Overflow Counter Register
Back Pressure Threshold Register
Flow Control Threshold Register
RX Flow Control Register
EEPROM & PHY Control Register
EEPROM & PHY Address Register
EEPROM & PHY Low Byte Data Register
EEPROM & PHY High Byte Data Register
Wake Up Control Register (in 8-bit mode)
Physical Address Register
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H-15H
Multicast Address Register
General Purpose Control Register (in 8-bit mode)
General Purpose Register
TX SRAM Read Pointer Address Low Byte
TX SRAM Read Pointer Address High Byte
RX SRAM Write Pointer Address Low Byte
RX SRAM Write Pointer Address High Byte
Vendor ID
Product ID
CHIP Revision
TX Control Register 2
Operation Control Register
Special Mode Control Register
Early Transmit Control/Status Register
Transmit Check Sum Control Register
Receive Check Sum Control Status Register
MII PHY Address Register
LED Pin Control Register
Processor Bus Control Register
INT Pin Control Register
System Clock Turn ON Control Register
16H-1DH
1EH
1FH
22H
23H
24H
25H
28H-29H
2AH-2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
38H
39H
50H
Final
Version: DM9000A-17-DS-F01
May 10, 2006
Default value
after reset
00H
00H
00H
00H
00H
00H
00H
00H
37H
38H
00H
00H
40H
XXH
XXH
00H
Determined by
EEPROM
XXH
01H
XXH
00H
00H
00H
0CH
0A46H
9000H
19H
00H
00H
00H
00H
00H
00H
00H
00H
61H
00H
00H
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DM9000A
Ethernet Controller with General Processor Interface
RSCCR
MRCMDX
MRCMDX1
MRCMD
MRRL
MRRH
MWCMDX
MWCMD
MWRL
MWRH
TXPLL
TXPLH
ISR
IMR
Resume System Clock Control Register
Memory Data Pre-Fetch Read Command Without Address
Increment Register
Memory Data Read Command With Address Increment
Register
Memory Data Read Command With Address Increment
Register
Memory Data Read_ address Register Low Byte
Memory Data Read_ address Register High Byte
Memory Data Write Command Without Address Increment
Register
Memory Data Write Command With Address Increment
Register
Memory Data Write_ address Register Low Byte
Memory Data Write _ address Register High Byte
TX Packet Length Low Byte Register
TX Packet Length High Byte Register
Interrupt Status Register
Interrupt Mask Register
Key to Default
In the register description that follows, the default column
takes the form:
<Reset Value>, <Access Type>
Where：
<Reset Value>:
1
Bit set to logic one
0
Bit set to logic zero
X
No default value
P = power on reset default value
S = software reset default value
E = default value from EEPROM
51H
F0H
XXH
XXH
F1H
XXH
F2H
XXH
F4H
F5H
F6H
00H
00H
XXH
F8H
XXH
FAH
FBH
FCH
FDH
FEH
FFH
00H
00H
XXH
XXH
00H
00H
T = default value from strap pin
<Access Type>:
RO = Read only
RW = Read/Write
R/C = Read and Clear
RW/C1=Read/Write and Cleared by write 1
WO = Write only
Reserved bits are shaded and should be written with 0.
Reserved bits are undefined on read access.
6.1 Network Control Register (00H)
Bit
Name
Default
Description
7
RESERVED
P0,RW
Reserved
When set, it enables the wakeup function. Clearing this bit will also clears all
WAKEEN
6
P0,RW
wakeup event status
This bit will not be affected after a software reset
5
RESERVED
0,RO
Reserved
4
FCOL
PS0,RW Force Collision Mode, used for testing
3
FDX
PS0,RO
Full-Duplex Mode of the internal PHY.
Loopback Mode
Bit 2 1
PS00,
0 0
Normal
2:1
LBK
0 1
MAC Internal loopback
RW
1 0
Internal PHY 100M mode digital loopback
1 1
(Reserved)
0
RST
P0,RW
Software reset and auto clear after 10us
Final
Version: DM9000A-17-DS-F01
May 10, 2006
14
DM9000A
Ethernet Controller with General Processor Interface
6.2 Network Status Register (01H)
Bit
Name
Default
7
SPEED
X,RO
6
LINKST
5
WAKEST
4
RESERVED
3
TX2END
2
TX1END
1
0
RXOV
RESERVED
X,RO
P0,
RW/C1
0,RO
PS0,
RW/C1
PS0,
RW/C1
PS0,RO
0,RO
6.3 TX Control Register (02H)
Bit
Name
Default
7
RESERVED
0,RO
6
TJDIS
PS0,RW
5
EXCECM
PS0,RW
4
3
2
1
0
PAD_DIS2
CRC_DIS2
PAD_DIS1
CRC_DIS1
TXREQ
PS0,RW
PS0,RW
PS0,RW
PS0,RW
PS0,RW
Description
Media Speed 0:100Mbps 1:10Mbps, when Internal PHY is used. This bit has no
meaning when LINKST=0
Link Status 0:link failed 1:link OK,
Wakeup Event Status. Clears by read or write 1 (work in 8-bit mode)
This bit will not be affected after software reset
Reserved
TX Packet 2 Complete Status. Clears by read or write 1
Transmit completion of packet index 2
TX Packet 1 Complete status. Clears by read or write 1
Transmit completion of packet index 1
RX FIFO Overflow
Reserved
Description
Reserved
Transmit Jabber Disable
When set, the transmit Jabber Timer (2048 bytes) is disabled. Otherwise it is
Enable
Excessive Collision Mode Control : 0:aborts this packet when excessive collision
counts more than 15, 1: still tries to transmit this packet
PAD Appends Disable for Packet Index 2
CRC Appends Disable for Packet Index 2
PAD Appends Disable for Packet Index 1
CRC Appends Disable for Packet Index 1
TX Request. Auto clears after sending completely
6.4 TX Status Register I ( 03H ) for packet index I
Bit
Name
Default
Description
Transmit Jabber Time Out
7
TJTO
PS0,RO
It is set to indicate that the transmitted frame is truncated due to more than 2048
bytes are transmitted
Loss of Carrier
6
LC
PS0,RO
It is set to indicate the loss of carrier during the frame transmission. It is not valid in
internal loopback mode
No Carrier
5
NC
PS0,RO
It is set to indicate that there is no carrier signal during the frame transmission. It is
not valid in internal loopback mode
Late Collision
4
LC
PS0,RO
It is set when a collision occurs after the collision window of 64 bytes
Collision Packet
3
COL
PS0,RO
It is set to indicate that the collision occurs during transmission
Excessive Collision
2
EC
PS0,RO
It is set to indicate that the transmission is aborted due to 16 excessive collisions
Final
Version: DM9000A-17-DS-F01
May 10, 2006
15
DM9000A
Ethernet Controller with General Processor Interface
1:0
RESERVED
0,RO
Reserved
6.5 TX Status Register II ( 04H ) for packet index I I
Bit
Name
Default
Description
Transmit Jabber Time Out
7
TJTO
PS0,RO
It is set to indicate that the transmitted frame is truncated due to more than 2048
bytes are transmitted
Loss of Carrier
6
LC
PS0,RO
It is set to indicate the loss of carrier during the frame transmission. It is not valid in
internal loopback mode
No Carrier
5
NC
PS0,RO
It is set to indicate that there is no carrier signal during the frame transmission. It is
not valid in internal loopback mode
Late Collision
4
LC
PS0,RO
It is set when a collision occurs after the collision window of 64 bytes
3
COL
PS0,RO
Collision packet, collision occurs during transmission
Excessive Collision
2
EC
PS0,RO
It is set to indicate that the transmission is aborted due to 16 excessive collisions
1:0
RESERVED
0,RO
Reserved
6.6 RX Control Register ( 05H )
Bit
Name
Default
7
RESERVED PS0,RW
6
WTDIS
PS0,RW
5
DIS_LONG
PS0,RW
4
3
2
1
0
DIS_CRC
ALL
RUNT
PRMSC
RXEN
PS0,RW
PS0,RW
PS0,RW
PS0,RW
PS0,RW
6.7 RX Status Register ( 06H )
Bit
Name
Default
7
RF
PS0,RO
6
MF
PS0,RO
5
LCS
PS0,RO
4
RWTO
PS0,RO
3
PLE
PS0,RO
2
AE
PS0,RO
Final
Version: DM9000A-17-DS-F01
May 10, 2006
Description
Reserved
Watchdog Timer Disable
When set, the Watchdog Timer (2048 bytes) is disabled. Otherwise it is enabled
Discard Long Packet
Packet length is over 1522byte
Discard CRC Error Packet
Pass All Multicast
Pass Runt Packet
Promiscuous Mode
RX Enable
Description
Runt Frame
It is set to indicate that the size of the received frame is smaller than 64 bytes
Multicast Frame
It is set to indicate that the received frame has a multicast address
Late Collision Seen
It is set to indicate that a late collision is found during the frame reception
Receive Watchdog Time-Out
It is set to indicate that it receives more than 2048 bytes
Physical Layer Error
It is set to indicate that a physical layer error is found during the frame reception
Alignment Error
It is set to indicate that the received frame ends with a non-byte boundary
16
DM9000A
Ethernet Controller with General Processor Interface
1
CE
PS0,RO
0
FOE
PS0,RO
CRC Error
It is set to indicate that the received frame ends with a CRC error
FIFO Overflow Error
It is set to indicate that a FIFO overflow error happens during the frame reception
6.8 Receive Overflow Counter Register ( 07H )
Bit
Name
Default
Description
Receive Overflow Counter Overflow
7
RXFU
PS0,R/C
This bit is set when the ROC has an overflow condition
Receive Overflow Counter
6:0
ROC
PS0,R/C
This is a statistic counter to indicate the received packet count upon FIFO overflow
6.9 Back Pressure Threshold Register (08H)
Bit
Name
Default
Description
Back Pressure High Water Overflow Threshold. MAC will generate the jam pattern
when RX SRAM free space is lower than this threshold value
7:4
BPHW
PS3, RW
The default is 3K-byte free space. Please do not exceed SRAM size
(1 unit=1K bytes)
Jam Pattern Time. Default is 200us
bit3 bit2 bit1 bit0
time
0 0 0 0
5us
0 0 0 1
10us
0 0 1 0
15us
0 0 1 1
25us
0 1 0 0
50us
0 1 0 1
100us
0 1 1 0
150us
3:0
JPT
PS7, RW
0 1 1 1
200us
1 0 0 0
250us
1 0 0 1
300us
1 0 1 0
350us
1 0 1 1
400us
1 1 0 0
450us
1 1 0 1
500us
1 1 1 0
550us
1 1 1 1
600us
6.10 Flow Control Threshold Register ( 09H )
Bit
Name
Default
Description
RX FIFO High Water Overflow Threshold
Send a pause packet with pause_ time=FFFFH when the RX RAM free space is
7:4
HWOT
PS3, RW less than this value., If this value is zero, its means no free RX SRAM space. The
default value is 3K-byte free space. Please do not exceed SRAM size (1 unit=1K
bytes)
Final
Version: DM9000A-17-DS-F01
May 10, 2006
17
DM9000A
Ethernet Controller with General Processor Interface
3:0
LWOT
Final
Version: DM9000A-17-DS-F01
May 10, 2006
PS8, RW
RX FIFO Low Water Overflow Threshold
Send a pause packet with pause_time=0000 when RX SRAM free space is larger
than this value. This pause packet is enabled after the high water pause packet is
transmitted. The default SRAM free space is 8K-byte. Please do not exceed SRAM
size
(1 unit=1K bytes)
18
DM9000A
Ethernet Controller with General Processor Interface
6.11 RX/TX Flow Control Register ( 0AH )
Bit
Name
Default
Description
TX Pause Packet
7
TXP0
PS0,RW Auto clears after pause packet transmission completion. Set to TX pause packet
with time = 0000h
TX Pause packet
6
TXPF
PS0,RW Auto clears after pause packet transmission completion. Set to TX pause packet
with time = FFFFH
Force TX Pause Packet Enable
5
TXPEN
PS0,RW
Enables the pause packet for high/low water threshold control
Back Pressure Mode
4
BKPA
PS0,RW This mode is for half duplex mode only. It generates a jam pattern when any
packet comes and RX SRAM is over BPHW of register 8.
Back Pressure Mode
3
BKPM
PS0,RW This mode is for half duplex mode only. It generates a jam pattern when a packet’s
DA matches and RX SRAM is over BPHW of register 8.
2
RXPS
PS0,R/C RX Pause Packet Status, latch and read clearly
1
RXPCS
PS0,RO
RX Pause Packet Current Status
Flow Control Enable
0
FLCE
PS0,RW
Set to enable the flow control mode (i.e. can disable DM9000A TX function)
6.12 EEPROM & PHY Control Register ( 0BH )
Bit
Name
Default
Description
7:6
RESERVED
0,RO
Reserved
5
REEP
P0,RW
Reload EEPROM. Driver needs to clear it up after the operation completes
4
WEP
P0,RW
Write EEPROM Enable
EEPROM or PHY Operation Select
3
EPOS
P0,RW
When reset, select EEPROM; when set, select PHY
EEPROM Read or PHY Register Read Command. Driver needs to clear it up after
2
ERPRR
P0,RW
the operation completes.
EEPROM Write or PHY Register Write Command. Driver needs to clear it up after
1
ERPRW
P0,RW
the operation completes.
EEPROM Access Status or PHY Access Status
0
ERRE
P0,RO
When set, it indicates that the EEPROM or PHY access is in progress
6.13 EEPROM & PHY Address Register ( 0CH )
Bit
Name
Default
Description
PHY Address bit 1 and 0, the PHY address bit [4:2] is force to 0. Force to 01 in
7:6
PHY_ADR
P01,RW
application.
5:0
EROA
P0,RW
EEPROM Word Address or PHY Register Number.
6.14 EEPROM & PHY Data Register (EE_PHY_L：0DH EE_PHY_H：0EH)
Bit
Name
Default
Description
EEPROM or PHY Low Byte Data
7:0
EE_PHY_L
P0,RW
The low-byte data read from or write to EEPROM or PHY.
EEPROM or PHY High Byte Data
7:0
EE_PHY_H
P0,RW
The high-byte data read from or write to EEPROM or PHY.
Final
Version: DM9000A-17-DS-F01
May 10, 2006
19
DM9000A
Ethernet Controller with General Processor Interface
6.15 Wake Up Control Register ( 0FH ) (in 8-bit mode)
Bit
Name
Type
Description
Reserved
7:6
RESERVED
0,RO
When set, it enables Link Status Change Wake up Event
5
LINKEN
P0,RW
This bit will not be affected after software reset
When set, it enables Sample Frame Wake up Event
4
SAMPLEEN
P0,RW
This bit will not be affected after software reset
When set, it enables Magic Packet Wake up Event
3
MAGICEN
P0,RW
This bit will not be affected after software reset
When set, it indicates that Link Change and Link Status Change Event occurred
2
LINKST
P0,RO
This bit will not be affected after software reset
When set, it indicates that the sample frame is received and Sample Frame Event
1
SAMPLEST
P0,RO
occurred. This bit will not be affected after software reset
When set, indicates the Magic Packet is received and Magic packet Event
0
MAGICST
P0,RO
occurred. This bit will not be affected after a software reset
6.16 Physical Address Register ( 10H~15H )
Bit
Name
Default
7:0
PAB5
E,RW
Physical Address Byte 5
7:0
PAB4
E,RW
Physical Address Byte 4
7:0
PAB3
E,RW
Physical Address Byte 3
7:0
PAB2
E,RW
Physical Address Byte 2
7:0
PAB1
E,RW
Physical Address Byte 1
7:0
PAB0
E,RW
Physical Address Byte 0
(15H)
(14H)
(13H)
(12H)
(11H)
(10H)
6.17 Multicast Address Register ( 16H~1DH )
Bit
Name
Default
7:0
MAB7
X,RW
Multicast Address Byte 7
7:0
MAB6
X,RW
Multicast Address Byte 6
7:0
MAB5
X,RW
Multicast Address Byte 5
7:0
MAB4
X,RW
Multicast Address Byte 4
7:0
MAB3
X,RW
Multicast Address Byte 3
7:0
MAB2
X,RW
Multicast Address Byte 2
7:0
MAB1
X,RW
Multicast Address Byte 1
7:0
MAB0
X,RW
Multicast Address Byte 0
(1DH)
(1CH)
(1BH)
(1AH)
(19H)
(18H)
(17H)
(16H)
Description
Description
6.18 General purpose control Register ( 1EH ) ( For 8 Bit mode only, For 16 bit mode, see reg . 34H)
Bit
Name
Default
Description
7
RESERVED
PH0,RO Reserved
General Purpose Control 6~4
P,
6:4
GPC64
Define the input/output direction of pins GP6~4 respectively.
111,RO
These bits are all forced to “1”s, so pins GP6~4 are output only.
Final
Version: DM9000A-17-DS-F01
May 10, 2006
20
DM9000A
Ethernet Controller with General Processor Interface
3:1
GPC31
P,
000,RW
0
RESERVED
P1,RO
Final
Version: DM9000A-17-DS-F01
May 10, 2006
General Purpose Control 3~1
Define the input/output direction of pins GP 3~1 respectively.
When a bit is set 1, the direction of correspondent bit of General Purpose Register
is output. Other defaults are input
Reserved
21
DM9000A
Ethernet Controller with General Processor Interface
6.19 General purpose Register ( 1FH ) ( For 8 Bit mode only, For 16 bit mode, see reg . 34H)
Bit
Name
Default
Description
7
RESERVED
0,RO
Reserved
General Purpose Output 6~4 (in 8-bit mode)
6-4
GPO
P0,RW
These bits are reflect to pin GP6~4 respectively.
General Purpose (in 8-bit mode)
When the correspondent bit of General Purpose Control Register is 1, the value of
P0,RW
3:1
GPIO
the bit is reflected to pin GP3~1 respectively.
When the correspondent bit of General Purpose Control Register is 0, the value of
the bit to be read is reflected from correspondent pins of GP3~1 respectively.
PHY Power Down Control
0
PHYPD
ET1,WO 1: power down PHY
0: power up PHY
6.20 TX SRAM Read Pointer Address Register (22H~23H)
Bit
Name
Default
Description
7:0
TRPAH
PS0,RO
TX SRAM Read Pointer Address High Byte (23H)
7:0
TRPAL
PS0.RO
TX SRAM Read Pointer Address Low Byte (22H)
6.21 RX SRAM Write Pointer Address Register (24H~25H)
Bit
Name
Default
Description
7:0
RWPAH PS,0CH,RO RX SRAM Write Pointer Address High Byte (25H)
7:0
RWPAL
PS,00H.RO RX SRAM Write Pointer Address Low Byte (24H)
6.22 Vendor ID Register (28H~29H)
Bit
Name
Default
7:0
VIDH
PE,0AH,RO
Vendor ID High Byte (29H)
7:0
VIDL
PE,46H.RO
Vendor ID Low Byte (28H)
6.23 Product ID Register (2AH~2BH)
Bit
Name
Default
7:0
PIDH
PE,90H,RO
Product ID High Byte (2BH)
7:0
PIDL
PE,00H.RO
Product ID Low Byte (2AH)
6.24 Chip Revision Register (2CH)
Bit
Name
Default
7:0
CHIPR
P,19H,RO CHIP Revision
Description
Description
Description
6.25 Transmit Control Register 2 ( 2DH )
Bit
Name
Default
Description
Led Mode
7
LED
P0,RW
When set, the LED pins act as led mode 1.
When cleared, the led mode is default mode 0 or depending EEPROM setting.
Retry Late_Collision Packet
6
RLCP
P0,RW
Re-transmit the packet with late-collision
Final
Version: DM9000A-17-DS-F01
May 10, 2006
22
DM9000A
Ethernet Controller with General Processor Interface
5
DTU
P0,RW
4
ONEPM
P0,RW
3~0
IFGS
P0,RW
Disable TX Underrun Retry
Disable to re-transmit the underruned packet
One Packet Mode
When set, only one packet transmit command can be issued before transmit
completed.
When cleared, at most two packet transmit command can be issued before
transmit completed.
Inter-Frame Gap Setting
0XXX: 96-bit
1000: 64-bit
1001: 72-bit
1010:80-bit
1011:88-bit
1100:96-bit
1101:104-bit
1110: 112-bit
1111:120-bit
6.26 Operation Test Control Register ( 2EH )
Bit
Name
Default
Description
System Clock Control
Set the internal system clock.
00: 50Mhz
7~6
SCC
P0,RW
01: 20MHz
10: 100MHz
11: Reserved
5
RESERVED
P0,RW
Reserved
4
SOE
P0,RW
Internal SRAM Output-Enable Always ON
3
SCS
P0,RW
Internal SRAM Chip-Select Always ON
2~0
PHYOP
P0,RW
Internal PHY operation mode for testing
6.27 Special Mode Control Register ( 2FH )
Bit
Name
Default
7
SM_EN
P0,RW
Special Mode Enable
6~3
RESERVED
P0,RW
Reserved
2
FLC
P0,RW
Force Late Collision
1
FB1
P0,RW
Force Longest Back-off time
0
FB0
P0,RW
Force Shortest Back-off time
Final
Version: DM9000A-17-DS-F01
May 10, 2006
Description
23
DM9000A
Ethernet Controller with General Processor Interface
6.28 Early Transmit Control/Status Register ( 30H )
Bit
Name
Default
Description
Early Transmit Enable
7
ETE
PS0, RW
Enable bits[2:0]
6
ETS2
PS0,RO
Early Transmit Status II
5
ETS1
PS0,RO
Early Transmit Status I
4~2
RESERVED
000,RO
Reserved
Early Transmit Threshold
Start transmit when data write to TX FIFO reach the byte-count threshold
1~0
ETT
PS0,RW
Bit-1 bit-0
----- ---0
0
0
1
1
0
1
1
threshold
------------: 12.5%
: 25%
: 50%
: 75%
6.29 Check Sum Control Register ( 31H )
Bit
Name
Default
Description
7~3
RESERVED
0,RO
Reserved
2
UDPCSE
PS0,RW
UDP CheckSum Generation Enable
1
TCPCSE
PS0,RW
TCP CheckSum Generation Enable
0
IPCSE
PS0,RW
IP CheckSum Generation Enable
6.30 Receive Check Sum Status Register ( 32H )
Bit
Name
Default
Description
UDP CheckSum Status
7
UDPS
PS0,RO
1: checksum fail, if UDP packet
TCP CheckSum Status
6
TCPS
PS0,RO
1: checksum fail, if TCP packet
IP CheckSum Status
5
IPS
PS0,RO
1: checksum fail, if IP packet
4
UDPP
PS0,RO
UDP Packet
3
TCPP
PS0,RO
TCP Packet
2
IPP
PS0,RO
IP Packet
Receive CheckSum Checking Enable
1
RCSEN
PS0,RW
When set, the checksum status (bit 7~2) will be stored in packet’s first byte(bit
7~2) of status header respectively.
Discard CheckSum Error Packet
0
DCSE
PS0,RW
When set, if IP/TCP/UDP checksum field is error, this packet will be discarded.
Final
Version: DM9000A-17-DS-F01
May 10, 2006
24
DM9000A
Ethernet Controller with General Processor Interface
6.31 MII PHY Address Register ( 33H )
Bit
Name
Default
Description
7
ADR_EN
HPS0,R External PHY Address Enabled
W
When register 34H bit 0 is set to ‘1’, the PHY address field in MII Management
Interface format is defined at bit 4~0.
6~5
Reserved
HPS0,RO Reserved
4~0
EPHYADR
HPS01,R External PHY Address Bit 4~0
W
The PHY address field in MII Management Interface format.
6.32 LED Pin Control Register ( 34H )
Bit
Name
Default
Description
7:2
Reserved
PS0,RO
Reserved
LED act as General Purpose signals in 16-bit mode
1
GPIO
P0,RW
1: Pin 38/39 (LED2/1) act as the general purpose pins that are controlled by
registers 1Eh bit 2/1 and 1Fh bit 2/1 respectively.
LED act as SMI signals in 16-bit mode
1: Pin 38/39 (LED2/1) act as the MII Management Interface mode.
In this mode, the LED1 act as data (MDIO) signal and the LED2 act as sourced
0
MII
P0,RW
clock (MDC) signal.
These two pin are controlled by registers 0Bh,0Ch, and 0Dh.
6.33 Processor Bus Control Register ( 38H )
Bit
Name
Default
Description
Data Bus Current Driving/Sinking Capability
000: 2mA
001: 4mA
010: 6mA
7:5
CURR
P011,RW
011: 8mA (default)
100: 10mA
101: 12mA
110: 14mA
111: 16mA
4
Reserved
P0,RW
Reserved
Enable Schmitt Trigger
3
EST
P0,RW
1: Pin 35/36/37 (IOR/IOW/CS#) have Schmitt trigger capability.
2
Reserved
P0,RW
Reserved
Eliminate IOW spike
1
IOW_SPIKE
P0,RW
1: eliminate about 2ns IOW spike
Eliminate IOR spike
0
IOR_SPIKE
P1,RW
1: eliminate about 2ns IOR spike
Final
Version: DM9000A-17-DS-F01
May 10, 2006
25
DM9000A
Ethernet Controller with General Processor Interface
6.34 INT Pin Control Register ( 39H )
Bit
Name
Default
7:2
Reserved
PS0,RO
Reserved
INT Pin Output Type Control
1
INT_TYPE
PET0,RW 1: INT Open-Collector output
0: INT direct output
INT Pin Polarity Control
0
INT_POL
PET0,RW 1: INT active low
0: INT active high
Description
6.35 System Clock Turn ON Control Register ( 50H )
Bit
Name
Default
Description
7:1
Reserved
Reserved
Stop Internal System Clock
0
DIS_CLK
P0,W
1: internal system clock turn off, internal PHYceiver also power down
0: internal system clock is ON
6.36 Resume System Clock Control Register ( 51H )
When the INDEX port set to 51H, the internal system clock is turn ON.
6.37 Memory Data Pre-Fetch Read Command without Address Increment Register (F0H)
Bit
Name
Default
Description
Read data from RX SRAM. After the read of this command, the read pointer of
7:0
MRCMDX
X,RO
internal SRAM is unchanged. And the DM9000A starts to pre-fetch the SRAM data
to internal data buffers.
6.38 Memory Data Read Command without Address Increment Register (F1H)
Bit
Name
Default
Description
Read data from RX SRAM. After the read of this command, the read pointer of
7:0
MRCMDX1
X,RO
internal SRAM is unchanged
6.39 Memory Data Read Command with Address Increment Register (F2H)
Bit
Name
Default
Description
Read data from RX SRAM. After the read of this command, the read pointer is
7:0
MRCMD
X,RO
increased by 1or 2 depends on the operator mode (8-bit or16-bit respectively)
6.40 Memory Data Read_address Register (F4H~F5H)
Bit
Name
Default
Description
7:0
MDRAH
PS0,RW Memory Data Read_ address High Byte. It will be set to 0Ch, when IMR bit7 =1
7:0
MDRAL
PS0,RW Memory Data Read_ address Low Byte
6.41 Memory Data Write Command without Address Increment Register (F6H)
Bit
Name
Default
Description
Final
Version: DM9000A-17-DS-F01
May 10, 2006
26
DM9000A
Ethernet Controller with General Processor Interface
7:0
MWCMDX
X,WO
Write data to TX SRAM. After the write of this command, the write pointer is
unchanged
6.42 Memory data write command with address increment Register (F8H)
Bit
Name
Default
Description
Write Data to TX SRAM
7:0
MWCMD
X,WO
After the write of this command, the write pointer is increased by 1 or 2, depends on
the operator mode. (8-bit or 16-bit respectively)
6.43 Memory data write_address Register (FAH~FBH)
Bit
Name
Default
Description
7:0
MDWAH
PS0,RW Memory Data Write_ address High Byte
7:0
MDWAL
PS0,RW Memory Data Write_ address Low Byte
6.44 TX Packet Length Register (FCH~FDH)
Bit
Name
Default
7:0
TXPLH
X,R/W
TX Packet Length High byte
7:0
TXPLL
X,,R/W
TX Packet Length Low byte
6.45 Interrupt Status Register (FEH)
Bit
Name
Default
7
IOMODE
T0, RO
6
5
4
3
2
1
0
RESERVED
LNKCHG
UDRUN
ROO
ROS
PT
PR
RO
PS0,RW/C1
PS0,RW/C1
PS0,RW/C1
PS0,RW/C1
PS0,RW/C1
PS0,RW/C1
6.46 Interrupt Mask Register (FFH)
Bit
Name
Default
7
PAR
PS0,RW
6
5
4
3
2
1
0
RESERVED
LNKCHGI
UDRUNI
ROOI
ROI
PTI
PRI
RO
PS0,RW
PS0,RW
PS0,RW
PS0,RW
PS0,RW
PS0,RW
Final
Version: DM9000A-17-DS-F01
May 10, 2006
Description
Description
0:
16-bit mode
1:
8-bit mode
Reserved
Link Status Change
Transmit Under-run
Receive Overflow Counter Overflow
Receive Overflow
Packet Transmitted
Packet Received
Description
Enable the SRAM read/write pointer to automatically return to the start
address when pointer addresses are over the SRAM size. Driver needs to
set. When driver sets this bit, REG_F5 will set to 0Ch automatically
Reserved
Enable Link Status Change Interrupt
Enable Transmit Under-run Interrupt
Enable Receive Overflow Counter Overflow Interrupt
Enable Receive Overflow Interrupt
Enable Packet Transmitted Interrupt
Enable Packet Received Interrupt
27
DM9000A
Ethernet Controller with General Processor Interface
7. EEPROM Format
name
MAC address
Word
0
Auto Load Control
3
Vendor ID
Product ID
4
5
pin control
6
Wake-up mode control
7
Final
Version: DM9000A-17-DS-F01
May 10, 2006
offset
Description
0~5 6 Byte Ethernet Address
Bit 1:0=01: Update vendor ID and product ID
Bit 3:2=01: Accept setting of WORD6 [8:0]
Bit 5:4=01: reserved
Bit 7:6=01: Accept setting of WORD7 [3:0] (in 8-bit mode)
6-7
Bit 9:8=01: reserved
Bit 11:10=01: Accept setting of WORD7 [7]
Bit 13:12=01: Accept setting of WORD7 [8]
Bit 15:14=01: Accept setting of WORD7 [15:12]
8-9
2 byte vendor ID (Default: 0A46H)
10-11 2 byte product ID (Default: 9000H)
When word 3 bit [3:2]=01, these bits can control the CS#, IOR#, IOW# and INT
pins polarity.
Bit0: CS# pin is active low when set (default active low)
Bit1: IOR# pin is active low when set (default: active low)
12-13
Bit2: IOW# pin is active low when set (default: active low)
Bit3: INT pin is active low when set (default: active high)
Bit4: INT pin is open-collected (default: force output)
Bit 15:5: Reserved
Bit0: The WAKE pin is active low when set (default: active high)
Bit1: The WAKE pin is in pulse mode when set (default: level mode)
Bit2: magic wakeup event is enabled when set. (default: disable)
Bit3: link_change wakeup event is enabled when set (default disable)
Bit6:4: reserved
Bit7: LED mode 1 (default: mode 0)
14-15
Bit8: internal PHY is enabled after power-on (default: disable)
Bit11:9: reserved
Bit13:12: 01 = LED2 act as IOWAIT in 16-bit mode
Bit13:12: 10 = LED2 act as WAKE in 16-bit mode
Bit14: 1: HP Auto-MDIX ON, 0: HP Auto-MDIX OFF(default ON)
Bit 15: LED1 act as IO16 in 16-bit mode
28
DM9000A
Ethernet Controller with General Processor Interface
8. PHY Register Description
ADD Name
15
00 CONTR Reset
OL
0
01 STATUS T4
Cap.
0
02 PHYID1
0
03 PHYID2
1
14
Loop
back
0
TX FDX
Cap.
1
0
0
13
12
11
Speed Auto-N Power
select
Enable Down
1
1
0
TX HDX 10 FDX 10 HDX
Cap.
Cap.
Cap.
1
1
1
0
0
0
1
1
1
04 Auto-Neg. Next
Advertise Page
05 Link Part. LP
Ability
Next
Page
06 Auto-Neg.
Expansio
n
16 Specifie BP
d
4B5B
Config.
17 Specifie 100
FDX
d
Conf/Stat
18
10T
Rsvd
Conf/Stat
FLP Rcv
Ack
LP
Ack
Remote
Fault
LP
RF
Reserved
Reserved
10
Isolate
0
9
8
Restart
Full
Auto-N Duplex
0
1
Reserved
7
Coll.
Test
0
0000
0
0
0
FC
Adv
LP
FC
T4
Adv
LP
T4
1
6
5
4
Pream.
Supr.
1
0
Auto-N
Compl.
0
0
Remote
Fault
0
0
1
Model No.
01010
TX FDX TX HDX 10 FDX 10 HDX
Adv
Adv
Adv
Adv
LP
LP
LP
LP
TX FDX TX HDX 10 FDX 10 HDX
Reserved
BP
SCR
BP
BP_ADP Reserve
ALIGN
OK
dr
100
HDX
10
FDX
LP
Enable
HBE
Enable
TX
19
PWDOR
20
Specified TSTSE1 TSTSE2 FORCE_ FORCE_
config
TXSD
FEF
JAB
Enable
2
Next Pg
Able
Reserve Reserve Force Reserve Reserve RPDCTR Reset
d
d
100LNK
d
d
-EN
St. Mch
Pream.
Supr.
Reserved
PHY ADDR [4:0]
Reserved
PD100l
PDchip
Extd
Cap.
1
1
New Pg LP AutoN
Rcv
Cap.
Sleep
mode
Remote
LoopOut
Auto-N. Monitor Bit [3:0]
Reserved
PD10DRV
0
Link Partner Protocol Selector Field
LP Next
Pg Able
Reserve
d
1
000_0000
Auto-N
Link
Jabber
Cap.
Status
Detect
1
0
0
0
0
0
Version No.
0000
Advertised Protocol Selector Field
Pardet
Fault
10 HDX Reserve Reverse Reverse
d
d
d
SQUE
Enable
3
Reserved
PDcrm
Polarity
Reverse
PDaeq
PDdrv
PDecli
PDeclo
PD10
MDIX_C AutoNeg Mdix_fix Mdix_do MonSel1 MonSel0 Reserve PD_valu
NTL
_llpbk
Value
wn
d
e
Key to Default
In the register description that follows, the default
column takes the form:
<Reset Value>, <Access Type> / <Attribute(s)>
Where：
<Reset Value>:
1
Bit set to logic one
0
Bit set to logic zero
X
No default value
RO = Read only
RW = Read/Write
<Attribute (s)>:
SC = Self clearing
P = Value permanently set
LL = Latching low
LH = Latching high
<Access Type>:
Final
Version: DM9000A-17-DS-F01
May 10, 2006
29
DM9000A
Ethernet Controller with General Processor Interface
8.1 Basic Mode Control Register (BMCR) - 00
Bit
0.15
0.14
0.13
0.12
0.11
0.10
0.9
Bit Name
Reset
Default
Description
0, RW/SC Reset
1=Software reset
0=Normal operation
This bit sets the status and controls the PHY registers to their
default states. This bit, which is self-clearing, will keep
returning a value of one until the reset process is completed
Loopback
0, RW Loopback
Loop-back control register
1 = Loop-back enabled
0 = Normal operation
When in 100Mbps operation mode, setting this bit may cause
the descrambler to lose synchronization and produce a 720ms
"dead time" before receive
Speed selection 1, RW Speed Select
1 = 100Mbps
0 = 10Mbps
Link speed may be selected either by this bit or by
auto-negotiation. When auto-negotiation is enabled and bit 12
is set, this bit will return auto-negotiation selected medium
type
Auto-negotiatio 1, RW Auto-negotiation Enable
n enable
1 = Auto-negotiation is enabled, bit 8 and 13 will be in
auto-negotiation status
Power down
0, RW Power Down
While in the power-down state, the PHY should respond to
management transactions.
1=Power down
0=Normal operation
Isolate
0,RW Isolate
Force to 0 in application.
Restart
0,RW/SC Restart Auto-negotiation
Auto-negotiation
1 = Restart auto-negotiation. Re-initiates the auto-negotiation
process. When auto-negotiation is disabled (bit 12 of this
register cleared), this bit has no function and it should be
cleared. This bit is self-clearing and it will keep returning to a
value of 1 until auto-negotiation is initiated by the DM9000A.
The operation of the auto-negotiation process will not be
affected by the management entity that clears this bit
0 = Normal operation
Final
Version: DM9000A-17-DS-F01
May 10, 2006
30
DM9000A
0.8
Duplex mode
1,RW
0.7
Collision test
0,RW
0.6-0.0
Reserved
0,RO
Ethernet Controller with General Processor Interface
Duplex Mode
1 = Full duplex operation. Duplex selection is allowed when
Auto-negotiation is disabled (bit 12 of this register is cleared).
With auto-negotiation enabled, this bit reflects the duplex
capability selected by auto-negotiation
0 = Normal operation
Collision Test
1 = Collision test enabled. When set, this bit will cause the
collision asserted during the transmit period.
0 = Normal operation
Reserved
Read as 0, ignore on write
8.2 Basic Mode Status Register (BMSR) - 01
Bit
1.15
Bit Name
100BASE-T4
Default
0,RO/P
1.14
100BASE-TX
full-duplex
1,RO/P
1.13
100BASE-TX
half-duplex
1,RO/P
1.12
10BASE-T
full-duplex
1,RO/P
1.11
10BASE-T
half-duplex
1,RO/P
1.10-1.7
Reserved
0,RO
1.6
MF preamble
1,RO
Final
Version: DM9000A-17-DS-F01
May 10, 2006
Description
100BASE-T4 Capable
1 = DM9000A is able to perform in 100BASE-T4 mode
0 = DM9000A is not able to perform in 100BASE-T4 mode
100BASE-TX Full Duplex Capable
1 = DM9000A is able to perform 100BASE-TX in full duplex
mode
0 = DM9000A is not able to perform 100BASE-TX in full
duplex mode
100BASE-TX Half Duplex Capable
1 = DM9000A is able to perform 100BASE-TX in half duplex
mode
0 = DM9000A is not able to perform 100BASE-TX in half
duplex mode
10BASE-T Full Duplex Capable
1 = DM9000A is able to perform 10BASE-T in full duplex
mode
0 = DM9000A is not able to perform 10BASE-TX in full
duplex mode
10BASE-T Half Duplex Capable
1 = DM9000A is able to perform 10BASE-T in half duplex
mode
0 = DM9000A is not able to perform 10BASE-T in half
duplex mode
Reserved
Read as 0, ignore on write
Frame Preamble Suppression
31
DM9000A
1.5
1.4
1.3
1.2
1.1
1.0
Ethernet Controller with General Processor Interface
suppression
1 = PHY will accept management frames with preamble
suppressed
0 = PHY will not accept management frames with preamble
suppressed
Auto-negotiation
0,RO
Auto-negotiation Complete
Complete
1 = Auto-negotiation process completed
0 = Auto-negotiation process not completed
Remote fault 0, RO/LH Remote Fault
1 = Remote fault condition detected (cleared on read or by a
chip reset). Fault criteria and detection method is DM9000A
implementation specific. This bit will set after the RF bit in
the ANLPAR (bit 13, register address 05) is set
0 = No remote fault condition detected
Auto-negotiation 1,RO/P Auto Configuration Ability
ability
1 = DM9000A is able to perform auto-negotiation
0 = DM9000A is not able to perform auto-negotiation
Link status
0,RO/LL Link Status
1 = Valid link is established (for either 10Mbps or 100Mbps
operation)
0 = Link is not established
The link status bit is implemented with a latching function, so
that the occurrence of a link failure condition causes the link
status bit to be cleared and remain cleared until it is read via
the management interface
Jabber detect 0, RO/LH Jabber Detect
1 = Jabber condition detected
0 = No jabber
This bit is implemented with a latching function. Jabber
conditions will set this bit unless it is cleared by a read to this
register through a management interface or a DM9000A reset.
This bit works only in 10Mbps mode
Extended
Capability
Extended
1,RO/P
1 = Extended register capable
capability
0 = Basic register capable only
Final
Version: DM9000A-17-DS-F01
May 10, 2006
32
DM9000A
Ethernet Controller with General Processor Interface
8.3 PHY ID Identifier Register #1 (PHYID1) - 02
The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9000A. The Identifier
consists of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a
model revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E.
Bit
2.15-2.0
Bit Name
OUI_MSB
Default
<0181h>
Description
OUI Most Significant Bits
This register stores bit 3 to 18 of the OUI (00606E) to bit 15
to 0 of this register respectively. The most significant two
bits of the OUI are ignored (the IEEE standard refers to these
as bit 1 and 2)
8.4 PHY ID Identifier Register #2 (PHYID2) - 03
Bit
3.15-3.1
0
Bit Name
OUI_LSB
3.9-3.4
VNDR_MDL
3.3-3.0
MDL_REV
Final
Version: DM9000A-17-DS-F01
May 10, 2006
Default
Description
<101110>, OUI Least Significant Bits
RO/P
Bit 19 to 24 of the OUI (00606E) are mapped to bit 15 to 10
of this register respectively
<001010>, Vendor Model Number
RO/P
Five bits of vendor model number mapped to bit 9 to 4 (most
significant bit to bit 9)
<0000>, Model Revision Number
RO/P
Five bits of vendor model revision number mapped to bit 3
to 0 (most significant bit to bit 4)
33
DM9000A
Ethernet Controller with General Processor Interface
8.5 Auto-negotiation Advertisement Register (ANAR) - 04
This register contains the advertised abilities of this DM9000A device as they will be transmitted to its
link partner during Auto-negotiation.
Bit
4.15
Bit Name
NP
Default
0,RO/P
4.14
ACK
0,RO
4.13
RF
0, RW
4.12
-4.11
4.10
Reserved
X, RW
FCS
0, RW
4.9
T4
0, RO/P
4.8
TX_FDX
1, RW
4.7
TX_HDX
1, RW
4.6
10_FDX
1, RW
4.5
10_HDX
1, RW
Final
Version: DM9000A-17-DS-F01
May 10, 2006
Description
Next page Indication
0 = No next page available
1 = Next page available
The DM9000A has no next page, so this bit is permanently
set to 0
Acknowledge
1 = Link partner ability data reception acknowledged
0 = Not acknowledged
The DM9000A's auto-negotiation state machine will
automatically control this bit in the outgoing FLP bursts and
set it at the appropriate time during the auto-negotiation
process. Software should not attempt to write to this bit.
Remote Fault
1 = Local device senses a fault condition
0 = No fault detected
Reserved
Write as 0, ignore on read
Flow Control Support
1 = Controller chip supports flow control ability
0 = Controller chip doesn’t support flow control ability
100BASE-T4 Support
1 = 100BASE-T4 is supported by the local device
0 = 100BASE-T4 is not supported
The DM9000A does not support 100BASE-T4 so this bit is
permanently set to 0
100BASE-TX Full Duplex Support
1 = 100BASE-TX full duplex is supported by the local
device
0 = 100BASE-TX full duplex is not supported
100BASE-TX Support
1 = 100BASE-TX half duplex is supported by the local
device
0 = 100BASE-TX half duplex is not supported
10BASE-T Full Duplex Support
1 = 10BASE-T full duplex is supported by the local device
0 = 10BASE-T full duplex is not supported
10BASE-T Support
1 = 10BASE-T half duplex is supported by the local device
34
DM9000A
4.4-4.0
Selector
<00001>,
RW
Ethernet Controller with General Processor Interface
0 = 10BASE-T half duplex is not supported
Protocol Selection Bits
These bits contain the binary encoded protocol selector
supported by this node
<00001> indicates that this device supports IEEE 802.3
CSMA/CD
8.6 Auto-negotiation Link Partner Ability Register (ANLPAR) – 05
This register contains the advertised abilities of the link partner when received during
Auto-negotiation.
Bit
5.15
Bit Name
NP
Default
0, RO
5.14
ACK
0, RO
5.13
RF
0, RO
5.12
-5.11
5.10
Reserved
0, RO
FCS
0, RO
5.9
T4
0, RO
5.8
TX_FDX
0, RO
5.7
TX_HDX
0, RO
Final
Version: DM9000A-17-DS-F01
May 10, 2006
Description
Next Page Indication
0 = Link partner, no next page available
1 = Link partner, next page available
Acknowledge
1 = Link partner ability data reception acknowledged
0 = Not acknowledged
The DM9000A's auto-negotiation state machine will
automatically control this bit from the incoming FLP bursts.
Software should not attempt to write to this bit
Remote Fault
1 = Remote fault indicated by link partner
0 = No remote fault indicated by link partner
Reserved
Read as 0, ignore on write
Flow Control Support
1 = Controller chip supports flow control ability by link
partner
0 = Controller chip doesn’t support flow control ability by
link partner
100BASE-T4 Support
1 = 100BASE-T4 is supported by the link partner
0 = 100BASE-T4 is not supported by the link partner
100BASE-TX Full Duplex Support
1 = 100BASE-TX full duplex is supported by the link partner
0 = 100BASE-TX full duplex is not supported by the link
partner
100BASE-TX Support
1 = 100BASE-TX half duplex is supported by the link
partner
0 = 100BASE-TX half duplex is not supported by the link
35
DM9000A
Ethernet Controller with General Processor Interface
5.6
10_FDX
0, RO
5.5
10_HDX
0, RO
5.4-5.0
Selector
<00000>,
RO
partner
10BASE-T Full Duplex Support
1 = 10BASE-T full duplex is supported by the link partner
0 = 10BASE-T full duplex is not supported by the link
partner
10BASE-T Support
1 = 10BASE-T half duplex is supported by the link partner
0 = 10BASE-T half duplex is not supported by the link
partner
Protocol Selection Bits
Link partner’s binary encoded protocol selector
8.7 Auto-negotiation Expansion Register (ANER)- 06
Bit
6.15-6.5
Bit Name
Reserved
Default
0, RO
6.4
PDF
0, RO/LH
6.3
LP_NP_ABL
E
0, RO
6.2
NP_ABLE
0,RO/P
6.1
PAGE_RX
0, RO/LH
6.0
LP_AN_ABL
E
0, RO
Description
Reserved
Read as 0, ignore on write
Local Device Parallel Detection Fault
PDF = 1: A fault detected via parallel detection function.
PDF = 0: No fault detected via parallel detection function
Link Partner Next Page Able
LP_NP_ABLE = 1: Link partner, next page available
LP_NP_ABLE = 0: Link partner, no next page
Local Device Next Page Able
NP_ABLE = 1: DM9000A, next page available
NP_ABLE = 0: DM9000A, no next page
DM9000A does not support this function, so this bit is
always 0
New Page Received
A new link code word page received. This bit will be
automatically cleared when the register (register 6) is read by
management
Link Partner Auto-negotiation Able
A “1” in this bit indicates that the link partner supports
Auto-negotiation
8.8 DAVICOM Specified Configuration Register (DSCR) - 16
Bit
16.15
Bit Name
BP_4B5B
Default
0,RW
16.14
BP_SCR
0, RW
Final
Version: DM9000A-17-DS-F01
May 10, 2006
Description
Bypass 4B5B Encoding and 5B4B Decoding
1 = 4B5B encoder and 5B4B decoder function bypassed
0 = Normal 4B5B and 5B4B operation
Bypass Scrambler/Descrambler Function
36
DM9000A
Ethernet Controller with General Processor Interface
1 = Scrambler and descrambler function bypassed
0 = Normal scrambler and descrambler operation
Bypass Symbol Alignment Function
1 = Receive functions (descrambler, symbol alignment and
symbol decoding functions) bypassed. Transmit functions
(symbol encoder and scrambler) bypassed
0 = Normal operation
BYPASS ADPOK
Force signal detector (SD) active. This register is for debug
only, not release to customer
1=Forced SD is OK,
0=Normal operation
Reserved
Force to 0 in application.
100BASE-TX/FX Mode Control
1 = 100BASE-TX operation
0 = 100BASE-FX operation
Reserved
Reserved
Force to 0 in application.
Force Good Link in 100Mbps
0 = Normal 100Mbps operation
1 = Force 100Mbps good link status
This bit is useful for diagnostic purposes
16.13
BP_ALIGN
0, RW
16.12
BP_ADPOK
0, RW
16.11
Reserved
0, RW
16.10
TX/FX
1, RW
16.9
16.8
Reserved
Reserved
0, RO
0, RW
16.7
F_LINK_100
0, RW
16.6
SPLED_CTL
0, RW
Reserved
0, RW
Force to 0 in application.
Reserved
Force to 0 in application.
16.5
COLLED_CT
L
16.4
16.3
16.2
16.1
RPDCTR-EN
SMRST
MFPSC
SLEEP
1, RW
0, RW
1, RW
0, RW
Reduced Power Down Control Enable
This bit is used to enable automatic reduced power down
0 = Disable automatic reduced power down
1 = Enable automatic reduced power down
Reset State Machine
When writes 1 to this bit, all state machines of PHY will be
reset. This bit is self-clear after reset is completed
MF Preamble Suppression Control
Frame preamble suppression control bit
1 = MF preamble suppression bit on
0 = MF preamble suppression bit off
Sleep Mode
Writing a 1 to this bit will cause PHY entering the Sleep
Final
Version: DM9000A-17-DS-F01
May 10, 2006
37
DM9000A
Ethernet Controller with General Processor Interface
mode and power down all circuit except oscillator and clock
generator circuit. When waking up from Sleep mode (write
this bit to 0), the configuration will go back to the state
16.0
RLOUT
0, RW
before sleep; but the state machine will be reset
Remote Loopout Control
When this bit is set to 1, the received data will loop out to the
transmit channel. This is useful for bit error rate testing
8.9 DAVICOM Specified Configuration and Status Register (DSCSR) - 17
Bit
17.15
17.14
17.13
17.12
17.11
-17.9
17.8
-17.4
Bit Name
100FDX
Description
100M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this
bit. If this bit is 1, it means the operation 1 mode is a 100M full
duplex mode. The software can read bit [15:12] to see which mode
is selected after auto-negotiation. This bit is invalid when it is not
in the auto-negotiation mode
100HDX
1, RO
100M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this
bit. If this bit is 1, it means the operation 1 mode is a 100M half
duplex mode. The software can read bit [15:12] to see which mode
is selected after auto-negotiation. This bit is invalid when it is not
in the auto-negotiation mode
10FDX
1, RO
10M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this
bit. If this bit is 1, it means the operation 1 mode is a 10M Full
Duplex mode. The software can read bit [15:12] to see which
mode is selected after auto-negotiation. This bit is invalid when it
is not in the auto-negotiation mode
10HDX
1, RO
10M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this
bit. If this bit is 1, it means the operation 1 mode is a 10M half
duplex mode. The software can read bit [15:12] to see which mode
is selected after auto-negotiation. This bit is invalid when it is not
in the auto-negotiation mode
Reserved
0, RO
Reserved
Read as 0, ignore on write
PHYADR (PHYADR), PHY Address Bit 4:0
[4:0]
RW
The first PHY address bit transmitted or received is the MSB of
the address (bit 4). A station management entity connected to
multiple PHY entities must know the appropriate address of each
PHY
Final
Version: DM9000A-17-DS-F01
May 10, 2006
Default
1, RO
38
DM9000A
17.3
-17.0
ANMB[3:
0]
0, RO
Ethernet Controller with General Processor Interface
Auto-negotiation Monitor Bits
These bits are for debug only. The auto-negotiation status will be
written to these bits.
B3
0
0
0
0
0
0
0
0
b2
0
0
0
0
1
1
1
1
b1
0
0
1
1
0
0
1
1
B0
0
1
0
1
0
1
0
1
In IDLE state
Ability match
Acknowledge match
Acknowledge match fail
Consistency match
Consistency match fail
Parallel detects signal_link_ready
Parallel detects signal_link_ready fail
8.10 10BASE-T Configuration/Status (10BTCSR) - 18
Bit
18.15
Bit Name
Reserved
Default
0, RO
18.14
LP_EN
1, RW
18.13
HBE
1,RW
18.12
SQUELCH
1, RW
18.11
JABEN
1, RW
18.10
Reserved
0, RW
18.9
-18.1
Reserved
0, RO
Final
Version: DM9000A-17-DS-F01
May 10, 2006
Description
Reserved
Read as 0, ignore on write
Link Pulse Enable
1 = Transmission of link pulses enabled
0 = Link pulses disabled, good link condition forced
This bit is valid only in 10Mbps operation
Heartbeat Enable
1 = Heartbeat function enabled
0 = Heartbeat function disabled
When the DM9000A is configured for full duplex operation, this
bit will be ignored (the collision/heartbeat function is invalid in
full duplex mode), This bit is valid only in 10Mbps operation.
Squelch Enable
1 = Normal squelch
0 = Low squelch
Jabber Enable
Enables or disables the Jabber function when the DM9000A is in
10BASE-T full duplex or 10BASE-T transceiver Loopback
mode
1 = Jabber function enabled
0 = Jabber function disabled
Reserved
Force to 0, in application.
Reserved
Read as 0, ignore on write
39
DM9000A
18.0
POLR
0, RO
Ethernet Controller with General Processor Interface
Polarity Reversed
When this bit is set to 1, it indicates that the 10Mbps cable
polarity is reversed. This bit is automatically set and cleared by
10BASE-T module
8.11 Power Down Control Register (PWDOR) - 19
Bit
Bit Name
Default
Description
19.15
Reserved
0, RO
Reserved
-19.9
Read as 0, ignore on write
19.8
PD10DRV
0, RW
Vendor power down control test
19.7
PD100DL
0, RW
Vendor power down control test
19.6
PDchip
0, RW
Vendor power down control test
19.5
PDcom
0, RW
Vendor power down control test
19.4
PDaeq
0, RW
Vendor power down control test
19.3
PDdrv
0, RW
Vendor power down control test
19.2
PDedi
0, RW
Vendor power down control test
19.1
PDedo
0, RW
Vendor power down control test
19.0
PD10
0, RW
Vendor power down control test
* when selected, the power down value is control by Register 20.0
8.12 (Specified config) Register – 20
Bit
20.15
20.14
20.13
20.12
20.11
-20.8
20.7
20.6
20.5
Bit Name
TSTSE1
TSTSE2
Description
Vendor test select control
Vendor test select control
FORCE_TXSD
Force Signal Detect
1: force SD signal OK in 100M
0: normal SD signal.
FORCE_FEF
0,RW
Vendor test select control
Reserved
0, RO
Reserved
Read as 0, ignore on write
MDIX_CNTL MDI/MDIX, The polarity of MDI/MDIX value
RO
1: MDIX mode
0: MDI mode
AutoNeg_lpbk
0,RW
Auto-negotiation Loopback
1: test internal digital auto-negotiation Loopback
0: normal.
Mdix_fix
0, RW
MDIX_CNTL force value:
Value
When Mdix_down = 1, MDIX_CNTL value depend on the
register value.
Final
Version: DM9000A-17-DS-F01
May 10, 2006
Default
0,RW
0,RW
0,RW
40
DM9000A
20.4
Mdix_down
0,RW
20.3
20.2
20.1
MonSel1
MonSel0
Reserved
0,RW
0,RW
0,RW
20.0
PD_value
0,RW
Final
Version: DM9000A-17-DS-F01
May 10, 2006
Ethernet Controller with General Processor Interface
HP Auto-MDIX Down
Manual force MDI/MDIX.
0: Enable HP Auto-MDIX
1: Disable HP Auto-MDIX , MDIX_CNTL value depend on
20.5
Vendor monitor select
Vendor monitor select
Reserved
Force to 0, in application.
Power down control value
Decision the value of each field Register 19.
1: power down
0: normal
41
DM9000A
Ethernet Controller with General Processor Interface
9. Functional Description
9.1 Host Interface
The host interface is a general processor local bus
that using chip select (pin CS#) to access DM9000A.
Pin CS# is default low active which can be re-defined
by EEPROM setting.
There are only two addressing ports through the
access of the host interface. One port is the INDEX
port and the other is the DATA port. The INDEX port is
decoded by the pin CMD =0 and the DATA port by the
pin CMD =1. The contents of the INDEX port are the
register address of the DATA port. Before the access
of any register, the address of the register must be
saved in the INDEX port.
9.2 Direct Memory Access Control
The DM9000A provides DMA capability to simplify the
access of the internal memory. After the programming
of the starting address of the internal memory and
then issuing a dummy read/write command to load the
current data to internal data buffer, the desired
location of the internal memory can be accessed by
the read/write command registers. The memory’s
address will be increased with the size that equals to
the current operation mode (i.e. the 8-bit or 16-bit
mode) and the data of the next location will be loaded
into internal data buffer automatically. It is noted that
the data of the first access (the dummy read/write
command) in a sequential burst should be ignored
because that the data was the contents of the last
read/write command.
The internal memory size is 16K bytes. The first
location of 3K bytes is used for the data buffer of the
packet transmission. The other 13K bytes are used for
the buffer of the receiving packets. So in the write
memory operation, when the bit 7 of IMR is set, the
memory address increment will wrap to location 0 if
the end of address (i.e. 3K) is reached. In a similar
way, in the read memory operation, when the bit 7 of
Final
Version: DM9000A-17-DS-F01
May 10, 2006
IMR is set, the memory address increment will wrap to
location 0x0C00 if the end of address (i.e. 16K) is
reached.
9.3 Packet Transmission
There are two packets, sequentially named as index I
and index II, can be stored in the TX SRAM at the
same time. The index register 02h controls the
insertion of CRC and pads. Their statuses are
recorded at index registers 03h and 04h respectively.
The start address of transmission is 00h and the
current packet is index I after software or hardware
reset. Firstly write data to the TX SRAM using the
DMA port and then write the byte count to byte_ count
register at index register 0fch and 0fdh. Set the bit 1 of
control register. The DM9000A starts to transmit the
index I packet. Before the transmission of the index I
packet ends, the data of the next (index II) packet can
be moved to TX SRAM. After the index I packet ends
the transmission, write the byte count data of the
index II to BYTE_COUNT register and then set the bit
1 of control register to transmit the index II packet.
The following packets, named index I, II, I, II,…, use
the same way to be transmitted.
9.4 Packet Reception
The RX SRAM is a ring data structure. The start
address of RX SRAM is 0C00h after software or
hardware reset. Each packet has a 4-byte header
followed with the data of the reception packet which
CRC field is included. The format of the 4-byte header
is 01h, status, BYTE_COUNT low, and
BYTE_COUNT high. It is noted that the start address
of each packet is in the proper address boundary
which depends on the operation mode (the 8-bit or
16-bit ).
42
DM9000A
Ethernet Controller with General Processor Interface
9.5 100Base-TX Operation
The transmitter section contains the following
functional blocks:
- 4B5B Encoder
- Scrambler
- Parallel to Serial Converter
- NRZ to NRZI Converter
- NRZI to MLT-3
- MLT-3 Driver
9.5.1 4B5B Encoder
The 4B5B encoder converts 4-bit (4B) nibble data
generated by the MAC Reconciliation Layer into a
5-bit (5B) code group for transmission, see reference
Table 1. This conversion is required for control and
packet data to be combined in code groups. The
4B5B encoder substitutes the first 8 bits of the MAC
preamble with a J/K code-group pair (11000 10001)
upon transmit. The 4B5B encoder continues to
replace subsequent 4B preamble and data nibbles
with corresponding 5B code-groups. At the end of the
transmit packet, upon the deassertion of the Transmit
Enable signal from the MAC Reconciliation layer, the
4B5B encoder injects the T/R code-group pair (01101
00111) indicating the end of frame. After the T/R
code-group pair, the 4B5B encoder continuously
injects IDLEs into the transmit data stream until
Transmit Enable is asserted and the next transmit
packet is detected.
The DM9000A includes a Bypass 4B5B conversion
option within the 100Base-TX Transmitter for support
of applications like 100 Mbps repeaters which do not
require 4B5B conversion.
9.5.2 Scrambler
The scrambler is required to control the radiated
emissions (EMI) by spreading the transmit energy
across the frequency spectrum at the media
connector and on the twisted pair cable in
100Base-TX operation.
Final
Version: DM9000A-17-DS-F01
May 10, 2006
By scrambling the data, the total energy presented to
the cable is randomly distributed over a wide
frequency range. Without the scrambler, energy levels
on the cable could peak beyond FCC limitations at
frequencies related to the repeated 5B sequences,
like the continuous transmission of IDLE symbols.
The scrambler output is combined with the NRZ 5B
data from the code-group encoder via an XOR logic
function. The result is a scrambled data stream with
sufficient randomization to decrease radiated
emissions at critical frequencies.
9.5.3 Parallel to Serial Converter
The Parallel to Serial Converter receives parallel 5B
scrambled data from the scrambler, and serializes it
(converts it from a parallel to a serial data stream).
The serialized data stream is then presented to the
NRZ to NRZI encoder block
9.5.4 NRZ to NRZI Encoder
After the transmit data stream has been scrambled
and serialized, the data must be NRZI encoded for
compatibility with the TP-PMD standard, for 100Base
-TX transmission over Category-5 unshielded twisted
pair cable.
9.5.5 MLT-3 Converter
The MLT-3 conversion is accomplished by converting
the data stream output, from the NRZI encoder into
two binary data streams, with alternately phased logic
one event.
9.5.6 MLT-3 Driver
The two binary data streams created at the MLT-3
converter are fed to the twisted pair output driver,
which converts these streams to current sources and
alternately drives either side of the transmit
transformer’s primary winding, resulting in a minimal
current MLT-3 signal.
43
DM9000A
Ethernet Controller with General Processor Interface
9.5.7 4B5B Code Group
Symbol
Meaning
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9
Data A
Data B
Data C
Data D
Data E
Data F
4B code
3210
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
5B Code
43210
11110
01001
10100
10101
01010
01011
01110
01111
10010
10011
10110
10111
11010
11011
11100
11101
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
I
J
K
T
R
H
Idle
SFD (1)
SFD (2)
ESD (1)
ESD (2)
Error
undefined
0101
0101
undefined
undefined
undefined
11111
11000
10001
01101
00111
00100
V
V
V
V
V
V
V
V
V
V
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
00000
00001
00010
00011
00101
00110
01000
01100
10000
11001
Table 1
Final
Version: DM9000A-17-DS-F01
May 10, 2006
44
DM9000A
Ethernet Controller with General Processor Interface
9.6 100Base-TX Receiver
The 100Base-TX receiver contains several function
blocks that convert the scrambled 125Mb/s serial data
to synchronous 4-bit nibble data.
The receive section contains the following functional
blocks:
- Signal Detect
- Digital Adaptive Equalization
- MLT-3 to Binary Decoder
- Clock Recovery Module
- NRZI to NRZ Decoder
- Serial to Parallel
- Descrambler
- Code Group Alignment
- 4B5B Decoder
9.6.1 Signal Detect
The signal detect function meets the specifications
mandated by the ANSI XT12 TP-PMD 100Base-TX
standards for both voltage thresholds and timing
parameters.
9.6.2 Adaptive Equalization
When transmitting data over copper twisted pair cable
at high speed, attenuation based on frequency
becomes a concern. In high speed twisted pair
signaling, the frequency content of the transmitted
signal can vary greatly during normal operation based
on the randomness of the scrambled data stream.
This variation in signal attenuation, caused by
frequency variations, must be compensated for to
ensure the integrity of the received data. In order to
ensure quality transmission when employing MLT-3
encoding, the compensation must be able to adapt to
various cable lengths and cable types depending on
the installed environment. The selection of long cable
lengths for a given implementation requires significant
compensation, which will be over-killed in a situation
that includes shorter, less attenuating cable lengths.
Conversely, the selection of short or intermediate
cable lengths requiring less compensation will cause
serious under-compensation for longer length cables.
Therefore, the compensation or equalization must be
adaptive to ensure proper conditioning of the received
signal independent of the cable length.
Final
Version: DM9000A-17-DS-F01
May 10, 2006
9.6.3 MLT-3 to NRZI Decoder
The DM9000A decodes the MLT-3 information
from the Digital Adaptive Equalizer into NRZI
data.
9.6.4 Clock Recovery Module
The Clock Recovery Module accepts NRZI data from
the MLT-3 to NRZI decoder. The Clock Recovery
Module locks onto the data stream and extracts the
125Mhz reference clock. The extracted and
synchronized clock and data are presented to the
NRZI to NRZ decoder.
9.6.5 NRZI to NRZ
The transmit data stream is required to be NRZI
encoded for compatibility with the TP-PMD standard
for 100Base-TX transmission over Category-5
unshielded twisted pair cable. This conversion
process must be reversed on the receive end. The
NRZI to NRZ decoder, receives the NRZI data stream
from the Clock Recovery Module and converts it to a
NRZ data stream to be presented to the Serial to
Parallel conversion block.
9.6.6 Serial to Parallel
The Serial to Parallel Converter receives a serial
data stream from the NRZI to NRZ converter. It
converts the data stream to parallel data to be
presented to the descrambler.
9.6.7 Descrambler
Because of the scrambling process requires to control
the radiated emissions of transmit data streams, the
receiver must descramble the receive data streams.
The descrambler receives scrambled parallel data
streams from the Serial to Parallel converter, and it
descrambles the data streams, and presents the data
streams to the Code Group alignment block.
45
DM9000A
Ethernet Controller with General Processor Interface
9.6.8 Code Group Alignment
The Code Group Alignment block receives un-aligned
5B data from the descrambler and converts it into 5B
code group data. Code Group Alignment occurs after
the J/K is detected, and subsequent data is aligned on
a fixed boundary.
9.9 Carrier Sense
9.6.9 4B5B Decoder
9.10 Auto-Negotiation
The 4B5B Decoder functions as a look-up table that
translates incoming 5B code groups into 4B (Nibble)
data. When receiving a frame, the first 2 5-bit code
groups receive the start-of-frame delimiter (J/K
symbols). The J/K symbol pair is stripped and two
nibbles of preamble pattern are substituted. The last
two code groups are the end-of-frame delimiter (T/R
Symbols).
The objective of Auto-negotiation is to provide a
means to exchange information between linked
devices and to automatically configure both devices to
take maximum advantage of their abilities. It is
important to note that Auto-negotiation does not test
the characteristics of the linked segment. The
Auto-Negotiation function provides a means for a
device to advertise supported modes of operation to a
remote link partner, acknowledge the receipt and
understanding of common modes of operation, and to
reject un-shared modes of operation. This allows
devices on both ends of a segment to establish a link
at the best common mode of operation. If more than
one common mode exists between the two devices, a
mechanism is provided to allow the devices to resolve
to a single mode of operation using a predetermined
priority resolution function.
The T/R symbol pair is also stripped from the nibble,
presented to the Reconciliation layer.
9.7 10Base-T Operation
The 10Base-T transceiver is IEEE 802.3u compliant.
When the DM9000A is operating in 10Base-T mode,
the coding scheme is Manchester. Data processed for
transmit is presented in nibble format, converted to a
serial bit stream, then the Manchester encoded.
When receiving, the bit stream, encoded by the
Manchester, is decoded and converted into nibble
format.
9.8 Collision Detection
For half-duplex operation, a collision is detected when
the transmit and receive channels are active
simultaneously. Collision detection is disabled in full
duplex operation.
Final
Version: DM9000A-17-DS-F01
May 10, 2006
Carrier Sense (CRS) is asserted in half-duplex
operation during transmission or reception of data.
During full-duplex mode, CRS is asserted only during
receive operations.
Auto-negotiation also provides a parallel detection
function for devices that do not support the
Auto-negotiation feature. During Parallel detection
there is no exchange of information of configuration.
Instead, the receive signal is examined. If it is
discovered that the signal matches a technology,
which the receiving device supports, a connection will
be automatically established using that technology.
This allows devices not to support Auto-negotiation
but support a common mode of operation to establish
a link.
46
DM9000A
Ethernet Controller with General Processor Interface
9.11 Power Reduced Mode
The Signal detect circuit is always turned to monitor whether
there is any signal on the media (cable disconnected). The
DM9000A automatically turns off the power and enters the
Power Reduced mode, whether its operation mode is
N-way or force mode. When enters the Power Reduced
mode, the transmit circuit still sends out fast link pules with
minimum power consumption. If a valid signal is detected
from the media, which might be N-ways fast link pules,
10Base-T normal link pules, or 100Base-TX MLT3 signals,
the device will wake up and resume a normal
operation mode.
That can be writing Zero to PHY Reg. 16.4 to disable Power
Reduced mode.
Final
Version: DM9000A-17-DS-F01
May 10, 2006
9.11.1 Power Down Mode
The PHY Reg.0.11 can be set high to enter the Power
Down mode, which disables all transmit and receive
functions, except the access of PHY registers.
9.11.2 Reduced Transmit Power Mode
The additional Transmit power reduction can be
gained by designing with 1.25:1 turns ration magnetic
on its TX side and using a 8.5KΩ resistor on BGRES
and AGND pins, and the TXO+/TXO- pulled high
resistors should be changed from 50 Ω to 78 Ω .
This configuration could be reduced about 20%
transmit power.
47
DM9000A
Ethernet Controller with General Processor Interface
10. DC and AC Electrical Characteristics
10.1 Absolute Maximum Ratings ( 25°C )
Symbol
Parameter
DVDD
Supply Voltage
VIN
DC Input Voltage (VIN)
VOUT
DC Output Voltage(VOUT)
Tstg
Storage Temperature range
Tc
Case Temperature
TA
Ambient Temperature
LT
Lead Temperature
(TL,soldering,10 sec.).
LT
Lead Temperature
(TL,soldering,10 sec.).
10.1.1 Operating Conditions
Symbol
Parameter
DVDD
Supply Voltage
Tc
Case Reserve
PD
100BASE-TX
(Power Dissipation) 10BASE-T TX (100% utilization)
10BASE-T idle
Auto-negotiation
Power Reduced Mode(without cable)
Power Down Mode
Power Down Mode (system clock off)
10.2 DC Electrical Characteristics (VDD = 3.3V)
Symbol
Parameter
Min.
Inputs
VIL
Input Low Voltage
VIH
Input High Voltage
2.0
IIL
Input Low Leakage Current
-1
IIH
Input High Leakage Current
Outputs
VOL
Output Low Voltage
VOH
Output High Voltage
2.4
Receiver
VICM
RX+/RX- Common Mode Input
Voltage
Transmitter
VTD100 100TX+/- Differential Output
1.9
Voltage
VTD10
10TX+/- Differential Output Voltage
4.4
ITD100
100TX+/- Differential Output
│19│
Current
ITD10
10TX+/- Differential Output Current │44│
Final
Version: DM9000A-17-DS-F01
May 10, 2006
Min.
-0.3
-0.5
-0.3
-65
0
0
－
Max.
3.6
5.5
3.6
+150
85
+70
+235
Unit
V
V
V
℃
°C
℃
℃
－
+260
℃
DM9000AEP
Min.
3.135
-----------------
Max.
3.465
85
87
92
38
56
31
21
7
Unit
V
°C
mA
mA
mA
mA
mA
mA
mA
Conditions
Typ.
Conditions
@Ta=0 ~ 70℃
DM9000AE
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
Max.
Unit
Conditions
-
0.8
1
V
V
uA
uA
VIN = 0.0V
VIN = 3.3V
-
0.4
-
V
V
IOL = 4mA
IOH = -4mA
2.5
-
V
100 Ω Termination
Across
2.0
2.1
V
Peak to Peak
5
│20│
5.6
│21│
V
mA
Peak to Peak
Absolute Value
│50│
│56│
mA
Absolute Value
48
DM9000A
Ethernet Controller with General Processor Interface
10.3 AC Electrical Characteristics & Timing Waveforms
10.3.1 TP Interface
Symbol
Parameter
tTR/F
100TX+/- Differential Rise/Fall Time
tTM
100TX+/- Differential Rise/Fall Time
Mismatch
tTDC
100TX+/- Differential Output Duty Cycle
Distortion
Tt/T
100TX+/- Differential Output Peak-to-Peak
Jitter
XOST
100TX+/- Differential Voltage Overshoot
10.3.2 Oscillator/Crystal Timing
Symbol
Parameter
TCKC
OSC Clock Cycle
TPWH
OSC Pulse Width High
TPWL
OSC Pulse Width Low
Min.
3.0
0
Typ.
-
Max.
5.0
0.5
Unit
ns
ns
0
-
0.5
ns
0
-
1.4
ns
0
-
5
%
Min.
39.998
16
16
Typ.
40
20
20
Max.
40.002
24
24
Conditions
Unit
ns
ns
ns
Conditions
50ppm
10.3.3 Processor I/O Read Timing
CS#,CMD
→
T1
←
→
T5
←
IOR#
←
SD
T2
← T3 →
IO16
→
Symbol
T1
T2
T3
T4
T5
T6
→←
→
←T7
Parameter
CS#,CMD valid to IOR# valid
IOR# width
System Data(SD) Delay time
IOR# invalid to System Data(SD) invalid
IOR# invalid to CS#,CMD invalid
IOR# invalid to next IOR#/IOW# valid
When read DM9000A register
T6
IOR# invalid to next IOR#/IOW# valid
When read DM9000A memory with F0h register
T2+T6 IOR# invalid to next IOR#/IOW# valid
When read DM9000A memory with F2h register
T7
CS#,CMD valid to IO16 valid
T8
CS#,CMD invalid to IO16 invalid
*Note：(the default clk period is 20ns)
1. The IO16 is valid when the SD bus width is 16-bit
and the system address is DATA port (i.e. CMD is
high) and the value of INDEX port is memory data
Final
Version: DM9000A-17-DS-F01
May 10, 2006
T4
→
T6
←
→
←T8
Min.
0
10
Typ.
Max.
0
2
Unit
ns
ns
ns
ns
ns
clk*
4
clk*
1
clk*
3
3
3
3
ns
ns
register index.（ex. F0H, F2H, F6H or F8H）
49
DM9000A
Ethernet Controller with General Processor Interface
10.3.4 Processor I/O Write Timing
CS# , CMD
→
T1
→
←
←
IOW#
→
T2
←
→
Symbol
T1
T2
T3
T4
T5
T6
T6
T2+T6
T7
T8
← T7
Parameter
CS#,CMD valid to IOW# valid
IOW# Width
System Data(SD) Setup Time
System Data(SD) Hold Time
IOW# Invalid to CS#,CMD Invalid
IOW# Invalid to next IOW#/IOR# valid
When write DM9000A INDEX port
IOW# Invalid to next IOW#/IOR# valid
When write DM9000A DATA port
IOW# Invalid to next IOW#/IOR# valid
When write DM9000A memory
CS#,CMD Valid to IO16 valid
CS#,CMD Invalid to IO16 Invalid
Note：(the default clk period is 20ns)
1. The IO16 is valid when the SD bus width is 16-bit
and system address is DATA port (i.e. CMD is high)
and the value of INDEX port is memory data
Final
Version: DM9000A-17-DS-F01
May 10, 2006
←
T3
→
T6
∫∫
→
SD
IO16
← T5
←
T4
→
→
Min.
0
10
10
3
0
1
←
T8
Typ.
Max.
Unit
ns
ns
ns
ns
ns
clk*
2
clk*
1
clk*
3
3
ns
ns
register index (ex. F0H, F2H, F6H or F8H）
50
DM9000A
Ethernet Controller with General Processor Interface
10.3.5 EEPROM Interface Timing
T2
T3
EECS
T1
EECK
T4
T6
EEDIO
T5
T7
Symbol
T1
T2
T3
T4
T5
T6
T7
Parameter
EECK Frequency
EECS Setup Time
EECS Hold Time
EEDIO Setup Time when output
EEDIO Hold Time when output
EEDIO Setup Time when input
EEDIO Hold Time when input
Final
Version: DM9000A-17-DS-F01
May 10, 2006
Min.
8
8
Typ.
0.375
500
2166
480
2200
Max.
Unit
Mhz
ns
ns
ns
ns
ns
ns
51
DM9000A
Ethernet Controller with General Processor Interface
11. Application Notes
11.1 Network Interface Signal Routing
Place the transformer as close as possible to the RJ-45
connector. Place all the 50Ω resistors as close as possible
to the DM9000A RXI± and TXO± pins. Traces routed
from RXI± and TXO± to the transformer should run in close
pairs directly to the transformer. The designer should be
careful not to cross the transmit and receive pairs. As
always, vias should be avoided as much as possible. The
network interface should be void of any signals other than
the TXO± and RXI± pairs between the RJ-45 to the
transformer and the transformer to the DM9000A.. There
should be no power or ground planes in the area under the
network side of the transformer to include the area under the
RJ-45 connector. (Refer to Figure 11-4 and 11-5) Keep
chassis ground away from all active signals. The RJ-45
connector and any unused pins should be tied to chassis
ground through a resistor divider network and a 2KV bypass
capacitor.
The Band Gap resistor should be placed as physically close
as pins 1 and 48 as possible (refer to Figure 11-1 and 11-2).
The designer should not run any high-speed signal near the
Band Gap resistor placement.
11.2 10Base-T/100Base-TX Auto MDIX Application
50
1%
RXI+
0.1µF
AUTO MDI-X
Transformer
RJ45
1:1
3
1
50
1%
RXIAVDD_25
AVDD_25
DM9000A
TX0+
2
4
2
9
3
2.5V AVCC
220µF
4
0.1µF
5
AGND
7
AGND
1:1
6
50
1%
TX0-
7
8
8
50
1%
BGRES
BGGND
1
0.1µF
75
1%
75
1%
75
1%
48
6.8K
1%
0.1µF/2KV
Chasis GND
AGND
Figure 11-1 Auto MDIX Application
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11.3 10Base-T/100Base-TX ( Non Auto MDIX Transformer Application )
50
1%
RXI+
0.1µF
Transformer
RJ45
1:1
3
1
50
1%
RXIAVDD_25
AVDD_25
DM9000A
TX0+
2
4
2
9
3
2.5V AVCC
220µF 0.1µF
4
5
AGND AGND
7
1:1
6
50
1%
TX0-
7
8
8
50
1%
BGRES
BGGND
1
0.1µF
75
1%
75
1%
75
1%
48
6.8K
1%
0.1µF/2KV
AGND
Chasis GND
Figure 11-2 Non Auto MDIX Transformer Application
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11.4 Power Decoupling Capacitors
Davicom Semiconductor recommends placing all the decoupling capacitors for all power supply pins as close as possible to
the power pads of the DM9000A (The best placed distance is < 3mm from pin). The recommended decoupling capacitor is
0.1μF or 0.01μF, as required by the design layout.
Figure 3
Figure 11-3 Power Decoupling Capacitors
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11.5 Ground Plane Layout
Davicom Semiconductor recommends a single ground
plane approach to minimize EMI. Ground plane partitioning
can cause increased EMI emissions that could make the
network interface card not comply with specific FCC
regulations (part 15). Figure 11-4 shows a recommended
ground layout scheme.
Figure 4
Figure 11-4 Ground Plane Layout
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11.6 Power Plane Partitioning
The power planes should be approximately illustrated in Figure 11-5.
Figure 11-5 Power Plane Partitioning
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11.7 Magnetics Selection Guide
using them in an application. The transformers listed
in Table 2 are electrical equivalents, but may not be
pin-to-pin equivalents.
Refer to Table 2 for transformer requirements.
Transformers, meeting these requirements, are
available from a variety of magnetic manufacturers.
Designers should test and qualify all magnetics before
Manufacturer
Pulse Engineering
Delta
YCL
MAGCOM
Halo
Nano Pulse Inc.
Fil-Mag
Bel Fuse
Valor
Macronics
Bothhand
Part Number
PE-68515, H1078, H1012, H1102
LF8200, LF8221x
20PMT04, 20PMT05, PH163112 , YCL 0303
PH163539 *(Auto MDIX)
HS9001 , HS9016
TG22-3506ND, TD22-3506G1, TG22-S010ND, TG22-S012ND
TG110-S050N2
NPI 6181-37, NPI 6120-30, NPI 6120-37
NPI 6170-30
PT41715
S558-5999-01, S558-5999-W2
ST6114, ST6118
HS2123, HS2213
TS6121C,16ST8515,16ST1086
Table 2
11.8 Crystal Selection Guide
A crystal can be used to generate the 25MHz
reference clock instead of an oscillator. The crystal
must be a fundamental type, and series-resonant.
Connects to pins X1 and X2, and shunts each crystal
lead to ground with a 22pf capacitor (see figure 11-6).
X1
X2
43
44
25MHz
22pf
DGND
22pf
DGND
Figure 11-6
Crystal Circuit Diagram
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12. Package Information
LQFP 48L (F.P. 2mm) Outline Dimensions
unit: inches/mm
D
D1
y
Symbol
A
A1
A2
b
b1
C
C1
D
D1
E
E1
L
L1
y
Dimensions in inches
Min.
Nom.
Max.
0.063
0.002
0.006
0.053
0.055
0.057
0.007
0.009
0.011
0.007
0.008
0.009
0.004
0.008
0.004
0.006
0.354BSC
0.276BSC
0.354BSC
0.276BSC
0.020BSC
Dimensions in mm
Min.
Nom.
Max.
1.60
0.05
0.15
1.35
1.40
1.45
0.17
0.22
0.27
0.17
0.20
0.23
0.09
0.20
0.09
0.16
9.00BSC
7.00BSC
9.00BSC
7.00BSC
0.50BSC
0.018
0.45
0.024
0.030
0.039REF
0.003MAX
0.60
1.00REF
0.08MAX
0.75
1. To be determined at seating plane.
2. Dimensions D1 and E 1do not include mold protrusion.
D1 and E1 are maximum plastic body size dimensions
including mold mismatch.
3. Dimensions b does not include dambar protrusion. Total
in excess of the b dimension at maximum material
condition. Dambar cannot be located on the lower radius
of the foot.
4. Exact shape of each corner is optional.
5. These dimensions apply to the flat section of the lead
between 0.10mm and 0.25mm from the lead tip.
6. A1 is defined as the distance from the seating plane to
the lowest point of the package body.
7. Controlling dimension: millimeter.
8. Reference documents: JEDEC MS-026, BBC.
Notes:
Θ
0-12°
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application circuits illustrated in this document are for
reference purposes only.
13. Ordering Information
Part Number
DM9000AE
Pin Count
48
DM9000AEP
48
Package
LQFP
LQFP
(Pb-Free)
Disclaimer
The information appearing in this publication is
believed to be accurate. Integrated circuits sold by
DAVICOM Semiconductor are covered by the
warranty and patent indemnification provisions
stipulated in the terms of sale only. DAVICOM makes
no warranty, express, statutory, implied or by
description regarding the information in this
publication or regarding the information in this
publication or regarding the freedom of the described
chip(s) from patent infringement. FURTHER,
DAVICOM MAKES NO WARRANTY OF
MERCHANTABILITY OR FITNESS FOR ANY
PURPOSE. DAVICOM reserves the right to halt
production or alter the specifications and prices at any
time without notice. Accordingly, the reader is
cautioned to verify that the data sheets and other
information in this publication are current before
placing orders. Products described herein are
intended for use in normal commercial applications.
Applications involving unusual environmental or
reliability requirements, e.g. military equipment or
medical life support equipment, are specifically not
recommended without additional processing by
DAVICOM for such applications. Please note that
DAVICOM’s terms and conditions printed on the order
acknowledgment govern all sales by DAVICOM.
DAVICOM will not be bound by any terms inconsistent
with these unless DAVICOM agrees otherwise in
writing. Acceptance of the buyer’s orders shall be
based on these terms.
Company Overview
DAVICOM Semiconductor Inc. develops and
manufactures integrated circuits for integration into
data communication products. Our mission is to
design and produce IC products that are the industry’s
best value for Data, Audio, Video, and
Internet/Intranet applications. To achieve this goal, we
have built an organization that is able to develop
chipsets in response to the evolving technology
requirements of our customers while still delivering
products that meet their cost requirements.
Products
We offer only products that satisfy high performance
requirements and which are compatible with major
hardware and software standards. Our currently
available and soon to be released products are based
on our proprietary designs and deliver high quality,
high performance chipsets that comply with modem
communication standards and Ethernet networking
standards.
Contact Windows
For additional information about DAVICOM products, contact the sales department at:
Headquarters
Hsin-chu Office:
No.6 Li-Hsin Rd. VI,
Science-based Industrial Park,
Hsin-chu City, Taiwan, R.O.C.
TEL: 886-3-5798797
FAX: 886-3-5646929
WARNING
Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near
the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and/or function.
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