DM9008AEP Ethernet Controller with General Processor Interface DAVICOM Semiconductor, Inc. DM9008AEP Ethernet Controller with General Processor Interface DATA SHEET Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 Preliminary Version: DM9008A-DS-P02 Apr. 11, 2006 1 DM9008AEP Ethernet Controller with General Processor Interface Content 1. General Description........................................................................................................... 6 2. Block Diagram.................................................................................................................... 6 3. Features.............................................................................................................................. 7 4. Pin Configuration............................................................................................................... 8 5. Pin Description .................................................................................................................. 9 5.1 Processor Interface................................................................................................................................... 9 5.2 EEPROM Interface ................................................................................................................................... 9 5.3 Clock Interface ........................................................................................................................................ 10 5.4 LED Interface .......................................................................................................................................... 10 5.5 10/100 PHY/Fiber ................................................................................................................................... 10 5.6 Miscellaneous ......................................................................................................................................... 10 5.7 Power Pins.............................................................................................................................................. 11 5.8 strap pins table........................................................................................................................................ 11 6. Vendor Control and Status Register Set ....................................................................... 12 6.1 Network Control Register (00H).............................................................................................................. 13 6.2 Network Status Register (01H) ............................................................................................................... 14 6.3 TX Control Register (02H) ...................................................................................................................... 14 6.4 TX Status Register I ( 03H ) for packet index I ....................................................................................... 14 6.5 TX Status Register II ( 04H ) for packet index I I .................................................................................... 15 6.6 RX Control Register ( 05H ).................................................................................................................... 15 6.7 RX Status Register ( 06H ) ..................................................................................................................... 15 6.8 Receive Overflow Counter Register ( 07H ) ........................................................................................... 16 6.9 Back Pressure Threshold Register (08H) ............................................................................................... 16 6.10 Flow Control Threshold Register ( 09H ) .............................................................................................. 16 6.11 RX/TX Flow Control Register ( 0AH ) ................................................................................................... 17 6.12 EEPROM & PHY Control Register ( 0BH )........................................................................................... 17 6.13 EEPROM & PHY Address Register ( 0CH ) ......................................................................................... 17 6.14 EEPROM & PHY Data Register (EE_PHY_L：0DH EE_PHY_H：0EH)........................................ 17 6.15 Wake Up Control Register ( 0FH ) (in 8-bit mode) ............................................................................... 18 6.16 Physical Address Register ( 10H~15H ) ............................................................................................... 18 6.17 Multicast Address Register ( 16H~1DH ).............................................................................................. 18 Preliminary Version: DM9008A-DS-P02 Apr. 11, 2006 2 DM9008AEP Ethernet Controller with General Processor Interface 6.18 General purpose control Register ( 1EH ) (in 8-bit mode) ................................................................. 18 6.19 General purpose Register ( 1FH ) ........................................................................................................ 19 6.20 TX SRAM Read Pointer Address Register (22H~23H) ........................................................................ 19 6.21 RX SRAM Write Pointer Address Register (24H~25H) ........................................................................ 19 6.22 Vendor ID Register (28H~29H) ............................................................................................................ 19 6.23 Product ID Register (2AH~2BH)........................................................................................................... 19 6.24 Chip Revision Register (2CH)............................................................................................................... 19 6.25 Transmit Control Register 2 ( 2DH ) ..................................................................................................... 19 6.26 Operation Test Control Register ( 2EH ) .............................................................................................. 20 6.27 Special Mode Control Register ( 2FH )................................................................................................. 20 6.28 Early Transmit Control/Status Register ( 30H ) .................................................................................... 21 6.29 Check Sum Control Register ( 31H ) .................................................................................................... 21 6.30 Receive Check Sum Status Register ( 32H ) ....................................................................................... 21 6.31 LED Pin Control Register ( 34H ).......................................................................................................... 21 6.32 Processor Bus Control Register ( 38H ) ............................................................................................... 22 6.33 INT Pin Control Register ( 39H )........................................................................................................... 23 6.34 System Clock Turn ON Control Register ( 50H ).................................................................................. 23 6.35 Resume System Clock Control Register ( 51H ) .................................................................................. 23 6.36 Memory Data Pre-Fetch Read Command without Address Increment Register (F0H) ....................... 24 6.37 Memory Data Read Command without Address Increment Register (F1H) ........................................ 24 6.38 Memory Data Read Command with Address Increment Register (F2H) ............................................. 24 6.39 Memory Data Read_address Register (F4H~F5H) .............................................................................. 24 6.40 Memory Data Write Command without Address Increment Register (F6H)......................................... 24 6.41 Memory data write command with address increment Register (F8H) ................................................ 24 6.42 Memory data write_address Register (FAH~FBH)............................................................................... 24 6.43 TX Packet Length Register (FCH~FDH) .............................................................................................. 24 6.44 Interrupt Status Register (FEH) ............................................................................................................ 25 6.45 Interrupt Mask Register (FFH) .............................................................................................................. 25 7. EEPROM Format .............................................................................................................. 26 8. MII Register Description.................................................................................................. 27 8.1 Basic Mode Control Register (BMCR) - 00............................................................................................. 27 8.2 Basic Mode Status Register (BMSR) - 01 .............................................................................................. 29 8.3 PHY ID Identifier Register #1 (PHYID1) - 02.......................................................................................... 30 8.4 PHY ID Identifier Register #2 (PHYID2) - 03.......................................................................................... 30 Preliminary Version: DM9008A-DS-P02 Apr. 11, 2006 3 DM9008AEP Ethernet Controller with General Processor Interface 8.5 Auto-negotiation Advertisement Register (ANAR) - 04 .......................................................................... 31 8.6 Auto-negotiation Link Partner Ability Register (ANLPAR) – 05 .............................................................. 32 8.7 Auto-negotiation Expansion Register (ANER)- 06.................................................................................. 33 8.8 DAVICOM Specified Configuration Register (DSCR) – 16..................................................................... 33 Reserved .............................................................................................................................. 34 Force to 0 in application. .................................................................................................... 34 8.9 DAVICOM Specified Configuration and Status Register (DSCSR) - 17................................................. 35 8.10 10BASE-T Configuration/Status (10BTCSR) - 18 ................................................................................ 36 8.11 (Specified config) Register – 20............................................................................................................ 36 9. Functional Description.................................................................................................... 38 9.1 Host Interface.......................................................................................................................................... 38 9.2 Direct Memory Access Control ............................................................................................................... 38 9.3 Packet Transmission............................................................................................................................... 38 9.4 Packet Reception.................................................................................................................................... 38 9.5 10Base-T Operation................................................................................................................................ 39 9.6 Collision Detection .................................................................................................................................. 39 9.7 Carrier Sense.......................................................................................................................................... 39 9.8 Auto-Negotiation ..................................................................................................................................... 39 9.9 Power Reduced Mode ............................................................................................................................ 40 9.9.1 Power Down Mode .............................................................................................................................. 40 9.9.2 Reduced Transmit Power Mode .......................................................................................................... 40 10. DC and AC Electrical Characteristics .......................................................................... 41 10.1 Absolute Maximum Ratings ( 25°C )..................................................................................................... 41 10.1.1 Operating Conditions ......................................................................................................................... 41 10.2 DC Electrical Characteristics (VDD = 3.3V).......................................................................................... 41 10.3 AC Electrical Characteristics & Timing Waveforms.............................................................................. 42 10.3.1 Oscillator/Crystal Timing.................................................................................................................... 42 10.3.2 Processor I/O Read Timing ............................................................................................................... 42 10.4.3 Processor I/O Write Timing................................................................................................................ 43 10.4.4 EEPROM Interface Timing ................................................................................................................ 44 11. Application Notes .......................................................................................................... 45 11.1 Network Interface Signal Routing ......................................................................................................... 45 HP Auto-MDIX Application............................................................................................................................ 45 11.3 Non HP Auto-MDIX Transformer Application ....................................................................................... 46 Preliminary Version: DM9008A-DS-P02 Apr. 11, 2006 4 DM9008AEP Ethernet Controller with General Processor Interface 11.4 Power Decoupling Capacitors .............................................................................................................. 46 11.41 DM9008A + DM8606A Circuit ............................................................................................................ 47 11.5 Magnetics Selection Guide ................................................................................................................... 48 11.6 Crystal Selection Guide ........................................................................................................................ 48 12. Package Information ..................................................................................................... 49 13. Ordering Information..................................................................................................... 50 Preliminary Version: DM9008A-DS-P02 Apr. 11, 2006 5 DM9008AEP Ethernet Controller with General Processor Interface 1. General Description The DM9008A is a fully integrated and cost-effective low pin count Ethernet controller with a general processor interface, a Medial Access Control (MAC), a 10Base-T PHY and 16K Byte SRAM. It is designed with low power and high performance process that support 3.3V with 5V IO tolerance. The DM9008A supports 8-bit and 16-bit data interfaces to internal memory accesses for various processors. The DM9008A also supports full duplex mode The PHY of the DM9008A can interface to the UTP3, 4, 5 in 10Base-T that is fully compliant with the IEEE 802.3 Spec.. The HP Auto-MDIX function of PHY is also supported to improve the media connection in convenience. 2. Block Diagram Preliminary Version: DM9008A-DS-P02 Apr. 11, 2006 6 DM9008AEP Ethernet Controller with General Processor Interface 3. Features ■ 48-pin LQFP ■ ■ Supports processor interface: byte/word of I/O ■ Supports early Transmit command to internal memory data operation ■ Comply to 10BASE-T of IEEE 802.3 with ■ ■ Supports automatically load vendor ID and product ID from EEPROM HP Auto-MDIX ■ Optional EEPROM configuration Supports back pressure mode for half-duplex ■ Very low power consumption mode: mode flow control – Power reduced mode (cable detection) Support 100M Fiber interface. – Power down mode ■ IEEE802.3x flow control for full-duplex mode ■ Supports wakeup frame, link status change and magic packet events for remote wake up ■ ■ Build in 3.3V to 2.5V regulator – Selectable TX drivers for 1:1 or 1.25:1 transformers for additional power reduction. ■ Compatible with 3.3V and 5.0V tolerant I/O Integrated 16K Byte SRAM Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 7 DM9008AEP Ethernet Controller with General Processor Interface IOR# INT GND CMD SD8_GP1 VDD SD9_GP2 SD10_GP3 SD11_GP4 SD12_GP5 SD13_GP6 35 34 33 31 30 29 28 27 26 25 32 IOW# 36 4. Pin Configuration CS# 37 24 SD14_LED3 LED2 38 23 LED1 39 22 VDD SD15_WAKE PWRST# 40 21 EECS TEST 41 20 EECK VDD 42 19 EEDIO X2 43 18 SD0 X1 44 17 SD1 GND 45 16 SD2 SD 46 15 GND RXGND 47 14 SD3 BGGND 48 13 SD4 Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 7 8 9 TX+ TX- TXVDD25 12 6 TXGND 11 5 RXGND SD5 4 RX- SD6 3 RX+ 10 2 RXVDD25 SD7 1 BGRES DM9008A 8 DM9008AEP Ethernet Controller with General Processor Interface 5. Pin Description I = Input O = Output # = asserted low 5.1 Processor Interface O/D = Open Drain P = Power PD = internal pull-low about 60K Pin No. Pin Name Type 35 IOR# I,PD 36 IOW# I,PD 37 CS# I,PD 32 CMD 34 INT 18,17,16,1 4,13,12,11 ,10 SD0~7 31, 29, 28, 27, 26, 25, 24, 22 I/O = Input/Output Description Processor Read Command This pin is low active at default, its polarity can be modified by EEPROM setting. See the EEPROM content description for detail Processor Write Command This pin is low active at default, its polarity can be modified by EEPROM setting. See the EEPROM content description for detail Chip Select A default low active signal used to select the DM9008A. Its polarity can be modified by EEPROM setting. See the EEPROM content description for detail. Command Type When high, the access of this command cycle is DATA port When low, the access of this command cycle is INDEX port Interrupt Request This pin is high active at default, its polarity can be modified by EEPROM O,PD setting or by strap pin EECK. See the EEPROM content description for detail I,PD Processor Data Bus bit 0~7 SD8_GP1, SD9_GP2, SD10_GP3, SD11_GP4, SD12_GP5, SD13_GP6, SD14_LED3, SD15_WAKE I/O,PD Processor Data Bus bit 8~15 In 16-bit mode (see EECS pin description), these pins act as the processor data bus bit 8~15; In 8-bit mode, these pins have other definitions in the followings: Pin 31,29,28,27,26,25 act as the general purpose pins that defined in REG.1Eh I/O,PD and 1Fh. The SD13_GP6 pin also act as trap pin for the INT output type. When SD13_GP6 is pulled high, the INT is Open-Drain output type; Otherwise it is force output type. Pin 24 is act as full-duplex LED in LED mode 1; otherwise it act as 10Base-T link LED in LED mode 0. (Note: LED mode is defined in EEPROM setting.) Pin 22 is act as a wake up signal. 5.2 EEPROM Interface Description Pin No. Pin Name 19 EEDIO I/O,PD IO Data to EEPROM Clock to EEPROM 20 EECK O,PD EECS Chip Select to EEPROM This pin is also used as a strap pin to define the internal memory data O,PD bus width. When it is pulled high, the memory access bus is 8-bit; Otherwise it is 16-bit. 21 Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 Type This pin is also used as the strap pin of the polarity of the INT pin When this pin is pulled high, the INT pin is low active; otherwise the INT pin is high active 9 DM9008AEP Ethernet Controller with General Processor Interface 5.3 Clock Interface Description Pin No. Pin Name Type 43 X2 O Crystal 25MHz Out 44 X1 I Crystal 25MHz In 5.4 LED Interface Pin No. Pin Name Description Type 39 LED1 O 38 LED2 O Speed LED Its low output indicates that the internal PHY is operated in 100M/S, or it is floating for the 10M mode of the internal PHY. This pin also acts as ISA bus IO16 function defined in EEPROM setting. Link / Active LED In LED mode 1, it is the combined LED of link and carrier sense signal of the internal PHY In LED mode 0, it is the LED of the carrier sense signal of the internal PHY only 5.5 10/100 PHY/Fiber Pin No. Pin Name Type Description Fiber-optic Signal Detect PECL signal, which indicates whether or not the fiber-optic receive pair is receiving valid levels Bandgap Ground 46 SD I 48 BGGND P 1 BGRES I/O 2 RXVDD25 P 2.5V power output for TP RX 9 TXVDD25 P 2.5V power output for TP TX 3 RX+ I/O TP RX Input 4 RX- I/O TP RX Input 5,47 RXGND P RX Ground 6 TXGND P TX Ground 7 TX+ I/O TP TX Output 8 TX- I/O TP TX Output Bandgap Pin 5.6 Miscellaneous Pin No. Pin Name Type 41 TEST I 40 PWRST# I Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 Description Operation Mode Force to ground in normal application Power on Reset Active low signal to initiate the DM9008A The DM9008A is ready after 5us when this pin deasserted 10 DM9008AEP Ethernet Controller with General Processor Interface 5.7 Power Pins Pin No. Pin Name Type 23,30,42 VDD P 15,33,45 GND P Description Digital VDD 3.3V power input Digital GND 5.8 strap pins table 1: pull-high 1K~10K, 0: floating (default) Pin No. Pin Name 20 EECK 21 EECS 22 WAKE 25 SD13_GP6 Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 Description Polarity of INT 1: INT pin low active; 0: INT pin high active DATA Bus Width 1: 8-bit 0: 16-bit Polarity of CS# in 8-bit mode 1: CS# pin active high 0: CS# pin active low INT output type in 8-bit mode 1: Open-Drain 0: force mode 11 DM9008AEP Ethernet Controller with General Processor Interface 6. Vendor Control and Status Register Set The DM9008A implements several control and status registers, which can be accessed by the host. These CSRs Register NCR NSR TCR TSR I TSR II RCR RSR ROCR BPTR FCTR FCR EPCR EPAR EPDRL EPDRH WCR PAR MAR GPCR GPR TRPAL TRPAH RWPAL RWPAH VID PID CHIPR TCR2 OCR SMCR ETXCSR TCSCR RCSCSR LEDCR BUSCR INTCR SCCR RSCCR are byte aligned. All CSRs are set to their default values by hardware or software reset unless they are specified Description Offset Network Control Register Network Status Register TX Control Register TX Status Register I TX Status Register II RX Control Register RX Status Register Receive Overflow Counter Register Back Pressure Threshold Register Flow Control Threshold Register RX Flow Control Register EEPROM & PHY Control Register EEPROM & PHY Address Register EEPROM & PHY Low Byte Data Register EEPROM & PHY High Byte Data Register Wake Up Control Register (in 8-bit mode) Physical Address Register 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H-15H Multicast Address Register General Purpose Control Register (in 8-bit mode) General Purpose Register TX SRAM Read Pointer Address Low Byte TX SRAM Read Pointer Address High Byte RX SRAM Write Pointer Address Low Byte RX SRAM Write Pointer Address High Byte Vendor ID Product ID CHIP Revision TX Control Register 2 Operation Control Register Special Mode Control Register Early Transmit Control/Status Register Transmit Check Sum Control Register Receive Check Sum Control Status Register LED Pin Control Register Processor Bus Control Register INT Pin Control Register System Clock Turn ON Control Register Resume System Clock Control Register 16H-1DH 1EH 1FH 22H 23H 24H 25H 28H-29H 2AH-2BH 2CH 2DH 2EH 2FH 30H 31H 32H 34H 38H 39H 50H 51H Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 Default value after reset 00H 00H 00H 00H 00H 00H 00H 00H 37H 38H 00H 00H 40H XXH XXH 00H Determined by EEPROM XXH 01H XXH 00H 00H 00H 0CH 0A46H 9000H 19H 00H 00H 00H 00H 00H 00H 00H 61H 00H 00H XXH 12 DM9008AEP Ethernet Controller with General Processor Interface MRCMDX MRCMDX1 MRCMD MRRL MRRH MWCMDX MWCMD MWRL MWRH TXPLL TXPLH ISR IMR Memory Data Pre-Fetch Read Command Without Address Increment Register Memory Data Read Command With Address Increment Register Memory Data Read Command With Address Increment Register Memory Data Read_ address Register Low Byte Memory Data Read_ address Register High Byte Memory Data Write Command Without Address Increment Register Memory Data Write Command With Address Increment Register Memory Data Write_ address Register Low Byte Memory Data Write _ address Register High Byte TX Packet Length Low Byte Register TX Packet Length High Byte Register Interrupt Status Register Interrupt Mask Register Key to Default In the register description that follows, the default column takes the form: <Reset Value>, <Access Type> Where： <Reset Value>: 1 Bit set to logic one 0 Bit set to logic zero X No default value P = power on reset default value H = hardware reset default value S = software reset default value F0H XXH F1H XXH F2H XXH F4H F5H F6H 00H 00H XXH F8H XXH FAH FBH FCH FDH FEH FFH 00H 00H XXH XXH 00H 00H E = default value from EEPROM T = default value from strap pin <Access Type>: RO = Read only RW = Read/Write R/C = Read and Clear RW/C1=Read/Write and Cleared by write 1 WO = Write only Reserved bits are shaded and should be written with 0. Reserved bits are undefined on read access. 6.1 Network Control Register (00H) Bit Name Default Description 7 RESERVED PH0,RW Reserved Wakeup Event Enable work in 8-bit mode WAKEEN When set, it enables the wakeup function. Clearing this bit will also clears all 6 P0,RW wakeup event status This bit will not be affected after a software reset 5 RESERVED 0,RO Reserved 4 FCOL PHS0,RW Force Collision Mode, used for testing 3 FDX PHS0,RO Full-Duplex Mode of the internal PHY. Loopback Mode Bit 2 1 PHS00, 2:1 LBK 0 0 Normal RW 0 1 MAC Internal loopback 1 X (Reserved) 0 RST PH0,RW Software reset and auto clear after 10us Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 13 DM9008AEP Ethernet Controller with General Processor Interface 6.2 Network Status Register (01H) Bit 7 6 Name RESERVED LINKST 5 WAKEST 4 RESERVED 3 TX2END 2 TX1END 1 0 RXOV RESERVED Default X,RO X,RO P0, RW/C1 0,RO PHS0, RW/C1 PHS0, RW/C1 PHS0,RO 0,RO 6.3 TX Control Register (02H) Bit Name Default 7 RESERVED 0,RO 6 TJDIS PHS0,RW 5 EXCECM PHS0,RW 4 3 2 1 0 PAD_DIS2 CRC_DIS2 PAD_DIS1 CRC_DIS1 TXREQ PHS0,RW PHS0,RW PHS0,RW PHS0,RW PHS0,RW Description Reserved Link Status 0:link failed 1:link OK, Wakeup Event Status. Clears by read or write 1 (work in 8-bit mode) This bit will not be affected after software reset Reserved TX Packet 2 Complete Status. Clears by read or write 1 Transmit completion of packet index 2 TX Packet 1 Complete status. Clears by read or write 1 Transmit completion of packet index 1 RX FIFO Overflow Reserved Description Reserved Transmit Jabber Disable When set, the transmit Jabber Timer (2048 bytes) is disabled. Otherwise it is Enable Excessive Collision Mode Control : 0:aborts this packet when excessive collision counts more than 15, 1: still tries to transmit this packet PAD Appends Disable for Packet Index 2 CRC Appends Disable for Packet Index 2 PAD Appends Disable for Packet Index 1 CRC Appends Disable for Packet Index 1 TX Request. Auto clears after sending completely 6.4 TX Status Register I ( 03H ) for packet index I Bit Name Default Description Transmit Jabber Time Out 7 TJTO PHS0,RO It is set to indicate that the transmitted frame is truncated due to more than 2048 bytes are transmitted Loss of Carrier 6 LC PHS0,RO It is set to indicate the loss of carrier during the frame transmission. It is not valid in internal loopback mode No Carrier 5 NC PHS0,RO It is set to indicate that there is no carrier signal during the frame transmission. It is not valid in internal loopback mode Late Collision 4 LC PHS0,RO It is set when a collision occurs after the collision window of 64 bytes Collision Packet 3 COL PHS0,RO It is set to indicate that the collision occurs during transmission Excessive Collision 2 EC PHS0,RO It is set to indicate that the transmission is aborted due to 16 excessive collisions 1:0 RESERVED 0,RO Reserved Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 14 DM9008AEP Ethernet Controller with General Processor Interface 6.5 TX Status Register II ( 04H ) for packet index I I Bit Name Default Description Transmit Jabber Time Out 7 TJTO PHS0,RO It is set to indicate that the transmitted frame is truncated due to more than 2048 bytes are transmitted Loss of Carrier 6 LC PHS0,RO It is set to indicate the loss of carrier during the frame transmission. It is not valid in internal loopback mode No Carrier 5 NC PHS0,RO It is set to indicate that there is no carrier signal during the frame transmission. It is not valid in internal loopback mode Late Collision 4 LC PHS0,RO It is set when a collision occurs after the collision window of 64 bytes 3 COL PHS0,RO Collision packet, collision occurs during transmission Excessive Collision 2 EC PHS0,RO It is set to indicate that the transmission is aborted due to 16 excessive collisions 1:0 RESERVED 0,RO Reserved 6.6 RX Control Register ( 05H ) Bit Name Default 7 RESERVED PHS0,RW 6 WTDIS PHS0,RW 5 DIS_LONG PHS0,RW 4 3 2 1 0 DIS_CRC ALL RUNT PRMSC RXEN PHS0,RW PHS0,RW PHS0,RW PHS0,RW PHS0,RW 6.7 RX Status Register ( 06H ) Bit Name Default 7 RF PHS0,RO 6 MF PHS0,RO 5 LCS PHS0,RO 4 RWTO PHS0,RO 3 PLE PHS0,RO 2 AE PHS0,RO 1 CE PHS0,RO 0 FOE PHS0,RO Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 Description Reserved Watchdog Timer Disable When set, the Watchdog Timer (2048 bytes) is disabled. Otherwise it is enabled Discard Long Packet Packet length is over 1522byte Discard CRC Error Packet Pass All Multicast Pass Runt Packet Promiscuous Mode RX Enable Description Runt Frame It is set to indicate that the size of the received frame is smaller than 64 bytes Multicast Frame It is set to indicate that the received frame has a multicast address Late Collision Seen It is set to indicate that a late collision is found during the frame reception Receive Watchdog Time-Out It is set to indicate that it receives more than 2048 bytes Physical Layer Error It is set to indicate that a physical layer error is found during the frame reception Alignment Error It is set to indicate that the received frame ends with a non-byte boundary CRC Error It is set to indicate that the received frame ends with a CRC error FIFO Overflow Error It is set to indicate that a FIFO overflow error happens during the frame reception 15 DM9008AEP Ethernet Controller with General Processor Interface 6.8 Receive Overflow Counter Register ( 07H ) Bit Name Default Description Receive Overflow Counter Overflow 7 RXFU PHS0,R/C This bit is set when the ROC has an overflow condition Receive Overflow Counter 6:0 ROC PHS0,R/C This is a statistic counter to indicate the received packet count upon FIFO overflow 6.9 Back Pressure Threshold Register (08H) Bit Name Default Description Back Pressure High Water Overflow Threshold. MAC will generate the jam pattern when RX SRAM free space is lower than this threshold value PHS3, 7:4 BPHW RW The default is 3K-byte free space. Please do not exceed SRAM size (1 unit=1K bytes) Jam Pattern Time. Default is 200us bit3 bit2 bit1 bit0 time 0 0 0 0 5us 0 0 0 1 10us 0 0 1 0 15us 0 0 1 1 25us 0 1 0 0 50us 0 1 0 1 100us PHS7, 0 1 1 0 150us 3:0 JPT RW 0 1 1 1 200us 1 0 0 0 250us 1 0 0 1 300us 1 0 1 0 350us 1 0 1 1 400us 1 1 0 0 450us 1 1 0 1 500us 1 1 1 0 550us 1 1 1 1 600us 6.10 Flow Control Threshold Register ( 09H ) Bit Name Default Description RX FIFO High Water Overflow Threshold Send a pause packet with pause_ time=FFFFH when the RX RAM free space is PHS3, less than this value., If this value is zero, its means no free RX SRAM space. The 7:4 HWOT RW default value is 3K-byte free space. Please do not exceed SRAM size (1 unit=1K bytes) RX FIFO Low Water Overflow Threshold Send a pause packet with pause_time=0000 when RX SRAM free space is larger PHS8, than this value. This pause packet is enabled after the high water pause packet is 3:0 LWOT RW transmitted. The default SRAM free space is 8K-byte. Please do not exceed SRAM size (1 unit=1K bytes) Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 16 DM9008AEP Ethernet Controller with General Processor Interface 6.11 RX/TX Flow Control Register ( 0AH ) Bit Name Default Description TX Pause Packet 7 TXP0 HPS0,RW Auto clears after pause packet transmission completion. Set to TX pause packet with time = 0000h TX Pause packet 6 TXPF HPS0,RW Auto clears after pause packet transmission completion. Set to TX pause packet with time = FFFFH Force TX Pause Packet Enable 5 TXPEN HPS0,RW Enables the pause packet for high/low water threshold control Back Pressure Mode 4 BKPA HPS0,RW This mode is for half duplex mode only. It generates a jam pattern when any packet comes and RX SRAM is over BPHW of register 8. Back Pressure Mode 3 BKPM HPS0,RW This mode is for half duplex mode only. It generates a jam pattern when a packet’s DA matches and RX SRAM is over BPHW of register 8. 2 RXPS HPS0,R/C RX Pause Packet Status, latch and read clearly 1 RXPCS HPS0,RO RX Pause Packet Current Status Flow Control Enable 0 FLCE HPS0,RW Set to enable the flow control mode (i.e. can disable DM9008A TX function) 6.12 EEPROM & PHY Control Register ( 0BH ) Bit Name Default Description 7:6 RESERVED 0,RO Reserved 5 REEP PH0,RW Reload EEPROM. Driver needs to clear it up after the operation completes 4 WEP PH0,RW Write EEPROM Enable EEPROM or PHY Operation Select 3 EPOS PH0,RW When reset, select EEPROM; when set, select PHY EEPROM Read or PHY Register Read Command. Driver needs to clear it up after 2 ERPRR PH0,RW the operation completes. EEPROM Write or PHY Register Write Command. Driver needs to clear it up after 1 ERPRW PH0,RW the operation completes. EEPROM Access Status or PHY Access Status 0 ERRE PH0,RO When set, it indicates that the EEPROM or PHY access is in progress 6.13 EEPROM & PHY Address Register ( 0CH ) Bit Name Default Description PHY Address bit 1 and 0, the PHY address bit [4:2] is force to 0. Force to 01 in 7:6 PHY_ADR PH01,RW application. 5:0 EROA PH0,RW EEPROM Word Address or PHY Register Number. 6.14 EEPROM & PHY Data Register (EE_PHY_L：0DH EE_PHY_H：0EH) Bit Name Default Description EEPROM or PHY Low Byte Data 7:0 EE_PHY_L PH0,RW The low-byte data read from or write to EEPROM or PHY. EEPROM or PHY High Byte Data 7:0 EE_PHY_H PH0,RW The high-byte data read from or write to EEPROM or PHY. Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 17 DM9008AEP Ethernet Controller with General Processor Interface 6.15 Wake Up Control Register ( 0FH ) (in 8-bit mode) Bit Name Type Description Reserved 7:6 RESERVED 0,RO When set, it enables Link Status Change Wake up Event 5 LINKEN P0,RW This bit will not be affected after software reset When set, it enables Sample Frame Wake up Event 4 SAMPLEEN P0,RW This bit will not be affected after software reset When set, it enables Magic Packet Wake up Event 3 MAGICEN P0,RW This bit will not be affected after software reset When set, it indicates that Link Change and Link Status Change Event occurred 2 LINKST P0,RO This bit will not be affected after software reset When set, it indicates that the sample frame is received and Sample Frame Event 1 SAMPLEST P0,RO occurred. This bit will not be affected after software reset When set, indicates the Magic Packet is received and Magic packet Event 0 MAGICST P0,RO occurred. This bit will not be affected after a software reset 6.16 Physical Address Register ( 10H~15H ) Bit Name Default 7:0 PAB5 E,RW Physical Address Byte 5 7:0 PAB4 E,RW Physical Address Byte 4 7:0 PAB3 E,RW Physical Address Byte 3 7:0 PAB2 E,RW Physical Address Byte 2 7:0 PAB1 E,RW Physical Address Byte 1 7:0 PAB0 E,RW Physical Address Byte 0 (15H) (14H) (13H) (12H) (11H) (10H) 6.17 Multicast Address Register ( 16H~1DH ) Bit Name Default 7:0 MAB7 X,RW Multicast Address Byte 7 7:0 MAB6 X,RW Multicast Address Byte 6 7:0 MAB5 X,RW Multicast Address Byte 5 7:0 MAB4 X,RW Multicast Address Byte 4 7:0 MAB3 X,RW Multicast Address Byte 3 7:0 MAB2 X,RW Multicast Address Byte 2 7:0 MAB1 X,RW Multicast Address Byte 1 7:0 MAB0 X,RW Multicast Address Byte 0 (1DH) (1CH) (1BH) (1AH) (19H) (18H) (17H) (16H) Description Description 6.18 General purpose control Register ( 1EH ) (in 8-bit mode) Bit Name Default Description 7 RESERVED PH0,RO Reserved General Purpose Control 6~4 PH, 6:4 GPC64 Define the input/output direction of pins GP6~4 respectively. 111,RO These bits are all forced to “1”s, so pins GP6~4 are output only. General Purpose Control 3~1 PH, Define the input/output direction of pins GP 3~1 respectively. 3:1 GPC31 000,RW When a bit is set 1, the direction of correspondent bit of General Purpose Register is output. Other defaults are input 0 RESERVED PH1,RO Reserved Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 18 DM9008AEP Ethernet Controller with General Processor Interface 6.19 General purpose Register ( 1FH ) Bit Name Default Description 7 RESERVED 0,RO Reserved General Purpose Output 6~4 (in 8-bit mode) 6-4 GPO PH0,RW These bits are reflect to pin GP6~4 respectively. General Purpose (in 8-bit mode) When the correspondent bit of General Purpose Control Register is 1, the value of PH0,RW the bit is reflected to pin GP3~1 respectively. 3:1 GPIO When the correspondent bit of General Purpose Control Register is 0, the value of the bit to be read is reflected from correspondent pins of GP3~1 respectively. PHY Power Down Control 0 PHYPD 1,WO 1: power down PHY 0: power up PHY 6.20 TX SRAM Read Pointer Address Register (22H~23H) Bit Name Default Description 7:0 TRPAH PS0,RO TX SRAM Read Pointer Address High Byte (23H) 7:0 TRPAL PS0.RO TX SRAM Read Pointer Address Low Byte (22H) 6.21 RX SRAM Write Pointer Address Register (24H~25H) Bit Name Default Description 7:0 RWPAH PS,0CH,RO RX SRAM Write Pointer Address High Byte (25H) 7:0 RWPAL PS,00H.RO RX SRAM Write Pointer Address Low Byte (24H) 6.22 Vendor ID Register (28H~29H) Bit Name Default 7:0 VIDH PHE,0AH,RO Vendor ID High Byte (29H) 7:0 VIDL PHE,46H.RO Vendor ID Low Byte (28H) 6.23 Product ID Register (2AH~2BH) Bit Name Default 7:0 PIDH PHE,90H,RO Product ID High Byte (2BH) 7:0 PIDL PHE,00H.RO Product ID Low Byte (2AH) 6.24 Chip Revision Register (2CH) Bit Name Default 7:0 CHIPR P,19H,RO CHIP Revision Description Description Description 6.25 Transmit Control Register 2 ( 2DH ) Bit Name Default Description Led Mode 7 LED PH0,RW When set, the LED pins act as led mode 1. When cleared, the led mode is default mode 0 or depending EEPROM setting. Retry Late_Collision Packet 6 RLCP PH0,RW Re-transmit the packet with late-collision Disable TX Underrun Retry 5 DTU PH0,RW Disable to re-transmit the underruned packet Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 19 DM9008AEP Ethernet Controller with General Processor Interface 4 ONEPM PH0,RW 3~0 IFGS PH0,RW One Packet Mode When set, only one packet transmit command can be issued before transmit completed. When cleared, at most two packet transmit command can be issued before transmit completed. Inter-Frame Gap Setting 0XXX: 96-bit 1000: 64-bit 1001: 72-bit 1010:80-bit 1011:88-bit 1100:96-bit 1101:104-bit 1110: 112-bit 1111:120-bit 6.26 Operation Test Control Register ( 2EH ) Bit Name Default Description System Clock Control Set the internal system clock. 00: 50Mhz 7~6 SCC PH0,RW 01: 20MHz 10: 100MHz 11: Reserved 5 RESERVED PH0,RW Reserved 4 SOE PH0,RW Internal SRAM Output-Enable Always ON 3 SCS PH0,RW Internal SRAM Chip-Select Always ON 2~0 PHYOP PH0,RW Internal PHY operation mode for testing 6.27 Special Mode Control Register ( 2FH ) Bit Name Default 7 SM_EN PH0,RW Special Mode Enable 6~3 RESERVED PH0,RW Reserved 2 FLC PH0,RW Force Late Collision 1 FB1 PH0,RW Force Longest Back-off time 0 FB0 PH0,RW Force Shortest Back-off time Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 Description 20 DM9008AEP Ethernet Controller with General Processor Interface 6.28 Early Transmit Control/Status Register ( 30H ) Bit Name Default Description Early Transmit Enable 7 ETE HPS0, RW Enable bits[2:0] 6 ETS2 HPS0,RO Early Transmit Status II 5 ETS1 HPS0,RO Early Transmit Status I 4~2 RESERVED 000,RO Reserved Early Transmit Threshold Start transmit when data write to TX FIFO reach the byte-count threshold 1~0 ETT HPS0,RW Bit-1 bit-0 ----- ---0 0 0 1 1 0 1 1 threshold ------------: 12.5% : 25% : 50% : 75% 6.29 Check Sum Control Register ( 31H ) Bit Name Default Description 7~3 RESERVED 0,RO Reserved 2 UDPCSE HPS0,RW UDP CheckSum Generation Enable 1 TCPCSE HPS0,RW TCP CheckSum Generation Enable 0 IPCSE HPS0,RW IP CheckSum Generation Enable 6.30 Receive Check Sum Status Register ( 32H ) Bit Name Default Description UDP CheckSum Status 7 UDPS HPS0,RO 1: checksum fail, if UDP packet TCP CheckSum Status 6 TCPS HPS0,RO 1: checksum fail, if TCP packet IP CheckSum Status 5 IPS HPS0,RO 1: checksum fail, if IP packet 4 UDPP HPS0,RO UDP Packet 3 TCPP HPS0,RO TCP Packet 2 IPP HPS0,RO IP Packet Receive CheckSum Checking Enable 1 RCSEN HPS0,RW When set, the checksum status (bit 7~2) will be stored in packet’s first byte(bit 7~2) of status header respectively. Discard CheckSum Error Packet 0 DCSE HPS0,RW When set, if IP/TCP/UDP checksum field is error, this packet will be discarded. 6.31 LED Pin Control Register ( 34H ) Bit Name Default Description 7:2 Reserved PS0,RO Reserved LED act as General Purpose signals in 16-bit mode 1 GPIO P0,RW 1: Pin 38/39 (LED2/1) act as the general purpose pins that are controlled by registers 1Eh bit 2/1 and 1Fh bit 2/1 respectively. Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 21 DM9008AEP Ethernet Controller with General Processor Interface 0 MII P0,RW LED act as SMI signals in 16-bit mode 1: Pin 38/39 (LED2/1) act as the MII Management Interface mode. In this mode, the LED1 act as data (MDIO) signal and the LED2 act as sourced clock (MDC) signal. These two pin are controlled by registers 0Bh,0Ch, and 0Dh. 6.32 Processor Bus Control Register ( 38H ) Bit Name Default Description Data Bus Current Driving/Sinking Capability 000: 2mA 001: 4mA 010: 6mA 7:5 CURR P011,RO 011: 8mA (default) 100: 10mA 101: 12mA 110: 14mA 111: 16mA 4 Reserved P0,RW Reserved Enable Schmitt Trigger 3 GPIO P0,RW 1: Pin 35/36/37 (IOR/IOW/CS#) have Schmitt trigger capability. 2 Reserved P0,RW Reserved Eliminate IOW spike 1 IOW_SPIKE P0,RW 1: eliminate about 2ns IOW spike Eliminate IOR spike 0 IOR_SPIKE P1,RW 1: eliminate about 2ns IOR spike Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 22 DM9008AEP Ethernet Controller with General Processor Interface 6.33 INT Pin Control Register ( 39H ) Bit Name Default 7:2 Reserved PS0,RO Reserved INT Pin Output Type Control 1 INT_TYPE PET0,RW 1: INT Open-Collector output 0: INT direct output INT Pin Polarity Control 0 INT_POL PET0,RW 1: INT active low 0: INT active high Description 6.34 System Clock Turn ON Control Register ( 50H ) Bit Name Default Description 7:1 Reserved Reserved Stop Internal System Clock 0 DIS_CLK P0,W 1: internal system clock turn off, internal PHYceiver also power down 0: internal system clock is ON 6.35 Resume System Clock Control Register ( 51H ) When the INDEX port set to 51H, the internal system clock is turn ON. Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 23 DM9008AEP Ethernet Controller with General Processor Interface 6.36 Memory Data Pre-Fetch Read Command without Address Increment Register (F0H) Bit Name Default Description Read data from RX SRAM. After the read of this command, the read pointer of 7:0 MRCMDX X,RO internal SRAM is unchanged. And the DM9008A starts to pre-fetch the SRAM data to internal data buffers. 6.37 Memory Data Read Command without Address Increment Register (F1H) Bit Name Default Description Read data from RX SRAM. After the read of this command, the read pointer of 7:0 MRCMDX1 X,RO internal SRAM is unchanged 6.38 Memory Data Read Command with Address Increment Register (F2H) Bit Name Default Description Read data from RX SRAM. After the read of this command, the read pointer is 7:0 MRCMD X,RO increased by 1or 2 depends on the operator mode (8-bit or16-bit respectively) 6.39 Memory Data Read_address Register (F4H~F5H) Bit Name Default Description 7:0 MDRAH PHS0,RW Memory Data Read_ address High Byte. It will be set to 0Ch, when IMR bit7 =1 7:0 MDRAL PHS0,RW Memory Data Read_ address Low Byte 6.40 Memory Data Write Command without Address Increment Register (F6H) Bit Name Default Description Write data to TX SRAM. After the write of this command, the write pointer is 7:0 MWCMDX X,WO unchanged 6.41 Memory data write command with address increment Register (F8H) Bit Name Default Description Write Data to TX SRAM 7:0 MWCMD X,WO After the write of this command, the write pointer is increased by 1 or 2, depends on the operator mode. (8-bit or 16-bit respectively) 6.42 Memory data write_address Register (FAH~FBH) Bit Name Default Description 7:0 MDRAH PHS0,RW Memory Data Write_ address High Byte 7:0 MDRAL PHS0,RW Memory Data Write_ address Low Byte 6.43 TX Packet Length Register (FCH~FDH) Bit Name Default 7:0 TXPLH X,R/W TX Packet Length High byte 7:0 TXPLL X,,R/W TX Packet Length Low byte Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 Description 24 DM9008AEP Ethernet Controller with General Processor Interface 6.44 Interrupt Status Register (FEH) Bit Name Default 7 IOMODE T0, RO 6 5 4 3 2 1 0 RESERVED LNKCHG UDRUN ROO RO PT PR RO PHS0,RW/C1 PHS0,RW/C1 PHS0,RW/C1 PHS0,RW/C1 PHS0,RW/C1 PHS0,RW/C1 6.45 Interrupt Mask Register (FFH) Bit Name Default 7 PAR HPS0,RW 6 5 4 3 2 1 0 RESERVED LNKCHGI UDRUNI ROOI ROI PTI PRI RO PHS0,RW PHS0,RW PHS0,RW PHS0,RW PHS0,RW PHS0,RW Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 Description 0: 16-bit mode 1: 8-bit mode Reserved Link Status Change Transmit Underrun Receive Overflow Counter Overflow Receive Overflow Packet Transmitted Packet Received Description Enable the SRAM read/write pointer to automatically return to the start address when pointer addresses are over the SRAM size. Driver needs to set. When driver sets this bit, REG_F5 will set to 0Ch automatically Reserved Enable Link Status Change Interrupt Enable Transmit Underrun Interrupt Enable Receive Overflow Counter Overflow Interrupt Enable Receive Overflow Interrupt Enable Packet Transmitted Interrupt Enable Packet Received Interrupt 25 DM9008AEP Ethernet Controller with General Processor Interface 7. EEPROM Format name MAC address Word 0 Auto Load Control 3 Vendor ID Product ID 4 5 pin control 6 Wake-up mode control 7 Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 offset Description 0~5 6 Byte Ethernet Address Bit 1:0=01: Update vendor ID and product ID Bit 3:2=01: Accept setting of WORD6 [8:0] Bit 5:4=01: reserved Bit 7:6=01: Accept setting of WORD7 [3:0] (in 8-bit mode) 6-7 Bit 9:8=01: reserved Bit 11:10=01: Accept setting of WORD7 [7] Bit 13:12=01: Accept setting of WORD7 [8] Bit 15:14=01: Accept setting of WORD7 [15:12] 8-9 2 byte vendor ID (Default: 0A46H) 10-11 2 byte product ID (Default: 9000H) When word 3 bit [3:2]=01, these bits can control the CS#, IOR#, IOW# and INT pins polarity. Bit0: CS# pin is active low when set (default active low) Bit1: IOR# pin is active low when set (default: active low) 12-13 Bit2: IOW# pin is active low when set (default: active low) Bit3: INT pin is active low when set (default: active high) Bit4: INT pin is open-collected (default: force output) Bit 15:5: Reserved Bit0: The WAKEUP pin is active low when set (default: active high) Bit1: The WAKEUP pin is in pulse mode when set (default: level mode) Bit2: magic wakeup event is enabled when set. (default: disable) Bit3: link_change wakeup event is enabled when set (default: disable) Bit6:4: reserved Bit7: LED mode 1 (default: 0) 14-15 Bit8: internal PHY is enabled after power-on (default: disable) Bit11:9: reserved Bit13:12: 01 = LED2 act as IOWAIT in 16-bit mode Bit13:12: 10 = LED2 act as WAKE in 16-bit mode Bit14: 1: HP Auto-MDIX ON, 0: HP Auto-MDIX OFF(default ON) Bit 15: LED1 act as IO16 in 16-bit mode 26 DM9008AEP Ethernet Controller with General Processor Interface 8. MII Register Description ADD Name 15 00 CONTR Reset OL 0 01 STATUS T4 Cap. 0 02 PHYID1 0 03 PHYID2 1 14 Loop back 0 TX FDX Cap. 1 0 0 13 12 11 Speed Auto-N Power select Enable Down 1 1 0 TX HDX 10 FDX 10 HDX Cap. Cap. Cap. 1 1 1 0 0 0 1 1 1 04 Auto-Neg. Next Advertise Page 05 Link Part. LP Ability Next Page 06 Auto-Neg. Expansio n 16 Specifie d Config. 17 Specifie d Conf/Stat 18 10T Rsvd Conf/Stat FLP Rcv Ack LP Ack Remote Fault LP RF Reserved Reserved 10 Isolate 0 9 8 Restart Full Auto-N Duplex 0 1 Reserved 0000 0 0 0 FC Adv LP FC T4 Adv LP T4 1 7 Coll. Test 0 6 5 4 Pream. Supr. 1 0 Auto-N Compl. 0 0 Remote Fault 0 0 1 Model No. 01010 TX FDX TX HDX 10 FDX 10 HDX Adv Adv Adv Adv LP LP LP LP TX FDX TX HDX 10 FDX 10 HDX LP Enable HBE Enable SQUE Enable LP Next Pg Able Next Pg Able RPDCTR Reset -EN St. Mch Pream. Supr. PHY ADDR [4:0] JAB Enable Reserve d 1 000_0000 Auto-N Link Jabber Cap. Status Detect 1 0 0 0 0 0 Version No. 0000 Advertised Protocol Selector Field Pardet Fault Reserved 2 0 Extd Cap. 1 1 Link Partner Protocol Selector Field Reserved Reversed 3 Reserved New Pg LP AutoN Rcv Cap. Sleep mode Remote LoopOut Auto-N. Monitor Bit [3:0] Reserved Polarity Reverse Key to Default In the register description that follows, the default column takes the form: <Reset Value>, <Access Type> / <Attribute(s)> Where： <Reset Value>: 1 Bit set to logic one 0 Bit set to logic zero X No default value RO = Read only RW = Read/Write <Attribute (s)>: SC = Self clearing P = Value permanently set LL = Latching low LH = Latching high <Access Type>: 8.1 Basic Mode Control Register (BMCR) - 00 Bit 0.15 Bit Name Reset Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 Default Description 0, RW/SC Reset 1=Software reset 0=Normal operation This bit sets the status and controls the PHY registers to their default states. This bit, which is self-clearing, will keep 27 DM9008AEP Ethernet Controller with General Processor Interface returning a value of one until the reset process is completed 0.14 0.13 0.12 0.11 0.10 0.9 0.8 0.7 Loopback Loopback Loop-back control register 1 = Loop-back enabled 0 = Normal operation Speed selection 1, RW Speed Select 1 = 100Mbps 0 = 10Mbps Link speed may be selected either by this bit or by auto-negotiation. When auto-negotiation is enabled and bit 12 is set, this bit will return auto-negotiation selected medium type Auto-negotiatio 1, RW Auto-negotiation Enable n enable 1 = Auto-negotiation is enabled, bit 8 and 13 will be in auto-negotiation status Power down 0, RW Power Down While in the power-down state, the PHY should respond to management transactions. During the transition to power-down state and while in the power-down state, the PHY should not generate spurious signals on the MII 1=Power down 0=Normal operation Isolate 0,RW Isolate Force to 0 in application. Restart 0,RW/SC Restart Auto-negotiation Auto-negotiation 1 = Restart auto-negotiation. Re-initiates the auto-negotiation process. When auto-negotiation is disabled (bit 12 of this register cleared), this bit has no function and it should be cleared. This bit is self-clearing and it will keep returning to a value of 1 until auto-negotiation is initiated by the DM9008A. The operation of the auto-negotiation process will not be affected by the management entity that clears this bit 0 = Normal operation Duplex mode 1,RW Duplex Mode 1 = Full duplex operation. Duplex selection is allowed when Auto-negotiation is disabled (bit 12 of this register is cleared). With auto-negotiation enabled, this bit reflects the duplex capability selected by auto-negotiation 0 = Normal operation Collision test 0,RW Collision Test 1 = Collision test enabled. When set, this bit will cause the COL signal to be asserted in response to the assertion of TX_EN in internal MII interface. Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 0, RW 28 DM9008AEP Ethernet Controller with General Processor Interface 0.6-0.0 Reserved 0,RO 0 = Normal operation Reserved Read as 0, ignore on write 8.2 Basic Mode Status Register (BMSR) - 01 Bit 1.15 Bit Name 100BASE-T4 1.14 100BASE-TX full-duplex 100BASE-TX half-duplex 10BASE-T full-duplex 1.13 1.12 1.11 10BASE-T half-duplex 1.10-1.7 Reserved 1.6 MF preamble suppression 1.5 Auto-negotiation Complete 1.4 Remote fault 1.3 Auto-negotiation ability Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 Default 0,RO/P Description 100BASE-T4 Capable The DM9008A is not support 100BASE-T4 mode. 1,RO/P 100BASE-TX Full Duplex Capable The DM9008A is not support 100BASE-TX full duplex mode. 1,RO/P 100BASE-TX Half Duplex Capable The DM9008A is not support 100BASE-TX half duplex mode 1,RO/P 10BASE-T Full Duplex Capable 1 = DM9008A is able to perform 10BASE-T in full duplex mode 0 = DM9008A is not able to perform 10BASE-TX in full duplex mode 1,RO/P 10BASE-T Half Duplex Capable 1 = DM9008A is able to perform 10BASE-T in half duplex mode 0 = DM9008A is not able to perform 10BASE-T in half duplex mode 0,RO Reserved Read as 0, ignore on write 1,RO MII Frame Preamble Suppression 1 = PHY will accept management frames with preamble suppressed 0 = PHY will not accept management frames with preamble suppressed 0,RO Auto-negotiation Complete 1 = Auto-negotiation process completed 0 = Auto-negotiation process not completed 0, RO/LH Remote Fault 1 = Remote fault condition detected (cleared on read or by a chip reset). Fault criteria and detection method is DM9008A implementation specific. This bit will set after the RF bit in the ANLPAR (bit 13, register address 05) is set 0 = No remote fault condition detected 1,RO/P Auto Configuration Ability 1 = DM9008A is able to perform auto-negotiation 0 = DM9008A is not able to perform auto-negotiation 29 DM9008AEP Ethernet Controller with General Processor Interface 1.2 Link status 1.1 Jabber detect 1.0 Extended capability 0,RO/LL Link Status 1 = Valid link is established 0 = Link is not established The link status bit is implemented with a latching function, so that the occurrence of a link failure condition causes the link status bit to be cleared and remain cleared until it is read via the management interface 0, RO/LH Jabber Detect 1 = Jabber condition detected 0 = No jabber This bit is implemented with a latching function. Jabber conditions will set this bit unless it is cleared by a read to this register through a management interface or a DM9008A reset. Extended Capability 1,RO/P 1 = Extended register capable 0 = Basic register capable only 8.3 PHY ID Identifier Register #1 (PHYID1) - 02 The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9008A. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a model revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E. Bit 2.15-2.0 Bit Name OUI_MSB Default <0181h> Description OUI Most Significant Bits This register stores bit 3 to 18 of the OUI (00606E) to bit 15 to 0 of this register respectively. The most significant two bits of the OUI are ignored (the IEEE standard refers to these as bit 1 and 2) 8.4 PHY ID Identifier Register #2 (PHYID2) - 03 Bit 3.15-3.1 0 Bit Name OUI_LSB 3.9-3.4 VNDR_MDL 3.3-3.0 MDL_REV Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 Default Description <101110>, OUI Least Significant Bits RO/P Bit 19 to 24 of the OUI (00606E) are mapped to bit 15 to 10 of this register respectively <001010>, Vendor Model Number RO/P Five bits of vendor model number mapped to bit 9 to 4 (most significant bit to bit 9) <0000>, Model Revision Number RO/P Five bits of vendor model revision number mapped to bit 3 to 0 (most significant bit to bit 4) 30 DM9008AEP Ethernet Controller with General Processor Interface 8.5 Auto-negotiation Advertisement Register (ANAR) - 04 This register contains the advertised abilities of this DM9008A device as they will be transmitted to its link partner during Auto-negotiation. Bit 4.15 Bit Name NP Default 0,RO/P 4.14 ACK 0,RO 4.13 RF 0, RW 4.12-4.1 1 4.10 Reserved X, RW FCS 0, RW 4.9 T4 0, RO/P 4.8 TX_FDX 1, RW 4.7 TX_HDX 1, RW 4.6 10_FDX 1, RW 4.5 10_HDX 1, RW 4.4-4.0 Selector <00001>, RW Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 Description Next page Indication 0 = No next page available 1 = Next page available The DM9008A has no next page, so this bit is permanently set to 0 Acknowledge 1 = Link partner ability data reception acknowledged 0 = Not acknowledged The DM9008A's auto-negotiation state machine will automatically control this bit in the outgoing FLP bursts and set it at the appropriate time during the auto-negotiation process. Software should not attempt to write to this bit. Remote Fault 1 = Local device senses a fault condition 0 = No fault detected Reserved Write as 0, ignore on read Flow Control Support 1 = Controller chip supports flow control ability 0 = Controller chip doesn’t support flow control ability 100BASE-T4 Support 100BASE-T4 is not supported by DM9008A. 100BASE-TX Full Duplex Support 100BASE-TX full duplex is not supported by DM9008A. 100BASE-TX Support 100BASE-TX half duplex is not supported by DM9008A. 10BASE-T Full Duplex Support 1 = 10BASE-T full duplex is supported by the local device 0 = 10BASE-T full duplex is not supported 10BASE-T Support 1 = 10BASE-T half duplex is supported by the local device 0 = 10BASE-T half duplex is not supported Protocol Selection Bits These bits contain the binary encoded protocol selector supported by this node <00001> indicates that this device supports IEEE 802.3 CSMA/CD 31 DM9008AEP Ethernet Controller with General Processor Interface 8.6 Auto-negotiation Link Partner Ability Register (ANLPAR) – 05 This register contains the advertised abilities of the link partner when received during Auto-negotiation. Bit 5.15 Bit Name NP Default 0, RO 5.14 ACK 0, RO 5.13 RF 0, RO 5.12-5.1 1 5.10 Reserved 0, RO FCS 0, RO 5.9 T4 0, RO 5.8 TX_FDX 0, RO 5.7 TX_HDX 0, RO 5.6 10_FDX 0, RO 5.5 10_HDX 0, RO Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 Description Next Page Indication 0 = Link partner, no next page available 1 = Link partner, next page available Acknowledge 1 = Link partner ability data reception acknowledged 0 = Not acknowledged The DM9008A's auto-negotiation state machine will automatically control this bit from the incoming FLP bursts. Software should not attempt to write to this bit Remote Fault 1 = Remote fault indicated by link partner 0 = No remote fault indicated by link partner Reserved Read as 0, ignore on write Flow Control Support 1 = Controller chip supports flow control ability by link partner 0 = Controller chip doesn’t support flow control ability by link partner 100BASE-T4 Support 1 = 100BASE-T4 is supported by the link partner 0 = 100BASE-T4 is not supported by the link partner 100BASE-TX Full Duplex Support 1 = 100BASE-TX full duplex is supported by the link partner 0 = 100BASE-TX full duplex is not supported by the link partner 100BASE-TX Support 1 = 100BASE-TX half duplex is supported by the link partner 0 = 100BASE-TX half duplex is not supported by the link partner 10BASE-T Full Duplex Support 1 = 10BASE-T full duplex is supported by the link partner 0 = 10BASE-T full duplex is not supported by the link partner 10BASE-T Support 1 = 10BASE-T half duplex is supported by the link partner 0 = 10BASE-T half duplex is not supported by the link 32 DM9008AEP Ethernet Controller with General Processor Interface 5.4-5.0 Selector <00000>, RO partner Protocol Selection Bits Link partner’s binary encoded protocol selector 8.7 Auto-negotiation Expansion Register (ANER)- 06 Bit 6.15-6.5 Bit Name Reserved Default 0, RO 6.4 PDF 0, RO/LH 6.3 LP_NP_ABL E 0, RO 6.2 NP_ABLE 0,RO/P 6.1 PAGE_RX 0, RO/LH 6.0 LP_AN_ABL E 0, RO Description Reserved Read as 0, ignore on write Local Device Parallel Detection Fault PDF = 1: A fault detected via parallel detection function. PDF = 0: No fault detected via parallel detection function Link Partner Next Page Able LP_NP_ABLE = 1: Link partner, next page available LP_NP_ABLE = 0: Link partner, no next page Local Device Next Page Able NP_ABLE = 1: DM9008A, next page available NP_ABLE = 0: DM9008A, no next page DM9008A does not support this function, so this bit is always 0 New Page Received A new link code word page received. This bit will be automatically cleared when the register (register 6) is read by management Link Partner Auto-negotiation Able A “1” in this bit indicates that the link partner supports Auto-negotiation 8.8 DAVICOM Specified Configuration Register (DSCR) – 16 Bit Bit Name Default 16.15 BP_4B5B 0,RW Description Bypass 4B5B Encoding and 5B4B Decoding 1 = 4B5B encoder and 5B4B decoder function bypassed 0 = Normal 4B5B and 5B4B operation 16.14 BP_SCR 0, RW Bypass Scrambler/Descrambler Function 1 = Scrambler and descrambler function bypassed 0 = Normal scrambler and descrambler operation 16.13 BP_ALIGN 0, RW Bypass Symbol Alignment Function 1 = Receive functions (descrambler, symbol alignment and symbol decoding functions) bypassed. Transmit functions (symbol encoder and scrambler) bypassed Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 33 DM9008AEP Ethernet Controller with General Processor Interface 0 = Normal operation 16.12 BP_ADPOK 0, RW BYPASS ADPOK Force signal detector (SD) active. This register is for debug only, not release to customer 1=Forced SD is OK, 0=Normal operation 16.11 Reserved 0, RW Reserved Force to 0 in application. 16.10 TX/FX 1, RW 100BASE-TX/FX Mode Control 1 = 100BASE-TX operation 0 = 100BASE-FX operation 16.9 Reserved 0, RO Reserved 16.8 Reserved 0, RW Reserved Force to 0 in application. 16.7 F_LINK_100 0, RW Force Good Link in 100Mbps 0 = Normal 100Mbps operation 1 = Force 100Mbps good link status This bit is useful for diagnostic purposes 16.6 SPLED_CTL 0, RW Reserved 16.5 COLLED_CT L 0, RW Force to 0 in application. Reserved Force to 0 in application. 16.4 RPDCTR-EN 1, RW Reduced Power Down Control Enable This bit is used to enable automatic reduced power down 0 = Disable automatic reduced power down 1 = Enable automatic reduced power down 16.3 SMRST 0, RW Reset State Machine When writes 1 to this bit, all state machines of PHY will be reset. This bit is self-clear after reset is completed 16.2 MFPSC 1, RW MF Preamble Suppression Control Frame preamble suppression control bit 1 = MF preamble suppression bit on 0 = MF preamble suppression bit off Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 34 DM9008AEP Ethernet Controller with General Processor Interface 16.1 SLEEP 0, RW Sleep Mode Writing a 1 to this bit will cause PHY entering the Sleep mode and power down all circuit except oscillator and clock generator circuit. When waking up from Sleep mode (write this bit to 0), the configuration will go back to the state before sleep; but the state machine will be reset 16.0 RLOUT 0, RW Remote Loopout Control When this bit is set to 1, the received data will loop out to the transmit channel. This is useful for bit error rate testing 8.9 DAVICOM Specified Configuration and Status Register (DSCSR) - 17 Bit 17.1517.12 17.1117.9 17.817.4 17.317.0 Bit Name RESERV ED Reserved Default 1111, RO Description Reserved 0, RO Reserved Read as 0, ignore on write PHYADR (PHYADR), PHY Address Bit 4:0 [4:0] RW The first PHY address bit transmitted or received is the MSB of the address (bit 4). A station management entity connected to multiple PHY entities must know the appropriate address of each PHY ANMB[3: 0, RO Auto-negotiation Monitor Bits 0] These bits are for debug only. The auto-negotiation status will be written to these bits. B3 0 0 0 0 0 0 0 0 Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 In IDLE state Ability match Acknowledge match Acknowledge match fail Consistency match Consistency match fail Parallel detects signal_link_ready Parallel detects signal_link_ready fail 35 DM9008AEP Ethernet Controller with General Processor Interface 8.10 10BASE-T Configuration/Status (10BTCSR) - 18 Bit 18.15 Bit Name Reserved Default 0, RO 18.14 LP_EN 1, RW 18.13 HBE 1,RW 18.12 SQUELCH 1, RW 18.11 JABEN 1, RW 18.10 Reserved 0, RW 18.918.1 18.0 Reserved 0, RO POLR 0, RO Description Reserved Read as 0, ignore on write Link Pulse Enable 1 = Transmission of link pulses enabled 0 = Link pulses disabled, good link condition forced This bit is valid only in 10Mbps operation Heartbeat Enable 1 = Heartbeat function enabled 0 = Heartbeat function disabled When the DM9008A is configured for full duplex operation, this bit will be ignored (the collision/heartbeat function is invalid in full duplex mode) Squelch Enable 1 = Normal squelch 0 = Low squelch Jabber Enable Enables or disables the Jabber function when the DM9008A is in 10BASE-T full duplex or 10BASE-T transceiver Loopback mode 1 = Jabber function enabled 0 = Jabber function disabled Reserved Force to 0, in application. Reserved Read as 0, ignore on write Polarity Reversed When this bit is set to 1, it indicates that the 10Mbps cable polarity is reversed. This bit is automatically set and cleared by 10BASE-T module 8.11 (Specified config) Register – 20 Bit Bit Name Default Description 20.15 TSTSE1 0,RW Vendor test select control 20.14 TSTSE2 0,RW Vendor test select control 20.13 FORCE_TXSD 0,RW Force Signal Detect 1: force SD signal OK in 100M Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 36 DM9008AEP Ethernet Controller with General Processor Interface 0: normal SD signal. 20.12 FORCE_FEF 0,RW Vendor test select control 20.11-20 Reserved 0, RO Reserved .8 20.7 Read as 0, ignore on write MDIX_CNTL MDI/MDIX, The polarity of MDI/MDIX value RO 1: MDIX mode 0: MDI 20.6 AutoNeg_lpbk 0,RW mode Auto-negotiation Loopback 1: test internal digital auto-negotiation Loopback 0: normal. 20.5 Mdix_fix 0, RW Value MDIX_CNTL force value: When Mdix_down = 1, MDIX_CNTL value depend on the register value. 20.4 Mdix_down 0,RW HP Auto-MDIX Down Manual force MDI/MDIX. 0: Enable HP Auto-MDIX 1: Disable HP Auto-MDIX , MDIX_CNTL value depend on 20.5 20.3 MonSel1 0,RW Vendor monitor select 20.2 MonSel0 0,RW Vendor monitor select 20.1 Reserved 0,RW Reserved Force to 0, in application. 20.0 PD_value 0,RW Power down control value Decision the value of each field Register 19. 1: power down 0: normal Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 37 DM9008AEP Ethernet Controller with General Processor Interface 9. Functional Description 9.1 Host Interface The host interface is a general processor local bus that using chip select (pin CS#) to access DM9008A. Pin CS# is default low active which can be re-defined by EEPROM setting. There are only two addressing ports through the access of the host interface. One port is the INDEX port and the other is the DATA port. The INDEX port is decoded by the pin CMD =0 and the DATA port by the pin CMD =1. The contents of the INDEX port are the register address of the DATA port. Before the access of any register, the address of the register must be saved in the INDEX port. 9.2 Direct Memory Access Control The DM9008A provides DMA capability to simplify the access of the internal memory. After the programming of the starting address of the internal memory and then issuing a dummy read/write command to load the current data to internal data buffer, the desired location of the internal memory can be accessed by the read/write command registers. The memory’s address will be increased with the size that equals to the current operation mode (i.e. the 8-bit or 16-bit mode) and the data of the next location will be loaded into internal data buffer automatically. It is noted that the data of the first access (the dummy read/write command) in a sequential burst should be ignored because that the data was the contents of the last read/write command. The internal memory size is 16K bytes. The first location of 3K bytes is used for the data buffer of the packet transmission. The other 13K bytes are used for the buffer of the receiving packets. So in the write memory operation, when the bit 7 of IMR is set, the memory address increment will wrap to location 0 if the end of address (i.e. 3K) is reached. In a similar way, in the read memory operation, when the bit 7 of Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 IMR is set, the memory address increment will wrap to location 0x0C00 if the end of address (i.e. 16K) is reached. 9.3 Packet Transmission There are two packets, sequentially named as index I and index II, can be stored in the TX SRAM at the same time. The index register 02h controls the insertion of CRC and pads. Their statuses are recorded at index registers 03h and 04h respectively. The start address of transmission is 00h and the current packet is index I after software or hardware reset. Firstly write data to the TX SRAM using the DMA port and then write the byte count to byte_ count register at index register 0fch and 0fdh. Set the bit 1 of control register. The DM9008A starts to transmit the index I packet. Before the transmission of the index I packet ends, the data of the next (index II) packet can be moved to TX SRAM. After the index I packet ends the transmission, write the byte count data of the index II to BYTE_COUNT register and then set the bit 1 of control register to transmit the index II packet. The following packets, named index I, II, I, II,…, use the same way to be transmitted. 9.4 Packet Reception The RX SRAM is a ring data structure. The start address of RX SRAM is 0C00h after software or hardware reset. Each packet has a 4-byte header followed with the data of the reception packet which CRC field is included. The format of the 4-byte header is 01h, status, BYTE_COUNT low, and BYTE_COUNT high. It is noted that the start address of each packet is in the proper address boundary which depends on the operation mode (the 8-bit or 16-bit ). 38 DM9008AEP Ethernet Controller with General Processor Interface 9.5 10Base-T Operation The 10Base-T transceiver is IEEE 802.3 compliant. When the DM9008A is operating in 10Base-T mode, the coding scheme is Manchester. Data processed for transmit is presented to the MII interface in nibble format, converted to a serial bit stream, then the Manchester encoded. When receiving, the bit stream, encoded by the Manchester, is decoded and converted into nibble format to present to the MII interface. 9.6 Collision Detection For half-duplex operation, a collision is detected when the transmit and receive channels are active simultaneously. When a collision is detected, it will be reported by the COL signal on the MII interface. Collision detection is disabled in Full Duplex operation. 9.7 Carrier Sense Carrier Sense (CRS) is asserted in half-duplex operation during transmission or reception of data. During full-duplex mode, CRS is asserted only during receive operations. 9.8 Auto-Negotiation means to exchange information between linked devices and to automatically configure both devices to take maximum advantage of their abilities. It is important to note that Auto-negotiation does not test the characteristics of the linked segment. The Auto-Negotiation function provides a means for a device to advertise supported modes of operation to a remote link partner, acknowledge the receipt and understanding of common modes of operation, and to reject un-shared modes of operation. This allows devices on both ends of a segment to establish a link at the best common mode of operation. If more than one common mode exists between the two devices, a mechanism is provided to allow the devices to resolve to a single mode of operation using a predetermined priority resolution function. Auto-negotiation also provides a parallel detection function for devices that do not support the Auto-negotiation feature. During Parallel detection there is no exchange of information of configuration. Instead, the receive signal is examined. If it is discovered that the signal matches a technology, which the receiving device supports, a connection will be automatically established using that technology. This allows devices not to support Auto-negotiation but support a common mode of operation to establish a link. The objective of Auto-negotiation is to provide a Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 39 DM9008AEP Ethernet Controller with General Processor Interface 9.9 Power Reduced Mode 9.9.1 Power Down Mode The Signal detect circuit is always turned to monitor whether there is any signal on the media (cable disconnected). The DM9008A automatically turns off the power and enters the Power Reduced mode, whether its operation mode is N-way or force mode. When enters the Power Reduced mode, the transmit circuit still sends out fast link pules with minimum power consumption. If a valid signal is detected from the media the device will wake up and resume a normal operation mode. The PHY Reg.0.11 can be set high to enter the Power Down mode, which disables all transmit, receive functions, except the MII management interface. That can be writing Zero to PHY Reg. 16.4 to disable Power Reduced mode. Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 9.9.2 Reduced Transmit Power Mode The additional Transmit power reduction can be gained by designing with 1.25:1 turns ration magnetic on its TX side and using a 8.5KΩ resistor on BGRES and AGND pins, and the TXO+/TXO- pulled high resistors should be changed from 50 Ω to 78 Ω . This configuration could be reduced about 20% transmit power. 40 DM9008AEP Ethernet Controller with General Processor Interface 10. DC and AC Electrical Characteristics 10.1 Absolute Maximum Ratings ( 25°C ) Symbol Parameter DVDD Supply Voltage VIN DC Input Voltage (VIN) VOUT DC Output Voltage(VOUT) Tstg Storage Temperature range TC Case Temperature TA Ambient Temperature LT Lead Temperature (TL,soldering,10 sec.). 10.1.1 Operating Conditions Symbol Parameter DVDD Supply Voltage Tc Case Reserve 10BASE-T TX (100% utilization) 10BASE-T idle Auto-negotiation Power Reduced Mode(without cable) Power Down Mode Power Down Mode (system clock off) 10.2 DC Electrical Characteristics (VDD = 3.3V) Symbol Parameter Min. Inputs VIL Input Low Voltage VIH Input High Voltage 2.0 IIL Input Low Leakage Current -1 IIH Input High Leakage Current Outputs VOL Output Low Voltage VOH Output High Voltage 2.4 Receiver VICM RX+/RX- Common Mode Input Voltage Transmitter VTD10 10TX+/- Differential Output Voltage 4.4 ITD10 10TX+/- Differential Output Current │44│ Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 Min. -0.3 -0.5 -0.3 -65 0 0 － Max. 3.6 5.5 3.6 +150 +85 +70 +235 Unit V V V ℃ ℃ ℃ ℃ Conditions Min. 3.135 --------------- Max. 3.465 85 92 38 56 31 21 7 Unit V °C mA mA mA mA mA mA Conditions Typ. asTA：70℃ 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V Max. Unit Conditions - 0.8 1 V V uA uA VIN = 0.0V VIN = 3.3V - 0.4 - V V IOL = 4mA IOH = -4mA 2.5 - V 100 Ω Termination Across 5 │50│ 5.6 │56│ V mA Peak to Peak Absolute Value 41 DM9008AEP Ethernet Controller with General Processor Interface 10.3 AC Electrical Characteristics & Timing Waveforms 10.3.1 Oscillator/Crystal Timing Symbol Parameter Min. TCKC OSC Clock Cycle 39.998 TPWH OSC Pulse Width High 16 TPWL OSC Pulse Width Low 16 Typ. 40 20 20 Max. 40.002 24 24 Unit ns ns ns Conditions 50ppm 10.3.2 Processor I/O Read Timing CS#,CMD → T1 ← → T5 ← IOR# ← SD T2 ← T3 → IO16 → Symbol T1 T2 T3 T4 T5 T6 →← → ←T7 Parameter CS#,CMD valid to IOR# valid IOR# width System Data(SD) Delay time IOR# invalid to System Data(SD) invalid IOR# invalid to CS#,CMD invalid IOR# invalid to next IOR#/IOW# valid When read DM9008A register T6 IOR# invalid to next IOR#/IOW# valid When read DM9008A memory with F0h register T2+T6 IOR# invalid to next IOR#/IOW# valid When read DM9008A memory with F2h register T7 CS#,CMD valid to IO16 valid T8 CS#,CMD invalid to IO16 invalid *Note：(the default clk period is 20ns) 1. The IO16 is valid when the SD bus width is 16-bit and the system address is DATA port (i.e. CMD is high) and the value of INDEX port is memory data Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 T4 → T6 ← → ←T8 Min. 0 10 Typ. Max. 0 2 Unit ns ns ns ns ns clk* 4 clk* 1 clk* 3 3 3 3 ns ns register index.（ex. F0H, F2H, F6H or F8H） 42 DM9008AEP Ethernet Controller with General Processor Interface 10.4.3 Processor I/O Write Timing CS# , CMD → T1 → ← ← IOW# → T2 ← → Symbol T1 T2 T3 T4 T5 T6 T6 T2+T6 T7 T8 ← T7 Parameter CS#,CMD valid to IOW# valid IOW# Width System Data(SD) Setup Time System Data(SD) Hold Time IOW# Invalid to CS#,CMD Invalid IOW# Invalid to next IOW#/IOR# valid When write DM9008A INDEX port IOW# Invalid to next IOW#/IOR# valid When write DM9008A DATA port IOW# Invalid to next IOW#/IOR# valid When write DM9008A memory CS#,CMD Valid to IO16 valid CS#,CMD Invalid to IO16 Invalid Note：(the default clk period is 20ns) 1. The IO16 is valid when the SD bus width is 16-bit and system address is DATA port (i.e. CMD is high) and the value of INDEX port is memory data Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 ← T3 → T6 ∫∫ → SD IO16 ← T5 ← T4 → → Min. 0 10 10 3 0 1 ← T8 Typ. Max. Unit ns ns ns ns ns clk* 2 clk* 1 clk* 3 3 ns ns register index (ex. F0H, F2H, F6H or F8H） 43 DM9008AEP Ethernet Controller with General Processor Interface 10.4.4 EEPROM Interface Timing T2 T3 EECS T1 EECK T4 T6 EEDIO T5 T7 Symbol T1 T2 T3 T4 T5 T6 T7 Parameter EECK Frequency EECS Setup Time EECS Hold Time EEDIO Setup Time when output EEDIO Hold Time when output EEDIO Setup Time when input EEDIO Hold Time when input Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 Min. 8 8 Typ. 0.375 500 2166 480 2200 Max. Unit Mhz ns ns ns ns ns ns 44 DM9008AEP Ethernet Controller with General Processor Interface 11. Application Notes 11.1 Network Interface Signal Routing Place the transformer as close as possible to the RJ-45 connector. Place all the 50Ω resistors as close as possible to the DM9008A RXI± and TXO± pins. Traces routed from RXI± and TXO± to the transformer should run in close pairs directly to the transformer. The designer should be careful not to cross the transmit and receive pairs. As always, vias should be avoided as much as possible. The network interface should be void of any signals other than the TXO± and RXI± pairs between the RJ-45 to the transformer and the transformer to the DM9008A.. There should be no power or ground planes in the area under the network side of the transformer to include the area under the RJ-45 connector. Keep chassis ground away from all active signals. The RJ-45 connector and any unused pins should be tied to chassis ground through a resistor divider network and a 2KV bypass capacitor. The Band Gap resistor should be placed as physically close as pins 1 and 48 as possible (refer to Figure 11-1 and 11-2). The designer should not run any high-speed signal near the Band Gap resistor placement. HP Auto-MDIX Application Figure 11-1 HP Auto-MDIX Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 45 DM9008AEP Ethernet Controller with General Processor Interface 11.3 Non HP Auto-MDIX Transformer Application Figure 11-2 Non HP Auto-MDIX 11.4 Power Decoupling Capacitors Davicom Semiconductor recommends placing all the decoupling capacitors for all power supply pins as close as possible to the power pads of the DM9008A (The best placed distance is < 3mm from pin). The recommended Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 decoupling capacitor is 0.1μF or 0.01μF, as required by the design layout. 46 XI 1M AGND 25MHZ X? + R? 49.9 R? 49.9 R? 49.9 R? 49.9 P3_TX+ P2_TX+ P1_TX+ P0_TX+ AGND C? 0.1UF R? 49.9 C? 0.1UF R? 49.9 C? 0.1UF R? 49.9 C? 0.1UF R? 49.9 P0_TX- P1_TX- P2_TX- P3_TX- C? 0.1UF C? 0.1UF C? 0.1UF C? 0.1UF Enable Prot 4 USE FX Enable AUTO-MDIX Enable Flow Control Enable Use SDC/SDIO Control R? 10K R? 10K R? 10K R? 10K R? 1K1% AGND AGND AGND AGND P0_RX+ P1_RX+ P2_RX+ C? 0.1UF R? 49.9 C? 0.1UF R? 49.9 C? 0.1UF R? 49.9 C? 0.1UF DGND R? 49.9 R? 49.9 R? 49.9 DGND C? 0.1UF C0603 P0_RX- P1_RX- P2_RX- P3_RX- C? 0.1UF C0603 R? 49.9 C? 0.1UF C0603 DGND R? 49.9 DGND C? 0.1UF C0603 DVDD_33 DVDD_33 DVDD_33 DVDD_33 AVDD_18 P3_RX+ AGND C? 0.1UF AVDD_18 AVDD_33 RTX CONTROL VREF DVDD_33 AGND C? 0.1UF C? 20P XO DGND EESK(SDC) P5_TXD0 P5_TXD3 P4_FX AGND C? 20P R? C? 1UF/6.3V EC-MR05-2 P3_DUPCOL P2_DUPCOL P1_DUPCOL P0_DUPCOL P0_TX+ P0_TX- RESET# P0_L/A_LED P1_L/A_LED P2_L/A_LED P3_L/A_LED P0_RX+ P0_RX- P4_DUPCOL U? QFP128-1 DM8606AF/QFP128 DGND C? 0.1UF DVDD_33 C? 0.1UF P0_TXP0_TX+ P0_RXP0_RX+ P1_TXP1_TX+ AGND C? 0.1UF 8 7 6 5 4 3 2 1 16 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 JP? 37 36 35 34 33 C? 0.1UF CS SK DI DO U? VCC NC NC GND 8 7 6 5 DGND MDIO MDC P1_LDSPD P0_LDSPD P3_LDSPD P2_LDSPD P4_LDSPD P5_TXD3 P5_TXD0 P4_FX 93LC46/93LC66/DIP8 1 2 3 4 R? 10K P4_RX+ P4_RX- P4_TX+ P4_TX- AGND C? 0.1UF CONTROL B 2SB1386 R? 182 R? 182 R? 182 R? 182 E Q? C DGND C? 0.1UF L? RST# C? 0.1UF D? 1N4148 SMD F.B/120/S0603 L? F.B/120/S0603 L? F.B/120/S0603 DVDD_33 TX+ TX- RX+ RX- C? 0.1UF DVDD_18 AVDD_33 + C? 220UF/6.3V EC-MR05-2 R? 69 R? 69 R? 69 R? 69 CS# R? 0 R? 0 25 26 27 28 29 30 31 32 33 34 35 36 SD13 SD12 SD11 SD10 SD9 VDD SD8 CMD GND INT IOR# IOW# U? DM9KA_GPIO0 DM9KA_GPIO1 1 C? 0.1UF 3 VIN C? 22PF C0603 2 C D? C D? C D? C D? C D? C D? AGND C D? LEDA C D? LEDA C D? C D? LEDA C D? LEDA C D? C D? LEDA C D? LEDA C D? + C? 220UF/16V EC-MR05-2 AVDD_25 LEDA LEDA LEDA LEDA LEDA LEDA LEDA LEDA LEDA 1K 1K 1K 1K 1K R? R? R? R? R? 1K 1K 1K 1K 1K R? 1K R? 1K R? 1K R? 1K R? 1K R? R? R? R? R? 8 7 6 5 DVDD_33 DVDD_33 DVDD_33 DGND SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 CS# IOR# IOW# CMD INT CPU_GPIO0 CPU_GPIO1 RESET# f or DM8606A RESET# f or DM9000A CPU_GPIO0 CPU_GPIO1 Date: Size Tuesday , April 11, 2006 Document Number Sheet 0 of 1 DM8606AF + DM9008A Reset for DM8606A and DM9008A RESET# RST# R? 0 R? 0 Rev 1.0 SY S_BUS_SD0 SY S_BUS_SD1 SY S_BUS_SD2 SY S_BUS_SD3 SY S_BUS_SD4 SY S_BUS_SD5 SY S_BUS_SD6 SY S_BUS_SD7 SY S_BUS_SD8 SY S_BUS_SD9 SY S_BUS_SD10 SY S_BUS_SD11 SY S_BUS_SD12 SY S_BUS_SD13 SY S_BUS_SD14 SY S_BUS_SD15 SY S_BUS_CS# SY S_BUS_IOR# SY S_BUS_IOW# SY S_BUS_CMD(SY S_BUS_SA2) SY S_BUS_INT DAVICOM Semiconductor Inc. Title MII_MDIO MII_MDC C? 0.1UF C0603 DVDD_33 Select GPIO of CPU to set DM8606A registor + C? 220UF/6.3V EC-MR05-2 DVDD_33 P0_L/A_LED P1_L/A_LED P2_L/A_LED P3_L/A_LED P4_L/A_LED P0_LDSPD P1_LDSPD P2_LDSPD P3_LDSPD P4_LDSPD P0_DUPCOL P1_DUPCOL P2_DUPCOL P3_DUPCOL P4_DUPCOL AGND R? 6.8K1% R0603 C? 0.1UF C0603 RXRX+ TXTX+ VCC NC NC GND 93LC46/DIP8 CS SK DI DO U? SYSTEM CONTROL BUS 12 11 10 9 8 7 6 5 4 3 2 1 R? 10K R0603 1 2 3 4 Preliminary (for Reference Only) AGND AVDD_18 C? + 220UF/6.3V EC-MR05-2 AVDD_33 DGND VOUT U? AP1084,TO-263 U? RT9172-25CM,TO-263 3 VIN VOUT + C? 220UF/6.3V EC-MR05-2 C? 0.1UF C? 22PF C0603 DGND DGND DGND Power 5V TO 3.3V C? 10UF/16V EC-MR05-2 + C? 220UF/6.3V EC-MR05-2 DVDD_5 DGND + R? 4.7K R0603 DVDD_33 Y? XTAL 25MHZ/49US DM9008AE/LQFP48 SD5 SD6 SD7 AVDD25 TXTX+ AGND AGND RXRX+ AVDD25 BGRES DM9008A-8/16bit Select GPIO of DM9000A to set DM8606A registor R? 10K DVDD_33DVDD_33 INT IOR# IOW# SD8 CMD SD13 SD12 SD11 SD10 SD9 DGND + DVDD_33 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 SD15 SD14 C? 330UF/16V EC-MR05-2 Pull high set DM8606A LED mode and AutoMDIX MII_MDIO MII_MDC DGND C? 0.1UF DVDD_33 Set DM9000A Software Fix PHY To Fiber Mode PHYREG 0x00 ==> 0x2100 PHYREG 0x10 ==> 0x4014 AGND 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 EECS EESK(SDC) EDI(SDIO) EDO DGND (CFGEN)P5_TXD0 P4_FX (P5_GPSI)P5_TXD1 P5_TXD2 P5_TXD3 P5_COL P5_CRS P5_RXD3 P5_RXD2 P5_RXD1 P5_RXD0 P5_RXDV P4_SPDTN DGND DVDD33 LDSPD3 LDSPD2 DVDD18 DGND MDC LDSPD1 LDSPD0 TEST MDIO P4_RXER Y CL PTC1411-31 8 7 6 5 4 3 2 1 16 15 14 13 12 11 10 9 P1_RXP1_RX+ P2_TXP2_TX+ 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 C? 0.1UF AVDD_18 C? 0.1UF C? C? 0.1UF 0.1UF C? 0.1UF P2_RXP2_RX+ P3_TXP3_TX+ P3_RXP3_RX+ P1_TX+ P1_TX- 100K P1_RX+ P1_RX- R? P4_TXD3 P4_TXD2 P4_TXD1(P4TY PE1) P4_TXD0(P4TY PE0) DPHALFP4 DGND DVDD33 DUPCOL3 DUPCOL2(RECBPEN) DUPCOL1(PHY AS1) DUPCOL0(RECANEN) P4_TXEN P4_TXCLL DVDD18 P4_RXCLK DGND RESET# XI XO DVDD18PLL DGNDPLL CONTROL VREF DGNDBIAS RTX DVDD33BIAS P2_TX+ P2_TX- 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 P2_RX+ P2_RX- DVDD_33 P3_TX+ P3_TX- DVDD_33 DVDD_18 P3_RX+ P3_RX- USE SMI Interface P4_RXP4_RX+ MII_MDC P4_L/A_LED 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 P4_RXD3 P4_RXD2 P4_RXD1 DGND LNKACT0 LNKACT1 LNKACT2 LNKACT3 DVDD18 DGND LNKFP4 DPHALFP5 LNKFP5 SPDTNP5 DVDD33 DGND CFG0 CKO25M EDO DGND DVDD18 EESK(XOVEN) EECS EDI(DUALCOLOR) P4_COL P4_CRS DGND DVDD18 P4_RXD0 P4_RXDV P5_RXCLK DVDD33 DGND DGND P5_RXER P5_TXCLK P5_TXEN(PHYAS0) DVDD18 AVDD18 P0_TX+ P0_TXAGND AGND P0_RX+ P0_RXAVDD33 AVDD18 P1_TX+ P1_TXAGND AGND P1_RX+ P1_RXAVDD33 AVDD18 P2_TX+ P2_TXAGND P2_RX+ P2_RXAVDD33 AVDD18 P3_TX+ P3_TXAGND AGND P3_RX+ P3_RXAVDD33 P4_RXP4_RX+ AGND AGND P4_TXP4_TX+ AVDD18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 MII_MDIO C A R? NC R? 0 R? NC R? 0 G 2 P4_TXP4_TX+ 24 23 22 21 20 19 18 17 16 15 14 13 SD14 VDD SD15 EEDCS EEDCK EEDIO SD0 SD1 SD2 GND SD3 SD4 CS# LED2(IOWAIT / WAKEUP for eeprom) LED1(IO16 for eeprom) PWRST# TEST VDD X2 X1 GND SD AGND BGGND G Version: DM9008AEP-DS-P03 Dec. 14, 2006 1 Preliminary 37 38 39 40 41 42 43 44 45 46 47 48 MDIO EDI(SDIO) MDC EESK(SDC) DM9008AEP Ethernet Controller with General Processor Interface 11.41 DM9008A + DM8606A Circuit 47 DM9008AEP Ethernet Controller with General Processor Interface 11.5 Magnetics Selection Guide Refer to Table 1 for transformer requirements. Transformers, meeting these requirements, are available from a variety of magnetic manufacturers. Designers should test and qualify all magnetics Manufacturer Pulse Engineering Delta YCL MAGCOM Halo Nano Pulse Inc. Fil-Mag Bel Fuse Valor Macronics Bothhand before using them in an application. The transformers listed in Table 1 are electrical equivalents, but may not be pin-to-pin equivalents. Part Number PE-68515, H1078, H1012, H1102 LF8200, LF8221x 20PMT04, 20PMT05, PH163112 , YCL 0303 PH163539 *(HP Auto-MDIX) HS9001 , HS9016 TG22-3506ND, TD22-3506G1, TG22-S010ND, TG22-S012ND TG110-S050N2 NPI 6181-37, NPI 6120-30, NPI 6120-37 NPI 6170-30 PT41715 S558-5999-01, S558-5999-W2 ST6114, ST6118 HS2123, HS2213 TS6121C,16ST8515,16ST1086 Table 1 11.6 Crystal Selection Guide A crystal can be used to generate the 25MHz reference clock instead of an oscillator. The crystal must be a fundamental type, and series-resonant. Connects to pins X1 and X2, and shunts each crystal lead to ground with a 22pf capacitor(see Figure 11-3). X1 X2 43 44 25MHz 22pf AGND 22pf AGND Figure 11-3 Crystal Circuit Diagram Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 48 DM9008AEP Ethernet Controller with General Processor Interface 12. Package Information LQFP 48L (F.P. 2mm) Outline Dimensions unit: inches/mm D D1 y Symbol Dimensions in inches Dimensions in mm Min. Nom. Max. Min. Nom. Max. A - - 0.063 - - 1.60 A1 0.002 - 0.006 0.05 - 0.15 A2 0.053 0.055 0.057 1.35 1.40 1.45 b 0.007 0.009 0.011 0.17 0.22 0.27 b1 0.007 0.008 0.009 0.17 0.20 0.23 C 0.004 - 0.008 0.09 - 0.20 C1 0.004 - 0.006 0.09 - 0.16 D 0.354BSC 9.00BSC D1 0.276BSC 7.00BSC E 0.354BSC 9.00BSC E1 0.276BSC 7.00BSC 0.020BSC 0.50BSC L Θ 0.018 0.024 0-12° Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 0.030 0.45 0.60 L1 0.039REF 1.00REF y 0.003MAX 0.08MAX Notes: 1. To be determined at seating plane. 2. Dimensions D1 and E 1do not include mold protrusion. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Dimensions b does not include dambar protrusion. Total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. 4. Exact shape of each corner is optional. 5. These dimensions apply to the flat section of the lead between 0.10mm and 0.25mm from the lead tip. 6. A1 is defined as the distance from the seating plane to the lowest point of the package body. 7. Controlling dimension: millimeter. 8. Reference documents: JEDEC MS-026, BBC. 0.75 0-12° 49 DM9008AEP Ethernet Controller with General Processor Interface reference purposes only. 13. Ordering Information Part Number DM9008AEP Pin Count 48 Package LQFP(Pb-Free) Disclaimer The information appearing in this publication is believed to be accurate. Integrated circuits sold by DAVICOM Semiconductor are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. DAVICOM makes no warranty, express, statutory, implied or by description regarding the information in this publication or regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHER, DAVICOM MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. DAVICOM reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by DAVICOM for such applications. Please note that application circuits illustrated in this document are for DAVICOM’s terms and conditions printed on the order acknowledgment govern all sales by DAVICOM. DAVICOM will not be bound by any terms inconsistent with these unless DAVICOM agrees otherwise in writing. Acceptance of the buyer’s orders shall be based on these terms. Company Overview DAVICOM Semiconductor Inc. develops and manufactures integrated circuits for integration into data communication products. Our mission is to design and produce IC products that are the industry’s best value for Data, Audio, Video, and Internet/Intranet applications. To achieve this goal, we have built an organization that is able to develop chipsets in response to the evolving technology requirements of our customers while still delivering products that meet their cost requirements. Products We offer only products that satisfy high performance requirements and which are compatible with major hardware and software standards. Our currently available and soon to be released products are based on our proprietary designs and deliver high quality, high performance chipsets that comply with modem communication standards and Ethernet networking standards. Contact Windows For additional information about DAVICOM products, contact the sales department at: Headquarters Hsin-chu Office: No.6 Li-Hsin Rd. VI, Science-based Industrial Park, Hsin-chu City, Taiwan, R.O.C. TEL: 886-3-5798797 FAX: 886-3-5646929 WARNING Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and/or function. Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 50