TI 74ACT16241

54ACT16241, 74ACT16241
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS189A – MARCH 1990 – REVISED APRIL 1996
D
D
D
D
D
D
D
D
Members of the Texas Instruments
Widebus Family
Inputs Are TTL-Voltage Compatible
3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers
Flow-Through Architecture Optimizes
PCB Layout
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
EPIC  (Enhanced-Performance Implanted
CMOS) 1-µm Process
500-mA Typical Latch-Up Immunity at
125°C
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
54ACT16241 . . . WD PACKAGE
74ACT16241 . . . DL PACKAGE
(TOP VIEW)
1OE
1Y1
1Y2
GND
1Y3
1Y4
VCC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
VCC
4Y1
4Y2
GND
4Y3
4Y4
4OE
description
The ’ACT16241 are 16-bit buffers or line drivers
designed specifically to improve both the
performance and density of 3-state memory
address drivers, clock drivers, and bus-oriented
receivers and transmitters. The devices can be
used as four 4-bit buffers, two 8-bit buffers, or one
16-bit buffer. These devices provide true outputs
and complementary output-enable (OE and OE)
inputs.
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
2OE
1A1
1A2
GND
1A3
1A4
VCC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
VCC
4A1
4A2
GND
4A3
4A4
3OE
The 74ACT16241 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The 54ACT16241 is characterized for operation over the full military temperature range of –55°C to 125°C. The
74ACT16241 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
54ACT16241, 74ACT16241
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS189A – MARCH 1990 – REVISED APRIL 1996
FUNCTION TABLES
INPUTS
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
INPUTS
OE
A
OUTPUT
Y
H
H
H
H
L
L
L
X
Z
logic symbol†
1OE
2OE
3OE
4OE
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
3A1
3A2
3A3
3A4
4A1
4A2
4A3
4A4
1
48
25
24
EN1
EN2
EN3
EN4
47
1
1
3
44
5
43
6
41
1
2
8
40
9
38
11
37
12
36
1
3
13
35
14
33
16
32
17
30
1
4
19
29
20
27
22
26
23
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
2
46
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
3Y1
3Y2
3Y3
3Y4
4Y1
4Y2
4Y3
4Y4
54ACT16241, 74ACT16241
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS189A – MARCH 1990 – REVISED APRIL 1996
logic diagram (positive logic)
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
1
3OE
47
2
46
3
44
5
43
6
1Y1
3A1
1Y2
3A2
1Y3
3A3
1Y4
3A4
48
4OE
41
8
40
9
38
11
37
12
2Y1
4A1
2Y2
4A2
2Y3
4A3
2Y4
4A4
25
36
13
35
14
33
16
32
17
3Y1
3Y2
3Y3
3Y4
24
30
19
29
20
27
22
26
23
4Y1
4Y2
4Y3
4Y4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mA
Maximum package power dissipation at TA = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . 1.2 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.
POST OFFICE BOX 655303
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3
54ACT16241, 74ACT16241
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS189A – MARCH 1990 – REVISED APRIL 1996
recommended operating conditions (see Note 3)
54ACT16241
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
High-level output current
IOL
∆t/∆v
Low-level output current
High-level input voltage
74ACT16241
MIN
2
2
TA
Operating free-air temperature
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
V
V
0.8
Input transition rise or fall rate
UNIT
0.8
V
VCC
VCC
V
–24
–24
mA
24
24
mA
VCC
VCC
0
0
V
0
10
0
10
ns/V
–55
125
–40
85
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –50
50 µA
VOH
24 mA
IOH = –24
IOH = –75 mA†
II
IOZ
ICC
IOL = 24 mA
54ACT16241
MIN
MAX
74ACT16241
MIN
4.5 V
4.4
4.4
4.4
5.5 V
5.4
5.4
5.4
4.5 V
3.94
3.8
3.8
5.5 V
4.94
4.8
4.8
3.85
3.85
UNIT
V
4.5 V
0.1
0.1
0.1
5.5 V
0.1
0.1
0.1
4.5 V
0.36
0.44
0.44
5.5 V
0.36
0.44
0.44
1.65
1.65
V
5.5 V
5.5 V
±0.1
±1
±1
µA
VO = VCC or GND
VI = VCC or GND,
5.5 V
±0.5
±5
±5
µA
5.5 V
8
80
80
µA
5.5 V
0.9
1
1
mA
IO = 0
One input at 3.4 V,
Other inputs at VCC or GND
Ci
VI = VCC or GND
VO = VCC or GND
5V
4.5
pF
5V
13
pF
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
MAX
IOL = 75 mA†
VI = VCC or GND
∆ICC‡
Co
TA = 25°C
MIN
TYP
MAX
5.5 V
IOL = 50 µA
VOL
VCC
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
54ACT16241, 74ACT16241
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS189A – MARCH 1990 – REVISED APRIL 1996
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
Y
tPZH
tPZL
OE or OE
Y
tPHZ
tPLZ
OE or OE
Y
MIN
TA = 25°C
TYP
MAX
54ACT16241
74ACT16241
MIN
MAX
MIN
MAX
3.3
6.5
8.4
3.3
9.5
3.3
9.5
2.3
6.3
8.2
2.3
9.1
2.3
9.1
2.3
6.5
8.3
2.3
9.4
2.3
9.4
2.9
7.3
9.3
2.9
10.5
2.9
10.5
4.3
8.9
10.6
4.3
11.6
4.3
11.6
4
8.1
9.8
4
10.7
4
10.7
UNIT
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
d
TEST CONDITIONS
Outputs enabled
Power dissipation capacitance
Outputs disabled
CL = 50 pF,
pF
TYP
f = 1 MHz
43
10
UNIT
pF
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
Output
Control
(low-level
enabling)
3V
1.5 V
1.5 V
0V
tPLH
tPHL
VOH
Output
S1
Open
2 × VCC
GND
500 Ω
LOAD CIRCUIT
Input
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
50% VCC
50% VCC
VOL
3V
0V
tPZL
[ VCC
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
1.5 V
50% VCC
VOL
tPHZ
tPZH
VOLTAGE WAVEFORMS
20% VCC
50% VCC
80% VCC
VOH
[0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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In order to minimize risks associated with the customer’s applications, adequate design and operating
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intellectual property right of TI covering or relating to any combination, machine, or process in which such
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright  1998, Texas Instruments Incorporated