HOLTEK HT95R25

HT95R25
Phone 8-bit MCU
Technical Document
· Application Note
- HA0075E MCU Reset and Oscillator Circuits Application Note
Features
· Operating voltage at fSYS= 3.58MHz: 2.2V~5.5V
· PFD driver output
· 16K´16 OTP type Program Memory
· DTMF generator
· 2112´8 Data Memory
· Power-down and wake-up feature for power-saving
operation: Idle mode, Sleep mode, Green mode and
normal mode
· 50 bidirectional I/Os with pull-high options
· 2 NMOS output-only lines
· Up to 1.117ms instruction cycle with 3.58MHz system
· External interrupt input
clock at VDD=2.2V~5.5V
· Dual 16-bit timers with interrupts
· Bit manipulation instructions
· Timer external input
· Table read function
· 8-level stack
· 63 powerful instructions
· 32768Hz system oscillator
· All instructions executed in 1 or 2 machine cycles
· 32768Hz to 3.58MHz frequency-up PLL circuit
· Supported by comprehensive suite of hardware and
· Real time clock function
software tools
· Watchdog timer function
· 64-pin LQFP package
General Description
The HT95R25 MCU is an 8-bit high performance, RISC
architecture microcontroller device specially designed
for telephone applications. Device flexibility is enhanced with their internal special features such as
power-down and wake-up functions, DTMF generator,
PFD driver, etc. These features combine to ensure applications require a minimum of external components
and therefore reduce overall product costs.
Rev. 1.00
Having the advantages of low-power consumption,
high-performance, I/O flexibility as well as low-cost,
these devices have the versatility to suit a wide range of
application possibilities such as deluxe feature phone,
cordless phones, fax and answering machines, etc.
The device is best suited for phone products that comply with versatile dialer specification requirements for
different areas or countries. The device is fully supported by the Holtek range of fully functional development and programming tools, providing a means for fast
and efficient product development cycles.
1
March 6, 2009
HT95R25
Block Diagram
W a tc h d o g
T im e r
O T P
P ro g ra m
M e m o ry
D a ta
M e m o ry
W a tc h d o g
T im e r O s c illa to r
R e s e t
C ir c u it
8 - b it
R IS C
M C U
C o re
S ta c k
In te rru p t
C o n tr o lle r
3 2 7 6 8 H z
C ry s ta l
O s c illa to r
P L L
I/O
P o rts
1 6 - b it
T im e r s
P r o g r a m m a b le
F re q u e n c y
G e n e ra to r
D T M F
G e n e ra to r
Pin Assignment
P E 3
P E 2
P E 1
P E 0
P F 7
P F 6
P F 5
P F 4
P F 3
P F 2
P F 1
P F 0
P G 3
P G 2
P G 1
P G 0
P A 7
P A 6
P A 5
P A 4
P A 3
P A 2
P A 1
P A 0
P B 7
P B 6
P B 5
P B 4
P B 3
P B 2
P B 1
P B 0
6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 4 5 3 5 2
1
2
4 8
4 7
4 6
3
4
4 5
5
4 4
6
7
8
9
1 0
H T 9 5 R 2 5
6 4 L Q F P -A
1 1
1 2
1 3
1 4
1 5
1 6
1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
P E 4
P E 5
P E 6
P E 7
P D 0
P D 1
P D 2
P D 3
P D 4
P D 5
P D 6
P D 7
M U S IC
R E S
T M R 0
D T M F
T M R
X C
X 2
X 1
N C
IN T
V D D
V S S
P C 0
P C 1
P C 2
P C 3
P C 4
P C 5
P C 6
P C 7
Rev. 1.00
2
March 6, 2009
HT95R25
Pin Description
Pad Name
I/O
Options
Description
PA0~PA7
I/O
Pull-high
Wake-up
Bidirectional 8-bit input/output port. Each individual pin on this port can
be configured as a wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input.
Configuration options determine which pins on the port have pull-high resistors.
PB0~PB7
I/O
Pull-high
Bidirectional 8-bit input/output port.Software instructions determine if the
pin is a CMOS output or Schmitt Trigger input. Configuration options determine which pins on the port have pull-high resistors.
PC0, PC5, PC7 I/O
Pull-high
Bidirectional input/output port. Software instructions determine if the pin
is a CMOS output or Schmitt Trigger input. Configuration options determine which pins on the port have pull-high resistors. When the
multi-function interrupt is enabled an interrupt will be generated whenever PC0 or PC5 has a falling edge, or PC7 has a rising edge.When in
the idle mode such an interrupt will wake up the device.
PC1, PC4, PC6 I/O
Pull-high
Bidirectional input/output port. Software instructions determine if the pin
is a CMOS output or Schmitt Trigger input. Configuration options determine which pins on the port have pull-high resistors.
PC2, PC3
O
¾
PD0~PD7
PE0~PE7
PF0~PF7
I/O
Pull-high
Bidirectional 8-bit input/output port.Software instructions determine if the
pin is a CMOS output or Schmitt Trigger input. Configuration options determine which nibble on the port have pull-high resistors.
PG0~PG3
I/O
Pull-high
Bidirectional 4-bit input/output port.Software instructions determine if the
pin is a CMOS output or Schmitt Trigger input. Configuration options determine if all the pins on the port have pull-high resistors.
INT
I
¾
External interrupt Schmitt trigger input. Edge trigger activated on high to
low transition. No pull-high resistor.
TMR0
I
¾
Timer/Event Counter 0 Schmitt trigger input . No pull-high resistor.
TMR1
I
¾
Timer/Event Counter 1 Schmitt trigger input . No pull-high resistor.
DTMF
O
¾
Dual Tone Multi Frequency Output
MUSIC
O
¾
CMOS output structure Programmable Frequency Divider pin.
X1
X2
I
O
¾
X1 and X2 are connected to an external 32768Hz crystal or resonator for
the system clock.
XC
¾
¾
External low pass filter pin used for the frequency up conversion circuit.
RES
I
¾
Schmitt trigger reset input. Active low.
VDD
¾
¾
Positive power supply
VSS
¾
¾
Negative power supply, ground.
Note:
NMOS output structures
Each pin on PA can be programmed through a configuration option to have a wake-up function.
Rev. 1.00
3
March 6, 2009
HT95R25
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
IOL Total ..............................................................150mA
Total Power Dissipation .....................................500mW
Operating Temperature...........................-40°C to 85°C
IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
2.2
¾
5.5
V
3V 32768Hz and 3.58MHz
oscillator off, system HALT,
5V WDT off, no load
¾
¾
1.5
¾
¾
2
3V 32768Hz and 3.58MHz
oscillator off, system HALT,
5V WDT on, no load
¾
¾
5
¾
¾
10
3V 32768Hz on, 3.58MHz
oscillator off, system HALT,
5V no load
¾
¾
15
¾
¾
30
3V 32768Hz on, 3.58MHz
oscillator off, system on,
5V no load
¾
¾
25
¾
¾
50
3V 32768Hz and 3.58MHz
oscillator on, system on,
5V DTMF generator off, no load
¾
¾
2
¾
¾
3
3V
66
200
330
33
100
166
VDD
Conditions
Operating Voltage
¾
¾
Idle Mode Current 1
General
VDD
CPU
IIDL1
IIDL2
ISLP
IGRN
INOR
Idle Mode Current 2
Sleep Mode Current
Green Mode Current
Normal Mode Current
¾
mA
mA
mA
mA
mA
RPH
Pull-high Resistor
VIL
I/O Port Input Low Voltage
¾
¾
0
¾
0.3VDD
V
VIH
I/O Port Input High Voltage
¾
¾
0.7VDD
¾
VDD
V
IOL1
3
4
I/O Port Sink Current
¾
4
6
¾
5V PC2/PC3= 0.5V
2.5
¾
¾
3V
-1
-2
¾
5V
-2
-3
¾
5V PC2/PC3= 5V
¾
¾
2.5
mA
0.45VDD
¾
0.7VDD
V
0.1
¾
¾
mA
5V
3V
VOL= 0.1VDD
5V
IOL2
PC2, PC3 Sink Current
IOH1
I/O Port Source Current
IOH2
PC2, PC3 Leakage Current
VOH= 0.9VDD
kW
mA
mA
mA
DTMF Generator (Operating Temperature: -20°C ~ 85°C)
VTDC
DTMF Output DC Level
¾
VTOL
DTMF Sink Current
¾
Rev. 1.00
¾
VDTMF= 0.5V
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March 6, 2009
HT95R25
A.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
Min.
Typ.
Max.
Unit
Conditions
General
fSYS1
System Clock 1
¾
Normal mode
32768Hz crystal oscillator
¾
3.5795
¾
MHz
fSYS2
System Clock 2
¾
Green mode
32768Hz crystal oscillator
¾
32
¾
kHz
tSST
System Start-up Timer Period ¾
Power-up, Reset or wake-up
from HALT
¾
1024
¾
tSYS
tWAKE
Wake-up Time for 32768Hz
Crystal OSC
¾
¾
200
ms
tFUP
32kHz oscillator is ON;
Settling Time for 32768Hz to
3.58MHz PLL (Frequency Up 3V 3.58MHz oscillator OFF ®
Conversion)
ON
¾
¾
20
ms
tS2G
Time from Sleep Mode to
¾
Green Mode
¾
0
¾
ms
3V 32kHz oscillator OFF ® ON
Wake-up from Sleep Mode
MCU
3V
¾
45
90
180
5V
¾
32
65
130
tRES
External Reset Low Pulse
¾
Width
¾
1
¾
¾
ms
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
690
¾
704
762
¾
778
tWDTOSC
Watchdog Oscillator Period
ms
DTMF Generator (Operating Temperature: -20°C ~ 85°C)
fDTMFO
Single Tone Output
Frequency
843
¾
861
Microcontroller normal mode;
932
2.5V DTMF generator single tone
1197
test mode
¾
950
¾
1221
1323
¾
1349
1462
¾
1492
1617
¾
1649
120
155
180
mVrms
Hz
VTAC
DTMF Output AC Level
¾
Row group, RL= 5kW
RL
DTMF Output Load
¾
T.H.D. £ -23dB
5
¾
¾
kW
ACR
Column Pre-emphasis
¾
Row group= 0dB
1
2
3
dB
THD
Tone Signal Distortion
¾
RL= 5kW
¾
-30
-23
dB
Rev. 1.00
5
March 6, 2009
HT95R25
System Architecture
A key factor in the high-performance features of the
Holtek range of microcontrollers is attributed to the internal system architecture. The range of devices take advantage of the usual features found within RISC
microcontrollers providing increased speed of operation
and enhanced performance. The pipelining scheme is
implemented in such a way that instruction fetching and
instruction execution are overlapped, hence instructions
are effectively executed in one cycle, with the exception
of branch or call instructions. An 8-bit wide ALU is used
in practically all operations of the instruction set. It carries out arithmetic operations, logic operations, rotation,
increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the
Accumulator and the ALU. Certain internal registers are
implemented in the Data Memory and can be directly or
indirectly addressed. The simple addressing methods of
these registers along with additional architectural features ensure that a minimum of external components is
required to provide a functional I/O control system with
maximum reliability and flexibility. This makes these devices suitable for low-cost, high-volume production for
phone controller applications requiring up to 16K words
of Program Memory and 2112 bytes of Data Memory
storage.
Clocking and Pipelining
The system clock is derived from an external 32768Hz
Crystal/ Resonator which then generates a 3.58MHz
system clock using internal frequency-up converter
circuitry. This internal clock is subdivided into four internally generated non-overlapping clocks, T1~T4. The
Program Counter is incremented at the beginning of the
T1 clock during which time a new instruction is fetched.
The remaining T2~T4 clocks carry out the decoding and
execution functions. In this way, one T1~T4 clock cycle
forms one instruction cycle. Although the fetching and
execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the
microcontroller ensures that instructions are effectively
executed in one instruction cycle. The exception to this
are instructions where the contents of the Program
Counter are changed, such as subroutine calls or
jumps, in which case the instruction will take one more
instruction cycle to execute.
For instructions involving branches, such as jump or call
instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as
the program takes one cycle to first obtain the actual
jump or call address and then another cycle to actually
execute the branch. The requirement for this extra cycle
should be taken into account by programmers in timing
sensitive applications.
O s c illa to r C lo c k
( S y s te m C lo c k )
P h a s e C lo c k T 1
P h a s e C lo c k T 2
P h a s e C lo c k T 3
P h a s e C lo c k T 4
P ro g ra m
C o u n te r
P ip e lin in g
P C
P C + 1
F e tc h In s t. (P C )
E x e c u te In s t. (P C -1 )
P C + 2
F e tc h In s t. (P C + 1 )
E x e c u te In s t. (P C )
F e tc h In s t. (P C + 2 )
E x e c u te In s t. (P C + 1 )
System Clocking and Pipelining
M O V A ,[1 2 H ]
2
C A L L D E L A Y
3
C P L [1 2 H ]
4
:
5
:
6
1
D E L A Y :
F e tc h In s t. 1
E x e c u te In s t. 1
F e tc h In s t. 2
E x e c u te In s t. 2
F e tc h In s t. 3
F lu s h P ip e lin e
F e tc h In s t. 6
E x e c u te In s t. 6
F e tc h In s t. 7
N O P
Instruction Fetching
Rev. 1.00
6
March 6, 2009
HT95R25
Program Counter
256 locations. When such program jumps are executed
it should also be noted that a dummy cycle will be inserted.
During program execution, the Program Counter is used
to keep track of the address of the next instruction to be
executed. It is automatically incremented by one each
time an instruction is executed except for instructions,
such as ²JMP² or ²CALL² that demand a jump to a
non-consecutive Program Memory address. Note that
the Program Counter width varies with the Program
Memory capacity depending upon which device is selected. However, it must be noted that only the lower 8
bits, known as the Program Counter Low Register, are
directly addressable by user.
Stack
This is a special part of the memory which is used to
save the contents of the Program Counter only. The
stack has 8 levels and is neither part of the data nor part
of the program space, and can neither be read from nor
written to. The activated level is indexed by the Stack
Pointer, SP, which can also neither be read from nor
written to. At a subroutine call or interrupt acknowledge
signal, the contents of the Program Counter are pushed
onto the stack. At the end of a subroutine or an interrupt
routine, signaled by a return instruction, RET or , the
Program Counter is restored to its previous value from
the stack. After a device reset, the Stack Pointer will
point to the top of the stack.
When executing instructions requiring jumps to
non-consecutive addresses such as a jump instruction,
a subroutine call, interrupt or reset, etc., the
microcontroller manages program control by loading the
required address into the Program Counter. For conditional skip instructions, once the condition has been
met, the next instruction, which has already been
fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained.
If the stack is full and an enabled interrupt takes place,
the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack
Pointer is decremented, by RET or RETI, the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack
overflow. Precautions should be taken to avoid such
cases which might cause unpredictable program
branching.
The lower byte of the Program Counter, known as the
Program Counter Low register or PCL, is available for
program control and is a readable and writable register.
By transferring data directly into this register, a short
program jump can be executed directly, however, as
only this low byte is available for manipulation, the
jumps are limited to the present page of memory, that is
Program Counter Bits
Mode
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
External Interrupt
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter 0
Overflow
0
0
0
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter 1
Overflow
0
0
0
0
0
0
0
0
0
0
1
1
0
0
Peripheral Interrupt
0
0
0
0
0
0
0
0
0
1
0
0
0
0
RTC Interrupt
0
0
0
0
0
0
0
0
0
1
0
1
0
0
Multi-Function Interrupt
0
0
0
0
0
0
0
0
0
1
1
0
0
0
@2
@1
@0
Skip
Program Counter + 2 (Within current bank)
Loading PCL
PC13 PC12 PC11 PC10 PC9 PC8
#12
#11
@7
@6
@5
@4
@3
Jump, Call Branch
#13
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S13 S12 S11 S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note:
PC13~PC8: Current Program Counter bits
@7~@0: PCL bits
#13~#0: Instruction code address bits
S13~S0: Stack register bits
Rev. 1.00
7
March 6, 2009
HT95R25
P ro g ra m
· Location 000H
C o u n te r
This vector is reserved for use by the device reset for
program initialisation. After a device reset is initiated, the
program will jump to this location and begin execution.
S ta c k L e v e l 1
S ta c k
P o in te r
S ta c k L e v e l 2
· Location 004H
P ro g ra m
M e m o ry
This vector is used by the external interrupt. If the external interrupt pin on the device goes low, the program will jump to this location and begin execution if
the external interrupt is enabled and the stack is not
full.
S ta c k L e v e l 8
Arithmetic and Logic Unit - ALU
· Location 008H
This internal vector is used by the Timer/Event Counter 0. If a counter overflow occurs, the program will
jump to this location and begin execution if the
timer/event counter 0 interrupt is enabled and the
stack is not full.
The arithmetic-logic unit or ALU is a critical area of the
microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main
microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or
logical operations after which the result will be placed in
the specified register. As these ALU calculation or operations may result in carry, borrow or other status
changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the
following functions:
· Location 00CH
This internal vector is used by the Timer/Event Counter 1. If a counter overflow occurs, the program will
jump to this location and begin execution if the
timer/event counter 1 interrupt is enabled and the
stack is not full.
· Location 014H
· Arithmetic operations ADD, ADDM, ADC, ADCM,
This location is used by the RTC. When the RTC is enabled and a time-out occurs, the program will jump to
this location and begin execution if the RTC interrupt
is enabled and the stack is not full.
SUB, SUBM, SBC, SBCM, DAA
· Logic operations AND, OR, XOR, ANDM, ORM,
XORM, CPL, CPLA
· Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,
· Location 018H
RLC
This location is used by the Multi-function Interrupt. If
a falling edge transition is detected on PC0 or PC5, or
a rising edge transition detected on PC7, the program
will jump to this location and begin execution if the
multi-function interrupt is enabled and the stack is not
full.
· Increment and Decrement INCA, INC, DECA, DEC
· Branch decision JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA,
SDZA, CALL, RET, RETI
Program Memory
0 0 0 H
The Program Memory is the location where the user
code or program is stored. For these devices the Program Memory is an OTP type, which means it can be
programmed once.
0 0 4 H
0 0 8 H
Structure
0 0 C H
The Program Memory has a capacity of 16K by 16 bits.
The Program Memory is addressed by the Program
Counter and also contains data, table information and
interrupt entries. Table data, which can be setup in any
location within the Program Memory, is addressed by a
separate table pointer register.
D e v ic e In itia liz a tio n P r o g r a m
E x te r n a l In te r r u p t S u b r o u tin e
T im e r /E v e n t C o u n te r 0
In te r r u p t S u b r o u tin e
T im e r /E v e n t C o u n te r 1
In te r r u p t S u b r o u tin e
0 1 0 H
0 1 4 H
0 1 8 H
Special Vectors
Within the Program Memory, certain locations are reserved for special usage such as reset and interrupts.
R T C In te r r u p t S u b r o u tin e
M u lti- F u n c tio n
In te r r u p t S u b r o u tin e
1 F F F H
1 6 b its
Program Memory Structure
Rev. 1.00
8
March 6, 2009
HT95R25
Look-up Table
Table Program Example
Any location within the Program Memory can be defined
as a look-up table where programmers can store fixed
data. To use the look-up table, the table pointer must
first be setup by placing the lower order address of the
look up data to be retrieved in the table pointer register,
TBLP. This register defines the lower 8-bit address of
the look-up table.
The following example shows how the table pointer and
table data is defined and retrieved from the device. This
example uses raw table data located in the last page
which is stored there using the ORG statement. The
value at this ORG statement is ²3F00H² which refers to
the start address of the last page within the 16K Program Memory of the microcontroller. The table pointer is
setup here to have an initial value of ²06H². This will ensure that the first data read from the data table will be at
the Program Memory address ²3F06H² or 6 locations
after the start of the last page. Note that the value for the
table pointer is referenced to the first address of the
present page if the ²TABRDC [m]² instruction is being
used. The high byte of the table data which in this case
is equal to zero will be transferred to the TBLH register
automatically when the ²TABRDL [m]² instruction is executed.
After setting up the table pointer, the table data can be
retrieved from the current Program Memory page or last
Program Memory page using the ²TABRDC[m]² or
²TABRDL [m]² instructions, respectively. When these instructions are executed, the lower order table byte from
the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the
Program Memory will be transferred to the TBLH special
register. Any unused bits in this transferred higher order
byte will have uncertain values.
Because the TBLH register is a read-only register and
cannot be restored, care should be taken to ensure its
protection if both the main routine and Interrupt Service
Routine use table read instructions. If using the table
read instructions, the Interrupt Service Routines may
change the value of the TBLH and subsequently cause
errors if used again by the main routine. As a rule it is
recommended that simultaneous use of the table read
instructions should be avoided. However, in situations
where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any
main routine table-read instructions. Note that all table
related instructions require two instruction cycles to
complete their operation.
The following diagram illustrates the addressing/data
flow of the look-up table:
P ro g ra m C o u n te r
H ig h B y te
P ro g ra m
M e m o ry
T B L P
T B L H
S p e c ifie d b y [m ]
H ig h B y te o f T a b le C o n te n ts
L o w
B y te o f T a b le C o n te n ts
Look-up Table
Table Location Bits
Instruction
b13
b12
b11
b10
b9
TABRDC [m] PC13 PC12 PC11 PC10 PC9
TABRDL [m]
1
1
1
1
1
b8
b7
b6
b5
b4
b3
b2
b1
b0
PC8
@7
@6
@5
@4
@3
@2
@1
@0
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note:
PC13~PC8: Current Program Counter bits
@7~@0: Table Pointer Lower-order bits (TBLP)
Rev. 1.00
9
March 6, 2009
HT95R25
tempreg1
tempreg2
:
:
db
db
?
?
; temporary register #1
; temporary register #2
mov a,06h
; initialise table pointer - note that this address
; is referenced
mov tblp,a
:
:
; to the last page or present page
tabrdl
tempreg1
dec tblp
tabrdl
;
;
;
;
transfers value in table referenced by table pointer
to tempregl
data at prog. memory address ²3F06H² transferred to
tempreg1 and TBLH
; reduce value of table pointer by one
tempreg2
;
;
;
;
;
;
;
;
transfers value in table referenced by table pointer
to tempreg2
data at prog.memory address ²3F05H² transferred to
tempreg2 and TBLH
in this example the data ²1AH² is transferred to
tempreg1 and data ²0FH² to register tempreg2
the value ²0FH² will be transferred to the high byte
register TBLH
:
:
org 3F00h
dc
; sets initial address of HT95R25 last page
00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
:
Data Memory
Structure
The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Divided into two sections, the first of
these is an area of RAM where special function registers
are located. These registers have fixed locations and
are necessary for correct operation of the device. Many
of these registers can be read from and written to directly under program control, however, some remain
protected from user manipulation. The second area of
RAM Data Memory is reserved for general purpose use.
All locations within this area are read and write accessible under program control.
S p e c ia l P u r p o s e
D a ta M e m o ry
The Special Purpose and General Purpose Data Memory are located at consecutive locations. All are implemented in RAM and are 8 bits wide. The start address of
the Data Memory is the address 00H. Registers which
are common to all microcontrollers, such as ACC, PCL,
etc., have the same Data Memory address. Note that after power-on, the contents of the Data Memory, will be in
an unknown condition, the programmer must therefore
ensure that the Data Memory is properly initialised. The
Special Purpose Data Memory is located in Bank 0
while the General Purpose Data Memory is divided into
11 individual areas or Banks known as Bank 0 to Bank
10. Switching between different banks is achieved by
setting the Bank Pointer to the correct value.
0 0 H
3 F H
4 0 H
B a n k 0
G e n e ra l P u rp o s e
D a ta M e m o ry
F F H
B a n k 0
B a n k 1 ~ 1 0
G e n e ra l P u rp o s e
D a ta M e m o ry
B a n k 1
B a n k 2
B a n k 3
B a n k 1 0
Data Memory Structure
Rev. 1.00
10
March 6, 2009
HT95R25
General Purpose Data Memory
All microcontroller programs require an area of
read/write memory where temporary data can be stored
and retrieved for use later. It is this area of RAM memory
that is known as General Purpose Data Memory. This
area of Data Memory is fully accessible by the user program for both read and write operations. By using the
²SET [m].i² and ²CLR [m].i² instructions, individual bits
can be set or reset under program control giving the
user a large range of flexibility for bit manipulation in the
Data Memory. As the General Purpose Data Memory is
located within 11 different banks, it is first necessary to
ensure that the Bank Pointer is properly set to the correct value before accessing the General Purpose Data
Memory. Only Bank 0 data can be read directly. Indirect
Addressing of Bank 0 is executed using Indirect Addressing Register IAR0 and Memory Pointer MP0. Data
in Banks 1~10 can only be read indirectly using Indirect
Addressing Register IAR1 and Memory Pointer MP1.
0 0 H
IA R
0 1 H
M P 0
0 2 H
IA R
0 3 H
M P 1
0 4 H
B P
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
1
0 8 H
T B L H
0 9 H
W D T S
0 A H
S T A T U S
0 B H
IN T C 0
0 C H
T M R 0 H
0 D H
T M R 0 L
0 E H
T M R 0 C
0 F H
T M R 1 H
1 0 H
T M R 1 L
1 1 H
T M R 1 C
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
1 6 H
P C
Special Purpose Data Memory
1 7 H
P C C
This area of Data Memory, is located in Bank 0, where
registers, necessary for the correct operation of the
microcontroller, are stored. Most of the registers are
both readable and writeable but some are protected and
are readable only, the details of which are located under
the relevant Special Function Register section. Note
that for locations that are unused, any read instruction to
these addresses will return the value ²00H². Although
the Special Purpose Data Memory registers are located
in Bank 0, they will still be accessible even if the Bank
Pointer has selected Banks 1~10.
1 8 H
P D
1 9 H
P D C
1 A H
P E
1 B H
P E C
1 C H
1 D H
1 E H
IN T C 1
1 F H
2 0 H
D T M F C
2 1 H
D T M F D
2 2 H
2 3 H
2 4 H
R T C C
2 5 H
2 6 H
2 7 H
Special Function Registers
2 B H
2 C H
To ensure successful operation of the microcontroller,
certain internal registers are implemented in the RAM
Data Memory area. These registers ensure correct operation of internal functions such as timers, interrupts,
watchdog, etc., as well as external functions such as I/O
data control. The location of these registers within the
RAM Data Memory begins at the address ²00H². Any
unused Data Memory locations between these special
function registers and the point where the General Purpose Memory begins is reserved for future expansion
purposes, attempting to read data from these locations
will return a value of ²00H².
M O D E
M F IC
2 D H
2 E H
P F D C
2 F H
3 0 H
P F D D
3 3 H
3 4 H
P F
3 5 H
P F C
3 6 H
P G
3 7 H
P G C
3 8 H
3 F H
Indirect Addressing Register - IAR0, IAR1
: U n u s e d b y te , re a d a s "0 0 "
The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register
space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data
manipulation uses these Indirect Addressing Registers
and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in
Rev. 1.00
0
Special Purpose Data Memory Structure
no actual read or write operation to these registers but
rather to the memory location specified by their corresponding Memory Pointer, MP0 or MP1. Acting as a
pair, IAR0 and MP0 can together only access data from
Bank 0, while the IAR1 and MP1 register pair can access data from both Bank 0 and Bank 1 to Bank 10. As
11
March 6, 2009
HT95R25
the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers
indirectly will return a result of ²00H² and writing to the
registers indirectly will result in no operation.
viding a convenient way with which to address and track
data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that
the microcontroller is directed to, is the address specified by the related Memory Pointer. MP0, together with
Indirect Addressing Register, IAR0, are used to access
data from Bank 0 only, while MP1 and IAR1 are used to
access data from Banks 0~10.
Memory Pointer - MP0, MP1
For all devices, two Memory Pointers, known as MP0
and MP1 are provided. These Memory Pointers are
physically implemented in the Data Memory and can be
manipulated in the same way as normal registers pro-
The following example shows how to clear a section of four RAM locations already defined as locations adres1 to
adres4.
data .section ¢data¢
adres1
db ?
adres2
db ?
adres3
db ?
adres4
db ?
block
db ?
code .section at 0 ¢code¢
org 00h
start:
mov
mov
mov
mov
a,04h
block,a
a,offset adres1
mp0,a
; setup size of block
loop:
clr
inc
sdz
jmp
IAR0
mp0
block
loop
; clear the data at address defined by MP0
; increment memory pointer
; check if last memory location has been cleared
; Accumulator loaded with first RAM address
; setup memory pointer with first RAM address
continue:
The important point to note here is that in the example shown above, no reference is made to specific RAM addresses.
Bank Pointer - BP
The Data Memory RAM is divided into eleven banks, known as Bank 0~Bank 10. All of the Special Purpose Registers
are contained in Bank 0. Selecting the required Data Memory area is achieved using the Bank Pointer. If data in Bank 0
is to be accessed, then the BP register must be loaded with the value ²00², while if data in Bank 1 is to be accessed,
then the BP register must be loaded with the value ²01² and so on for the other registers. Using Memory Pointer MP0
and Indirect Addressing Register IAR0 will always access data from Bank 0, irrespective of the value of the Bank
Pointer.
The Data Memory is initialised to Bank 0 after a reset, except for a WDT time-out reset in the Power Down Mode, in
which case, the Data Memory bank remains unaffected. It should be noted that Special Function Data Memory is not affected by the bank selection, which means that the Special Function Registers can be accessed from Bank 0 to Bank
10. Directly addressing the Data Memory will always result in Bank 0 being accessed irrespective of the value of the
Bank Pointer.
b 7
B P 7
B P 6
B P 5
B P 4
B P 3
B P 2
B P 1
b 0
B P 0
B a n k P o in te r
B P 7 ~ B P 0
0
1
2
3
4
5
6
7
8
9
1 0
Rev. 1.00
12
D a ta M
B
B
B
B
B
B
B
B
B
B
B
e m
a n
a n
a n
a n
a n
a n
a n
a n
a n
a n
a n
o ry
k 0
k 1
k 2
k 3
k 4
k 5
k 6
k 7
k 8
k 9
k 1 0
March 6, 2009
HT95R25
Accumulator - ACC
Watchdog Timer Register - WDTS
The Accumulator is central to the operation of any
microcontroller and is closely related with operations
carried out by the ALU. The Accumulator is the place
where all intermediate results from the ALU are stored.
Without the Accumulator it would be necessary to write
the result of each calculation or logical operation such
as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads.
Data transfer operations usually involve the temporary
storage function of the Accumulator; for example, when
transferring data between one user defined register and
another, it is necessary to do this by passing the data
through the Accumulator as no direct transfer between
two registers is permitted.
The Watchdog feature of the microcontroller provides
an automatic reset function giving the microcontroller a
means of protection against spurious jumps to incorrect
Program Memory addresses. To implement this, a timer
is provided within the microcontroller which will issue a
reset command when its value overflows. To provide
variable Watchdog Timer reset times, the Watchdog
Timer clock source can be divided by various division ratios, the value of which is set using the WDTS register.
By writing directly to this register, the appropriate division ratio for the Watchdog Timer clock source can be
setup. Note that only the lower 3 bits are used to set division ratios between 1 and 128.
Status Register - STATUS
Program Counter Low Register - PCL
This 8-bit register contains the zero flag (Z), carry flag
(C), auxiliary carry flag (AC), overflow flag (OV), power
down flag (PDF), and watchdog time-out flag (TO).
These arithmetic/logical operation and system management flags are used to record the status and operation of
the microcontroller.
To provide additional program control functions, the low
byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area
of the Data Memory. By manipulating this register, direct
jumps to other program locations are easily implemented. Loading a value directly into this PCL register
will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only
jumps within the current Program Memory page are permitted. When such operations are used, note that a
dummy cycle will be inserted.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO
flag can be affected only by a system power-up, a WDT
time-out or by executing the ²CLR WDT² or ²HALT² instruction. The PDF flag is affected only by executing the
²HALT² or ²CLR WDT² instruction or during a system
power-up.
Look-up Table Registers - TBLP, TBLH
These two special function registers are used to control
operation of the look-up table which is stored in the Program Memory. TBLP is the table pointer and indicates
the location where the table data is located. Its value
must be setup before any table read commands are executed. Its value can be changed, for example using the
²INC² or ²DEC² instructions, allowing for easy table data
pointing and reading. TBLH is the location where the
high order byte of the table data is stored after a table
read data instruction has been executed. Note that the
lower order table data byte is transferred to a user defined location.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
· C is set if an operation results in a carry during an ad-
dition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C
is also affected by a rotate through carry instruction.
· AC is set if an operation results in a carry out of the
low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is
cleared.
b 7
b 0
T O
P D F
O V
Z
A C
C
S T A T U S R e g is te r
A r
C a
A u
Z e
ith m e
r r y fla
x ilia r y
r o fla g
O v e r flo w
g
tic /L o g ic O p e r a tio n F la g s
c a r r y fla g
fla g
S y s te m M
P o w e r d o w
W a tc h d o g
N o t im p le m
a n
n
tim
e
a g e m e n t F la g s
fla g
e - o u t fla g
n te d , re a d a s "0 "
Status Register
Rev. 1.00
13
March 6, 2009
HT95R25
PBC, PCC, PDC, PEC, PFC and PGC, also mapped to
specific addresses with the Data Memory. The control
register specifies which pins of that port are set as inputs
and which are set as outputs. To setup a pin as an input,
the corresponding bit of the control register must be set
high, for an output it must be set low. During program initialization, it is important to first setup the control registers to specify which pins are outputs and which are
inputs before reading data from or writing data to the I/O
ports. One flexible feature of these registers is the ability
to directly program single bits using the ²SET [m].i² and
²CLR [m].i² instructions. The ability to change I/O pins
from output to input and vice versa by manipulating specific bits of the I/O control registers during normal program operation is a useful feature of these devices.
· Z is set if the result of an arithmetic or logical operation
is zero; otherwise Z is cleared.
· OV is set if an operation results in a carry into the high-
est-order bit but not a carry out of the highest-order bit,
or vice versa; otherwise OV is cleared.
· PDF is cleared by a system power-up or executing the
²CLR WDT² instruction. PDF is set by executing the
²HALT² instruction.
· TO is cleared by a system power-up or executing the
²CLR WDT² or ²HALT² instruction. TO is set by a
WDT time-out.
In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status registers are important and if the subroutine
can corrupt the status register, precautions must be
taken to correctly save it.
DTMF Registers - DTMFC, DTMFD
The device contains fully integrated DTMF generator
circuitry for generation of DTMF signals. The DTMF
generator also requires two registers for its operation, a
DTMFC register for its overall control and DTMFD register to store the digital codes that are to be generated as
DMTF signals.
Interrupt Control Register - INTC0, INTC1
These two 8-bit register, known as the INTC0 and
INTC1 registers, control the operation of both external
and internal timer, interrupts, etc. By setting various bits
within this register using standard bit manipulation instructions, the enable/disable function of the external
and timer interrupts can be independently controlled. A
master interrupt bit within this register, the EMI bit, acts
like a global enable/disable and is used to set all of the
interrupt enable bits on or off. This bit is cleared when an
interrupt routine is entered to disable further interrupt
and is set by executing the ²RETI² instruction.
Mode Register - MODE
The device supports two system clock and four operation modes. The system clock could be 32768Hz or
3.58MHz and operation mode could be Normal, Green,
Sleep or Idle mode. These are all selected by the software.
MFIC Register - MFIC
PC0, PC5 and PC7 could be used to trigger an extra interrupt. They are enabled or disabled individually by
bit0~bit2 of MFIC. When a multi-function interrupt occurs, the programmer should check bit4~bit6 of MFIC to
determine the cause of the interrupt.
Timer/Event Counter Registers
This device contains two 16-bit Timer/Event Counters,
which have associated register pairs known as TMR0L/
TMR0H and TMR1L/TMR1H. These are the locations
where the timers 16-bit value is located. Two associated
control registers, known as TMR0C and TMR1C, contain the setup information for these two timers.
PFD Registers - PFDC/PFDD
The device contains a Programmable Frequency Divider function which can generate accurate frequencies
based on the system clock. The clock source, enable
function and output frequency is controlled using these
two registers.
Input/Output Ports and Control Registers
Within the area of Special Function Registers, the I/O
registers and their associated control registers play a
prominent role. All I/O ports have a designated register
correspondingly labeled as PA, PB, PC, PD, PE, PF and
PG. These labeled I/O registers are mapped to specific
addresses within the Data Memory as shown in the Data
Memory table, which are used to transfer the appropriate output or input data on that port. with each I/O port
there is an associated control register labeled PAC,
Rev. 1.00
RTCC Register
The device contains a Real Time Clock function otherwise known as the RTC. To control this function a register known as the RTCC register is provided which
provides the overall on/off control and time out flag.
14
March 6, 2009
HT95R25
Input/Output Ports
ware control. Each pin of the I/O ports is directly mapped
to a bit in its associated port control register. For the I/O
pin to function as an input, the corresponding bit of the
control register must be written as a ²1². This will then
allow the logic state of the input pin to be directly read by
instructions. When the corresponding bit of the control
register is written as a ²0², the I/O pin will be setup as a
CMOS output. If the pin is currently setup as an output,
instructions can still be used to read the output register.
However, it should be noted that the program will in fact
only read the status of the output data latch and not the
actual logic status of the output pin.
Holtek microcontrollers offer considerable flexibility on
their I/O ports. With the input or output designation of every pin fully under user program control, pull-high options for all ports and wake-up options on certain pins,
the user is provided with an I/O structure to meet the
needs of a wide range of application possibilities. The
device provides 34 bidirectional input/output lines labeled with port names PA, PB, PC, PD, PE, PF and PG.
These I/O ports are mapped to the Data Memory with
specific addresses as shown in the Special Purpose
Data Memory table. All of these I/O ports can be used
for input and output operations. For input operation,
these ports are non-latching, which means the inputs
must be ready at the T2 rising edge of instruction ²MOV
A,[m]², where m denotes the port address. For output
operation, all the data is latched and remains unchanged until the output latch is rewritten.
I/O Pin Structures
Unlike other port lines, PC2 and PC3 are supplied as
NMOS output-only lines.
The following diagrams illustrate the I/O pin internal
structures. As the exact logical construction of the I/O
pin may differ from these drawings, they are supplied as
a guide only to assist with the functional understanding
of the I/O pins.
Pull-high Resistors
Programming Considerations
Many product applications require pull-high resistors for
their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have
the capability of being connected to an internal pull-high
resistor. These pull-high resistors are selectable via
configuration options and are implemented using a
weak PMOS transistor. Note that if the pull-high option
is selected, then all I/O pins on that port will be connected to pull-high resistors, individual pins cannot be
selected for pull-high resistor options.
Within the user program, one of the first things to consider is port initialization. After a reset, all of the I/O data
and port control registers will be set high. This means
that all I/O pins will default to an input state, the level of
which depends on the other connected circuitry and
whether pull-high options have been selected. If the port
control registers, PAC, PBC, PCC, PDC, PEC, PFC and
PGC, are then programmed to setup some pins as outputs, these output pins will have an initial high output
value unless the associated port data registers, PA, PB,
PC, PD, PE, PF and PG, are first programmed. Selecting which pins are inputs and which are outputs can
be achieved byte-wide by loading the correct values into
the appropriate port control register or by programming
individual bits in the port control register using the ²SET
[m].i² and ²CLR [m].i² instructions. Note that when using
these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in
the data on the entire port, modify it to the required new
bit values and then rewrite this data back to the output
ports.
Port A Wake-up
Each device has a HALT instruction enabling the
microcontroller to enter a Power Down Mode and preserve power, a feature that is important for battery and
other low-power applications. Various methods exist to
wake-up the microcontroller, one of which is to change
the logic condition on one of the Port A pins from high to
low. After a ²HALT² instruction forces the microcontroller
into entering the Power Down mode, the device will remain idle or in a low-power state until the logic condition
of the selected wake-up pin on Port A changes from high
to low. This function is especially suitable for applications that can be woken up via external switches. Note
that each pin on Port A can be selected individually to
have this wake-up feature.
T 1
S y s te m
T 3
T 4
T 1
T 2
T 3
T 4
P o rt D a ta
W r ite to P o r t
R e a d fro m
P o rt
Read/Write Timing
Port A has the additional capability of providing wake-up
functions. When the device is in the Power Down Mode,
various methods are available to wake the device up.
One of these is a high to low transition of any of the Port
A pins. Single or multiple pins on Port A can be setup to
have this function.
I/O Port Control Registers
Each I/O port has its own control register PAC, PBC,
PCC, PDC, PEC, PFC and PGC, to control the input/output configuration. with this control register, each
CMOS output or input with or without pull-high resistor
structures can be reconfigured dynamically under softRev. 1.00
T 2
C lo c k
15
March 6, 2009
HT95R25
V
P u ll- H ig h
O p tio n
C o n tr o l B it
D a ta B u s
Q
D
W r ite C o n tr o l R e g is te r
C K
D D
W e a k
P u ll- u p
Q
S
C h ip R e s e t
P A 0 ~ P A 7
R e a d C o n tr o l R e g is te r
D a ta B it
Q
D
W r ite D a ta R e g is te r
C K
S
Q
M
R e a d D a ta R e g is te r
S y s te m
U
X
S c h m itt T r ig g e r In p u t O p tio n
W a k e -u p
W a k e - u p O p tio n
PA Input/Output Port
V
P u ll- H ig h
O p tio n
C o n tr o l B it
D a ta B u s
Q
D
W r ite C o n tr o l R e g is te r
C K
P B 0
P C 0
P D 0
P E 0
P F 0
P G 0
R e a d C o n tr o l R e g is te r
D a ta B it
Q
D
W r ite D a ta R e g is te r
C K
S
W e a k
P u ll- u p
Q
S
C h ip R e s e t
D D
~ P
, P
~ P
~ P
~ P
~ P
B 7
C 1 , P C 4 ~ P C 7
D 7
E 7
F 7
G 3
Q
M
U
R e a d D a ta R e g is te r
X
M F I ( P C 0 ¯ , P C 5 ¯ , P C 7 ­ o n ly )
PB, PC (Except for PC2 and PC3), PD, PE, PF and PG Input/Output Ports
D a ta B u s
W r ite D a ta R e g is te r
D a ta B it
Q
D
C K
S
P C 2 , P C 3
Q
C h ip R e s e t
R e a d D a ta R e g is te r
PC2, PC3 NMOS Output Port
Rev. 1.00
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March 6, 2009
HT95R25
Timer/Event Counters
Timer Registers - TMR0L/TMR0H, TMR1L/TMR1H
The provision of timers form an important part of any
microcontroller, giving the designer a means of carrying
out time related functions. The device contains two
count-up timers of 16-bit capacity. As each timer has
three different operating modes, they can be configured
to operate as a general timer, an external event counter
or as a pulse width measurement device.
The timer registers are special function register pairs located in the Special Purpose Data Memory and is the
place where the 16-bit actual timer value is stored.
These register pairs are known as TMR0L/TMR0H and
TMR1L/TMR1H. The value in the timer register pair increases by one each time an internal clock pulse is received or an external transition occurs on the external
timer pin. The timer will count from the initial value
loaded by the preload register to the full count of FFFFH
at which point the timer overflows and an internal interrupt signal is generated. The timer value will then be reset with the initial preload register value and continue
counting.
There are two types of registers related to the
Timer/Event Counters. The first are the registers that
contains the actual value of the Timer/Event Counter
and into which an initial value can be preloaded, and are
known as TMR0L/TMR0H and TMR1L/TMR1H. Reading these register pairs retrieves the contents of the
Timer/Event Counters. The second type of associated
register are the Timer Control Registers, which defines
the timer options and determines how the Timer/Event
Counters are to be used, and have the name TMR0C
and TMT1C. The device can have the timer clock configured to come from the internal clock source or from an
external timer pin.
To achieve a maximum full range count of FFFFH the
preload register must first be cleared to all zeros. It
should be noted that after power-on, the preload register
will be in an unknown condition. Note that if the
Timer/Event Counter is switched off and data is written
to its preload register, this data will be immediately written into the actual timer register. However, if the
Timer/Event Counter is enabled and counting, any new
data written into the preload data register during this period will remain in the preload register and will only be
written into the timer register the next time an overflow
occurs.
An external clock source is used when the Timer/Event
Counter is in the event counting mode, with the clock
source being provided on the external timer pins. These
pins have the name TMR0 and TMR1. Depending upon
the condition of the T0E or T1E bit in the Timer Control
Register, each high to low, or low to high transition on
the external timer input pin will increment the
Timer/Event Counter by one.
Reading from and writing to these registers is carried
out in a specific way. It must be noted that when using instructions to preload data into the low byte register,
namely TMR0L or TMR1L, the data will only be placed in
a low byte buffer and not directly into the low byte register. The actual transfer of the data into the low byte register is only carried out when a write to its associated
high byte register, namely TMR0H or TMR1H, is executed. Also, using instructions to preload data into the
high byte timer register will result in the data being directly written to the high byte register. At the same time
the data in the low byte buffer will be transferred into its
associated low byte register. For this reason, when
preloading data into the 16-bit timer registers, the low
byte should be written first. It must also be noted that to
read the contents of the low byte register, a read to the
high byte register must first be executed to latch the contents of the low byte buffer from its associated low byte
register. After this has been done, the low byte register
can be read in the normal way. Note that reading the low
byte timer register directly will only result in reading the
previously latched contents of the low byte buffer and
not the actual contents of the low byte timer register.
Configuring the Timer/Event Counter Input Clock
Source
For Timer/Event Counter 0, the internal timer clock
source can originate from either the system clock/4 system clock or from an external clock source. For
Timer/Event Counter 1, the internal timer clock source
can originate from the 32768Hz system clock or from an
external clock source. The system clock input timer
source is used when the timer is in the timer mode or in
the pulse width measurement mode.
An external clock source is used when the timer is in the
event counting mode, the clock source being provided
on the external timer pins TMR0 or TMR1. Depending
upon the condition of the T0E or T01 bit, each high to
low, or low to high transition on the external timer pin will
increment the counter by one.
Rev. 1.00
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HT95R25
D a ta B u s
L o w
T 0 M 1
fS
T M R 0
Y S
/4
1 6 - b it
P r e lo a d R e g is te r
T 0 M 0
T im e r /E v e n t C o u n te r
M o d e C o n tro l
T 0 E
B y te B u ffe r
H ig h B y te
L o w
R e lo a d
O v e r flo w
to In te rru p t
B y te
1 6 - B it T im e r /E v e n t C o u n te r
T 0 O N
16-bit Timer/Event Counter 0 Structure
D a ta B u s
L o w
T 1 M 1
T M R 1
3 2 7 6 8 H z
T 1 E
1 6 - b it
P r e lo a d R e g is te r
T 1 M 0
T im e r /E v e n t C o u n te r
M o d e C o n tro l
B y te B u ffe r
H ig h B y te
L o w
R e lo a d
B y te
1 6 - B it T im e r /E v e n t C o u n te r
T 1 O N
O v e r flo w
to In te rru p t
16-bit Timer/Event Counter 1 Structure
Timer Control Registers - TMR0C, TMR1C
Counter is to operate in, either in the timer mode, the
event counting mode or the pulse width measurement
mode, bits 7 and 6 of the Timer Control Register, which
are known as the bit pair T0M1/T0M0 and T1M1/T1M0,
must be set to the required logic levels. The Timer/Event
Counter on/off bit, which is bit 4 of the Timer Control
Register, and known as T0ON and T1ON, provides the
basic on/off control of the Timer/Event Counter. Setting
the bit high allows the Timer/Event Counter to run, clearing the bit stops it running. If the Timer/Event Counter is
in the event count or pulse width measurement mode,
the active transition edge level type is selected by the
logic level of bit 3 of the Timer Control Register which is
known as T0E and T1E.
The flexible features of the Holtek microcontroller
Timer/Event Counters enable them to operate in three
different modes, the options of which are determined by
the contents of their control register, which has the
name TMR0C/TMR1C. It is the Timer Control Register
together with its corresponding timer register pair that
control the full operation of each Timer/Event Counter.
Before the Timer/Event Counter can be used, it is essential that the Timer Control Register is fully programmed with the right data to ensure its correct
operation, a process that is normally carried out during
program initialisation.
To choose which of the three modes the Timer/Event
b 7
T 0 M 1 T 0 M 0
b 0
T 0 O N
T 0 E
T M R 0 C
R e g is te r
N o t im p le m e n te d , r e a d a s " 0 "
E v
1 :
0 :
P u
1 :
0 :
e n t C
c o u n
c o u n
ls e W
s ta rt
s ta rt
o u n te r A c tiv e E d g
t o n fa llin g e d g e
t o n r is in g e d g e
id th M e a s u r e m e n
c o u n tin g o n r is in g
c o u n tin g o n fa llin g
e S e le c t
t A c tiv e E d g e S e le c t
e d g e , s to p o n fa llin g e d g e
e d g e , s to p o n r is in g e d g e
T im e r /E v e n t C o u n te r C o u n tin g E n a b le
1 : e n a b le
0 : d is a b le
N o t im p le m e n te d , r e a d a s " 0 "
O p e r a tin g
T 1 M 1 T
0
0
1
1
M o d e S e
1 M 0
n o
0
e v
1
tim
0
p u
1
le c t
m o d
e n t c
e r m
ls e w
e a v a ila b le
o u n te r m o d e
o d e
id th m e a s u r e m e n t m o d e
Timer/Event Counter 0 Control Register
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HT95R25
b 7
T 1 M 1 T 1 M 0
b 0
T 1 O N
T 1 E
T M R 1 C
R e g is te r
N o t im p le m e n te d , r e a d a s " 0 "
E v
1 :
0 :
P u
1 :
0 :
e n t C
c o u n
c o u n
ls e W
s ta rt
s ta rt
o u n te r A c tiv e E d g
t o n fa llin g e d g e
t o n r is in g e d g e
id th M e a s u r e m e n
c o u n tin g o n r is in g
c o u n tin g o n fa llin g
e S e le c t
t A c tiv e E d g e S e le c t
e d g e , s to p o n fa llin g e d g e
e d g e , s to p o n r is in g e d g e
T im e r /E v e n t C o u n te r C o u n tin g E n a b le
1 : e n a b le
0 : d is a b le
N o t im p le m e n te d , r e a d a s " 0 "
O p e r a tin g
T 1 M 1 T
0
0
1
1
M o d e S e
1 M 0
n o
0
e v
1
tim
0
p u
1
le c t
m o d
e n t c
e r m
ls e w
e a v a ila b le
o u n te r m o d e
o d e
id th m e a s u r e m e n t m o d e
Timer/Event Counter 1 Control Register
events, occurring on the external timer pin, can be recorded by the Timer/Event Counter. To operate in this
mode, the Operating Mode Select bit pair in the Timer
Control Register must be set to the correct value as
shown.
Configuring the Timer Mode
In this mode, the Timer/Event Counters can be utilised
to measure fixed time intervals, providing an internal interrupt signal each time the Timer/Event Counter overflows. To operate in this mode, the Operating Mode
Select bit pair in the Timer Control Register must be set
to the correct value as shown.
Control Register Operating Mode
Select Bits for the Event Counter Mode
Bit7 Bit6
0
1
Bit7 Bit6
Control Register Operating Mode
Select Bits for the Timer Mode
1
In this mode the external timer pin is used as the
Timer/Event Counter clock source, however it is not divided by the internal prescaler. After the other bits in the
Timer Control Register have been setup, the enable bit,
which is bit 4 of the Timer Control Register, can be set
high to enable the Timer/Event Counter to run. If the Active Edge Select bit, which is bit 3 of the Timer Control
Register, is low, the Timer/Event Counter will increment
each time the external timer pin receives a low to high
transition. If the Active Edge Select bit is high, the counter will increment each time the external timer pin receives a high to low transition. When it is full and
overflows, an interrupt signal is generated and the
Timer/Event Counter will reload the value already
loaded into the preload register and continue counting.
The interrupt can be disabled by ensuring that the
Timer/Event Counter Interrupt Enable bit in the Interrupt
Control Register, is reset to zero.
0
In this mode the internal clock, is used as the
Timer/Event Counter clock. After the other bits in the
Timer Control Register have been setup, the enable bit,
which is bit 4 of the Timer Control Register, can be set
high to enable the Timer/Event Counter to run. Each
time an internal clock cycle occurs, the Timer/Event
Counter increments by one. When it is full and overflows, an interrupt signal is generated and the
Timer/Event Counter will reload the value already
loaded into the preload register and continue counting.
The interrupt can be disabled by ensuring that the
Timer/Event Counter Interrupt Enable bit in the Interrupt
Control Register, is reset to zero.
Configuring the Event Counter Mode
In this mode, a number of externally changing logic
P r e s c a le r O u tp u t
In c re m e n t
T im e r C o n tr o lle r
T im e r + 1
T im e r + 2
T im e r + N
T im e r + N
+ 1
Timer Mode Timing Diagram
E x te r n a l T im e
P in In p u t
T E = 1
In c re m e n t
T im e r C o u n te r
T im e r + 1
T im e r + 2
T im e r + 3
Event Counter Mode Timing Diagram
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HT95R25
To ensure that the timer pin is configured to operate as
an event counter input pin the Timer Control Register
must place the Timer/Event Counter in the Event
Counting Mode. It should be noted that in the event
counting mode, even if the microcontroller is in the
Power Down Mode, the Timer/Event Counter will continue to record externally changing logic events on the
timer input pin. As a result when the timer overflows it
will generate a timer interrupt and corresponding
wake-up source.
able bit can only be reset to zero under program control.
Configuring the Pulse Width Measurement Mode
It should be noted that in this mode the Timer/Event
Counter is controlled by logical transitions on the external timer pin and not by the logic level. When the
Timer/Event Counter is full and overflows, an interrupt
signal is generated and the Timer/Event Counter will reload the value already loaded into the preload register
and continue counting. The interrupt can be disabled by
ensuring that the Timer/Event Counter Interrupt Enable
bit in the Interrupt Control Register, is reset to zero.
The residual value in the Timer/Event Counter, which
can now be read by the program, therefore represents
the length of the pulse received on the external timer
pin. As the enable bit has now been reset, any further
transitions on the external timer pin will be ignored. Not
until the enable bit is again set high by the program can
the timer begin further pulse width measurements. In
this way, single shot pulse measurements can be easily
made.
In this mode, the Timer/Event Counter can be utilised to
measure the width of external pulses applied to the external timer pin. To operate in this mode, the Operating
Mode Select bit pair in the Timer Control Register must
be set to the correct value as shown.
Control Register Operating Mode
Select Bits for the Pulse Width
Measurement Mode
Bit7 Bit6
1
1
To ensure that the timer pin is configured to operate as a
pulse width measurement pin the Timer Control Register must place the Timer/Event Counter in the Pulse
Width Measurement Mode.
In this mode the internal clock is used as the
Timer/Event Counter clock. After the other bits in the
Timer Control Register have been setup, the enable bit,
which is bit 4 of the Timer Control Register, can be set
high to enable the Timer/Event Counter, however it will
not actually start counting until an active edge is received on the external timer pin.
Programming Considerations
When configured to run in the timer mode, the internal
system clock is used as the timer clock source and is
therefore synchronized with the overall operation of the
microcontroller. In this mode, when the appropriate
timer register is full, the microcontroller will generate an
internal interrupt signal directing the program flow to the
respective internal interrupt vector. For the pulse width
measurement mode, the internal system clock is also
used as the timer clock source but the timer will only run
when the correct logic condition appears on the external
timer input pin. As this is an external event and not synch r o n i se d w i t h t h e i n t e r n a l t i m e r cl o ck, t h e
microcontroller will only see this external event when the
next timer clock pulse arrives. As a result there may be
small differences in measured values requiring programmers to take this into account during programming.
The same applies if the timer is configured to be in the
event counting mode which again is an external event
and not synchronised with the internal system or timer
clock.
If the Active Edge Select bit, which is bit 3 of the Timer
Control Register, is low, once a high to low transition has
been received on the external timer pin, the Timer/Event
Counter will start counting until the external timer pin returns to its original high level. At this point the enable bit
will be automatically reset to zero and the Timer/Event
Counter will stop counting. If the Active Edge Select bit
is high, the Timer/Event Counter will begin counting
once a low to high transition has been received on the
external timer pin and stop counting when the external
timer pin returns to its original low level. As before, the
enable bit will be automatically reset to zero and the
Timer/Event Counter will stop counting. It is important to
note that in the Pulse Width Measurement Mode, the
enable bit is automatically reset to zero when the external control signal on the external timer pin returns to its
original level, whereas in the other two modes the enE x te r n a l T im e r
P in In p u t
T O N
( w ith T E = 0 )
P r e s c a le r O u tp u t
In c re m e n t
T im e r C o u n te r
T im e r
+ 1
+ 2
+ 3
+ 4
P r e s c a le r O u tp u t is s a m p le d a t e v e r y fa llin g e d g e o f T 1 .
Pulse Width Measure Mode Timing Diagram
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20
March 6, 2009
HT95R25
When the Timer/Event Counter is read or if data is written to the preload registers, the clock is inhibited to
avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. Care must be taken to ensure that the timers are
properly initialised before using them for the first time.
The associated timer enable bits in the interrupt control
register must be properly set otherwise the internal interrupt associated with the timer will remain inactive.
The edge select, timer mode and clock source control
bits in timer control register must also be correctly set to
ensure the timer is properly configured for the required
application. It is also important to ensure that an initial
value is first loaded into the timer register before the
timer is switched on; this is because after power-on the
initial value of the timer register is unknown. After the
timer has been initialised the timer can be turned on and
off by controlling the enable bit in the timer control register. Note that setting the timer enable bit high to turn the
timer on, should only be executed after the timer mode
bits have been properly setup. Setting the timer enable
bit high together with a mode bit modification, may lead
to improper timer operation if executed as a single timer
control register byte write instruction.
When the Timer/Event counter overflows, its corresponding interrupt request flag in the interrupt control
register will be set. If the timer interrupt is enabled this
will in turn generate an interrupt signal. However irrespective of whether the interrupts are enabled or not, a
Timer/Event counter overflow will also generate a
wake-up signal if the device is in a Power-down condition. This situation may occur if the Timer/Event Counter
is in the Event Counting Mode and if the external signal
continues to change state. In such a case, the
Timer/Event Counter will continue to count these external events and if an overflow occurs the device will be
woken up from its Power-down condition. To prevent
such a wake-up from occurring, the timer interrupt request flag should first be set high before issuing the
HALT instruction to enter the Power Down Mode.
Timer Program Example
This program example shows how the Timer/Event
Counter registers are setup, along with how the interrupts are enabled and managed. Note how the
Timer/Event Counter is turned on, by setting bit 4 of the
Timer Control Register. The Timer/Event Counter can
be turned off in a similar way by clearing the same bit.
This example program sets the Timer/Event Counter tobe in the timer mode, which uses the internal system clock as
the clock source.
Org 04h
; external interrupt vector
reti
Org 08h
; Timer/Event Counter 0 interrupt vector
jmp tmr0nt
; jump here when Timer 0 overflows
:
org 20h
; main program
;internal Timer/Event Counter interrupt routine
tmr0nt:
:
; Timer/Event Counter main program placed here
:
reti
:
:
begin:
;setup Timer registers
mov a,01fh
; setup preload value - timer counts from this value to FFFFH
mov tmr01,a
mov a,09bh
mov tmr0h,a
mov a,080h
; setup Timer control register
mov tmr0c,a
; timer mode
; setup interrupt register
mov a,005h
; enable master interrupt and timer interrupt
mov intc0,a
set tmrc0.4
; start Timer - note mode bits must be previously setup
:
:
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HT95R25
Interrupts
struction to be executed, will be transferred onto the
stack. The Program Counter will then be loaded with a
new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch
its next instruction from this interrupt vector. The instruction at this vector will usually be a JMP statement which
will take program execution to another section of program which is known as the interrupt service routine.
Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated
with a RETI statement, which retrieves the original Program Counter address from the stack and allows the
microcontroller to continue with normal execution at the
point where the interrupt occurred.
Interrupts are an important part of any microcontroller
system. When an external event or an internal function
such as a Timer/Event Counter requires microcontroller
attention, their corresponding interrupt will enforce a
temporary suspension of the main program allowing the
microcontroller to direct attention to their respective
needs. Each device contains a single external interrupt
and single internal timer interrupt functions. The external interrupt is controlled by the action of the external
INT pin, while the internal interrupt are controlled by
Timer/Event Counter overflow, a Real Time Clock overflow, a DTMF reciever valid character reception etc.
Interrupt Register
Overall interrupt control, which means interrupt enabling
and request flag setting, is controlled by two interrupt
control registers, INTC0 and INTC1, located in the Data
Memory. By controlling the appropriate enable bits in
this register each individual interrupt can be enabled or
disabled. Also when an interrupt occurs, the corresponding request flag will be set by the microcontroller.
The global enable flag if cleared to zero will disable all
interrupts.
The various interrupt enable bits, together with their associated request flags, are shown in the accompanying
diagram with their order of priority.
Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will be cleared automatically. This will prevent any further interrupt nesting
from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be
immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing
while the program is already in another interrupt service
routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the
related interrupt is enabled, until the Stack Pointer is
decremented. If immediate service is desired, the stack
must be prevented from becoming full.
Interrupt Operation
A Timer/Event Counter overflow, the reception of a valid
DTMF character etc. or the external interrupt line being
pulled low will all generate an interrupt request by setting their corresponding request flag, if their appropriate
interrupt enable bit is set. When this happens, the Program Counter, which stores the address of the next inb 7
b 0
T 1 F
T 0 F
E IF
E T 1 I
E T 0 I
E E I
E M I
IN T C 0 R e g is te r
M a s te r In te r r u p t G lo b a l E n a b le
1 : g lo b a l e n a b le
0 : g lo b a l d is a b le
E x te r n a l In te r r u p t E n a b le
1 : e n a b le
0 : d is a b le
T im e r /E v e n t C o u n te r 0 In te r r u p t E n a b le
1 : e n a b le
0 : d is a b le
T im e r /E v e n t C o u n te r 1 In te r r u p t E n a b le
1 : e n a b le
0 : d is a b le
E x te r n a l In te r r u p t R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
T im e r /E v e n t C o u n te r 0 In te r r u p t R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
T im e r /E v e n t C o u n te r 1 In te r r u p t R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
N o t im p le m e n te d , r e a d a s " 0 "
Interrupt Control 0 Register
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HT95R25
b 7
b 0
M F F
R T C F
E M F I R T C I
IN T C 1 R e g is te r
N o t im p le m e n te d , r e a d a s " 0 "
R e a l T im e C lo c k In te r r u p t E n a b le
1 : e n a b le
0 : d is a b le
M u lti- fu n c tio n I/O
1 : e n a b le
0 : d is a b le
In te r r u p t E n a b le
N o t im p le m e n te d , r e a d a s " 0 "
R e a l T im e C lo c k In te r r u p t R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
M u lti- fu n c tio n I/O
1 : a c tiv e
0 : in a c tiv e
In te r r u p t R e q u e s t F la g
N o t im p le m e n te d , r e a d a s " 0 "
Interrupt Control 1 Register
b 7
b 0
P C 7 F P C 5 F P C 0 F
E P C 7 I E P C 5 I E P C 0 I M F IC
P C 0 In te r r u p t ( F a llin g E d g e )
1 : e n a b le
0 : d is a b le
P C 5 In te r r u p t ( F a llin g E d g e )
1 : e n a b le
0 : d is a b le
P C 7 In te r r u p t ( R is in g E d g e )
1 : e n a b le
0 : d is a b le
N o t im p le m e n te d , r e a d a s " 0 "
P C 0 In te r r u p t ( F a llin g E d g e ) R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
P C 5 In te r r u p t ( F a llin g E d g e ) R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
P C 7 In te r r u p t ( R is in g E d g e ) R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
N o t im p le m e n te d , r e a d a s " 0 "
MFIC Register
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HT95R25
A u to m a tic a lly C le a r e d b y IS R
M a n u a lly S e t o r C le a r e d b y S o ftw a r e
A u to m a tic a lly D is a b le d b y IS R
C a n b e E n a b le d M a n u a lly
P r io r ity
E x te rn a l In te rru p t
R e q u e s t F la g E IF
E E I
T im e r /E v e n t C o u n te r 0
In te r r u p t R e q u e s t F la g T 0 F
E T 0 I
T im e r /E v e n t C o u n te r 1
In te r r u p t R e q u e s t F la g T 1 F
E T 1 I
E M I
H ig h
In te rru p t
P o llin g
E R T C I
R T C In te rru p t
R e q u e s t F la g R T F
M u lti- fu n c tio n In te r r u p t
R e q u e s t F la g M F F
E M F I
L o w
Interrupt Structure
Interrupt Priority
Timer/Event Counter Interrupt
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of simultaneous requests, the
following table shows the priority that is applied. These
can be masked by resetting the EMI bit.
Reset
1
External Interrupt
2
Timer 0 Interrupt
3
Timer 1 Interrupt
4
For a Timer/Event Counter interrupt to occur, the global
interrupt enable bit, EMI, and the corresponding timer
interrupt enable bit, ET0I or ET1I, must first be set. An
actual Timer/Event Counter interrupt will take place
when the Timer/Event Counter request flag, T0F or T1F,
is set, a situation that will occur when the Timer/Event
Counter overflows. When the interrupt is enabled, the
stack is not full and a Timer/Event Counter overflow occurs, a subroutine call to the timer interrupt vector at location 08H or 0CH, will take place. When the interrupt is
serviced, the timer interrupt request flag, T0F or T1F, will
be automatically reset and the EMI bit will be automatically cleared to disable other interrupts.
Real Time Clock Interrupt
5
Real Time Clock Interrupt
Multi-function Interrupt
6
For a Real Time Clock interrupt to occur, the global interrupt enable bit, EMI, and the corresponding real timer
clock interrupt enable bit, RTCI, must first be set. An actual Real Time Clock interrupt will take place when the
Real Time Clock request flag, RTCF, is set, a situation
that will occur when the RTC times out which will occur
every second. When the interrupt is enabled, the stack
is not full and a Real Time Clock interrupt request occurs, a subroutine call to the real time clock interrupt
vector at location 14H, will take place. When the interrupt is serviced, the timer interrupt request flag, RTCF,
will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts.
Interrupt Source
All Devices Priority
In cases where both external and internal interrupts are
enabled and where an external and internal interrupt occurs simultaneously, the external interrupt will always
have priority and will therefore be serviced first. Suitable
masking of the individual interrupts using the INTC register can prevent simultaneous occurrences.
External Interrupt
For an external interrupt to occur, the global interrupt enable bit, EMI, and external interrupt enable bit, EEI,
must first be set. An actual external interrupt will take
place when the external interrupt request flag, EIF, is
set, a situation that will occur when a high to low transition appears on the INT line. When the interrupt is enabled, the stack is not full and a high to low transition
appears on the external interrupt pin, a subroutine call to
the external interrupt vector at location 04H, will take
place. When the interrupt is serviced, the external interrupt request flag, EIF, will be automatically reset and the
EMI bit will be automatically cleared to disable other interrupts.
Rev. 1.00
Multi-function Interrupt
For a Multi-function interrupt to occur, the global interrupt enable bit, EMI, and the corresponding
multi-function interrupt enable bit, EMFI, must first be
set. An actual Multi-function interrupt will take place
when the Multi-function interrupt request flag, MFF, is
set, a situation that will occur when PC0 or PC5 has a
falling edge or PC7 has a rising edge. When the interrupt is enabled, the stack is not full and a Multi-function
24
March 6, 2009
HT95R25
high. Another type of reset is when the Watchdog Timer
overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup.
interrupt request occurs, a subroutine call to the
multi-function interrupt vector at location 18H, will take
place. When the interrupt is serviced, the multi-function
interrupt request flag, MFF, will be automatically reset
and the EMI bit will be automatically cleared to disable
other interrupts.
Reset Functions
There are five ways in which a microcontroller reset can
occur, through events occurring both internally and externally:
Programming Considerations
By disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced, however,
once an interrupt request flag is set, it will remain in this
condition in the INTC register until the corresponding interrupt is serviced or until the request flag is cleared by a
software instruction.
· Power-on Reset
The most fundamental and unavoidable reset is the
one that occurs after power is first applied to the
microcontroller. As well as ensuring that the Program
Memory begins execution from the first memory address, a power-on reset also ensures that certain
other registers are preset to known conditions. All the
I/O port and port control registers will power up in a
high condition ensuring that all pins will be first set to
inputs.
Although the microcontroller has an internal RC reset
function, if the VDD power supply rise time is not fast
enough or does not stabilise quickly at power-on, the
internal reset function may be incapable of providing
proper reset operation. For this reason it is recommended that an external RC network is connected to
the RES pin, whose additional time delay will ensure
that the RES pin remains low for an extended period
to allow the power supply to stabilise. During this time
delay, normal operation of the microcontroller will be
inhibited. After the RES line reaches a certain voltage
value, the reset delay time tRSTD is invoked to provide
an extra delay time after which the microcontroller will
begin normal operation. The abbreviation SST in the
figures stands for System Start-up Timer.
It is recommended that programs do not use the ²CALL
subroutine² instruction within the interrupt subroutine.
Interrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications. If
only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged
once a ²CALL subroutine² is executed in the interrupt
subroutine.
All of these interrupts have the capability of waking up
the processor when in the Power Down Mode. Only the
Program Counter is pushed onto the stack. If the contents of the register or status register are altered by the
interrupt service program, which may corrupt the desired control sequence, then the contents should be
saved in advance.
Reset and Initialisation
V D D
A reset function is a fundamental part of any
microcontroller ensuring that the device can be set to
some predetermined condition irrespective of outside
parameters. The most important reset condition is after
power is first applied to the microcontroller. In this case,
internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready
to execute the first program instruction. After this
power-on reset, certain important internal registers will
be set to defined states before the program commences. One of these registers is the Program Counter,
which will be reset to zero forcing the microcontroller to
begin program execution from the lowest Program
Memory address.
0 .9 V
R E S
tR
D D
S T D
S S T T im e - o u t
In te rn a l R e s e t
Power-On Reset Timing Chart
For most applications a resistor connected between
VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES
pin should be kept as short as possible to minimise
any stray noise interference.
V D D
In addition to the power-on reset, situations may arise
where it is necessary to forcefully apply a reset condition
when the microcontroller is running. One example of this
is where after power has been applied and the
microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the microcontroller registers remain
unchanged allowing the microcontroller to proceed with
normal operation after the reset line is allowed to return
Rev. 1.00
1 0 0 k W
R E S
0 .1 m F
V S S
Basic Reset Circuit
25
March 6, 2009
HT95R25
· Watchdog Time-out Reset during Power Down
For applications that operate within an environment
where more noise is present the Enhanced Reset Circuit shown is recommended.
0 .0 1 m F
The Watchdog time-out Reset during Power Down is
a little different from other kinds of reset. Most of the
conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to
²0² and the TO flag will be set to ²1². Refer to the A.C.
Characteristics for tSST details.
V D D
1 0 0 k W
R E S
W D T T im e - o u t
tS
1 0 k W
V S S
WDT Time-out Reset during Power Down
Timing Chart
Enhanced Reset Circuit
Reset Initial Conditions
More information regarding external reset circuits is
located in Application Note HA0075E on the Holtek
website.
The different types of reset described affect the reset
flags in different ways. These flags, known as PDF and
TO are located in the status register and are controlled
by various microcontroller operations, such as the
Power Down function or Watchdog Timer. The reset
flags are shown in the table:
· RES Pin Reset
This type of reset occurs when the microcontroller is
already running and the RES pin is forcefully pulled
low by external hardware such as an external switch.
In this case as in the case of other reset, the Program
Counter will reset to zero and program execution initiated from this point.
R E S
0 .4 V
S T
S S T T im e - o u t
0 .1 m F
0 .9 V
TO PDF
D D
D D
tR
S T D
S S T T im e - o u t
In te rn a l R e s e t
RESET Conditions
0
0
RES reset during power-on
u
u
RES reset during normal operation
1
u
WDT time-out reset during normal operation
1
1
WDT time-out reset during Power Down
Note: ²u² stands for unchanged
RES Reset Timing Chart
The following table indicates the way in which the various components of the microcontroller are affected after
a power-on reset occurs.
· Watchdog Time-out Reset during Normal Operation
The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except
that the Watchdog time-out flag TO will be set to ²1².
Program Counter
Reset to zero
W D T T im e - o u t
Interrupts
All interrupts will be disabled
S S T T im e - o u t
WDT
Clear after reset, WDT begins
counting
In te rn a l R e s e t
Timer/Event
Counters
The Timer Counters will be
turned off
Input/Output Ports
I/O ports will be setup as inputs
Stack Pointer
Stack Pointer will point to the
top of the stack
tR
Item
S T D
WDT Time-out Reset during Normal Operation
Timing Chart
Rev. 1.00
26
Condition After RESET
March 6, 2009
HT95R25
The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable
continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller
is in after a particular reset occurs. The following table describes how each type of reset affects each of the
microcontroller internal registers.
Reset (Power-on)
RES Reset
(Normal/Green)
RES Reset
(Sleep/Idle)
WDT Time-out
(Normal/Green)
WDT Time-out
(Sleep/Idle)
IAR0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
IAR1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
BP
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
PCL
0000H
0000H
0000H
0000H
0000H
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
STATUS
--00 xxxx
--uu uuuu
-- 01 uuuu
-- 1u uuuu
--11 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
TMR0H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR0L
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR0C
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
TMR1H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1L
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1C
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PCC
1111 --11
1111 --11
1111 --11
1111 --11
uuuu --uu
PD
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PDC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PE
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PEC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PF
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PFC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PG
---- 1111
---- 1111
---- 1111
---- 1111
---- uuuu
PGC
---- 1111
---- 1111
---- 1111
---- 1111
---- uuuu
INTC1
-00- -00-
-00- -00-
-00- -00-
-00- -00-
-uu- -uu-
DTMFC
---- 0--1
---- 0--1
---- 0--1
---- 0--1
---- -u-u
DTMFD
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
RTCC
0-0- ----
u-u- ----
u-u- ----
u-u- ----
u-u- ----
Register
Rev. 1.00
27
March 6, 2009
HT95R25
Reset (Power-on)
RES Reset
(Normal/Green)
RES Reset
(Sleep/Idle)
WDT Time-out
(Normal/Green)
WDT Time-out
(Sleep/Idle)
MODE
000- ----
00u- ----
00u- ----
00u- ----
00u- ----
MFIC
-000 -000
-000 -000
-000 -000
-000 -000
-uuu -uuu
PFDC
0000 ----
0000 ----
0000 ----
0000 ----
uuuu ----
PFDD
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
Register
Note:
²u² stands for unchanged
²x² stands for unknown
²-² stands for unimplemented
Oscillator
There are two oscillator circuits within the controller.
One is for the system clock which uses an externally
connected 32768Hz crystal. The other is an internal
watchdog oscillator.
ever the WDT oscillator will continue to run and keep the
watchdog function active. However, as the WDT will
consume a certain amount of power when in the Power
Down Mode, for low power applications, it may be desirable to disable the WDT oscillator by configuration option.
System Crystal/Ceramic Oscillator
The system clock is generated using an external
32768Hz crystal or ceramic resonator connected between pins X1 and X2. From this clock source an internal circuit generates a 3.58MHz clock source which is
also required by the system. This frequency generator
circuit requires the addition of externally connected RC
components to pin XC to form a low pass filter for the
3.58MHz output frequency stabilisation.
Operation Mode, Power-down and
Wake-up
There are four operational modes, known as the idle
mode, sleep mode, green mode, and normal mode. The
chosen mode is selected using the MODE0, MODE1
and UPEN bits in the PFDC register but also depends
upon whether the HALT instruction has been executed
or not.
X 1
X 2
X C
Idle Mode
1 5 k W
3 n F
When the device enters this mode, the normal operating
current, will be reduced to an extremely low standby current level. This occurs because when the device enters
the Power Down Mode, both the 3.58MHz and 32768Hz
system oscillators are stopped which reduces the power
consumption to extremely low levels, however, as the
device maintains its present internal condition, it can be
woken up at a later stage and continue running, without
requiring a full reset. This feature is extremely important
in application areas where the microcontroller must
have its power supply constantly maintained to keep the
device in a known condition but where the power supply
capacity is limited such as in battery applications.
4 7 n F
Crystal/Ceramic Oscillator
Watchdog Timer Oscillator
The WDT oscillator is a fully integrated free running RC
oscillator with a typical period of 65ms at 5V, requiring no
external components. It is selected via configuration option. If selected, when the device enters the Power
Down Mode, the system clock will stop running, how-
HALT
Instruction
MODE1
MODE0
UPEN
Operation
Mode
32768Hz
Not executed
1
X
1
Normal
Not executed
0
X
0
Green
Executed
0
0
0
Executed
0
1
0
Note:
3.58MHz
System
Clock
ON
ON
3.58MHz
ON
OFF
32768Hz
Sleep
ON
OFF
Stopped
Idle
OFF
OFF
Stopped
²X² means don¢t care
MODE0 will be cleared to 0 automatically after wake-up from Idle Mode.
Rev. 1.00
28
March 6, 2009
HT95R25
b 7
M O D E 1 M O D E 0
b 0
U P E N
P F D C
N o t im p le m e n te d , r e a d a s " 0 "
F r e q u e n c y u p c o n v e r s io n to g e n e r a te 3 .5 8 M H z e n a b le
1 : e n a b le
0 : d is a b le
3 2 7 6 8 H z o s c illa to r e n a b le w h ile th e H A L T in s tr u c tio n is e x e c u te
1 : d is a b le 3 2 7 6 8 H z o s c illa to r ( Id le m o d e )
0 : e n a b le 3 2 7 6 8 H z o s c illa to r ( S le e p m o d e )
S y s te m c lo c k s e le c t
1 : s e le c t 3 .5 8 M H z a s C P U c lo c k s y s te m
0 : s e le c t 3 2 7 6 8 H z a s C P U c lo c k s y s te m
PFDC Register
· Normal mode or Green mode to Idle mode:
Sleep Mode
Step 1: Set bit MODE0 to 1
Step 2: Clear bit MODE1 to 0
Step 3: Clear bit UPEN to 0
Step 4: Execute the HALT instruction
After Step 4, the operational mode will be changed to
the Idle mode.
In the Sleep Mode is similar to the mode, except here
the 32768Hz oscillator continues running after after the
HALT instruction has been executed. This feature enables the device to continue with instruction execution
immediately after wake-up.
· Green mode to Normal mode:
Green Mode
Step 1: Set bit UPEN to 1
Step 2: Execute a 20ms software delay
Step 3: Set bit MODE1 to 1
After Step 3, the operational mode will be changed to
the Normal mode.
In the Green Mode, the 32768Hz oscillator is used as
the system clock for instruction execution. The following
conditions will force the microcontroller enter the Green
Mode:
· Any reset condition from any operational mode
· Sleep mode or Idle mode to Green mode:
· Any interrupt occurring during the Sleep Mode or Idle
Method 1: The occurrence of any reset condition
Method 2: Any active interrupt
Method 3: A Port A wake-up
mode
· A Port A Wake-up from the Sleep Mode or Idle Mode
Note that a Timer/Event Counter 0/1 and RTC interrupt
will not be generated when in the Idle mode as the
32768Hz crystal oscillator is stopped.
Normal Mode
In the Normal mode the device uses the 3.58MHz generated by the frequency-up conversion circuit as the
system clock for instruction execution.
Standby Current Considerations
As the main reason for entering the Power Down Mode
is to keep the current consumption of the MCU to as low
a value as possible, perhaps only in the order of several
micro-amps, there are other considerations which must
also be taken into account by the circuit designer if the
power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All
high-impedance input pins must be connected to either
a fixed high or low level as any floating input pins could
create internal oscillations and result in increased current consumption. Care must also be taken with the
loads, which are connected to I/Os, which are setup as
outputs. These should be placed in a condition in which
minimum current is drawn or connected only to external
circuits that do not draw current, such as other CMOS
inputs. Also note that additional standby current will also
be required if the configuration options have enabled the
Watchdog Timer internal oscillator.
Changing the Operational Mode
Holtek¢s telephone controllers support two system
clocks and four operational modes. The system clock
can be either 32768Hz or 3.58MHz and the operational
mode can be either Normal, Green, Sleep or Idle mode.
The operation mode is selected using software in the
following way:
· Normal mode to Green mode:
Clear bit MODE1 to 0, which will change the operational mode to the Green mode.
The UPEN bit status is not changed. However, the
UPEN bit can be cleared by software.
· Normal mode or Green mode to Sleep mode:
Step 1: Clear bit MODE0 to 0
Step 2: Clear bit MODE1 to 0
Step 3: Clear bit UPEN to 0
Step 4: Execute the HALT instruction
After Step 4, the operational mode will be changed to
the Sleep mode.
Rev. 1.00
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March 6, 2009
HT95R25
Wake-up
· The PDF flag is set and the TO flag is cleared by hard-
A reset, interrupt or port A wake-up can all wake up the
device from the Sleep Mode or the Idle Mode. A reset
can include a power-on reset, an external reset or a
WDT time-out reset. By examining the device status
flags, PDF and TO, the program can distinguish between the different reset conditions. Refer to the Reset
section for a more detailed description.
ware.
Watchdog Timer
The Watchdog Timer is provided to prevent program
malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events
such as electrical noise. It operates by providing a device reset when the WDT counter overflows. The WDT
clock is supplied by one of two sources selected by a
configuration option. These an be either its own
self-contained dedicated internal WDT oscillator, or the
instruction clock which is the system clock divided by 4.
Note that if the WDT configuration option has been disabled, then any instruction relating to its operation will
result in no operation.
A port A wake-up and an interrupt can be considered as
a continuation of normal execution. Each bit in port A
can be independently selected to wake-up the device
using configuration options. When awakened by a Port
A stimulus, the program will resume execution at the
next instruction following the HALT instruction.
Any valid interrupt during the Sleep Mode or Idle Mode
may have one of two consequences. One is if the related interrupt is disabled or the interrupt is enabled but
the stack is full, the program will resume execution at the
next instruction. The other is if the interrupt is enabled
and the stack is not full, the regular interrupt response
takes place. It is necessary to mention that if an interrupt
request flag is set to "1" before entering the Sleep mode
or Idle mode, the Wake-up function of the related interrupt will be disabled.
A configuration option can select the instruction clock,
which is the system clock divided by 4, as the WDT clock
source instead of the internal WDT oscillator. If the instruction clock is used as the clock source, it must be
noted that when the system enters the Power Down
Mode, as the system clock is stopped, then the WDT
clock source will also be stopped. Therefore the WDT
will lose its protecting purposes. In such cases the system cannot be restarted by the WDT and can only be restarted using external signals. For systems that operate
in noisy environments, using the internal WDT oscillator
is therefore the recommended choice.
Once a Sleep mode or Idle mode Wake-up event occurs, it will take an SST delay time, which is 1024 system clock periods, to resume to the Green mode. This
means that a dummy period is inserted after a Wake-up.
If the Wake-up results from an interrupt acknowledge
signal, the actual interrupt subroutine execution will be
delayed by one or more cycles. If the Wake-up results in
the next instruction execution, this will be executed immediately after the dummy period has finished.
Under normal program operation, a WDT time-out will
initialise a device reset and set the status bit TO. However, if the system is in the Power Down Mode, when a
WDT time-out occurs, only the Program Counter and
Stack Pointer will be reset. Three methods can be
adopted to clear the contents of the WDT and the WDT
prescaler. The first is an external hardware reset, which
means a low level on the RES pin, the second is using
the watchdog software instructions and the third is via a
²HALT² instruction.
To minimise power consumption, all the I/O pins should
be carefully managed before entering the Sleep Mode
or Idle Mode.
The Sleep Mode or Idle Mode is initialised by a HALT instruction and results in the following.
· The system clock will be turned off.
There are two methods of using software instructions to
clear the Watchdog Timer, one of which must be chosen
by configuration option. The first option is to use the single ²CLR WDT² instruction while the second is to use
the two commands ²CLR WDT1² and ²CLR WDT2². For
the first option, a simple execution of ²CLR WDT² will
clear the WDT while for the second option, both ²CLR
WDT1² and ²CLR WDT2² must both be executed to
successfully clear the WDT. Note that for this second
option, if ²CLR WDT1² is used to clear the WDT, successive executions of this instruction will have no effect,
only the execution of a ²CLR WDT2² instruction will
clear the WDT. Similarly, after the ²CLR WDT2² instruction has been executed, only a successive ²CLR WDT1²
instruction can clear the Watchdog Timer.
· The WDT function will be disabled if the WDT clock
source is the instruction clock.
· The WDT function will be disabled if the WDT clock
source is the 32768Hz oscillator in the Idle mode.
· The WDT will still function if the WDT clock source is
the WDT internal oscillator.
· If the WDT function is still enabled, the WDT counter
and WDT prescaler will be cleared and resume counting.
· The contents of the on chip Data Memory and regis-
ters remain unchanged.
· All the I/O ports maintain their original status.
Rev. 1.00
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March 6, 2009
HT95R25
b 7
b 0
W S 2
W S 1
W S 0
W D T S R e g is te r
W D T p r e s c a le r r a te s e le c t
W D T R
W S 0
W S 1
W S 2
1 :1
0
0
0
1 :2
1
0
0
1 :4
0
1
0
1 :8
1
1
0
1 :1
0
0
1
1 :3
1
0
1
1 :6
0
1
1
1 :1
1
1
1
a te
6
2
4
2 8
N o t u s e d
Watchdog Timer Register
C L R W D T 1 F la g
C L R W D T 2 F la g
C le a r W D T T y p e
C o n fig u r a tio n O p tio n
1 o r 2 In s tr u c tio n s
fS Y S /4
W D T O s c illa to r
3 2 7 6 8 H z
W D T C lo c k S o u r c e
C o n fig u r a tio n
O p tio n
C L R
fS
1 5 - b it C o u n te r
¸
2
2
W D T T im e - o u t
1 5 / f
S ~ 2 1 6 /fS
W D T C lo c k S o u r c e
Watchdog Timer
DTMF Generator
The device includes a fully integrated DTMF, Dual-Tone Multiple-Frequency, generator function. This functional block
can generate the necessary16 dual tones and 8 single tones for DTMF signal generation. The signal will be provided on
the DTMF pin of the device. The DTMF generator also includes a power down and a tone on/off function. The clock
source for the DTMF generator is the 3.58MHz oscillator. Before the DTMF function is used, the device must have been
placed into the Normal mode.
DTMF Generator Control
The DTMF Generator is controlled by two registers, a control register known as DTMFC and a data register known as
DTMFD. The power down mode will terminate all the DTMF generator functions and can be activated by setting the
D_PWDN bit in the DTMFC register to 1. These two registers, DTMFC and DTMFD are still accessible even if the
DTMF function is in the power down mode. The generation duration time of the DTMF output signal should be determined by the software. The DTMFD register value can be changed as desired, at which point the DTMF pin will output
the new dual-tone simultaneously.
b 7
b 0
T O N E
D _ P W D N
D T M F C
D T M F G e n e r a to r P o w e r D o w n E n a b le
1 : e n a b le
0 : d is a b le
N o t im p le m e n te d , r e a d a s " 0 "
T o n e O u tp u t E n a b le
1 : e n a b le
0 : d is a b le
N o t im p le m e n te d , r e a d a s " 0 "
DTMF Generator Control Register
Rev. 1.00
31
March 6, 2009
HT95R25
DTMF Generator Frequency Selection
The DTMF pin output is controlled using a combination of the D_PWDN, TONE, TR~TC bits.
C O L 1
C O L 2
C O L 3
C O L 4
1
2
3
A
R O W 2
4
5
6
B
R O W 3
7
8
9
C
0
#
D
R O W 1
R O W 4
*
DTMF Dialing Matrix
b 7
T R 4
b 0
T R 3
T R 2
T R 1
T C 4
T C 3
T C 2
T C 1
D T M F D
H ig h g r o u p ( c o lu m n ) to n e fr e q u e n c y s e le c t
L o w
g r o u p ( r o w ) to n e fr e q u e n c y s e le c t
DTMF Generator Data Register
Control Register Bits
D_PWDN
DTMF Pin Output Status
TONE
TR4~TR1/TC4~TC1
1
x
x
0
0
0
x
1/2 VDD
0
1
0
1/2 VDD
0
1
Any valid value
16 dual tones or 8 signal tones, bias at 1/2 VDD
Output Frequency (Hz)
% Error
Specified
697
Actual
699
770
766
-0.52%
852
847
941
1209
948
1215
-0.59%
+0.74%
+0.50%
+0.29%
1336
1332
-0.30%
1477
1472
-0.34%
% Error does not contain the crystal frequency shift
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DTMF Frequency Selection Table
Low Group
High Group
DTMF Output
TR4
TR3
TR2
TR1
TC4
TC3
TC2
TC1
Low
High
Code
0
0
0
1
0
0
0
1
697
1209
1
0
0
0
1
0
0
1
0
697
1336
2
0
0
0
1
0
1
0
0
697
1477
3
0
0
0
1
1
0
0
0
697
1633
A
0
0
1
0
0
0
0
1
770
1209
4
0
0
1
0
0
0
1
0
770
1336
5
0
0
1
0
0
1
0
0
770
1477
6
0
0
1
0
1
0
0
0
770
1633
B
0
1
0
0
0
0
0
1
852
1209
7
0
1
0
0
0
0
1
0
852
1336
8
0
1
0
0
0
1
0
0
852
1477
9
0
1
0
0
1
0
0
0
852
1633
C
1
0
0
0
0
0
0
1
941
1209
*
1
0
0
0
0
0
1
0
941
1336
0
1
0
0
0
0
1
0
0
941
1477
#
1
0
0
0
1
0
0
0
941
1633
D
Single tone for testing only
0
0
0
1
0
0
0
0
697
x
x
0
0
1
0
0
0
0
0
770
x
x
0
1
0
0
0
0
0
0
852
x
x
1
0
0
0
0
0
0
0
941
x
x
0
0
0
0
0
0
0
1
x
1209
x
0
0
0
0
0
0
1
0
x
1336
x
0
0
0
0
0
1
0
0
x
1477
x
0
0
0
0
1
0
0
0
x
1633
x
Writing other values to TR4~TR1, TC4~TC1 may generate an unpredictable tone.
D _ P D W N = 0
D _ P D W N = 1
1 /2 V D D
T O N E = 1
T O N E = 0
T O N E = 1
T O N E = 0
T O N E = 1
T O N E = 0
A ll th e tim in g o f th e T O N E = 1 a n d T O N E = 0 a r e d e te r m in e d b y s o ftw a r e
DTMF Output
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HT95R25
Programmable Frequency Divider (PFD) Generator - MUSIC
A Programmable Frequency Divider function, otherwise known as PFD, is integrated within the microcontroller, providing a means of accurate frequency generation. It is composed of two functional blocks: a prescaler and a general counter.
3 2 7 6 8 H z
3 .5 8 M H z /4
P r e s c a le r
P r e s c a le r
O u tp u t
M U S IC
P F D
O u tp u t
P F D D
P R E S 1 , P R E S 0
B u z z e r
P F D E N
PFD Control Register
The overall PFD function is controlled using the PFDD register. The prescaler is controlled by the register bits, PRES0
and PRES1. The general counter is programmed by an 8-bit register PFDD. The clock source for the PFD can be selected to be either the 3.58MHz/4 or the 32768Hz oscillator. To enable the PFD output, the PFDEN bit should be set to
1. When the PFD is disabled the PFDD register is inhibited to be written to. To modify the PFDD contents, the PFD must
be enabled. When the generator is disabled, the PFDD is cleared by hardware.
b 7
b 0
F P F D
P R E S 1
P R E S 0
P F D E N
P F D D
N o t im p le m e n te d , r e a d a s " 0 "
P F D O u tp u t E n a b le
1 : e n a b le
0 : d is a b le
P F
0 0
0 1
1 0
1 1
D P
: P r
: P r
: P r
: P r
re
e s
e s
e s
e s
s c
c a
c a
c a
c a
a le
le r
le r
le r
le r
r S
o u
o u
o u
o u
e le
tp u
tp u
tp u
tp u
c t
t =
t =
t =
t =
P F D fr
P F D fr
P F D fr
P F D fr
e q u
e q u
e q u
e q u
e n c
e n c
e n c
e n c
y s o
y s o
y s o
y s o
u rc
u rc
u rc
u rc
e /1
e /2
e /4
e /8
P F D F r e q u e n c y S o u r c e S e le c t
1 : 3 .5 8 M H z /4
0 : 3 2 7 6 8 H z
PFD Data Register
Bit No.
Label
R/W
7~0
¾
RW
Function
PFD data register
PFDD (2FH) Register
PFD_Output_Frequency=
Prescaler_Output
, where N = the value of the PFD Data
2x(N+ 1)
RTC Function
When RTC 1000ms time-out occurs, the hardware will set the interrupt request flag RTCF and the RTCTO flag to 1.
When the interrupt service routine is serviced, the interrupt request flag (RTCF) will be cleared to 0, but the flag RTCTO
remains in its original values. This bit (RTCTO) should be cleared only by software. However, next RTC interrupt will
still occur, even though the RTCTO flag is not cleared.
b 7
R T C T O
b 0
R T C E N
R T C C
R e g is te r
N o t im p le m e n te d , r e a d a s " 0 "
R T C F u n c tio n E n a b le
1 : e n a b le
0 : d is a b le
N o t im p le m e n te d , r e a d a s " 0 "
R T C T im e - o u t F la g
1 : R T C tim e - o u t o c c u r s
0 : R T C tim e - o u t d o e s n o t o c c u r
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HT95R25
Configuration Options
Configuration options refer to certain options within the MCU that are programmed into the MTP Program Memory device during the programming process. During the development process, these options are selected using the HT-IDE
software development tools. As these options are programmed into the device using the hardware programming tools,
once they are selected they cannot be changed later by the application software.
All options must be defined for proper system function, the details of which are shown in the table.
Name
Options
Wake-up PA
Port A wake-up selection.
Define the activity of wake-up function.
All port A have the capability to wake-up the chip from a HALT.
This wake-up function is selected per bit.
Pull-high PA
Pull-high PB
Pull-high PC0~PC1
Pull-high PC4~PC7
Pull-high PD
Pull-high PE
Pull-high PF
Pull-high PG3~PG0
Pull-high option.
This option determines whether the pull-high resistance is viable or not.
Port A pull-high option is selected per bit.
Port B pull-high option is selected per bit.
Port C pull-high option is selected per bit.
Port D pull-high option is selected per nibble.
Port E pull-high option is selected per nibble.
Port F pull-high option is selected per nibble.
Port G pull-high option is selected per nibble.
CLRWDT
This option defines how to clear the WDT by instruction.
One clear instruction: The ²CLR WDT² can clear the WDT.
Two clear instructions: Only when both of the ²CLR WDT1² and ²CLR WDT2² have been executed, then WDT can be cleared.
WDT
Watchdog enable/disable
WDT Clock Source
WDT clock source selection
RC ® Select the WDT OSC to be the WDT source.
T1 ® Select the instruction clock to be the WDT source.
32kHz ® Select the external 32768Hz to be the WDT source.
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Application Circuits
T e le p h o n e C ir c u it
a n d
S p e e c h N e tw o rk
H K S
H D I
H F I
P C 0
P C 5
P C 7
E x tra I/O
In te rru p t
P C 1 ~ P C 4 ,
P C 6
D T M F
D T M F O u tp u t
M U S IC
P F D
O u tp u t
0 .1 m F
V
D D
H T 9 5 R 2 5
1 0 0 k W
R E S
0 .1 m F
I/O
1
2
3
K e y 1
K e y 5
K e y 9
4
5
6
K e y 2
K e y 6
K e y 1 0
7
8
9
K e y 3
K e y 7
K e y 1 1
* /T
0
#
K e y 4
K e y M a tr ix
K e y 8
I/O
5 .1 V
V D D
K e y 1 2
0 .1 m F
IN T
T M R 0 T M R 1
X 1
X 2
V
D D
1 0 0 m F
V S S
X C
1 5 k W
3 2 7 6 8 H z
4 7 n F
T im e r 1
T im e r 0
E x te rn a l
In te rru p t
Rev. 1.00
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Instruction Set
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for
subtraction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Introduction
C e n t ra l t o t he s uc c es s f ul oper a t i on o f a n y
microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontrollers, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of programming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
codes, they have been subdivided into several functional groupings.
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 8MHz system
oscillator, most instructions would be implemented
within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to implement. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the subroutine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
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Bit Operations
Other Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The feature removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² instruction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electromagnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using registers. However, when working with large amounts of
fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
Mnemonic
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Description
Cycles
Flag Affected
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1
1Note
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rev. 1.00
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
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HT95R25
Mnemonic
Description
Cycles
Flag Affected
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
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HT95R25
Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
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CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Each bit of the specified Data Memory is cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Bit i of the specified Data Memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
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HT95R25
CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Data in the specified Data Memory is decremented by 1.
Operation
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
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INC [m]
Increment Data Memory
Description
Data in the specified Data Memory is incremented by 1.
Operation
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Move Data Memory to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
The immediate data specified is loaded into the Accumulator.
Operation
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Move ACC to Data Memory
Description
The contents of the Accumulator are copied to the specified Data Memory.
Operation
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
No operation
Affected flag(s)
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
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OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
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HT95R25
RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
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March 6, 2009
HT95R25
SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Each bit of the specified Data Memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Bit i of the specified Data Memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
None
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HT95R25
SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
Rev. 1.00
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March 6, 2009
HT95R25
SWAP [m]
Swap nibbles of Data Memory
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Operation
Skip if [m] = 0
Affected flag(s)
None
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
Affected flag(s)
None
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
Rev. 1.00
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March 6, 2009
HT95R25
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
Rev. 1.00
49
March 6, 2009
HT95R25
Package Information
64-pin LQFP (7mm´7mm) Outline Dimensions
C
D
4 8
G
3 3
H
I
3 2
4 9
F
A
B
E
6 4
1 7
K
a
J
1 6
1
Symbol
Rev. 1.00
Dimensions in mm
Min.
Nom.
Max.
A
8.9
¾
9.1
B
6.9
¾
7.1
C
8.9
¾
9.1
D
6.9
¾
7.1
E
¾
0.4
¾
F
0.13
¾
0.23
G
1.35
¾
1.45
H
¾
¾
1.6
I
0.05
¾
0.15
J
0.45
¾
0.75
K
0.09
¾
0.20
a
0°
¾
7°
50
March 6, 2009
HT95R25
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Copyright Ó 2009 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
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