LD4000 PR4/EPR4 Read/Write Controller GENERAL DESCRIPTION The part is a high performance BICMOS read channel IC that provides all of the functions needed to implement an entire Partial Response Class 4 (PR4) read channel for zoned recording hard disk drive systems with data rates from 67 to 212 Mbps. Functional blocks include a serial port, an automatic gain control amplifier, a programmable filter, an offset canceller, a peak detecting pulse qualifier, an adaptive transversal filter, a Viterbi qualifier, a 8/9 GCR ENDEC, a data synchronizer, a time base generator, an integrating servo demodulator, as shown in figure 1. The part requires a single +5V power supply. The part utilizes an advanced BiCMOS process technology along with advanced circuit design techniques which results in a high performance device with low power consumption. FEATURES GENERAL • • • • • • • • • • • • • • • Register programmable data rates from 67 to 212 Mbit/s Sampled data read channel with Viterbi qualification Programmable filter for PR4 equalization Five tap transversal filter with adaptive PR4 equalization 8/9 GCR ENDEC Data Scrambler / Descrambler Presettable Precoder state Programmable write precompensation Low operating power - 1000mW maximum at 5.5V to allow use of TOFP packages. Active power management is applied to achieve this target Register programmable power management (<5 mW power down mode) 4-bit nibble and byte wide bi-directional NRZ data interface 8 bit direct write mode automatically configured for CLK=VCO/8 Serial Interface port for access to internal program storage registers Single power supply (5V ± 10%) Small package footprint: 100 lead TOFP AUTOMATIC GAIN CONTROL • • • • • • • • • • Dual mode AGC, continuous time during acquisition, sampled during data reads Separate AGC level storage pins for data and servo Dual rate attack and decay charge pump for rapid AGC recovery in continuous time mode Programmable, symmetric, charge pump currents for data reads in sampled mode Charge pump currents track programmable data rate during data reads Low drift AGC hold circuitry Low-Z circuitry at AGC input provides for rapid external coupling capacitor recovery AGC Amplifier squelch during Low-Z Wide bandwidth amplitude feedback circuit to allow improved stability of AGC level vs. frequency Programmable AGC controls • Separate external input pins for AGC hold, fast recovery, and Low-Z control or • Internal Low-Z and fast recovery timing for rapid transient recovery and AGC acquisition. Timing set with external resistors (2). Ultra fast decay current set with external resistor. version 2.1 LD4000 PR4/EPR4 Read/Write Controller FILTER / EQUALIZER DATA SEPARATOR • • • • • • • • • • • • • Programmable, 7-pole, continuous time filter with asymmetrical zeros Channel filter and pulse slimming equalization for coarse equalization to PR4 Programmable cutoff frequency from 10 to 56 MHz Programmable boost/equalization of 0 to 13 dB Programmable “zeros” equalization provides asymmetry compensation ±30% group delay variation from 0.3Fc to Fc with Fc=56 MHz Low-Z switch for fast offset recovery at the filter output No external coupling capacitors required DC offset compensation provided at the filter output Three or Five tap transversal filter for fine equalization to PR4. Self adapting symmetric Inner taps Programmable symmetric outer taps with 4 bits of resolution • Equalization hold input • Asymmetry factor output and “zeros” channel quality output • • • • • • • • • • • SERVO • • • PULSE QUALIFICATION • • • • Sampled Viterbi qualification of signal equalized to PR4 Register programmable hysteresis or window qualification peak detector for servo reads, with programmable thresholds Selectable RDS pulse width for servo grey code reads RDS and PPOL outputs are disabled during burst capture to reduce noise generation Fully integrated data separator includes data synchronizer and 8/9 GCR ENDEC Register programmable to 212 Mbps Fast Acquisition, sampled data phase locked loop Decision directed clock recovery from data samples Adaptive clock recovery thresholds Programmable damping ratio for data synchronizer PLL is constant for all data rates Data scrambler / descrambler to reduce fixed pattern effects Byte wide NRZ data interface and 4 bits nibble interface Time base tracking, programmable write precompensation Differential PECL write data output Surface defect scan mode Direct Write modes • • • • 6-burst servo capture with A-B, C-D, E-F outputs Internal hold capacitors Separate, automatically selected, registers for servo fc, boost, and threshold Wide bandwidth, high precision full-wave rectifier is optimized for low-level linearity “Soft Landing” charge pump architecture Programmable selection of normal or differentiated filter output to servo-capture block Programmable gain with 2 external inputs TIME BASE GENERATOR • • • • Better than 1% frequency resolution Up to 225 MHz frequency output Independent M and N divide-by registers No active external components required Page 2 version 2.1 Page 3 LOWZ WG RG SG SDATA SCLK SDEN VREF VMIN HOLD UFDC SG 28 29 83 10 9 11 73 93 94 SP CONTROL LOGIC SERIAL PORT & CONTROL REGISTERS VREF AGC CONTROL LOGIC UFDC SP SQUELCH LOWZ HOLD FASTREC 7 CONV AGC CHARGE PUMP SFC 6 SAMPLED AGC CHARGE PUMP 92 5 3 4 SP SMS DAC SERVO 70 FULL WAVE RECTIFIER 69 DECODE LOGIC SERVO LEAKAGE + - SFWR SP LOWZ SP VREFS FULL WAVE RECTIFIER 77 78 82 A C 71 E SP DSCLK 5-TAP EQUALIZER 2-ADAPTIVE 2-PROG SP UFDC AGCDEL FASTREC WRDEL VCC AGCRST HOLDB BYPD BYPS SQUELCH RX SP TPD SFC TPDB DN SFWR EN TPC LOWZ ON- TPCB FASTREC DP TPE DC OFFSET CANCEL PPOL ON+ RDS/RDSB 97 81 79 FROM LEVEL QUAL 80 SP 13 SP MUX VRDT FREF C-D E-F A-B N/X AV1 AV0 1/(N+1) 1/(M+1) TBGOUT SFC SP CODE WORD BOUNDARY DETECTOR 67 69 Fig 1 LD4000 Block Diagram SP SP SYNC FIELD COUNTER ASYMM FACTOR SSBYP VITERBI DETECTOR CHANQUAL To SFC TPA VIAB EQHOLD TEST POINT MUX 8 VNS LEVEL OR HYSTERISIS PULSE QUAL TPAB 63 VNS CN TPB 64 TPBB 65 PHASE/ FREQ DETECTOR SP 18 37 DSCLK 72 95 SFC CHARGE PUMP 16 17 VCO CHARGE PUMP 57 56 VCO SP WRITE PRECOMP SP DAMPING CONTROL DATA SYNCHRONIZER MUX AUTOMATIC TRAINING & SYNC BYTE GENERATOR VCO SYNC PATTERN GEN TIME BASE GENERATOR PHASE/ FREQ DETECTOR DECISION DIRECTED PHASE DETECTOR TBGOUT PARALLEL TO SERIAL 38 SCRAMBLER 15 8/9 (0,4/4) ENCODER 12 47 DESCRAMBLER 58 9/8 (0,4/4) DECODER 68 PRECODER 62 86 SERIAL TO PARALLEL 14 CWBD 54 MUX 55 VNP 66 VNF 60 VNC 85 VNT 84 VNA CP 87 VND TPE MUX VPS OD- OD+ 91 VPS PROGRAMMABLE 7th ORDER LOW-PASS FILTER ASYMMETRIC 0's 90 VPP TPD MUX VPC AGC AMP 89 VPF 98 88 VPT TPC MUX VPD VIA SP VPA 96 DSCLK CWBD 46 SP POWER DOWN CONTROL DACs ASYMM FACTOR VREFS SP 32 31 30 61 44 45 22 21 20 19 43 33-36, 39-42 RCLK ATO TEST MUX RCLK CLOCK GEN WRITE FLIP-FLOP CHANQUAL TBGOUT MUX RCLK NIBBLE INTERFACE PARALLEL INTERFACE PARITY GEN/CHK DUAL "OR" TYPE SYNC BYTE DETECTOR ATO RCLK DWRB WDB WD DWB DW WCLK NRZ0-7 NRZP PERR/NCLK SBDB LD4000 PR4/EPR4 Read/Write Controller PDWNB FLTR2B FLTR2 FLTR1B FLTR1 RR VREFS STROBE RESETB version 2.1 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 N/C N/C VREF RR VREFS RESETB STROBE VPS VNS TPA TPAB TPB TPBB VPS ATO EQHOLD VNS VPP FLTR2 FLTR2B VNP VNC N/C N/C N/C 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 N/C N/C WG/WGB RG SBDB PERR NRZP NRZ0 NRZ1 NRZ2 NRZ3 VND VPD NRZ4 NRZ5 NRZ6 NRZ7 WCLK RCLK DWRB PDWNB VPC N/C N/C N/C N/C N/C BYPD BYPS HOLDB LOWZ FASTREC VRDT SCLK SDATA SDEN VPF FREF VNF VPT FLTR1 FLTR1B VNT DW1B DW1 WDB WD N/C N/C N/C 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 N/C N/C VIA VIAB RX VPA WRDEL AGCDEL AGCRST TPCB TPC TPDB TPD TPE VNA PPOL RDS/RDSB SG N/X A-B C-D E-F AV1 AV0 N/C LD4000 PR4/EPR4 Read/Write Controller LD4000 100-Lead TQFP Page 54 version 2.1