ETC WS6264

High Speed Super Low Power SRAM
WS6264
8K-Word By 8 Bit
GENERAL DESCRIPTION
The WS6264 is a high performance, high speed and super low power CMOS Static Random
Access Memory organized as 8,192 words by 8bits and operates from a single 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high speed, super low power features and
maximum access time of 70ns in 5.0V operation. Easy memory expansion is provided by using two chip
enable inputs (/CE1, CE2) and active LOW output enable (/OE).
The WS6264 has an automatic power down feature, reducing the power consumption significantly
when chip is deselected. The WS6264 is available in JEDEC standard 28-pin SOP(300 mil) and PDIP
(600 mil) packages.
FEATURES
Operation voltage : 4.5 ~ 5.5V
Ultra low power consumption:
Operating current 1mA@1MHz & CMOS standby current 1.0uA (Typ.) in Vcc=5.0V
High speed access time: 70ns.
Automatic power down when chip is deselected.
Three state outputs and TTL compatible.
Data retention supply voltage as low as 2.0V.
Easy expansion with /CE1, CE2 and /OE options.
PRODUCT FAMILY
Product Family
Operating Temp.
Vcc Range
Speed (ns)
Standby Current (Typ.)
ICCSB1
28 SOP
WS6264LLFP
WS6264LLP
WS6264LLFPI
WS6264LLPI
0~70oC
o
-40~85 C
Package Type
4.5~5.5V
70
1.0uA
70
1.0uA
28 PDIP
28 SOP
28 PDIP
Rev. 1.0
1
High Speed Super Low Power SRAM
WS6264
8K-Word By 8 Bit
PIN CONFIGURATIONS
NC
1
28
VCC
A12
2
27
WE
A7
3
26
CE2
A6
4
25
A8
A5
5
24
A9
A4
6
A3
7
A2
8
A1
9
A0
DQ0
23
A11
22
OE
21
A10
20
CE1
10
19
DQ7
11
18
DQ6
DQ1
12
17
DQ5
DQ2
13
16
DQ4
GND
14
15
DQ3
28L SOP
28L PDIP
FUNCTIONAL BLOCK DIAGRAM
128 x512
Rev. 1.0
2
High Speed Super Low Power SRAM
WS6264
8K-Word By 8 Bit
PIN DESCRIPTIONS
Name
Type
A0 – A12
Input
Function
Address inputs for selecting one of the 8,192 x 8 bit words in the RAM
/CE1 is active LOW and CE2 is active HIGH. Both chip enables must be
Input
/CE1,CE2
active when data read from or write to the device. If either chip enable is not
active, the device is deselected and in a standby power down mode. The DQ
pins will be in high impedance state when the device is deselected.
The Write enable input is active LOW. It controls read and write operations.
Input
/WE
With the chip selected, when /WE is HIGH and /OE is LOW, output data will
be present on the DQ pins, when /WE is LOW, the data present on the DQ
pins will be written into the selected memory location.
The output enable input is active LOW. If the output enable is active while the
Input
/OE
chip is selected and the write enable is inactive, data will be present on the
DQ pins and they will be enabled. The DQ pins will be in the high impedance
state when /OE is inactive.
These 8 bi-directional ports are used to read data from or write data into the
DQ0~DQ7
I/O
Vcc
Power
Power Supply
Gnd
Power
Ground
RAM.
No connection
NC
TRUTH TABLE
MODE
/CE1
CE2
/WE
/OE
H
X
X
X
X
L
X
X
Output
Disable
L
H
H
Read
L
H
Write
L
H
Standby
DQ0~7
Vcc Current
High Z
ICCSB, ICCSB1
H
High Z
ICC
H
L
DOUT
ICC
L
X
DIN
ICC
Rev. 1.0
3
High Speed Super Low Power SRAM
WS6264
8K-Word By 8 Bit
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Parameter
Rating
Terminal Voltage with Respect to GND
VTERM
Unit
-0.5 to Vcc+0.5
V
TBIAS
Temperature Under Bias
-40 to +125
O
TSTG
Storage Temperature
-65 to +150
O
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
50
mA
C
C
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
OPERATING RANGE
Range
Ambient Temperature
Vcc
Commercial
0~70oC
4.5 ~ 5.5V
Industrial
-40~85oC
4.5 ~ 5.5V
CAPACITANCE(1)(TA=25℃,f=1.0MHz)
Symbol
Parameter
CIN
Input Capacitance
CDQ
Input/Output Capacitance
Conduction
MAX.
Unit
VIN=0V
8
pF
VDI/O=0V
10
pF
1.This parameter is guaranteed, and not 100% tested.
Rev. 1.0
4
High Speed Super Low Power SRAM
WS6264
8K-Word By 8 Bit
DC ELECTRICAL CHARACTERISTICS
Name
VIL
VIH
IIL
Parameter
Guaranteed Input Low
Voltage (2)
Guaranteed Input High
Voltage (2)
Input Leakage Current
o
o
( TA = 0 ~70 C, Vcc = 5.0V) )
Test Condition
MIN
TYP(1)
MAX
Unit
Vcc=5.0V
-0.5
0.8
V
Vcc=5.0V
2.2
Vcc+0.5
V
VCC=MAX, VIN=0 to VCC
-1
1
uA
-1
1
uA
0.4
V
VCC=MAX, /CE1=VIh, or
IOL
Output Leakage Current
CE2= VIL, or /OE=VIh ,or
/WE= VIL VIO=0V to VCC
VOL
Output Low Voltage
VCC=MAX, IOL = 1mA
VOH
Output High Voltage
VCC=MIN, IOH = -1mA
Operating Power Supply
/CE1=VIL, IDQ=0mA,
Current
F=FMAX =1/ tRC
ICCSB
TTL Standby Supply
/CE1=VIH, IDQ=0mA,
ICCSB1
CMOS Standby Current
ICC
/CE1≧VCC-0.2V, CE2= 0.2V,
VIN≧VCC-0.2V or VIN≦0.2V,
2.4
V
1
30
mA
10
mA
10
uA
o
1. Typical characteristics are at TA = 25 C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are
included.
Rev. 1.0
5
High Speed Super Low Power SRAM
WS6264
8K-Word By 8 Bit
DATA RETENTION CHARACTERISTICS
Name
VDR
ICCDR
TCDR
tR
Parameter
VCC for Data Retention
o
o
( TA = 0 ~70 C, Vcc = 5.0V) )
Test Condition
/CE1 ≧ VCC-0.2V,
VIN ≧
VCC-0.2V or VIN≦0.2V
MIN TYP(1) MAX
2.0
/CE1≧VCC-0.2V, VIN≧
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
Refer to
Retention Waveform
V
0.5
VCC-0.2V or VIN≦0.2V
Unit
5
uA
0
ns
tRC (2)
ns
o
1.TA = 25 C
2. tRC= .Read Cycle Time
LOW Vcc DATA RETENTION WAVEFORM(1) ( /CE1 Controlled )
VCC
tCDR
CE1
VIH
Data Retention Mode
VDR > 2.0V
CE1 > VCC - 0.2V
tR
VIH
Rev. 1.0
6
High Speed Super Low Power SRAM
WS6264
8K-Word By 8 Bit
LOW Vcc DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
VCC
tCDR
AC TEST CONDITIONS
Input Pulse Levels
Vcc/0V
Input Rise and Fall Times
Input and Output Timing
Reference Level
Output Load
tR
CE2 < 0.2v
VIL
CE2
Data Retention Mode
VDR > 2.0V
5ns
VIL
KEY TO SWITCHING WAVEFORMS
WAVEFORMS
INPUTS
OUTPUTS
MUST BE STEADY MUST BE STEADY
0.5Vcc
See FIGURE 1A
MAY CHANGE
FROM H TO L
WILL BE CHANGE FROM H
TO L
MAY CHANGE
FROM L TO H
WILL BE CHANGE FROM L
TO H
DON’T CARE ANY
CHANGE
PERMITTED
CHANGE STATE
UNKNOWN
DOES NOT APPLY
CENTER LINE IS HIGH
IMPEDANCE OFF STATE
and 1B
Rev. 1.0
7
High Speed Super Low Power SRAM
WS6264
8K-Word By 8 Bit
AC TEST LOADS AND WAVEFORMS
5V
5V
FIGURE 1A
1500Ω
5pF
1500Ω
OUTPUT
30pF
OUTPUT
3857Ω
INCLUDING
JIG AND
SCOPE
3857Ω
INCLUDING
JIG AND
SCOPE
FIGURE 1B
AC ELECTRICAL CHARACTERISTICS ( 0℃~70℃；Vcc=5V )
< READ CYCLE >
JEDEC
Name
Symbol
tAVAX
tRC
Read Cycle Time
tAVQV
tAA
Address Access Time
70
ns
tELQV
tACE
Chip Select Access Time
70
ns
tGLQV
tOE
Output Enable to Output Valid
40
ns
tELQX
tCLZ(5)
Chip Select to Output Low Z
10
ns
tGLQX
tOLZ(5)
Output Enable to Output in Low Z
5
ns
tEHQZ
tCHZ(5)
Chip Deselect to Output in High Z
0
35
ns
tGHQZ
tOHZ(5)
Output Disable to Output in High Z
0
30
ns
tAXOX
tOH
Address Change to Out Disable
10
Description
-70
MIN
MAX
70
Unit
ns
ns
Rev. 1.0
8
High Speed Super Low Power SRAM
8K-Word By 8 Bit
WS6264
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE 1 [1,2,4]
READ CYCLE 2 [1,3,4]
READ CYCLE 3
[1,4]
Rev. 1.0
9
High Speed Super Low Power SRAM
WS6264
8K-Word By 8 Bit
NOTES:
1. /WE is high in read Cycle.
2. Device is continuously selected when /CE1 = VIL and CE2=VIH.
3. Address valid prior to or coincident with /CE1 transition low and /or CE2 transition high.
4. /OE = VIL.
5. Transition is measured ±500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is
guaranteed but not 100% tested.
AC ELECTRICAL CHARACTERISTICS ( 0℃~70℃；Vcc=5V )
< WRITE CYCLE >
JEDEC
Name
Symbol
tAVAX
tWC
Write Cycle Time
70
ns
tE1LWH
tCW
Chip Select to End of Write
70
ns
tAVWL
tAS
Address Setup Time
0
ns
tAVWH
tAW
Address Valid to End of Write
70
ns
tWLWH
tWP
Write Pulse Width
50
ns
tWHAX
tWR
Write Recovery Time
0
ns
tWLQZ
tWHZ(10)
tDVWH
tDW
Data to Write Time Overlap
40
ns
tWHDX
tDH
Data Hold for Write End
0
ns
tGHQZ
tOHZ(10)
Output Disable to Output in High Z
0
tWHOX
tOW(10)
End of Write to Output Active
5
Description
-70
MIN
Write to Output in High Z
MAX
35
30
Unit
ns
ns
ns
Rev. 1.0
10
High Speed Super Low Power SRAM
8K-Word By 8 Bit
WS6264
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (Write Enable Controlled)
WRITE CYCLE2 (Chip Enable Controlled)
Rev. 1.0
11
High Speed Super Low Power SRAM
WS6264
8K-Word By 8 Bit
NOTES:
1. TAS is measured from the address valid to the beginning of write.
2. The internal write time of the memory is defined by the overlap of /CE1 and CE2 active and /WE
low. All signals must be active to initiate a write and any one signal can terminate a write by going
inactive. The data input setup and hold timing should be referenced to the second transition edge
of the signal that terminates the write.
3. TWR is measured from the earlier of /CE1 or /WE going high or CE2 going low at the end of write
cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to
the outputs must not be applied.
5. If the /CE1 low transition or CE2 high transition occurs simultaneously with the /WE low
transitions or after the /WE transition, output remain in a high impedance state.
6. /OE is continuously low (/OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If /CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data
input signals of opposite phase to the outputs must not be applied to them.
10. Transition is measured ±500mV from steady state with CL = 5pF as shown in Figure 1B. The
parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of /CE1 going low or CE2 going high to the end of write.
ORDER INFORMATION
WS6264LL X X X XX
LL: Low Low power
Package:
NormalFP: 28L SOP-330mil
P: 28L PDIP-600mil
Temperature:
Blank: 0~70°C
I: -40~85°C
Speed:
70: 70ns
Package Material:
-: Normal
R: Lead and Halogen Free
Rev. 1.0
12
High Speed Super Low Power SRAM
WS6264
8K-Word By 8 Bit
PACKAGE DIMENSIONS
28 pin SOP (330 mil) :
SYMBOL
b1
c
0.20
_
0.20 17.983 8.280 11.506 1.118 0.700 1.520
_
18.110 8.407 11.811 1.270 0.964 1.720
_
Nom. 2.692 0.226 2.489
0.35
_
Max. 2.844 0.350 2.616
0.50
0.45
0.32
0.28 18.237 8.534 12.116 1.422 1.228 1.920
0.1
_
Min.
mm
y
b
0.35
_
UNIT
A
A1
A2
2.540 0.102 2.362
c1
D
E
E1
e
L
L1
0.100 0.004 0.093 0.014 0.014 0.008 0.008 0.708 0.326 0.453 0.044 0.0276 0.0598
_
_
_
_
0.713 0.331 0.465 0.050 0.0380 0.0677
inch Nom. 0.106 0.009 0.098
Min.
0°
_
_
10°
0°
_
_
Max. 0.112 0.014 0.103 0.020 0.018 0.012 0.011 0.718 0.336 0.477 0.056 0.0484 0.0756 0.004
10°
28 pin PDIP (600mil):
SYM BOL
UNIT
A1
0.254
_
Nom.
_
M ax.
M in.
mm
0.010
_
Nom.
_
M ax.
M in.
inch
c
D
E
e
eB
S
Q1
1.778
1.651
3°
2.032
1.778
6°
2.286
1.905
9°
0.120
0.070
0.065
3°
0.130
0.080
0.070
6°
0.140
0.090
0.075
9°
L
A2
B
B1
3.683
0.330
1.270
3.810
0.457
1.524
3.937
0.584
1.778
2.540
0.254 37.084 15.240 13.818 (TYP) 16.256 3.302
16.764 3.556
0.356 37.211 15.494 13.920
0.145
0.013
0.050
0.006
1.455
0.590
0.540
0.150
0.018
0.060
0.010
1.460
0.600
0.544
0.155
0.023
0.070
0.014
1.465
0.610
0.548
E1
0.152 36.957 14.986 13.716
15.748 3.048
0.620
0.100
(TYP) 0.640
0.660
Rev. 1.0
13