LTC3220/LTC3220-1 360mA Universal 18-Channel LED Driver FEATURES DESCRIPTION n The LTC3220/LTC3220-1 are highly integrated multi-display LED drivers. These parts contain a high efficiency, low noise charge pump to provide power to up to eighteen universal LED current sources. The LTC3220/LTC3220-1 require only five small ceramic capacitors to form a complete LED power supply and current controller. n n n n n n n n n n n Eighteen 20mA Universal Current Sources with 64-Step Linear Brightness Control Independent On/Off, Brightness Level, Blinking and Gradation Control for Each Current Source Using 2-Wire I2C Interface Low Noise Multi-Mode Charge Pump (1x, 1.5x, 2x) Provides Up to 91% Efficiency Slew Limited Switching Reduces Conducted and Radiated Noise (EMI) Up to 360mA Total Output Current Internal Current Reference Single Reset Pin for Asynchronous Shutdown and Reset of All Data Registers Two I2C Addresses Are Available (LTC3220: 0011100, LTC3220-1: 0011101) Automatic or Forced Mode Switching Internal Soft-Start Limits Inrush Current Short-Circuit/Thermal Protection 4mm × 4mm Ultrathin (0.55mm) 28-Lead QFN Package n n The LTC3220/LTC3220-1 charge pump optimizes efficiency based on the voltage across the LED current sources. The part powers up in 1x mode and will automatically switch to boost mode whenever any enabled LED current source begins to enter dropout. The first dropout switches the parts into 1.5x mode and a subsequent dropout switches the LTC3220/LTC3220-1 into 2x mode. The parts reset to 1x mode whenever a data bit is updated via the I2C port. L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 6411531. APPLICATIONS n The LED currents are set by an internal precision current reference. Independent dimming, on/off, blinking and gradation control for all universal current sources is achieved via the I2C serial interface. 6-bit linear DACs are available to adjust brightness levels independently for each universal LED current source. Video Phones with QVGA+ Displays Keypad Lighting General/Miscellaneous Lighting TYPICAL APPLICATION 6-LED Main, 4 RGB LEDs C2 2.2μF C3 2.2μF C1P C1M C2P C2M VIN CPO C1 LTC3220 2.2μF LTC3220-1 VIN DVCC DVCC RESET RGB2 RGB3 RGB4 MAIN C4 4.7μF 18 ULED1-18 0.1μF I2C RGB1 3220 TA01 SCL/SDA RST GND 32201fb 1 LTC3220/LTC3220-1 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1, 4) C2M C1M VIN RST C2P C1P CPO TOP VIEW 28 27 26 25 24 23 22 ULED1 1 21 ULED18 ULED2 2 20 ULED17 ULED3 3 19 ULED16 ULED4 4 18 ULED15 29 ULED5 5 17 ULED14 ULED6 6 16 ULED13 ULED7 7 ULED11 ULED10 SDA SCL DVCC 9 10 11 12 13 14 ULED9 15 ULED12 8 ULED8 VIN, DVCC, CPO to GND ................................ –0.3V to 6V ULED1-ULED18 to GND ............................... –0.3V to 6V SDA, SCL, RST............................–0.3V to (DVCC + 0.3V) ICPO (Continuous) (Note 2) ..................................360mA IULED1-18 (Note 2) ..................................................25mA CPO Short-Circuit Duration .............................. Indefinite Operating Temperature Range (Note 3) LTC3220E/LTC3220E-1 ........................ –40°C to 85°C LTC3220I/LTC3220I-1 ........................ –40°C to 125°C Storage Temperature Range................... –65°C to 150°C PF PACKAGE 28-LEAD UTQFN (4mm s 4mm) TJMAX = 125°C, θJA = 37°C/W EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3220EPF#PBF LTC3220EPF#TRPBF LTC3220EPF-1#PBF LTC3220EPF-1#TRPBF 3220T 28-Lead UTQFN (4mm × 4mm) –40°C to 85°C 2201T 28-Lead UTQFN (4mm × 4mm) –40°C to 85°C LTC3220IPF#PBF LTC3220IPF#TRPBF 3220T 28-Lead UTQFN (4mm × 4mm) –40°C to 125°C LTC3220IPF-1#PBF LTC3220IPF-1#TRPBF 2201T 28-Lead UTQFN (4mm × 4mm) –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, DVCC = 3V, RST = high, C1 = C2 = C3 = 2.2μF, C4 = 4.7μF, unless otherwise noted. SYMBOL PARAMETER VIN Operating Voltage IVIN Operating Current DVCC UVLO Threshold DVCC Operating Voltage VIN UVLO Threshold CONDITIONS l MIN 2.9 ICPO = 0, 1x Mode ICPO = 0, 1.5x Mode ICPO = 0, 2x Mode TYP MAX 5.5 580 2.4 3.2 1 l 1.5 5.5 1.5 UNITS V μA mA mA V V V 32201fb 2 LTC3220/LTC3220-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, DVCC = 3V, RST = high, C1 = C2 = C3 = 2.2μF, C4 = 4.7μF, unless otherwise noted. SYMBOL PARAMETER VIN Shutdown Current DVCC Shutdown Current Universal LED Current, 6-Bit Linear DACs, ULED = 1V Full-Scale LED Current Minimum (ILSB) LED Current Step Minimum Programmable Current CONDITIONS l LED Current Matching LED Dropout Voltage Blink Rate Period ULED Up/Down Gradation Ramp Times REG19, D1 and D2 Gradation Period REG19, D1 and D2 Clock Frequency CPO Short-Circuit Detection Threshold Voltage Test Current SDA, SCL, RST VIL VIH IIH IIL Digital Output Low (SDA) VOL RST Timing Reset Pulse Duration Serial Port Timing (Notes 6, 7) Clock Operating Frequency fSCL Bus Free Time Between Stop and Start tBUF Condition Hold Time After (Repeated) Start Condition tHD,STA Repeated Start Condition Setup Time tSU,STA Stop Condition Setup Time tSU,STO TYP 3.2 MAX 7 1 18 20 0.314 0.395 22 l ULED Data Register Programmed to 0b00000001 Any Two Outputs, 50% of FS ILED = FS REG19, D3 and D4 VOL General Purpose Output Mode (GPO) LED Turn-On Delay Charge Pump (CPO) 1x Mode Output Impedance 1.5x Mode Output Impedance 2x Mode Output Impedance CPO Regulation Voltage MIN l 1.5 120 1.25 2.5 0.24 0.48 0.96 0.313 0.625 1.25 5 4 IOUT = 1mA, Single Output Enabled From Stop Bit, Part Enabled VIN = 3V, VCPO = 4.2V (Note 5) VIN = 3V, VCPO = 4.8V (Note 5) 1.5x Mode, ICPO = 20mA 2x Mode, ICPO = 20mA CPO = 0V l 0.65 l 0.4 10 l 0.6 3.6 4.1 4.5 5.03 0.85 l 0.410 0.820 1.640 0.7 • DVCC –1 l –1 l l 0.12 mA mA mA % mV Sec Sec Sec Sec Sec Sec Sec Sec mV μs 1.05 Ω Ω Ω V V MHz 1.3 30 V mA 0.3 • DVCC V V μA μA V ns l SDA, SCL, RST = DVCC SDA, SCL, RST = 0V IPULLUP = 3mA UNITS μA μA 1 1 0.4 10 1.3 400 kHz μs 0.6 0.6 0.6 μs μs μs 32201fb 3 LTC3220/LTC3220-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, DVCC = 3V, RST = high, C1 = C2 = C3 = 2.2μF, C4 = 4.7μF, unless otherwise noted. SYMBOL tHD,DAT(OUT) tHD,DAT(IN) tSU,DAT tLOW tHIGH tf tr tSP PARAMETER Data Hold Time Input Data Hold Time Data Setup Time Clock Low Period Clock High Period Clock Data Fall Time Clock Data Rise Time Spike Supression Time CONDITIONS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Based on long term current density limitations. Note 3: The LTC3220E/LTC3220E-1 are guaranteed to meet performance specifications from 0°C to 85°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3220I/LTC3220I-1 are guaranteed to meet performance specifications over the full –40°C to 125°C operating temperature range. MIN 0 0 100 1.3 0.6 20 20 1.5s 2x Mode CPO Ripple 2s 1s VCPO 20mV/DIV AC COUPLED VCPO 20mV/DIV AC COUPLED 250μs/DIV 300 300 50 UNITS ns ns ns μs μs ns ns ns TA = 25°C unless otherwise noted. 1.5x Mode CPO Ripple VCPO 1V/DIV VIN = 3.6V MAX 900 Note 4: These devices include overtemperature protection that is intended to protect the devices during momentary overload conditions. Junction temperatures will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may result in device degradation or failure. Note 5: 1.5x mode output impedance is defined as (1.5VIN – VCPO)/IOUT. 2x mode output impedance is defined as (2VIN – VCPO)/IOUT. Note 6: All values are referenced to VIH and VIL levels. Note 7: Guaranteed by design. TYPICAL PERFORMANCE CHARACTERISTICS Mode Switch Dropout Times TYP 3220 G01 VIN = 3.6V ICPO = 200mA CCPO = 4.7μF 500ns/DIV 3220 G02 VIN = 3.6V ICPO = 200mA CCPO = 4.7μF 500ns/DIV 3220 G03 32201fb 4 LTC3220/LTC3220-1 TYPICAL PERFORMANCE CHARACTERISTICS 1.5x Mode Charge Pump Open-Loop Output Resistance vs Temperature 1x Mode Switch Resistance vs Temperature 0.65 VIN = 3.6V 0.60 0.55 VIN = 3.9V 0.50 0.45 0.40 0.35 4.3 4.6 3.6V 4.1 3.9 3.5 3.3 3.1 2.9 4.9 5.2 4.7 5.1 4.5 5.0 4.3 4.9 3.9 3.5 3.6 800 2.9 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 4.2 3V 3.0 60 120 180 240 ICPO (mA) 300 770 760 TA = 85°C 730 2.9 360 TA = 125°C 3.55 4.2 4.85 DVCC CURRENT (μA) 5.5 VIN VOLTAGE (V) 3220 G09 1x Mode No Load VIN Current vs VIN Voltage 610 RST = SDA = DVCC 2.5 TA = 125°C 605 2.0 fSCL = 400kHz 1.5 fSCL = 100kHz 1.0 0.5 2.5 TA = –45°C 780 DVCC Current vs DVCC Voltage 3.5 TA = 25°C 3220 G08 7.5 360 740 0 VIN Shutdown Current vs VIN Voltage TA = –40°C 300 750 3220 G07 4.5 180 240 ICPO (mA) 790 3.2V 3.1V 4.5 4.3 TA = 25°C 120 3220 G06 3.3V-3.6V 4.6 3.1 5.5 60 Oscillator Frequency vs VIN Voltage 4.7 4.4 TA = 85°C 0 810 4.8 3.3 6.5 4.0 2x Mode CPO Voltage vs ICPO CPO VOLTAGE (V) OPEN-LOOP OUTPUT RESISTANCE (Ω) 2x Mode Charge Pump Open-Loop Output Resistance vs Temperature 3.7 3V 3.1V 3.2V 3.3V 3.4V 3220 G05 3220 G04 4.1 4.2 3.8 2.5 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 0.30 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 3.5V 4.4 2.7 FREQUENCY (kHz) VIN = 3.3V VIN CURRENT (μA) 0.70 CPO VOLTAGE (V) OPEN-LOOP OUTPUT RESISTANCE (Ω) 0.75 VIN SHUTDOWN CURRENT (μA) 1.5x Mode CPO Voltage vs ICPO 4.8 4.5 0.80 SWITCH RESISTANCE (Ω) TA = 25°C unless otherwise noted. 600 595 590 585 fSCL = 10kHz 0 1.5 2.9 3.55 4.2 VOLTAGE (V) 4.85 5.5 3220 G10 580 1.5 2.5 3.5 4.5 DVCC VOLTAGE (V) 5.5 3220 G11 2.9 3.55 4.2 4.85 VIN VOLTAGE (V) 5.5 3220 G12 32201fb 5 LTC3220/LTC3220-1 TYPICAL PERFORMANCE CHARACTERISTICS 2x Mode VIN Current vs ICPO (IVIN – 2ICPO) 16 14 14 12 VIN CURRENT (mA) VIN CURRENT (mA) 12 10 8 6 ULED Pin Current vs ULED Pin Voltage 25 ULED PIN CURRENT (mA) 1.5x Mode VIN Current vs ICPO (IVIN – 1.5ICPO) TA = 25°C unless otherwise noted. 10 8 6 4 4 20 15 10 5 2 2 0 0 60 120 240 180 ICPO (mA) 0 300 360 0 60 120 240 180 ICPO (mA) 300 3220 G13 360 0 0 0.1 0.05 0.15 ULED PIN VOLTAGE (V) 3220 G14 0.2 3220 G15 18-LED ULED Display Efficiency vs VIN Voltage ULED Current vs Input Code 25 100 ULED EFFICIENCY (PLED/PIN) (%) 90 ULED CURRENT (mA) 20 15 10 5 80 70 60 50 40 30 20 10 0 0 09 24 1B 12 2D INPUT CODE (HEX) 36 3F 0 2.9 3.225 3.55 3.875 4.2 4.525 4.85 5.175 5.5 VIN VOLTAGE (V) 3220 G17 3220 G16 PIN FUNCTIONS ULED1-ULED18 (Pins 1-9,13-21): Current Source Outputs for Driving LEDs. The LED current can be set from 0mA to 20mA in 64 steps via software control and internal 6-bit linear DAC. Each output can be disabled by setting the associated data register REG1 to REG18 low. ULED1 to ULED18 can also be used as I2C controlled open-drain general purpose outputs. Connect unused outputs to ground. DVCC (Pin 10): Supply Voltage for All digital I/O lines. This pin sets the logic reference level of the LTC3220/LTC3220-1. DVCC will reset the data registers when set below the undervoltage lockout threshold. A 0.1μF X5R or X7R ceramic capacitor should be connected to ground. SCL (Pin 11): I2C Clock Input. The logic level for SCL is referenced to DVCC. 32201fb 6 LTC3220/LTC3220-1 PIN FUNCTIONS SDA (Pin 12): Input Data for the Serial Port. Serial data is shifted in one bit per clock cycle to control the LTC3220/ LTC3220-1. The logic level is referenced to DVCC. RST (Pin 25): Active Low Reset Input. RST Resets all internal registers and forces LTC3220/LTC3220-1 into shutdown mode. C1P, C2P, C1M, C2M (Pins 27, 26, 23, 22): Charge Pump Flying Capacitor Pins. A 2.2μF X7R or X5R ceramic capacitor should be connected from C1P to C1M and C2P to C2M. CPO (Pin 28): Output of the Charge Pump. Used to power all LEDs. A 4.7μF X5R or X7R ceramic capacitor should be connected to ground. VIN (Pin 24): Supply Voltage for the Entire Device. This pin must be bypassed with a single 2.2μF low ESR ceramic capacitor. Exposed Pad (Pin 29): Ground. The Exposed Pad must be soldered to PCB ground. BLOCK DIAGRAM 27 23 C1P 26 C1M 22 C2P EXPOSED PAD C2M 850kHz OSCILLATOR CPO CHARGE PUMP 24 VIN ULED1 ULED2 1.22V + – ULED3 ULED4 ULED5 18 10 ULED6 18 UNIVERSAL CURRENT SOURCES AND DACS DVCC ULED7 ULED8 25 RST CONTROL LOGIC 29 28 1 2 3 4 5 6 7 8 MASTER/SLAVE REG 12 11 SDA SHIFT REGISTER SCL ULED18 ULED17 ULED16 ULED15 ULED14 ULED13 ULED12 21 20 19 18 17 16 15 ULED11 14 ULED9 ULED10 13 9 3220 BD 32201fb 7 LTC3220/LTC3220-1 OPERATION Power Management Soft-Start The LTC3220/LTC3220-1 use a switched capacitor charge pump to boost CPO as much as 2 times the input voltage up to 5.1V. The part starts up in 1x mode. In this mode, VIN is connected directly to CPO. This mode provides maximum efficiency and minimum noise. The LTC3220/ LTC3220-1 will remain in 1x mode until an LED current source drops out. Dropout occurs when a current source voltage becomes too low for the programmed current to be supplied. When dropout is detected, the LTC3220/ LTC3220-1 will switch into 1.5x mode. The CPO voltage will then start to increase and will attempt to reach 1.5× VIN up to 4.6V. Any subsequent dropout will cause the part to enter the 2x mode. The CPO voltage will attempt to reach 2× VIN up to 5.1V. Initially, when the part is in shutdown, a weak switch connects VIN to CPO. This allows VIN to slowly charge the CPO output capacitor and prevent large charging currents from occurring. The LTC3220/LTC3220-1 also employ a soft-start feature on the charge pump to prevent excessive inrush current and supply droop when switching into the step-up modes. The current available to the CPO pin is increased linearly over a typical period of 125μs. Soft-start occurs at the start of both 1.5x and 2x mode changes. Charge Pump Strength When the LTC3220/LTC3220-1 operate in either 1.5x mode or 2x mode, the charge pump can be modeled as a Thevenin-equivalent circuit to determine the amount of current available from the effective input voltage and effective open-loop output resistance, ROL (Figure 1). A 2-phase non-overlapping clock activates the charge pump switches. In the 2x mode the flying capacitors are charged on alternate clock phases from VIN to minimize CPO voltage ripple. In 1.5x mode the flying capacitors are charged in series during the first clock phase and stacked in parallel on VIN during the second phase. This sequence of charging and discharging the flying capacitors continues at a constant frequency of 850kHz. ROL is dependent on a number of factors including the switching term, 1/(2fOSC • CFLY), internal switch resistances and the non-overlap period of the switching circuit. However, for a given ROL, the amount of current available will be directly proportional to the advantage voltage of 1.5VIN – CPO for 1.5x mode and 2VIN – CPO for 2x mode. Consider the example of driving LEDs from a 3.1V supply. The current delivered by each LED current source is controlled by an associated DAC. Each DAC is programmed via the I2C port. ROL + – + 1.5VIN OR 2VIN CPO – 3220 F01 Figure 1. Charge Pump Open-Loop Thevenin Equivalent Circuit 32201fb 8 LTC3220/LTC3220-1 OPERATION If the LED forward voltage is 3.8V and the current sources require 100mV, the advantage voltage for 1.5x mode is 3.1V • 1.5 – 3.8V – 0.1V or 750mV. Notice that if the input voltage is raised to 3.2V, the advantage voltage jumps to 900mV, a 20% improvement in available strength. From Figure 1, for 1.5x mode the available current is given by: IOUT = 1.5VIN − VCPO ROL (1) For 2x mode, the available current is given by: IOUT = 2VIN − VCPO ROL (2) Notice that the advantage voltage in this case is 3.1V • 2 – 3.8V – 0.1V = 2.3V. ROL is higher in 2x mode but a significant overall increase in available current is achieved. Mode Switching The LTC3220/LTC3220-1 will automatically switch from 1x mode to 1.5x mode and subsequently to 2x mode whenever a dropout condition is detected at an LED pin. Dropout occurs when a current source voltage becomes too low for the programmed current to be supplied. The mode change will not occur unless dropout exists for approximately 400μs. The mode will automatically switch back to 1x whenever a register is updated via the I2C port, when gradation completes ramping down and after each blink period. The parts can be forced to operate in 1x, 1.5x or 2x mode by writing the appropriate bits into REG0. This feature may be used for operating loads powered by CPO. Non-programmed current sources do not affect dropout. Universal Current Sources (ULED1 to ULED18) There are eighteen universal 20mA current sources. Each current source has a 6-bit linear DAC for current control. The output current range is 0mA to 20mA in 64 steps. Each current source is disabled when an all zero data word is written. The supply current for that source is reduced to zero. Unused outputs should be connected to GND. GPO Mode ULED1 to ULED18 can be used as general purpose outputs (GPO). Current sources in the GPO mode can be used as I2C controlled open-drain drivers. A ULED output can be selected to operate in GPO mode by programming both Bit 6 and Bit 7 of its data register (REG1 to REG18) to a logic high. In the GPO mode, dropout detection is disabled and output swings to ground will not cause mode switching. The GPOs can be programmed to either act as a switch (strong pull-down mode) in which the part will only consume approximately 3μA of quiescent current, or they can be programmed to have a regulated current of up to 20mA (current limit mode), which would require several hundred microamps of additional quiescent current. When a ULED output is used in GPO mode during shutdown, CPO should not be used as a power source since the current available from the CPO pin would be limited by the weak pull-up current source. This weak pull-up is only meant to keep the output capacitor charged to VIN during shutdown and is unable to supply large amounts of current. CPO can, however, be used as a power source when the part is enabled. Conversely, when a ULED output is used in GPO strong pull-down mode, a current limiting resistor should be used in series with the ULED output so that the current does not exceed the Absolute Maximum rated current. 32201fb 9 LTC3220/LTC3220-1 OPERATION Blinking Each universal output (ULED1 to ULED18) can be set to blink with an on time of 0.156 seconds, or 0.625 seconds and a period of 1.25 seconds, or 2.5 seconds via the I2C port. The blinking rate is selected via REG19 and ULED outputs are selected via REG1 to REG18. Blinking and gradation rates are independent. Please refer to Application Note 115 for detailed information and examples on programming blinking. Gradation Universal LED outputs ULED1 to ULED18 can be set to have the current ramp up and down at 0.24 seconds, 0.48 seconds and 0.96 seconds rates via the I2C port. Each of these outputs can have either blinking or gradation enabled. The gradation time is set via REG19 and ULED outputs are selected via REG1 to REG18. The ramp direction is also controlled via REG19. Setting the up bit high causes gradation to ramp up, setting this bit to a low causes gradation to ramp down. Please refer to Application Note 115 for detailed information and examples on programming gradation. When gradation is disabled the LED output current remains at the programmed value. The charge pump mode is reset to 1x mode after gradation completes ramping down. Chip Reset (RST) The RST pin is used to turn off the chip, including the charge pump and all ULED outputs, and clear all registers in the LTC3220/LTC3220-1. When RST is low, the part is in shutdown and cannot be programmed through the I2C port. Shutdown Current Shutdown occurs when all the current source data bits have been written to zero, when the shutdown bit in REG0 is written with a logic 1, when RST is pulled low, or when DVCC is set below the undervoltage lockout voltage. Although the LTC3220/LTC3220-1 are designed to have very low shutdown current, they will draw about 3μA from VIN when in shutdown. Internal logic ensures that the LTC3220/LTC3220-1 are in shutdown when DVCC is low. Note, however that all of the logic signals that are referenced to DVCC (SCL, SDA and RST) will need to be at DVCC or below (i.e., ground) to avoid violation of the absolute maximum specifications on these pins. EMI Reduction The flying capacitor pins C1M, C1P, C2M and C2P have controlled slew rates to reduce conducted and radiated noise. Serial Port The microcontroller compatible I2C serial port provides all of the command and control inputs for the LTC3220/ LTC3220-1. Data on the SDA input is loaded on the rising edge of SCL. D7 is loaded first and D0 last. There are 20 data registers, one address register and one sub-address register. Once all address bits have been clocked into the address register, an acknowledge occurs. The 32201fb 10 LTC3220/LTC3220-1 OPERATION sub-address register is then written to, followed by the data register. Each data register has a sub-address. After the data register has been written a load pulse is created after the stop bit. The load pulse transfers all of the data held in the data registers to the DAC registers. The stop bit can be delayed until all of the data master registers have been written. At this point the LED current will be changed to the new settings. The serial port uses static logic registers so there is no minimum speed at which it can be operated. when the bus is not in use. External pull-up resistors or current sources, such as the LTC1694 SMBus accelerator, are required on these lines. The LTC3220/LTC3220-1 are receive-only (slave) devices. There are two I2C addresses available. The LTC3220 I2C address is 0011100 and the LTC3220-1 I2C address is 0011101. The I2C address is the only difference between the LTC3220 and LTC3220-1. Write Word Protocol Used By the LTC3220/LTC3220-1 I2C Interface 1 The LTC3220/LTC3220-1 communicate with a host (master) using the standard I2C 2-wire interface. The Timing Diagram (Figure 3) shows the timing relationship of the signals on the bus. The two bus lines, SDA and SCL, must be high 7 1 1 8 S Slave Address Wr A *Sub-Address A 0 ADDRESS 0 1 1 1 1 1 Data Byte A P** DATA BYTE WR 0 0 ADDRESS LTC3220-1 8 S = Start Condition, Wr = Write Bit = 0, A = Acknowledge, P = Stop Condition *The sub-address uses only the first 5 bits, D0, D1, D2, D3 and D4. **Stop can be delayed until all of the data registers have been written. SUB-ADDRESS LTC3220 1 0 S7 S6 S5 S4 S3 S2 S1 S0 7 6 5 4 3 2 1 0 WR 0 0 1 1 1 0 1 0 SDA 0 0 1 1 1 0 0 0 ACK S7 S6 S5 S4 S3 S2 S1 S0 ACK 7 6 5 4 3 2 1 0 ACK SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 START STOP 9 3220 FO2 Figure 2. Bit Assignments SDA tBUF tSU, STA tSU, DAT tLOW tHD, STA tHD, DAT tSU, STO 3220 F03 SCL t tHIGH HD, STA START CONDITION tr tSP tf REPEATED START CONDITION STOP CONDITION START CONDITION Figure 3. Timing Parameters 32201fb 11 LTC3220/LTC3220-1 OPERATION Sub-Address Byte MSB LSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register Function 0 REG0 COMMAND 1 REG1 ULED1 0 REG2 ULED2 1 REG3 ULED3 0 0 REG4 ULED4 1 0 1 REG5 ULED5 1 1 0 REG6 ULED6 0 1 1 1 REG7 ULED7 1 0 0 0 REG8 ULED8 1 0 0 1 REG9 ULED9 0 0 0 0 1 0 1 0 REG10 ULED10 0 0 0 0 1 0 1 1 REG11 ULED11 0 0 0 0 1 1 0 0 REG12 ULED12 0 0 0 0 1 1 0 1 REG13 ULED13 0 0 0 0 1 1 1 0 REG14 ULED14 0 0 0 0 1 1 1 1 REG15 ULED15 0 0 0 1 0 0 0 0 REG16 ULED16 0 0 0 1 0 0 0 1 REG17 ULED17 0 0 0 1 0 0 1 0 REG18 ULED18 0 0 0 1 0 0 1 1 REG19 GRAD/ BLINK REG0, Command Byte. Register Sub-Address = 0000 MSB LSB D7 D6 D5 D4 D3 D2 D1 D0 Unused Unused Unused Unused Shutdown Force2x Force1p5x Quick write Quick write 0 1 Serial write to each register Parallel write, REG1 data is written to all eighteen universal registers Force1p5 1 0 Forces charge pump into 1.5x mode Enables mode logic to control mode changes based on dropout signal Force2x 1 0 Forces charge pump into 2x mode Enables mode logic to control mode changes based on dropout signal Force1x Shutdown D2 (Force1p5x) = 1 D3 (Force2x) = 1 1 0 Forces Charge Pump into 1x Mode Shuts down part while preserving data in registers Normal operation 32201fb 12 LTC3220/LTC3220-1 OPERATION Data Bytes REG1 to REG18, Universal LED 6-bit linear DAC data with blink/gradation. Sub-Address 00001 to 10010 per Sub-Address Table Blink/Gradation/Dropout Enable LED Current Data MSB LSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 1 0 1 0 D5 D5 D5 D4 D4 D4 D3 D3 D3 D2 D2 D2 D1 D1 D1 D0 D0 D0 1 1 0 1 1 0 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 0 Normal Blink Enabled Gradation Enabled GPO Mode* Strong Pull-Down Mode Current Limited Mode High Impedance/Off *(Gradation/Blink/Dropout Off) REG19, Gradation and Blinking MSB LSB D7 D6 D5 D4 D3 D2 D1 D0 Unused Unused Unused GB4 GB3 GB2 GB1 Up Up 0 1 Gradation counts down Gradation counts up Blink Times and Period Gradation Ramp Times and Period D4 (GB4) D3 (GB3) On Time Period D2 (GB2) D1 (GB1) Ramp Time Period 0 0 1 1 0 1 0 1 0.625s 0.156s 0.625s 0.156s 1.25s 1.25s 2.5s 2.5s 0 0 1 1 0 1 0 1 Disabled 0.24s 0.48s 0.96s Disabled 0.313s 0.625s 1.25s 32201fb 13 LTC3220/LTC3220-1 OPERATION Bus Speed Acknowledge The I2C port is designed to be operated at speeds up to 400kHz. It has built-in timing delays to ensure correct operation when addressed from an I2C compliant master device. It also contains input filters designed to suppress glitches should the bus become corrupted. The Acknowledge signal is used for handshaking between the master and the slave. An Acknowledge (active low) generated by the slave (LTC3220/LTC3220-1) lets the master know that the latest byte of information was received. The Acknowledge related clock pulse is generated by the master. The master releases the SDA line (high) during the Acknowledge clock cycle. The slave-receiver must pull down the SDA line during the Acknowledge clock pulse so that it remains a stable low during the high period of this clock pulse. Start and Stop Conditions A bus-master signals the beginning of a communication to a slave device by transmitting a Start condition. A Start condition is generated by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a Stop condition by transitioning SDA from low to high while SCL is high. The bus is then free for communication with another I2C device. Byte Format Each byte sent to the LTC3220/LTC3220-1 must be 8 bits long followed by an extra clock cycle for the Acknowledge bit to be returned by the LTC3220/LTC3220-1. The data should be sent to the LTC3220/LTC3220-1 most significant bit (MSB) first. Slave Address Each version of LTC3220/LTC3220-1 responds to a unique address which has been factory programmed (Table 1). The eighth bit of the address byte (R/W) must be 0 for the LTC3220/LTC3220-1 to recognize the address since it is a write only device. This effectively forces the address to be 8 bits long where the least significant bit of the address is 0. If the correct seven bit address is given but the R/W bit is 1, the LTC3220/LTC3220-1 will not respond. Table 1. LTC3220/LTC3220-1 Factory Programmed Slave Address PART NUMBER SLAVE ADDRESS LTC3220 0011100 LTC3220-1 0011101 32201fb 14 LTC3220/LTC3220-1 OPERATION Bus Write Operation The master initiates communication with the LTC3220/ LTC3220-1 with a Start condition and a 7-bit address followed by the Write Bit R/W = 0. If the address matches that of the LTC3220/LTC3220-1, the LTC3220/LTC3220-1 return an Acknowledge. The master should then deliver the most significant sub-address byte for the data register to be written. Again the LTC3220/LTC3220-1 acknowledge and then the data is delivered starting with the most significant bit. This cycle is repeated until all of the required data registers have been written. Any number of data latches can be written. Each data byte is transferred to an internal holding latch upon the return of an Acknowledge. After all data bytes have been transferred to the LTC3220/LTC3220-1, the master may terminate the communication with a Stop condition. Alternatively, a Repeat-Start condition can be initiated by the master and another chip on theI2C bus can be addressed. This cycle can continue indefinitely and the LTC3220/LTC3220-1 will remember the last input of valid data that it received. Once all chips on the bus have been addressed and sent valid data, a global Stop condition can be sent and the LTC3220/LTC3220-1 will update all registers with the data that it had received. In certain circumstances the data on the I2C bus may become corrupted. In these cases the LTC3220/LTC3220-1 respond appropriately by preserving only the last set of complete data that it has received. For example, assume the LTC3220/LTC3220-1 has been successfully addressed and is receiving data when a Stop condition mistakenly occurs. The LTC3220/LTC3220-1 will ignore this Stop condition and will not respond until a new Start condition, correct address, sub-address and new set of data and Stop condition are transmitted. Likewise, if the LTC3220/LTC3220-1 were previously addressed and sent valid data but not updated with a Stop, they will respond to any Stop that appears on the bus with only one exception, independent of the number of RepeatStart’s that have occurred. If a Repeat-Start is given and the LTC3220/LTC3220-1 successfully acknowledge their addresses and first byte, they will not respond to a Stop until all bytes of the new data have been received and acknowledged. Quick Write Registers REG1 to REG18 can be written in parallel by setting Bit 0 of REG 0 high. When this bit is set high the next write sequence to REG1 will write the data to REG1 through REG18, which are all of the universal LED registers. 32201fb 15 LTC3220/LTC3220-1 APPLICATIONS INFORMATION VIN, CPO Capacitor Selection The style and value of the capacitors used with the LTC3220/ LTC3220-1 determine several important parameters such as regulator control loop stability, output ripple, charge pump strength and minimum start-up time. To reduce noise and ripple, it is recommended that low equivalent series resistance (ESR) ceramic capacitors are used for both CVIN and CCPO. Tantalum and aluminum capacitors are not recommended due to high ESR. The value of CCPO directly controls the amount of output ripple for a given load current. Increasing the size of CCPO will reduce output ripple at the expense of higher start-up current. The peak-to-peak output ripple of the 1.5x mode is approximately given by the expression: VRIPPLEP-P = IOUT 3fOSC • CCPO (3) where fOSC is the LTC3220/LTC3220-1 oscillator frequency or typically 850kHz and CCPO is the output storage capacitor. The output ripple in 2x mode is very small due to the fact that load current is supplied on both cycles of the clock. Both type and value of the output capacitor can significantly affect the stability of the LTC3220/LTC3220-1. As shown in the Block Diagram, the LTC3220/LTC3220-1 use a control loop to adjust the strength of the charge pump to match the required output current. The error signal of the loop is stored directly on the output capacitor. The output capacitor also serves as the dominant pole for the control loop. To prevent ringing or instability, it is important for the output capacitor to maintain at least 3.2μF of capacitance over all conditions and the ESR should be less than 80mΩ. Multilayer ceramic chip capacitors typically have exceptional ESR performance. MLCCs combined with a tight board layout will result in very good stability. As the value of CCPO controls the amount of output ripple, the value of CVIN controls the amount of ripple present at the input pin (VIN). The LTC3220/LTC3220-1 input current will be relatively constant while the charge pump is either in the input charging phase or the output charging phase but will drop to zero during the clock nonoverlap times. Since the nonoverlap time is small (~25ns), these missing “notches” will result in only a small perturbation on the input power supply line. Note that a higher ESR capacitor such as tantalum will have higher input noise due to the higher ESR. Therefore, ceramic capacitors are recommended for low ESR. Input noise can be further reduced by powering the LTC3220/LTC3220-1 through a very small series inductor as shown in Figure 4. A 10nH inductor will reject the fast current notches, thereby presenting a nearly constant current load to the input power supply. For economy, the 10nH inductor can be fabricated on the PC board with about 1cm (0.4") of PC board trace. VBAT LTC3220 LTC3220-1 GND 3220 F04 Figure 4. 10nH Inductor Used for Input Noise Reduction (Approximately 1cm of Board Space) 32201fb 16 LTC3220/LTC3220-1 APPLICATIONS INFORMATION Flying Capacitor Selection Warning: Polarized capacitors such as tantalum or aluminum should never be used for the flying capacitors since their voltage can reverse upon start-up of the LTC3220/LTC3220-1. Ceramic capacitors should always be used for the flying capacitors. The flying capacitors control the strength of the charge pump. In order to achieve the rated output current it is necessary to have at least 1.6μF of capacitance for each of the flying capacitors. Capacitors of different materials lose their capacitance with higher temperature and voltage at different rates. For example, a ceramic capacitor made of X7R material will retain most of its capacitance from –40°C to 85°C, whereas a Z5U or Y5V style capacitor will lose considerable capacitance over that range. Z5U and Y5V capacitors may also have a very poor voltage coefficient causing them to lose 60% or more of their capacitance when the rated voltage is applied. Therefore, when comparing different capacitors, it is often more appropriate to compare the amount of achievable capacitance for a given case size rather than comparing the specified capacitance value. For example, over rated voltage and temperature conditions, a 1μF, 10V, Y5V ceramic capacitor in a 0603 case may not provide any more capacitance than a 0.22μF, 10V, X7R available in the same case. The capacitor manufacturer’s data sheet should be consulted to determine what value of capacitor is needed to ensure minimum capacitances at all temperatures and voltages. Table 2 shows a list of ceramic capacitor manufacturers and how to contact them: Table 2. Recommended Capacitor Vendors AVX www.avxcorp.com Kemet www.kemet.com Murata www.murata.com Taiyo Yuden www.t-yuden.com Vishay www.vishay.com Layout Considerations and Noise The LTC3220/LTC3220-1 have been designed to minimize EMI. However due to their high switching frequency and the transient currents produced by the LTC3220/LTC3220-1, careful board layout is necessary. A true ground plane and short connections to all capacitors will improve performance and ensure proper regulation under all conditions. The flying capacitor pins C1P, C2P, C1M and C2M have controlled edge rate waveforms. The large dv/dt on these pins can couple energy capacitively to adjacent PCB runs. Magnetic fields can also be generated if the flying capacitors are not close to the LTC3220/LTC3220-1 (i.e., the loop area is large). To decouple capacitive energy transfer, a Faraday shield may be used. This is a grounded PCB trace between the sensitive node and the LTC3220/LTC3220-1 pins. For a high quality AC ground, it should be returned to a solid ground plane that extends all the way to the LTC3220/LTC3220-1. 32201fb 17 LTC3220/LTC3220-1 APPLICATIONS INFORMATION Power Efficiency To calculate the power efficiency (η) of an LED driver chip, the LED power should be compared to the input power. The difference between these two numbers represents lost power whether it is in the charge pump or the current sources. Stated mathematically, the power efficiency is given by: η= PLED PIN ηIDEAL = (4) The efficiency of the LTC3220/LTC3220-1 depends upon the mode in which it is operating. Recall that the LTC3220/ LTC3220-1 operate as pass switches, connecting VIN to CPO, until dropout is detected at the ILED pin. This feature provides the optimum efficiency available for a given input voltage and LED forward voltage. When it is operating as a switch, the efficiency is approximated by: P V •I V η = LED = LED LED = LED PIN VIN •IIN VIN In 1.5x boost mode, the efficiency is similar to that of a linear regulator with an effective input voltage of 1.5 times the actual input voltage. This is because the input current for a 1.5x charge pump is approximately 1.5 times the load current. In an ideal 1.5x charge pump, the power efficiency would be given by: (5) since the input current will be very close to the sum of the LED currents. At moderate to high output power, the quiescent current of the LTC3220/LTC3220-1 is negligible and the expression above is valid. Once dropout is detected at any LED pin, the LTC3220/ LTC3220-1 enable the charge pump in 1.5x mode. PLED V •I V = LED LED = LED PIN VIN • 1.5 •ILED 1.5 • VIN Similarly, in 2x boost mode, the efficiency is similar to that of a linear regulator with an effective input voltage of 2 times the actual input voltage. In an ideal 2x charge pump, the power efficiency would be given by: ηIDEAL = PLED VLED •ILED V = = LED PIN VIN • 2 •ILED 2 • VIN Thermal Management For higher input voltages and maximum output current, there can be substantial power dissipation in the LTC3220/ LTC3220-1. If the junction temperature increases above approximately 150°C, the thermal shutdown circuitry will automatically deactivate the output current sources and charge pump. To reduce maximum junction temperature, a good thermal connection to the PC board is recommended. Connecting the Exposed Pad to a ground plane and maintaining a solid ground plane under the device will reduce the thermal resistance of the package and PC board considerably. 32201fb 18 LTC3220/LTC3220-1 PACKAGE DESCRIPTION PF Package 28-Lead UTQFN (4mm × 4mm) (Reference LTC DWG # 05-08-1759 Rev Ø) 0.70 ±0.05 2.64 ± 0.05 2.40 REF 4.50 ± 0.05 3.10 ± 0.05 2.64 ± 0.05 PACKAGE OUTLINE 0.20 ±0.05 0.40 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 ± 0.10 BOTTOM VIEW—EXPOSED PAD 0.55 ± 0.05 R = 0.05 TYP R = 0.10 TYP 27 28 0.40 ± 0.5 PIN 1 TOP MARK (NOTE 6) 1 2.64 ± 0.10 4.00 ± 0.10 PIN 1 NOTCH R = 0.20 TYP OR 0.25 × 45° CHAMFER 2 2.40 REF 2.64 ± 0.10 (PF28) UTQFN 0907 0.127 REF NOTE: 0.00 – 0.05 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.20 ± 0.05 0.40 BSC 32201fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC3220/LTC3220-1 TYPICAL APPLICATION Cellular Phone Multi-Display LED Controller with Auxiliary Current Source Output 2.2μF VIN 2.2μF C1P C1M C2P C2M VIN CPO 2.2μF LTC3220 LTC3220-1 DVCC DVCC CAM MAIN RGB BLINKING STATUS INDICATORS GPO 1, 2, 3 VIN 60mA 4.7μF 18 100k GPO4 ULED1-18 3220 TA02 0.1μF I2C SCL/SDA RST GND RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC3205 250mA, 1MHz, Multi-Display LED Controller VIN: 2.8V to 4.5V, VOUT(MAX) = 5.5V, IQ = 50μA, ISD < 1μA, QFN Package LTC3206 400mA, 800kHz, Multi-Display LED Controller VIN: 2.8V to 4.5V, VOUT(MAX) = 5.5V, IQ = 50μA, ISD < 1μA, QFN Package LTC3207 VBAT: 2.9V to 5.5V, 12 Universal Individually Controlled LED Drivers, One Camera Driver, 4mm × 4mm QFN Package High Current Software Configurable Multi-Display VIN: 2.9V to 4.5V, VOUT(MAX) = 5.5V, IQ = 250μA, ISD < 3μA, 17 Current Sources (MAIN, SUB, RGB, CAM, AUX), 5mm × 5mm QFN Package LED Controller 600mA MAIN/Camera/AUX LED Controller VIN: 2.9V to 4.5V, IQ = 400mA, Up to 94% Efficiency, 4mm × 4mm QFN-20 Package MAIN/CAM LED Controller in 3mm × 3mm QFN VIN: 2.9V to 4.5V, IQ = 400μA, 3-Bit DAC Brightness Control for MAIN and CAM LEDs, 3mm × 3mm QFN Package MAIN/CAM LED Controller with 64-Step 6-Bit DAC Brightness Control for MAIN and 3-Bit Brightness Control for CAM, Brightness Control 3mm × 3mm QFN Package MAIN/CAM LED Controller with 32-Step Drives 4 MAIN LEDs, 3mm × 3mm QFN Package Brightness Control MAIN/CAM LED Controller with 32-Step Drives 3 MAIN LEDs, 3mm × 3mm QFN Package Brightness Control RGB LED Driver and Charge Pump Drives RGB LEDs, 25mA/LED × 3, VIN Range: 2.9V to 4.5V, 2mm × 3mm DFN Package 500mA Camera LED Charge Pump VIN: 2.9V to 4.5V, Single Output, 3mm × 3mm DFN Package 600mA Universal Multi-Output LED/CAM Driver LTC3208 LTC3209-1/ LTC3209-2 LTC3210 LTC3210-1 LTC3210-2 LTC3210-3 LTC3212 LTC3214 LTC3215 LTC3217 700mA Low Noise High Current LED Charge Pump 1A Low Noise High Current LED Charge Pump with Independent Flash/Torch Current Control 600mA Low Noise Multi-LED Camera Light LTC3218 400mA Single-Wire Camera LED Charge Pump LTC3219 250mA Universal Multi-Output LED Driver LTC3440/LTC3441 600mA/1.2A IOUT, 2MHz/1MHz, Synchronous Buck-Boost DC/DC Converter 600mA/1.2A IOUT, 600kHz, Synchronous Buck-Boost DC/DC Converter 1MHz, 800mA Synchronous Buck-Boost High Power LED Driver LTC3216 LTC3443 LTC3453 VIN: 2.9V to 4.4V, VOUT(MAX) = 5.5V, IQ = 300μA, ISD < 2.5μA, DFN Package VIN: 2.9V to 4.4V, VOUT(MAX) = 5.5V, IQ = 300μA, ISD < 2.5μA, DFN Package VIN: 2.9V to 4.4V, IQ = 400μA, Four 100mA Outputs, QFN Package 91% Efficiency, VIN Range: 2.9V to 4.5V, 2mm × 3mm DFN Package, High Side Current Sense VBAT 2.9V to 5.5V, Nine Universal Individually Controlled LED Drivers, 3mm × 3mm QFN Package VIN: 2.4V to 5.5V, VOUT(MAX) = 5.25V, IQ = 25μA/50μA, ISD <1μA, MS/DFN Packages VIN: 2.4V to 5.5V, VOUT(MAX) = 5.25V, IQ = 28μA, ISD <1μA, DFN Package VIN(MIN): 2.7V to 5.5V, VIN(MAX): 2.7V to 4.5V, IQ = 2.5mA, ISD < 6μA, QFN Package 32201fb 20 Linear Technology Corporation LT 0908 REV B • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2007