PERICOM PI3B16232

PI3B16232
3.3V, Synchronous 16-Bit to 32-Bit
FET Mux/Demux BusSwitch
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PI3B16232
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3.3V, Synchronous 16-Bit to 32-Bit FET
Mux/Demux BusSwitch
Product Features
Product Description
• Near-Zero propagation delay.
Pericom Semiconductor’s PI3B series of logic circuits are produced
using the company's advanced 0.35micron CMOS technology.
• 5Ω Switches Connect Between Two Ports
• Packages Available :
- 56-pin 240mil Wide Thin Plastic TSSOP(A)
- 56-pin 300mil Wide Plastic SSOP(V)
The PI3B16232 is a 3.3 volt, 16-bit to 32-bit synchronous switch.
Two select inputs (S0 and S1) control the data flow. A clock (CLK)
and a clock enable (CLKEN) synchronize the device operation.
When CLKEN is high, the bus switch remains in the last clocked
function.
Product Pin Configuration
Logic Block Diagram
56-Pin
A, V
Truth Table
S1
S0
CLK
CLKEN
Function
X
X
X
H
Last State
L
L
↑
L
Disconnect
L
H
↑
L
A = B1 and A = B2
H
L
↑
L
A = B1
H
H
↑
L
A = B2
1
PS8178B
11/09/98
PI3B16232
3.3V, Synchronous 16-Bit to 32-Bit
FET Mux/Demux BusSwitch
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ..................................................... –65°C to +150°C
Ambient Temperature with Power Applied .................... –40°C to +85°C
Supply Voltage Range ......................................................–0.5V to +4.6V
DC Input Voltage .............................................................–0.5V to +4.6V
DC Output Current ....................................................................... 120 mA
Power Dissipation ............................................................................. 0.5W
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 3.0V to 3.6V)
Test Conditions(1)
Parameters Description
Min.
Typ(2)
Max.
Units
VIH
Input HIGH Voltage
Guaranteed Logic HIGH Level
2.0
—
—
V
VIL
Input LOW Voltage
Guaranteed Logic LOW Level
–0.5
—
0.8
V
IIH
IIL
Input HIGH Current
Input LOW Current
VCC = Max., VIN = VCC
VCC = MAX. , VIN = GND
—
—
—
±1
±1
µA
µA
IOZH
High Impedance Output Current
0 ≤ A, B ≤ VCC
—
—
±1
µA
VIK
Clamp Diode Voltage
VCC = Min.,VIN = –18mA
—
-0.7
-1.2
V
VCC = Min., IIN = 0.0V, ION = 48mA or 64mA
VCC = Min.,VIN = 2.4 V, ION = 15mA
—
—
5
10
8
15
Ω
Ω
Ron
(3)
Switch on Resistance
Capacitance (TA = 25°C, f = 1 MHz)
Parameters(4)
CIN
CON
Description
Test Conditions
Typ.
Units
Input Capacitance
A/B Capacitance, Switch On
VIN = 0V
VIN = 0V
3.0
25.0
pF
pF
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device.
2. Typical values are at Vcc = 3.3V, TA = 25°C ambient and maximum loading.
3. Measured by the voltage drop between A and B pin at indicated current through the switch. ON resistance is determined by the
lower of the voltages on the two (A,B) pins.
4. This parameter is determined by device characterization but is not production tested.
2
PS8178B
11/09/98
PI3B16232
3.3V, Synchronous 16-Bit to 32-Bit
FET Mux/Demux BusSwitch
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Power Supply Characteristics
Parameters
Test Conditions(1)
Description
Min.
Typ(2)
Max.
Units
ICC
Quiescent Power
Supply Current
VCC = MAX.
VIN = GND or VCC
—
—
10
µA
∆ICC
Supply Current per
Input @ TTL HIGH
VCC = MAX.
VIN = 3.0 V(3)
—
—
750
µA
ICCD
Supply Current per
Input per MHz(4)
VCC = Max.,
A and B Pins Open
BE = GND
Control Input Toggling
50% Duty Cycling
—
—
0.25
mA/
MHz
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for applicable device.
2. Typical values are at Vcc = 3.3V, +25°C ambient.
3. Per TTL driven input (control inputs only); A and B pins do not contribute to Icc.
4. This current applies to the control inputs only and represent the current required to switch internal capacitance at the specified
frequency. The A and B inputs generate no significant AC or DC currents as they transition. This parameter is not tested, but is
guaranteed by design.
Switching Characteristics over Operating Range
Vcc = 3.0 to 3.6V
Parame te r
fCLK
D e s cription
Te s t Conditions (1)
Clock Frequency
M in.
M ax.
Units
0
150
MHz
tW
Pulse Duration
CLK high or low
3.3
ts
Setup Time
S0, S1 before CLK↑
1.9
CLK EN before CLK↑
1.9
th
Hold Time
ten
Enable Time
CLK to B1, B2
1
5
tdis
Disable Time
CLK to B1, B2
1
6
tpd1(2,3)
Propagation
Delay
A to B
tpd2
Propagation
Delay
CLK to A
S0, S1 after CLK↑
1
CLK EN after CLK↑
1.8
ns
0.25
1
4.5
Notes:
1. See Test Circuits and Waveforms.
2. This parameter is guaranteed by design but not tested.
3. The bus switch contributes no propagational delay other than the RC delay of ON resistance of the switch and
the load capacitance.
3
PS8178B
11/09/98