PI3B4010 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 3.3V, High-Bandwidth, 40:10-Bit DDR Mux/Demux NanoSwitch™ Product Features Product Description • • • • • • Pericom Semiconductor’s PI3B series of logic circuits are produced using the Company’s advanced submicron CMOS technology, achieving industry-leading performance. RON is 35 ohms max. Standard Operating Temperature: 0ºC to +70ºC Channel ON Capacitance: 15pF max. VCC Operating Range: +3.0V to +3.6V Fast switching time: 3ns max. Package options include: - 64-ball Thin Fine Pitch Ball Grid Array (TFBGA) The PI3B4010 is a 3.3V, 10- to 40-bit demultiplexing/multiplexing bus switch. It is intended for multiple data or address muxing. Industry leading advantages include a propagation delay of 300ps, resulting from the 35-ohm channel resistance, and low I/O capacitance. The A-port multiplexes to one of four or all outputs allowing a complete bank of 10 bits to switch. The switch is bidirectional. Applications • DDR DIMM bank switching Expanded Block Diagram Logic Block Diagram 10Ω A0 .... 0B0 1B0 10Ω A1 2B0 A2 1B9 A9 2B9 .... 3B0 A3 A4 3B9 SEL0 10Ω 10Ω 10Ω SEL1 A5 SEL2 SEL3 A 10Ω B A6 10Ω SEL A7 A8 A9 3B0 0B 1 1B1 2B1 0B9 .... 10Ω .... . . . . . . A0 0B0 1B0 2B0 10Ω 10Ω 10Ω 3B1 0B 2 1B2 2B2 3B2 0B 3 1B3 2B3 3B3 0B 4 1B4 2B4 3B4 0B 5 1B5 2B5 3B5 0B 6 1B6 2B6 3B6 0B 7 1B7 2B7 3B7 0B 8 1B8 2B8 3B8 0B 9 1B9 2B9 3B9 SEL0 SEL1 SEL2 SEL3 1 PS8571A 12/11/02 PI3B4010 3.3V, High Bandwidth, 40:10-Bit, DDR Mux/Demux NanoSwitch 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123 Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................................. –65ºC to +150ºC Supply Voltage Range ................................................ –0.5V to +4.6V DC Input Voltage .......................................................... –0.5V to +4.6V DC Output Current .................................................................... 120mA Power Dissipation ........................................................................ 0.5W Product Pinout by Location on Connection Diagram 1 A NC 2 3 4 SEL1 VDD B SEL2 NC SEL0 GND 5 6 7 1B0 2B0 3B0 0B0 Ao 0B1 8 1B1 Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Product Pin Description 9 10 11 Pin Name 2B1 3B1 0B2 AN A1 GND 1B2 2B2 C VDD SEL3 A2 D GND 3B2 De s cription Demux Input Pins NB0 - NB9 SELN Mux Input Pins Bank Select Pins (Active LOW) GND Ground VDD Power E 2B9 3B9 0B3 1B3 Note: N = 0 through 3 for each set of 10 Bits F 1B9 A9 A3 2B3 Truth Table G 0B9 3B8 GND 3B3 H 2B8 0B4 A4 1B4 A5 3B4 2B4 2B5 1B5 0B5 J 1B8 A8 K 0B8 GND A7 L 3B7 2B7 1B7 NC = No Connection 0B7 3B6 A6 GND 2B6 1B6 0B6 3B5 Function SEL0 SEL1 SEL2 SEL3 Connect AN to 0BN L H H H Connect AN to 1BN H L H H Connect AN to 2BN H H L H Connect AN to 3BN H H H L H H H H 0BN, 1BN, 2BN, 3BN AN = Hi- Z = Pulldown, Top View 2 PS8571A 12/11/02 PI3B4010 3.3V, High Bandwidth, 40:10-Bit, DDR Mux/Demux NanoSwitch 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Electrical Characteristics over Operating Range (TA = 0°C to 70°C, VCC = 3.3V ±5%) Parame te r Te s t Conditions (1) De s cription M in. Typ.(2) M ax. VIH Input HIGH Voltage Guaranteed HIGH Level 1.6 – VCC +0.3 VIL Input LOW Voltage Guaranteed HIGH Level –0.3 – 0.9 VIK Clamp Diode Voltage VCC = Max., VIN = –18mA – –0.7 –1.2 IIH Input HIGH Current VCC = Max., VIN = VCC – – ±10 IIL Input LOW Current VCC = Max., VIN = GND – – ±10 RON Switch On Resistance(3) VCC = Min., 0.8V ≤VIN ≤2.5V, IIN = –20mA – 25 35 RFLAT(ON) On Resistance Flatness(4) VCC = Min., [email protected] and 1.7V IIN = –20mA – 1.0 – ∆RON On Resistance match from center ports to any other port(4) VCC = Min., 0.8V ≤VIN ≤2.5V, IIN = –20mA – 0.9 2 Pull- Down Resistance VIN = 0V to 2.5V 80 100 130 RPD Units V µA Ω Capacitance (TA = 25°C, f = 1 MHz) Parame te rs CIN De s cription Te s t Conditions Input Capacitance COFF(A) Port A Capacitance, Switch OFF CON(A/B) A/B Capacitance, Switch ON COFF(B) Port B Capacitance, Switch OFF VIN = 0V Typ.(4) M ax. 3.5 – 12.0 – 15 . 0 – 4.5 – Units pF Notes: 1. For min. or max. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, TA = 25°C ambient and maximum loading. 3. Measured by the voltage drop between A and B pins at indicated current through the switch. ON resistance is determined by the lower of the voltages on the two (A & B) pins. 4. This parameter is determined by device characterization but is not production tested. Power Supply Characteristics Parame te rs ICC De s cription Quiscent Power Supply Current Te s t Conditions (1) M in. Typ.(2) M ax. Units VCC = Max., VIN = GND or VCC – – 10 µA Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3. Per TTL driven input (control inputs only); A and B pins do not contribute to ICC. 3 PS8571A 12/11/02 PI3B4010 3.3V, High Bandwidth, 40:10-Bit, DDR Mux/Demux NanoSwitch 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123 Switching Characteristics (over operating range over recommended operating free-air temperature range). Parame te r De s cription Conditions Com M in. Typ M a x. tIY Propagation Delay(2,3) AN to BN w/ZO = 50 Ohms – – 0.3 – tSY Bus Select Time - SELN to AN, BN – 0.5 – 3.0 tPZL Bus Enable Time - SELN to AN, BN – 0.5 – 3.0 tPLZ Bus Disable Time - SELN to AN, BN – 0.5 – 3.0 tSK(o) Output skew between center ports (A4 & A5) to any other port(2) – – 0.1 0.2 – – 0.1 0.2 tSK(p) (2) Skew between opposite transitions of the same output (ItPHL - tPLHI) Units ns Notes: 1. See test circuit and waveforms. 2. This parameter is guaranteed by design. 3. The bus switch contributes no propagational delay other than the RC delay of the ON resistance of the switch and the load capacitance. The time constant for the switch alone is of the order of 0.75ns for 50pF load. Since this time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagational delay to the system. Propagational delay of the bus switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side. Test Circuits for All Outputs(1) Switch Positions Te s t 5.0V VCC 500Ω Pulse Generator VIN 55Ω D.U.T RT VOUT 55Ω 8pF CL Switch Disable LOW, Enable LOW (output on A side) 5.0V Disable HIGH, Enable HIGH (output on A side) GND Disable/Enable High (output on B side) & Prop Delay Open 500Ω Notes: 1. CL = Load capacitance: includes jig and probe capacitance. 2. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator 3. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 4. All input impulses are supplied by generators having the following characteristics: PRR ≤ MHz, ZO = 50Ω, tR ≤ 2.5ns, tF ≤ 2.5ns. 5. The outputs are measured one at a time with one transition per measurement. 4 PS8571A 12/11/02 PI3B4010 3.3V, High Bandwidth, 40:10-Bit, DDR Mux/Demux NanoSwitch 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Switching Waveforms 2.5V SEL 1.25V 1.25V 0V 2.5V 1.25V Input Output A 1.25V tPZL 0V tPLH tPLZ 2.5V 1.25V tPHL VOL +0.15V VOH Output 1.25V Output A VOL VOH VOH –0.15V 1.25V 1.25V VOL tPHZ tPZH 0V tPHZ tPZH VOH 1.25V 1.25V Output B Voltage Waveforms Propagation Delay Times 0V Voltage Waveforms Enable and Disable Times 2.5V 1.25V Data In at Ax or Ay 0V tPLHX 2.5V tPHLX 1.25V VOH Input 0V 1.25V Data Out at MBx I tPLH tPHL VOH VOL tSK(o) 1.25V Output VOH VOL 1.25V Data Out at MBy tPLHy tPHLy tSK(p) = I tPHL – tPLH I VOL tSK(o) = I tPLHy – tPLHx I or I tPHLy – tPHLx I Pulse Skew - tSK(p) Output Skew - tSK(o) 5 PS8571A 12/11/02 PI3B4010 3.3V, High Bandwidth, 40:10-Bit, DDR Mux/Demux NanoSwitch 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123 64-Pin TFBGA Package .276 7.0 BSC. 0.08 0.10 .197 5.0 BSC .197 5.0 BSC .276 7.0 BSC. .020 0.5 BSC. Pin #1 Corner Pin #1 Corner .011 .015 0.28 0.38 BOTTOM VIEW .030 0.77 MAX .007 .011 0.18 0.28 TOP VIEW .043 1.10 MAX Ordering Information Part Pin - Package PI3B4010NC 64 - TFBGA Applications Information Logic Inputs The logic control inputs can be driven up to +3.6V regardless of the supply voltage. For example, given a + 3.3V supply, IN may be driven low to 0V and high to 3.6V. Driving IN Rail-to-Rail® minimizes power consumption. Power-Supply Sequencing and Hot-Plug Information Proper power-supply sequencing is recommended for all CMOS devices. Always apply VCC and GND before applying signals to input/output or control pins. Rail-to-Rail is a registeredtrademark of Nippon Motorola, Ltd. Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 6 PS8571A 12/11/02