PLL500-27/-37/-47 Low Power CMOS Output VCXO Family (27MHz to 200MHz) FEATURES • • • • • • • VCXO output for the 27MHz to 200MHz range - PLL500-27: 27MHz to 65MHz - PLL500-37: 65MHz to 130MHz - PLL500-47: 100MHz to 200MHz Low phase noise (-130 dBc @ 10kHz offset). CMOS output with OE tri-state control. Selectable output drive (Standard or High drive). - Standard: 12mA drive capability at TTL level. - High: 36mA drive capability at TTL level. Fundamental crystal input. Integrated high linearity variable capacitors. +/- 150 ppm pull range, max 5% linearity. Low jitter (RMS): 2.5ps period jitter. 2.5-3.3V operation. Available in 8-Pin SOIC or DIE. XIN 1 DRIVSEL^ 2 VCON 3 GND 4 PLL500-x7 • • • PIN CONFIGURATION 8 XOUT 7 OE^ 6 VDD 5 CLK ^: Denotes internal Pull-up DIE PAD LAYOUT 8 1 7 2 DESCRIPTION 6 The PLL500-27/-37/-47 are a low cost, high performance, low phase noise, and high linearity VCXO family for the 27 to 200MHz range, providing less than 130dBc at 10kHz offset. The very low jitter (2.5 ps RMS period jitter) makes these chips ideal for applications requiring voltage controlled frequency sources. The IC’s are designed to accept fundamental resonant mode crystals. 3 5 4 FREQUENCY RANGE PART # MULTIPLIER FREQUENCY PLL500-27 No PLL 27 – 65 MHz PLL500-37 No PLL 65 – 130 MHz PLL500-47 No PLL 100 – 200 MHz BLOCK DIAGRAM XIN XOUT XTAL OSC VARICAP OE VCON 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 01/21/04 Page 1 PLL500-27/-37/-47 Low Power CMOS Output VCXO Family (27MHz to 200MHz) PIN AND PAD DESCRIPTION Name Pin# XIN Die Pad Position Type Description X (µ µ m) Y (µ µ m) 1 94.183 768.599 I Crystal input pin. DRIVSEL 2 94.157 605.029 I Output drive select pin. High drive if set to ‘0’. Low drive if set to ‘1’. Internal pull-up. VCON 3 94.183 331.756 I Frequency control voltage input pin. GND 4 94.193 140.379 P Ground pin. CLK 5 715.472 203.866 O Output clock pin. VDD 6 715.307 455.726 P OE 7 715.472 626.716 I XOUT 8 476.906 888.881 I VDD power supply pin. Output Enable input pin. Disables the output when low. Internal pull-up enables output by default if pin is not connected low. Crystal output pin. Ref clock input. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. MAX. UNITS V CC - 0.5 7 V Input Voltage Range VI - 0.5 V CC + 0.5 V Output Voltage Range VO - 0.5 V CC + 0.5 V 260 °C -65 150 °C 0 70 °C Supply Voltage Range Soldering Temperature Storage Temperature TS Ambient Operating Temperature Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 01/21/04 Page 2 PLL500-27/-37/-47 Low Power CMOS Output VCXO Family (27MHz to 200MHz) 2. AC Electrical Specifications PARAMETERS SYMBOL Input Crystal Frequency Output Clock Rise/Fall Time Output Clock Duty Cycle CONDITIONS MIN. TYP. MAX. PLL500-27 27 65 PLL500-37 65 130 PLL500-47 100 200 0.8V ~ 2.0V with 10 pF load 1.15 0.3V ~ 3.0V with 15 pF load 3.7 Measured @ 1.4V 45 50 MHz ns 55 ±50 Short Circuit Current UNITS % mA 3. Voltage Control Crystal Oscillator PARAMETERS VCXO Stabilization Time * SYMBOL T VCXOSTB CONDITIONS MIN. From power valid TYP. MAX. 10 UNITS ms VCXO Tuning Range XTAL C 0 /C 1 < 250 300 ppm CLK output pullability 0V ≤ VCON ≤ 3.3V ±150 ppm VCXO Tuning Characteristic 100 Pull range linearity Power Supply Rejection PWSRR Frequency change with VDD varied +/- 10% VCON pin input impedance VCON modulation BW 0V ≤ VCON ≤ 3.3V, -3dB -1 ppm/V 5 % +1 ppm 1000 kΩ 45 kHz Note: Preliminary Specifications still to be characterized. Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 4. Jitter and Phase Noise specification PARAMETERS RMS Period Jitter CONDITIONS MIN. TYP. MAX. UNITS (1 sigma – 1000 samples) With capacitive decoupling between VDD and GND. 2.5 ps Phase Noise relative to carrier @100Hz offset -80 dBc/Hz Phase Noise relative to carrier @1kHz offset -110 dBc/Hz Phase Noise relative to carrier @10kHz offset -130 dBc/Hz Phase Noise relative to carrier @100kHz offset -138 dBc/Hz Phase Noise relative to carrier @1MHz offset -145 dBc/Hz 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 01/21/04 Page 3 PLL500-27/-37/-47 Low Power CMOS Output VCXO Family (27MHz to 200MHz) 5. DC Specification PARAMETERS SYMBOL Supply Current, Dynamic, with Loaded Outputs Allowable output load capacitance I DD CL (Output) CONDITIONS TYP. MAX. F XIN = 36MHz, 15pF output load 5 6 F XIN = 77MHz, 15pF output load 10 12 F XIN = 155MHz, 15pF output load 15 18 pF PLL500-37 and-47: Std drive 15 pF PLL500-37 and-47: High drive 10 pF 3.63 V Output High Voltage V OH I OH = -12mA Output Low Voltage V OL I OL = 12mA 2.25 2.4 V 0.4 I OH = -4mA V DD – 0.4 12 17 High drive at TTL level 36 51 mA ±50 VCON ESD Protection 0 Human Body Model V V Standard drive at TTL level Short Circuit Current VCXO Control Voltage mA N/A V DD Output drive current UNITS PLL500-27 Operating Voltage Output High Voltage at CMOS level MIN. mA 3.3 2000 V V 6. Crystal Specifications PARAMETERS Crystal Loading Rating (VCON = 1.65V) SYMBOL MIN. C L (xtal) TYP. MAX. 8.5 Maximum Sustainable Drive Level pF 200 Operating Drive Level Max C0 for PLL500-27 3.5 Max C0 for PLL500-37 2.5 Max C0 for PLL500-47 2 ESR RS µW µW 50 C0/C1 UNITS pF 250 - 30 Ω Note: The crystal must be such that it oscillates (parallel resonant) at nominal frequency when presented a C Load as specified above. If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This however may reduce the pull range. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 01/21/04 Page 4 PLL500-27/-37/-47 Low Power CMOS Output VCXO Family (27MHz to 200MHz) PACKAGE INFORMATION 8 PIN ( dimensions in mm ) Narrow SOIC Symbol Min. Max. A 1.47 1.73 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 4.95 E 3.80 4.00 H 5.80 6.20 L 0.38 1.27 e E H D A A 1 C 1.27 BSC L B e ORDERING INFORMATION PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL500-x7 x x Part Number Temperature C=Commercial Package S=SOIC D=Die Order Number Marking PLL500-27SC PLL500-27SC-R PLL500-27DC PLL500-37SC PLL500-37SC-R PLL500-37DC PLL500-47SC PLL500-47SC-R PLL500-47DC P500-27SC P500-27SC P500-27DC P500-37SC P500-37SC P500-37DC P500-47SC P500-47SC P500-47DC Package Option 8-Pin SOIC (Tube) 8-Pin SOIC (Tape and Reel) Die (Waffle Pack) 8-Pin SOIC (Tube) 8-Pin SOIC (Tape and Reel) Die (Waffle Pack) 8-Pin SOIC (Tube) 8-Pin SOIC (Tape and Reel) Die (Waffle Pack) PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 01/21/04 Page 5