SILAN SA1469PH

SA1469PH
4-CH BTL DRIVER FOR CD PLAYER WITH 3.3V OUTPUT VOLTAGE
DESCRIPTION
The SA1469PH, an IC for CD players, has a 4-channel BTL driver,
3.3V regulator (attached PNP transistor required), standard operational
amplifier, and internal reset output linked to an internal thermal shutdown
circuit. The driver has gain adjustment input pins for each channel,
allowing gain to be set to the desired value. Also, the internal level shift
circuit helps reduce the number of attached components.
FEATURES
* 1-phase, full-wave, linear DC motor driver
* Gain is adjustable with an attached resistor.
* Internal standard operational amplifier.
* Internal 3.3V regulator. (required attached PNP transistor)
* Internal thermal shutdown circuit with hysteresis capabilities.
ORDERING INFORMATION
Device
Package
SA1469PH
HSOP-28-375-0.8
BLOCK DIAGRAM
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2008.07.23
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SA1469PH
ABSOLUTE MAXIMUM RATING (Tamb=25°C, unless otherwise specified)
Symbol
Value
Unit
Supply Voltage
Characteristic
VCC
12
V
Power Dissipation
PD
1.7(Note)
W
Operating Temperature
Topr
-40~+85
°C
Storage Temperature
Tstg
-55~+150
°C
Maximum Output Current
Imax
1
A
Note: 1. When mounted on 76mm x 114mm x 1.57mm PCB (Phenolic resin material).
2. Power dissipation reduces 13.6mW / °C for using above Tamb=25 °C.
3. Do not exceed Pd and SOA (Safe Operating Area).
2.0
1.5
1.0
0.5
0
0
25
50
75
100
125
150
175
Ambient temperature: ( Tamb ℃)
ELECTRICAL CHARACTERISTICS (Tamb=25°C, VCC=8.0V, unless otherwise specified)
Parameter
Symbol
Test conditions
Min.
Typ.
Max.
Unit
A REGULATOR PART
Regulator Output Voltage
VREG
IL=100mA
3.13
3.3
3.47
V
Load Regulation
ΔVRL
IL=0mA to 200mA
-40.0
0
10.0
mV
Line Regulation
ΔVCC
IL=200mA, VCC=6 to 9V
-10.0
0
20.0
mV
Quiescent Circuit Current
ICCQ
VI=0
5.5
9.5
13.5
mA
Input Offset Voltage
VOF
-
-5.0
0
5.0
mV
Output Offset Voltage
VOO
-
-30
0
30
mV
Maximum Sink Current
ISINK
RL=4Ω, VCC
0.5
0.8
--
A
Maximum Source Current
ISOU
RL=4Ω, GND
0.5
0.8
--
A
Maximum Output Voltage
VOM
VI=2VRMS, 1kHz
2.5
3.0
--
V
Closed Loop Voltage Gain
A/F
VI=0.1VRMS, 1kHz
7.0
8.0
9.0
Db
Ripple Rejection Ratio
RR
VI=-20dB, 120Hz
60.0
80.0
--
dB
Slew Rate
SR
100Hz, squarewave
1.0
2.0
--
V/μs
B DRIVER PART
(To be continued)
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SA1469PH
(Continued)
Parameter
Symbol
Test conditions
Min.
Typ.
Max.
Unit
C OP AMP
Input Offset Voltage
VOF1
-
-5.0
0
5.0
mV
IB1
-
--
--
300
nA
High Level Output Voltage
VOH1
-
6
-
-
V
Low Level Output Voltage
VOL1
-
-
-
1.8
V
Output Sink Current
ISINK1
RL=50Ω, GND
10
40
-
mA
ISOURCE1
RL=50Ω, VCC
10
50
-
mA
GVO1
VIN=-75dB, f=1kHz
65
78
-
dB
RR1
VIN=-20dB, 120Hz
50
70
-
dB
Square, VOUT=2Vp-p, f=120kHz
0.5
1
-
V/μs
VIN=-20dB, 1kHz
70
84
-
dB
Input Bias Current
Output Source Current
Open Loop Voltage Gain
Ripple Rejection Ratio
Slew Rate
SR
Common Mode Rejection Ratio
CMRR1
PIN CONFIGURATION
28 27 26 25 24 23 22
21 20 19 18 17 16 15
SA1469PH
1
2
3
4
5
6
7
8
9
10 11 12 13 14
PIN DESCRIPTION
Pin No.
Symbol
I/O
Description
1
OUT1A
O
Drive output
2
OUT1B
O
Drive output
3
IN1A
I
Drive input
4
IN1B
I
Drive input
5
REG
6
REO
O
Regulator output
7
MUTE
I
Mute
8
GND
--
Ground
Regulator
(To be continued)
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SA1469PH
(Continued)
Pin No.
Symbol
I/O
Description
9
IN2B
I
Drive input
10
IN2A
I
Drive input
11
OUT2B
O
Drive output
12
OUT2A
O
Drive output
13
GND
--
Ground
14
OPOUT
O
Opamp output
15
OPIN (-)
I
Opamp input (-)
16
OPIN (+)
I
Opamp input (+)
17
OUT3A
O
Drive output
18
OUT3B
O
Drive output
19
IN3A
I
Drive input
20
IN3B
I
Drive input
21
VCC
--
Supply voltage
22
VCC
--
Supply voltage
23
VREF
I
2.5V bias voltage
24
IN4B
I
Drive input
25
IN4A
I
Drive input
26
OUT4B
O
Drive output
27
OUT4A
O
Drive output
28
GND
--
Ground
FUNCTIONAL DESCRIPTION
1. MUTE
Function
Mute
Operation conditions
Thermal shutdown
○
T≥175°C
External muting
○
V(mute)≤ 1.4V or open
Output Driver
Bias
7
1)
The circuit is muted during thermal shutdown and during the mute-on state.In each case, only the drivers are
muted.
2)
During mute, the output pins remain at the internal bias voltage, roughly (Vcc-Vf)/2.
3)
When the mute pin # 7 is open or the voltage of the mute pin # 7 is below 0.5V, the mute circuit is activated
so that the output circuit will be muted..
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SA1469PH
4)
When the voltage of the mute pin is above 2V, the mute circuit is stopped and the output circuit is operated
normally.
5)
If the chip temperature rises above 175°C, then the TSD (Thermal Shutdown) circuit is activated and the
output circuit is muted.
2. TSD (THERMAL SHUTDOWN)
VREF
Output Driver
Bias
R1
Qn
R2
1)
The VREF is the output voltage of the band-gap-referenced biasing circuit and acts as the input voltage of
the TSD circuit.
2)
The base-emitter voltage of the TR, Qn is designed to turn-on at below voltage.
VBE=VREF * R2/(R1+R2)=460mV
3)
When the chip temperature rises up to 175°C, then the turn-on voltage of the Qn would drop down to 460mV.
(Hysteresis: 25°) and, the Qn would turn on so the output circuit will be muted.
3. OP-AMP
OP-Amp is integrated in the IC for user convenuence.
OPIN(-)
+ -
OPIN(+)
OPOUT
Pins 14, 15 and 16 may be left open when the operational amplifier is not used.
4. DRIVER
1)
The voltage, VREF, is the reference voltage given by the BIAS voltage of the pin # 23.
2)
The input signal through the pin # 3 is amplified by 13K/10K times and then fed to the level shift.
3)
The level shift produces the current due to the difference between the input signal and the arbitrary reference
signal. The current produced as +ΔV and -ΔV is fed into the driver buffer.
4)
Driver buffer operates the power TR of the output stage according to the state of the input signal.
5)
The output stage is the BTL driver and the motor is rotating in forward direction by operating TR Q1 and TR
Q4. on the other hand, if TR Q2 and TR Q3 is operating, the motor is rotating in reverse direction.
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SA1469PH
6)
When the input voltage through the pin # 3 is below the VREF, then the direction of the motor in forward
7)
When the input voltage through the pin # 3 is above the VREF, then the direction of the motor in reverse
direction.
direction.
8)
If it is desired to change the gain, then the pin # 4 or # 24 can be used.
5. RADIATION FIN IS CONNECTING TO THE INTERNAL GND OF THE PACKAGE.
Connect the fin to the external GND.
6. REGULATOR
This is a typical series regulator that generates a reference voltage internally. A PNP low saturation type transistor must be connected.
+ -
REG
Attached
PNP
VOUT
VREF
REO
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Oscillation prevention
REV:1.4
2008.07.23
Page 6 of 11
SA1469PH
TEST CIRCUIT
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2008.07.23
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SA1469PH
TYPICAL APPLICATION CIRCUIT
ELECTRICAL CHARACTERISTICS CURVES
Fig.1 Driver I/O characteristics (variable load)
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Fig.2 Driver I/O characteristics
(variable power supply)
REV:1.4
2008.07.23
Page 8 of 11
SA1469PH
Fig. 3 Power supply voltage vs.
Fig. 4 Driver gain vs. temperature
output offset voltage
(RIN connected via gain adjustment pin)
Fig. 5 Regulator voltage vs. temperature
Fig. 6 Load current vs. regulator voltage
Fig. 7 Operational amplifier vs. open loop
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
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REV:1.4
2008.07.23
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SA1469PH
PACKAGE OUTLINE
9.525±0.2
2.30±0.20
+0.10
-0.05
0.15
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http://www.silan.com.cn
7.5±0.2
UNIT: mm
10.2±0.3
HSOP-28-375-0.8
REV:1.4
2008.07.23
Page 10 of 11
SA1469PH
ATTACH
Revision History
Data
REV
Description
2003.05.26
1.0
Original
2007.03.12
1.1
Modify the “Operating Temperature”
2007.08.13
1.2
2007.10.25
1.3
Add the “Power dissipation curve”
2008.07.23
1.4
Modify the “Power dissipation curve”
1
Modify the “Block Diagram”, “Supply Voltage”, “Functional
Description” and “Typical Application Circuit”
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Page
1,4,7
2
REV:1.4
2008.07.23
Page 11 of 11