TERIDIAN 71M6531D

71M6531D/F, 71M6532D/F
Energy Meter IC
Simplifying System IntegrationTM
DATA SHEET
October 2009
GENERAL DESCRIPTION
FEATURES
The Teridian 71M6531D/F and 71M6532D/F are highly integrated SOCs with an MPU core, RTC, FLASH and LCD driver.
Teridian’s patented Single Converter Technology® with a 22-bit
delta-sigma ADC, four analog inputs, digital temperature compensation, precision voltage reference, battery voltage monitor
and 32-bit computation engine (CE) supports a wide range of
residential metering applications with very few low-cost external
components.
A 32-kHz crystal time base for the entire system and internal battery backup support for RAM and RTC further reduce system
cost. The IC supports 2-wire, and 3-wire single-phase and
dual-phase residential metering along with tamper-detection
mechanisms. The 71M6531D/F offers single-ended inputs for
two current channels and two single-ended voltage inputs. The
71M6532D/F has two differential current inputs and three single-ended voltage inputs.
2
Maximum design flexibility is provided by multiple UARTs, I C,
μWire, up to 21 DIO pins and in-system programmable FLASH
memory, which can be updated with data or application code in
operation.
A complete array of ICE and development tools, programming
libraries and reference designs enable rapid development and
certification of TOU, AMR and Prepay meters that comply with
worldwide electricity metering standards.
CT/SHUNT
A
LOAD
NEUTRAL
B
CT
POWER SUPPLY
LOAD
ADC
IAP*
IAN*
VA
IBP*
IBN*
VB
V3.3A
V3.3
SYS
TERIDIAN
71M6531
71M6532
GNDA GNDD
PWR MODE
CONTROL
WAKE-UP
REGULATOR
VBAT
V2.5
VOLTAGE REF
VREF
VBIAS
SERIAL PORTS
TX
AMR
TEMP
SENSOR
COM0..3
RAM
FLASH
MEMORY
LCD SEG
RX/DIO1
POWER
FAULT
SENSE
DRIVE/MOD
TX/DIO2
COMPARATOR
V1
OSC/PLL
XIN
32 kHz
XOUT
*
v1.2
88. 88. 8888
SEG/DIO
I2C or µWire
EEPROM
RX
IR
BATTERY
LCD & DIO
COMPUTE
ENGINE
TEST PULSES
MPU
TIMERS
SPI
SPI HOST
RTC
ICE I/F
Differential pins only on 6532D/F
ICE_E
02/18/2009
V3P3D
GNDD
• Wh accuracy < 0.1% over 2000:1 current
range
• Exceeds IEC62053/ANSI C12.20 standards
• Four sensor inputs
• Low-jitter Wh and VARh plus two additional
pulse test outputs (4 total, 10 kHz maximum)
with pulse count
• Four-quadrant metering
• Tamper detection (Neutral current with CT,
Rogowski or shunt, magnetic tamper input)
• Line frequency count for RTC
• Digital temperature compensation
• Sag detection for phase A and B
• Independent 32-bit compute engine
• 46-64 Hz line frequency range with same
calibration. Phase compensation (± 7°)
• Three battery modes with wake-up on timer
or push-button:
Brownout mode (52 µA typ.)
LCD mode (21 µA typ., DAC active)
Sleep mode (0.7 µA typ.)
• Energy display during mains power failure
• 39 mW typical consumption @ 3.3 V, MPU
clock frequency 614 kHz
• 22-bit delta-sigma ADC with 3360 Hz or
2520 Hz sample rate
• 8-bit MPU (80515), 1 clock cycle per instruction, 10 MHz maximum, with integrated
ICE for debug
• RTC for TOU functions with clock-rate adjust
register
• Hardware watchdog timer, power fail monitor
• LCD driver with 4 common segment drivers:
Up to 156 (71M6531D/F) or 268 pixels
(71M6532D/F)
• Up to 22 (71M6531D/F) or 43
(71M6532D/F) general-purpose I/O pins.
Digital I/O pins compatible with 5 V inputs
• 32 kHz time base
• High-speed slave SPI interface to data RAM
• Two UARTs for IR and AMR, IR driver with
modulation
• FLASH memory with security and in-system
program update:
128 KB (71M6531D/32D)
256 KB (71M6531F/32F)
• 4 KB MPU XRAM
• Industrial temperature range
• 68-pin QFN package for 71M6531D/F pincompatible with 71M6521, 100-pin LQFP
package for 71M6532D/F, lead free
© 2005-2009 TERIDIAN Semiconductor Corporation
1
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
Table of Contents
1
2
Hardware Description ....................................................................................................................... 10
1.1 Hardware Overview ................................................................................................................... 10
1.2 Analog Front End (AFE)............................................................................................................. 10
1.2.1 Signal Input Pins ............................................................................................................ 10
1.2.2 Input Multiplexer ............................................................................................................ 11
1.2.3 A/D Converter (ADC) ..................................................................................................... 12
1.2.4 FIR Filter ........................................................................................................................ 12
1.2.5 Voltage References ....................................................................................................... 12
1.2.6 Temperature Sensor ...................................................................................................... 14
1.2.7 Battery Monitor............................................................................................................... 14
1.2.8 AFE Functional Description ........................................................................................... 14
1.3 Digital Computation Engine (CE) ............................................................................................... 15
1.3.1 Meter Equations ............................................................................................................. 16
1.3.2 Real-Time Monitor ......................................................................................................... 16
1.3.3 Pulse Generators ........................................................................................................... 16
1.3.4 Data RAM (XRAM) ........................................................................................................ 17
1.3.5 CE Functional Overview ................................................................................................ 17
1.4 80515 MPU Core ....................................................................................................................... 19
1.4.1 Memory Organization and Addressing .......................................................................... 19
1.4.2 Special Function Registers (SFRs) ............................................................................... 21
1.4.3 Generic 80515 Special Function Registers ................................................................... 22
1.4.4 Special Function Registers (SFRs) Specific to the 71M6531D/F and 71M6532D/F ..... 25
1.4.5 Instruction Set ................................................................................................................ 26
1.4.6 UARTs ........................................................................................................................... 26
1.4.7 Timers and Counters ..................................................................................................... 29
1.4.8 WD Timer (Software Watchdog Timer) ......................................................................... 30
1.4.9 Interrupts ........................................................................................................................ 30
1.5 On-Chip Resources ................................................................................................................... 37
1.5.1 Oscillator ........................................................................................................................ 37
1.5.2 Internal Clocks ............................................................................................................... 37
1.5.3 Real-Time Clock (RTC) ................................................................................................. 38
1.5.4 Temperature Sensor ...................................................................................................... 39
1.5.5 Physical Memory............................................................................................................ 39
1.5.6 Optical Interface ............................................................................................................. 41
1.5.7 Digital I/O – 71M6531D/F .............................................................................................. 42
1.5.8 Digital I/O – 71M6532D/F .............................................................................................. 43
1.5.9 Digital IO – Common Characteristics for 71M6531D/F and 71M6532D/F .................... 45
1.5.10 LCD Drivers – 71M6531D/F .......................................................................................... 46
1.5.11 LCD Drivers – 71M6532D/F .......................................................................................... 46
1.5.12 LCD Drivers – Common Characteristics for 71M6531D/F and 71M6532D/F ............... 47
1.5.13 Battery Monitor............................................................................................................... 47
1.5.14 EEPROM Interface ........................................................................................................ 47
1.5.15 SPI Slave Port................................................................................................................ 50
1.5.16 Hardware Watchdog Timer ............................................................................................ 51
1.5.17 Test Ports (TMUXOUT pin) ........................................................................................... 52
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
2
3
4
v1.2
Data Sheet 71M6531D/F-71M6532D/F
Functional Description ..................................................................................................................... 53
2.1 Theory of Operation ................................................................................................................... 53
2.2 System Timing Summary ........................................................................................................... 54
2.3 Battery Modes ............................................................................................................................ 54
2.3.1 BROWNOUT Mode ....................................................................................................... 56
2.3.2 LCD Mode ...................................................................................................................... 57
2.3.3 SLEEP Mode ................................................................................................................. 57
2.4 Fault and Reset Behavior .......................................................................................................... 59
2.4.1 Reset Mode.................................................................................................................... 59
2.4.2 Power Fault Circuit ........................................................................................................ 59
2.5 Wake-Up Behavior ..................................................................................................................... 60
2.5.1 Wake on PB ................................................................................................................... 60
2.5.2 Wake on Timer............................................................................................................... 60
2.6 Data Flow ................................................................................................................................... 60
2.7 CE/MPU Communication ........................................................................................................... 61
Application Information.................................................................................................................... 62
3.1 Connection of Sensors............................................................................................................... 62
3.2 Connecting 5-V Devices ............................................................................................................ 62
3.3 Temperature Measurement ....................................................................................................... 63
3.4 Temperature Compensation ...................................................................................................... 63
3.4.1 Temperature Coefficients: ............................................................................................. 63
3.4.2 Temperature Compensation for VREF .......................................................................... 63
3.4.3 System Temperature Compensation ............................................................................. 63
3.4.4 Temperature Compensation for the RTC ...................................................................... 63
3.5 Connecting LCDs ....................................................................................................................... 64
3.6 Connecting I2C EEPROMs ........................................................................................................ 64
3.7 Connecting Three-Wire EEPROMs ........................................................................................... 65
3.8 UART0 (TX/RX) ......................................................................................................................... 65
3.9 Optical Interface (UART1).......................................................................................................... 66
3.10 Connecting V1 and Reset Pins .................................................................................................. 67
3.11 Connecting the Emulator Port Pins............................................................................................ 67
3.12 Connecting a Battery ................................................................................................................. 68
3.13 Flash Programming.................................................................................................................... 68
3.14 MPU Firmware Library ............................................................................................................... 69
3.15 Crystal Oscillator ........................................................................................................................ 69
3.16 Meter Calibration ........................................................................................................................ 69
Firmware Interface ............................................................................................................................ 70
4.1 I/O RAM and SFR Map – Functional Order ............................................................................... 70
4.2 I/O RAM Description – Alphabetical Order ................................................................................ 75
4.3 CE Interface Description ............................................................................................................ 86
4.3.1 CE Program ................................................................................................................... 86
4.3.2 CE Data Format ............................................................................................................. 86
4.3.3 Constants ....................................................................................................................... 86
4.3.4 Environment ................................................................................................................... 86
4.3.5 CE Calculations ............................................................................................................. 87
4.3.6 CE Status and Control ................................................................................................... 87
4.3.7 CE Transfer Variables ................................................................................................... 89
4.3.8 Pulse Generation ........................................................................................................... 91
4.3.9 CE Calibration Parameters ............................................................................................ 92
4.3.10 Other CE Parameters .................................................................................................... 93
© 2005-2009 TERIDIAN Semiconductor Corporation
3
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
4.3.11 CE Flow Diagrams ......................................................................................................... 93
5
Electrical Specifications................................................................................................................... 95
5.1 Absolute Maximum Ratings ....................................................................................................... 95
5.2 Recommended External Components ....................................................................................... 96
5.3 Recommended Operating Conditions........................................................................................ 96
5.4 Performance Specifications ....................................................................................................... 97
5.4.1 Input Logic Levels .......................................................................................................... 97
5.4.2 Output Logic Levels ....................................................................................................... 97
5.4.3 Power-Fault Comparator ............................................................................................... 97
5.4.4 Battery Monitor............................................................................................................... 97
5.4.5 Supply Current ............................................................................................................... 98
5.4.6 V3P3D Switch ................................................................................................................ 98
5.4.7 2.5 V Voltage Regulator................................................................................................. 98
5.4.8 Low-Power Voltage Regulator ....................................................................................... 98
5.4.9 Crystal Oscillator ............................................................................................................ 99
5.4.10 LCD DAC ....................................................................................................................... 99
5.4.11 LCD Drivers ................................................................................................................... 99
5.4.12 Optical Interface ............................................................................................................. 99
5.4.13 Temperature Sensor .................................................................................................... 100
5.4.14 VREF ........................................................................................................................... 100
5.4.15 ADC Converter, V3P3A Referenced ........................................................................... 101
5.5 Timing Specifications ............................................................................................................... 102
5.5.1 Flash Memory .............................................................................................................. 102
5.5.2 EEPROM Interface ...................................................................................................... 102
5.5.3 RESET ......................................................................................................................... 102
5.5.4 RTC.............................................................................................................................. 102
5.5.5 SPI Slave Port (MISSION Mode) ................................................................................. 103
5.6 Typical Performance Data ....................................................................................................... 104
5.7 Package Outline....................................................................................................................... 105
5.8 71M6531D/F Package ............................................................................................................. 105
5.8.1 71M6531D/F Pinout (QFN-68)..................................................................................... 106
5.8.2 Recommended PCB Land Pattern for the QFN-68 Package ...................................... 107
5.9 71M6532D/F Package ............................................................................................................. 108
5.9.1 71M6532D/F Pinout (LQFP-100) ................................................................................. 108
5.9.2 LQFP-100 Mechanical Drawing ................................................................................... 109
5.10 Pin Descriptions ....................................................................................................................... 110
5.10.1 Power and Ground Pins............................................................................................... 110
5.10.2 Analog Pins .................................................................................................................. 110
5.10.3 Digital Pins: .................................................................................................................. 111
5.10.4 I/O Equivalent Circuits ................................................................................................. 111
6
Ordering Information ...................................................................................................................... 113
7
Related Information ........................................................................................................................ 113
8
Contact Information ........................................................................................................................ 113
Appendix A: Acronyms .......................................................................................................................... 114
Appendix B: Revision History ............................................................................................................... 115
4
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
Figures
Figure 1: 71M6531D/F IC Functional Block Diagram ................................................................................... 8
Figure 2: 71M6532D/F IC Functional Block Diagram ................................................................................... 9
Figure 3: General Topology of a Chopped Amplifier .................................................................................. 13
Figure 4: CROSS Signal with CHOP_E = 00 ............................................................................................... 13
Figure 5: AFE Block Diagram (Shown for the 71M6532D/F) ...................................................................... 14
Figure 6: Samples from Multiplexer Cycle .................................................................................................. 17
Figure 7: Accumulation Interval .................................................................................................................. 18
Figure 8: Interrupt Structure ........................................................................................................................ 36
Figure 9: Optical Interface ........................................................................................................................... 41
Figure 10: Connecting an External Load to DIO Pins ................................................................................. 46
Figure 11: 3-Wire Interface. Write Command, HiZ=0. ............................................................................... 49
Figure 12: 3-Wire Interface. Write Command, HiZ=1 ................................................................................ 49
Figure 13: 3-Wire Interface. Read Command. ........................................................................................... 49
Figure 14: 3-Wire Interface. Write Command when CNT=0 ...................................................................... 49
Figure 15: 3-Wire Interface. Write Command when HiZ=1 and WFR=1. .................................................. 50
Figure 16: SPI Slave Port: Typical Read and Write operations .................................................................. 51
Figure 17: Functions defined by V1 ............................................................................................................ 51
Figure 18: Voltage, Current, Momentary and Accumulated Energy ........................................................... 53
Figure 19: Timing Relationship between ADC MUX, Compute Engine ...................................................... 54
Figure 20: RTM Output Format ................................................................................................................... 54
Figure 21: Operation Modes State Diagram ............................................................................................... 55
Figure 22: Transition from BROWNOUT to MISSION Mode when System Power Returns ...................... 58
Figure 23: Power-Up Timing with V3P3SYS and VBAT tied together ........................................................ 58
Figure 24: Power-Up Timing with VBAT only.............................................................................................. 59
Figure 25: Wake Up Timing ........................................................................................................................ 60
Figure 26: MPU/CE Data Flow .................................................................................................................... 61
Figure 27: MPU/CE Communication ........................................................................................................... 61
Figure 28: Resistive Voltage Divider ........................................................................................................... 62
Figure 29: CT with Single Ended (Left) and Differential Input (Right) Connection ..................................... 62
Figure 30: Resistive Shunt (Left) and Rogowski Sensor (Right) Connection ............................................. 62
Figure 31: Connecting LCDs ....................................................................................................................... 64
Figure 32: I2C EEPROM Connection .......................................................................................................... 65
Figure 33: Three-Wire EEPROM Connection ............................................................................................. 65
Figure 34: Connections for UART0 ............................................................................................................. 66
Figure 35: Connection for Optical Components .......................................................................................... 66
Figure 36: Voltage Divider for V1 ................................................................................................................ 67
Figure 37: External Components for the RESET Pin: Push-button (Left), Production Circuit (Right) ........ 67
Figure 38: External Components for the Emulator Interface ...................................................................... 68
Figure 39: Connecting a Battery ................................................................................................................. 68
Figure 40: CE Data Flow: Multiplexer and ADC.......................................................................................... 93
Figure 41: CE Data Flow: Scaling, Gain Control, Intermediate Variables .................................................. 94
Figure 42: CE Data Flow: Squaring and Summation Stages...................................................................... 94
Figure 43: SPI Slave Port (MISSION Mode) Timing ................................................................................. 103
Figure 44: Wh Accuracy, 0.1 A to 200 A at 240 V/50 Hz and Room Temperature .................................. 104
Figure 45: QFN-68 Package Outline, Top and Side View ........................................................................ 105
Figure 46: QFN-68 Package Outline, Bottom View Table 83: QFN 68 Package Dimensions (in mm) .... 105
Figure 47: Pinout for QFN-68 Package..................................................................................................... 106
Figure 48: PCB Land Pattern for QFN 68 Package .................................................................................. 107
Figure 49: PCB Land Pattern for LQFP-100 Package .............................................................................. 108
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
5
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
Figure 50: LQFP-100 Package, Mechanical Drawing............................................................................... 109
Figure 51: I/O Equivalent Circuits ............................................................................................................. 112
Tables
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles ....................................................... 11
Table 2: ADC Resolution............................................................................................................................. 12
Table 3: ADC RAM Locations ..................................................................................................................... 12
Table 4: XRAM Locations for ADC Results ................................................................................................ 15
Table 5: Meter Equations ............................................................................................................................ 16
Table 6: CKMPU Clock Frequencies .......................................................................................................... 19
Table 7: Memory Map ................................................................................................................................. 20
Table 8: Internal Data Memory Map ........................................................................................................... 21
Table 9: Special Function Register Map ..................................................................................................... 22
Table 10: Generic 80515 SFRs - Location and Reset Values .................................................................... 22
Table 11: PSW Bit Functions (SFR 0xD0) ................................................................................................... 23
Table 12: Port Registers ............................................................................................................................. 24
Table 13: Stretch Memory Cycle Width ...................................................................................................... 25
Table 14: 71M6531D/F and 71M6532D/F Specific SFRs........................................................................... 25
Table 15: Baud Rate Generation ................................................................................................................ 27
Table 16: UART Modes............................................................................................................................... 27
Table 17: The S0CON (UART0) Register (SFR 0x98) ................................................................................. 28
Table 18: The S1CON (UART1) register (SFR 0x9B) .................................................................................. 28
Table 19: PCON Register Bit Description (SFR 0x87) ................................................................................ 28
Table 20: Timers/Counters Mode Description ............................................................................................ 29
Table 21: Allowed Timer/Counter Mode Combinations .............................................................................. 29
Table 22: TMOD Register Bit Description (SFR 0x89) ................................................................................ 30
Table 23: The TCON Register Bit Functions (SFR 0x88)............................................................................ 30
Table 24: The IEN0 Bit Functions (SFR 0xA8)............................................................................................ 31
Table 25: The IEN1 Bit Functions (SFR 0xB8)............................................................................................ 31
Table 26: The IEN2 Bit Functions (SFR 0x9A)............................................................................................ 31
Table 27: TCON Bit Functions (SFR 0x88) ................................................................................................. 32
Table 28: The T2CON Bit Functions (SFR 0xC8) ........................................................................................ 32
Table 29: The IRCON Bit Functions (SFR 0xC0) ........................................................................................ 32
Table 30: External MPU Interrupts .............................................................................................................. 33
Table 31: Interrupt Enable and Flag Bits .................................................................................................... 33
Table 32: Interrupt Priority Level Groups .................................................................................................... 34
Table 33: Interrupt Priority Levels ............................................................................................................... 34
Table 34: Interrupt Priority Registers (IP0 and IP1) .................................................................................... 34
Table 35: Interrupt Polling Sequence.......................................................................................................... 35
Table 36: Interrupt Vectors.......................................................................................................................... 35
Table 37: Clock System Summary .............................................................................................................. 37
Table 38: Bank Switching with FL_BANK[2:0] ............................................................................................ 40
Table 39: Data/Direction Registers and Internal Resources for DIO Pins (71M6531D/F) ......................... 42
Table 40: Data/Direction Registers and Internal Resources for DIO Pins (71M6532D/F) ......................... 44
Table 41: DIO_DIR Control Bit .................................................................................................................... 45
Table 42: Selectable Controls using the DIO_DIR Bits ............................................................................... 45
Table 43: EECTRL Bits for 2-pin Interface ................................................................................................... 47
Table 44: EECTRL Bits for the 3-Wire Interface .......................................................................................... 48
Table 45: SPI Command Description.......................................................................................................... 50
6
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
Table 46: TMUX[4:0] Selections ................................................................................................................. 52
Table 47: Available Circuit Functions.......................................................................................................... 56
Table 48: I/O RAM Map in Functional Order............................................................................................... 70
Table 49: I/O RAM Description - Alphabetical ............................................................................................ 75
Table 50: CE EQU Equations and Element Input Mapping ........................................................................ 87
Table 51: CESTATUS Bit Definitions ............................................................................................................ 87
Table 52: CECONFIG Bit Definitions ........................................................................................................... 88
Table 53: Sag Threshold Control ................................................................................................................ 89
Table 54: Gain Adjust Control ..................................................................................................................... 89
Table 55: CE Transfer Variables ................................................................................................................. 90
Table 56: CE Energy Measurement Variables............................................................................................ 90
Table 57: Useful CE Measurement Parameters ......................................................................................... 91
Table 58: CE Pulse Generation Parameters............................................................................................... 92
Table 59: CE Calibration Parameters ......................................................................................................... 92
Table 60: CE Parameters for Noise Suppression and Code Version ......................................................... 93
Table 61: Absolute Maximum Ratings ........................................................................................................ 95
Table 62: Recommended External Components ........................................................................................ 96
Table 63: Recommended Operating Conditions ......................................................................................... 96
Table 64: Input Logic Levels ....................................................................................................................... 97
Table 65: Output Logic Levels .................................................................................................................... 97
Table 66: Power-Fault Comparator Performance Specifications............................................................... 97
Table 67: Battery Monitor Performance Specifications (BME= 1) ............................................................... 97
Table 68: Supply Current Performance Specifications ............................................................................... 98
Table 69: V3P3D Switch Performance Specifications ................................................................................ 98
Table 70: 2.5 V Voltage Regulator Performance Specifications ................................................................. 98
Table 71: Low-Power Voltage Regulator Performance Specifications ....................................................... 98
Table 72: Crystal Oscillator Performance Specifications ............................................................................ 99
Table 73: LCD DAC Performance Specifications ....................................................................................... 99
Table 74: LCD Driver Performance Specifications ..................................................................................... 99
Table 75: Optical Interface Performance Specifications ............................................................................. 99
Table 76: Temperature Sensor Performance Specifications .................................................................... 100
Table 77: VREF Performance Specifications............................................................................................ 100
Table 78: ADC Converter Performance Specifications ............................................................................. 101
Table 79: Flash Memory Timing Specifications ........................................................................................ 102
Table 80: EEPROM Interface Timing........................................................................................................ 102
Table 81: RESET Timing .......................................................................................................................... 102
Table 82: SPI Slave Port (MISSION Mode) Timing .................................................................................. 103
Table 83: Recommended PCB Land Pattern Dimensions........................................................................ 107
Table 84: Power and Ground Pins ............................................................................................................ 110
Table 85: Analog Pins ............................................................................................................................... 110
Table 86: Digital Pins ................................................................................................................................ 111
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
7
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
VREF
GNDD
GNDA
V3P3A V3P3SYS
∆Σ ADC
CONVERTER
VBIAS
VADC
RTM
22
IA
VA
ADC_E
VREF
VREF
MUX
VREF_CAL
VREF_DIS
IB
V3P3D
CE
FIR
FIR_LEN
VB
PLS_INV
PLS_INTERVAL
PLS_MAXWIDTH
CE_LCTN
EQU
PRE_SAMPS
SUM_CYCLES
2.5V_NV
16
RTCLK (32KHz)
MCK
PLL
CK_CE
XIN
XOUT
LCD_ONLY
SLEEP
XPULSE
YPULSE
CE_PROG
VBAT
VOLT
REG
RPULSE
WPULSE
RTM_0..3
RTM_E
CE_E
EQU
MUX_ALT
MUX_DIV
VBAT
to TMUX
32
CE_DATA
2.5V to logic
2.5V_NV
XRAM
4kB
FLASH
128KB/
256KB
V2P5
YPULSE
XPULSE
WPULSE
RPULSE
VBIAS
OSC
(32KHz)
CKOUT_E
RTCA_ADJ
CKTEST
RTC
2.5V_NV
TEMP
SENSOR
TEST
RST_SUBSEC
QREG
PREG
RTC_DAY
RTC_HR
RTC_DATE
RTC_MIN
RTC_MO
RTC_SEC
RTC_YR
LCD_DAC
LCD_MODE
COM0..3
LCD_CLK
LCD_E
4
LCD_BLKMAP
LCD_SEG
SEG...
LCD_Y
RX
DIGITAL I/O
DIO_DIR
DIO_R
DIO
UART1
XRAM BUS
SPI SLAVE
8
PB
PCMD
EEPROM
EEDATA
EECTRL
PCSZ
PCLK
PSI
PSO
NVRAM
SPE
SDATA
SCLK
DIO_EEX
OPT_TXE
MUX_SYNC_E
2.5V_NV
GP0-GP7
IRAM BUS
8
POWER FAULT
DIO15/SEG35
DIO14/SEG34
DIO13/SEG33
DIO12/SEG32
DIO11/SEG31
DIO10/SEG30
4
DIO...
UART2--OPTICAL
OPT_TX
OPT_RXDIS
OPT_RXINV
OPT_RX
OPT_TXE
OPT_TXINV
OPT_TXMOD
OPT_FDC
V1
DIO17/SEG37
LCD DISPLAY
DRIVER
TEST
MODE
TX
DIO29/SEG49
DIO28/SEG48
CKOUT_E
MULTIPURPOSE
IO
MPU
PB
DIO46/SEG66
DIO45/SEG65
DIO44/SEG64
DIO43/SEG63
DIO_PV
DIO_PW
DIO_PX
DIO_PY
CK_MPU
IRAM
256B
EMULATOR
E_RXTX
E_TCLK
E_RSTZ
ICE_E
FAULTZ
TEST
MUX
COM0...3
DIO9/SEG29/YPULSE
DIO8/SEG28/XPULSE
DIO7/SEG27/RPULSE
DIO6/SEG26/WPULSE
DIO5/SEG25/SDATA
DIO4/SEG24/SDCK
SEG19/CKTEST
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11/E_RST
SEG10/E_TCLK
SEG9/E_RXTX
SEG8
SEG7/MUX_SYNC
SEG6/PSDI
SEG5/PCSZ
SEG4/PSDO
SEG3/PCLK
SEG2
SEG1
SEG0
DIO2/OPT_TX/WPULSE/RPULSE
DIO1/OPT_RX
TMUXOUT
TMUX[4:0]
RESET
ICE_E
02/18/2009
Figure 1: 71M6531D/F IC Functional Block Diagram
8
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
VREF
GNDD
GNDA
V3P3A V3P3SYS
∆Σ ADC
CONVERTER
IAP
VBIAS
VADC
RTM
22
IAN
MUX
VA
ADC_E
VREF
VREF
VREF_CAL
VREF_DIS
IBP
PLS_INV
PLS_INTERVAL
PLS_MAXWIDTH
CE_LCTN
EQU
PRE_SAMPS
SUM_CYCLES
VB
VBAT
2.5V_NV
16
RTCLK (32KHz)
MCK
PLL
CK_CE
XIN
VOLT
REG
RPULSE
WPULSE
LCD_ONLY
SLEEP
XPULSE
YPULSE
CE_PROG
EQU
MUX_ALT
MUX_DIV
VBAT
to TMUX
RTM_0..3
RTM_E
CE_E
IBN
XOUT
V3P3D
CE
FIR
FIR_LEN
32
CE_DATA
2.5V to logic
2.5V_NV
XRAM
4kB
FLASH
128KB/
256KB
V2P5
YPULSE
XPULSE
WPULSE
RPULSE
VBIAS
DIO_PV
DIO_PW
DIO_PX
DIO_PY
CK_MPU
OSC
(32KHz)
CKOUT_E
RTCA_ADJ
CKTEST
RTC
2.5V_NV
TEMP
SENSOR
TEST
RST_SUBSEC
QREG
PREG
RTC_DAY
RTC_HR
RTC_DATE
RTC_MIN
RTC_MO
RTC_SEC
RTC_YR
MULTIPURPOSE
IO
LCD_DAC
LCD_MODE
COM0..3
LCD_CLK
LCD_E
4
LCD_BLKMAP
LCD_SEG
SEG...
LCD_Y
MPU
RX
DIGITAL I/O
DIO_DIR
DIO_R
DIO
UART1
XRAM BUS
SPI SLAVE
8
PB
18
LCD DISPLAY
DRIVER
TEST
MODE
TX
5
6
CKOUT_E
PB
PCMD
EEPROM
EEDATA
EECTRL
COM0...3
4
DIO...
PCSZ
PCLK
PSI
PSO
SPE
SDATA
SCLK
DIO_EEX
4
7
UART2--OPTICAL
OPT_TX
OPT_RXDIS
OPT_RXINV
OPT_RX
OPT_TXE
OPT_TXINV
OPT_TXMOD
OPT_FDC
NVRAM
OPT_TXE
MUX_SYNC_E
2.5V_NV
GP0-GP7
3
IRAM BUS
8
V1
POWER FAULT
IRAM
256B
EMULATOR
DIO47/SEG67...DIO51/SEG71
DIO40/SEG60...DIO45/SEG65
DIO30/SEG50
DIO29/SEG59
DIO10/SEG30...DIO27/SEG47
DIO9/SEG29/YPULSE
DIO8/SEG28/XPULSE
DIO7/SEG27/RPULSE
DIO6/SEG26/WPULSE
DIO5/SEG25/SDATA
DIO4/SEG24/SDCK
E_RXTX
E_TCLK
E_RSTZ
3
ICE_E
FAULTZ
TEST
MUX
SEG20...SEG23
SEG19/CKTEST
SEG12...SEG18
SEG11/E_RST
SEG10/E_TCLK
SEG9/E_RXTX
SEG8
SEG7/MUX_SYNC
SEG6/PSDI
SEG5/PCSZ
SEG4/PSDO
SEG3/PCLK
SEG0...SEG2
DIO56...DIO58
DIO3
DIO2/OPT_TX/WPULSE/RPULSE
DIO1/OPT_RX
TMUXOUT
TMUX[4:0]
RESET
ICE_E
02/18/2009
Figure 2: 71M6532D/F IC Functional Block Diagram
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
9
Data Sheet 71M6531D/F-71M6532D/F
1
Hardware Description
1.1
Hardware Overview
FDS 6531/6532 005
The Teridian 71M6531D/F and 71M6532D/F single-chip energy meters integrates all primary functional
blocks required to implement a solid-state electricity meter. Included on the chips are:
• An analog front end (AFE)
• An Independent digital computation engine (CE)
• An 8051-compatible microprocessor (MPU) which executes one instruction per clock cycle (80515)
• A voltage reference
• A temperature sensor
• LCD drivers
• RAM and Flash memory
• A real time clock (RTC)
• A variety of I/O pins
Various current sensor technologies are supported including Current Transformers (CT), Resistive Shunts
and Rogowski coils.
In a typical application, the 32-bit compute engine (CE) of the 71M6531D/F and 71M6532D/F sequentially
process the samples from the voltage inputs on pins IA, VA, IB, VB and performs calculations to measure
active energy (Wh) and reactive energy (VARh), as well as A2h and V2h for four-quadrant metering.
These measurements are then accessed by the MPU, processed further and output using the peripheral
devices available to the MPU.
In addition to advanced measurement functions, the real time clock function allows the 71M6531D/F and
71M6532D/F to record time of use (TOU) metering information for multi-rate applications and to timestamp tamper events. Measurements can be displayed on 3.3 V LCDs commonly used in low-temperature environments. Flexible mapping of LCD display segments facilitate integration of existing custom LCDs. Design trade-off between the number of LCD segments and DIO pins can be implemented in
software to accommodate various requirements.
In addition to the temperature-trimmed ultra-precision voltage reference, the on-chip digital temperature
compensation mechanism includes a temperature sensor and associated controls for correction of unwanted temperature effects on measurement and RTC accuracy, e.g. to meet the requirements of ANSI
and IEC standards. Temperature-dependent external components such as a crystal oscillator, current
transformers (CTs) and their corresponding signal conditioning circuits can be characterized and their
correction factors can be programmed to produce electricity meters with exceptional accuracy over the
industrial temperature range.
One of the two internal UARTs is adapted to support an Infrared LED with internal drive and sense configuration and can also function as a standard UART. The optical output can be modulated at 38 kHz.
This flexibility makes it possible to implement AMR meters with an IR interface. A block diagram of the
71M6531D/F IC is shown in Figure 1. A block diagram of the 71M6532D/F IC is shown in Figure 2.
1.2
Analog Front End (AFE)
The AFE consists of an input multiplexer, a delta-sigma A/D converter and a voltage reference.
1.2.1
Signal Input Pins
All analog signal input pins are sensitive to voltage. In the 71M6531D/F, the VA and VB pins, as well as the
IA and IB pins are single-ended. In the 71M6532D/F, the IAP/IAN and IBP/IBN pins can be programmed
individually to be differential (see I/O RAM bit SEL_IAN and SEL_IBN) or single-ended. The differential signal is applied between the IAP and IAN input pins and between the IBP and IBN input pins. Single-ended
signals are applied to the IAP and IBP input pins whereas the common signal, return, is the V3P3A pin.
When using the differential mode, inputs can be chopped, i.e. a connection from V3P3A to IAP or IAN (or
IBP an IBN, respectively) alternates in each multiplexer cycle.
10
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
1.2.2
Data Sheet 71M6531D/F-71M6532D/F
Input Multiplexer
The input multiplexer supports up to four input signals that are applied to pins IA (IAP/IAN), VA, IB
(IBP/IBN), and VB of the device. Additionally, using the alternate multiplexer selection, it has the ability to
select temperature and the battery voltage. The multiplexer can be operated in two modes:
•
During a normal multiplexer cycle, the signals from the IA (IAP/IAN), IB (IBP/IBN), VA and VB pins
are selected.
• During the alternate multiplexer cycle, the temperature signal (TEMP) and the battery monitor are
selected, along with some of the voltage and/or current signal sources shown in Table 1. To prevent
unnecessary drainage on the battery, the battery monitor is only active when enabled with the BME
bit (0x2020[6]) in the I/O RAM.
The alternate multiplexer cycles are usually performed infrequently (every second or so) by the MPU. In
order to prevent disruption of the voltage tracking PLL and voltage allpass networks, VA is not replaced in
the ALT selections. Table 1 details the regular and alternative multiplexer sequences. The computation
engine (CE) fills in missing samples due to an ALT multiplexer sequence.
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles
Regular Slot
Time Slot
0
1
2
3
-------
Alternate Slot
Typical Selections
Register
SLOT0_SEL
SLOT1_SEL
SLOT2_SEL
SLOT3_SEL
SLOT4_SEL
SLOT5_SEL
SLOT6_SEL
SLOT7_SEL
SLOT8_SEL
SLOT9_SEL
RAM Address
0
1
2
3
---–
–
–
Signal for
ADC
IA
VB
IB
VA
---–
–
–
Typical Selections
Register
SLOT0_ALTSEL
SLOT1_ALTSEL
SLOT2_ALTSEL
SLOT3_ALTSEL
SLOT4_ALTSEL
SLOT5_ALTSEL
SLOT6_ALTSEL
SLOT7_ALTSEL
SLOT8_ALTSEL
SLOT9_ALTSEL
RAM Address
A
1
B
3
---–
–
–
Signal for
ADC
TEMP
VB
VBAT
VA
---–
–
–
The sequence of sampled channels is fully programmable using I/O RAM registers. SLOTn_SEL selects
the input for the nth state in a standard multiplexer frame, while SLOTn_ALTSEL selects the input for the
nth state in an alternate multiplexer frame. The states shown in Table 1 are examples for possible multiplexer state sequences.
In a typical application, IA (IAN/IAP) and IB (IBN/IBP) are connected to current transformers that sense
the current on each phase of the line voltage. VA and VB are typically connected to voltage sensors
through resistor dividers.
The multiplexer control circuit (MUX_CTRL signal) controls multiplexer advance, FIR initiation and VREF
chopping. Additionally, MUX_CTRL launches each pass through the CE program. Conceptually,
MUX_CTRL is clocked by CK32, the 32768 Hz clock from the PLL block. The behavior of MUX_CTRL is
governed by MUX_ALT, EQU, CHOP_E and MUX_DIV.
The MUX_ALT bit requests an alternative multiplexer frame. The bit may be asserted on any MPU cycle
and may be subsequently de-asserted on any cycle including the next one. A rising edge on MUX_ALT
will cause MUX_CTRL to wait until the next multiplexer frame and implement a single alternate multiplexer frame.
Another control input to the MUX is MUX_DIV. These four bits can request from 1 to 10 multiplexer states
per frame. The multiplexer always starts at the beginning of its list and proceeds until the number of
states defined by MUX_DIV have been converted.
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
11
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
The duration of each multiplexer state depends on the number of ADC samples processed by the FIR,
which is set by FIR_LEN. Each multiplexer state will start on the rising edge of CK32. The MUX_CTRL
signal sends an FIR_START command to begin the calculation of a sample value from the ADC bit
stream by the FIR. Upon receipt of the FIR_DONE signal from the FIR, the multiplexer will wait until the
next CK32 rising edge to increment its state and initiate the next FIR conversion. FIR conversions require
1, 2, or 3 CK32 cycles. The number of CK32 cycles is determined by FIR_LEN, as shown in Table 2.
1.2.3
A/D Converter (ADC)
A single delta-sigma A/D converter digitizes the voltage and current inputs to the 71M6531D/F and
71M6532D/F. The resolution of the ADC is programmable using the I/O RAM registers M40MHZ and
M26MHZ (see Table 2).
Table 2: ADC Resolution
Setting for [M40MHZ,
M26MHZ]
[00], [10] or [11]
FIR_LEN
0
1
2
0
1
2
[01]
CK32
Cycles
1
2
3
1
2
3
FIR CE Cycles
Resolution
138
288
384
186
384
588
18 bits
21 bits
22 bits
19 bits
22 bits
24 bits
Initiation of each ADC conversion is controlled by MUX_CTRL as described above. At the end of each
ADC conversion, the FIR filter output data is stored into the CE RAM location determined by the MUX
selection.
1.2.4
FIR Filter
The finite impulse response filter is an integral part of the ADC and it is optimized for use with the multiplexer. The purpose of the FIR filter is to decimate the ADC output to the desired resolution. At the end of
each ADC conversion, the output data is stored into the fixed CE RAM location determined by the multiplexer selection as shown in Table 3. FIR data is stored LSB justified, but shifted left by eight bits.
Table 3: ADC RAM Locations
Address (HEX)
0x00
0x01
0x02
0x03
1.2.5
Name
IA
VB
IB
VA
Address (HEX)
0x09
0x0A
0x0B
Name
AUX
TEMP
VBAT
Voltage References
The device includes an on-chip precision bandgap voltage reference that incorporates auto-zero techniques. The reference is trimmed to minimize errors caused by component mismatch and drift. The result is a voltage output with a predictable temperature coefficient.
The amplifier within the reference is chopper stabilized, i.e. the polarity can be switched by the MPU using the I/O RAM register CHOP_E (0x2002[5:4]). The two bits in the CHOP_E register enable the MPU to
operate the chopper circuit in regular or inverted operation, or in toggling mode. When the chopper circuit
is toggled in between multiplexer cycles, DC offsets on the measured signals will automatically be averaged out.
The general topology of a chopped amplifier is shown in Figure 3.
12
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
A
Vinp
B
A
Vinn
A
+
Voutp
B
G
A
-
B
Voutn
B
CROSS
Figure 3: General Topology of a Chopped Amplifier
It is assumed that an offset voltage Voff appears at the positive amplifier input. With all switches, as controlled by CROSS, in the A position, the output voltage is:
Voutp – Voutn = G (Vinp + Voff – Vinn) = G (Vinp – Vinn) + G Voff
With all switches set to the B position by applying the inverted CROSS signal, the output voltage is:
Voutn – Voutp = G (Vinn – Vinp + Voff) = G (Vinn – Vinp) + G Voff, or
Voutp – Voutn = G (Vinp – Vinn) - G Voff
Thus, when CROSS is toggled, e.g. after each multiplexer cycle, the offset will alternately appear on the
output as positive and negative, which results in the offset effectively being eliminated, regardless of its
polarity or magnitude.
When CROSS is high, the connection of the amplifier input devices is reversed. This preserves the overall polarity of that amplifier gain; it inverts its input offset. By alternately reversing the connection, the amplifier’s offset is averaged to zero. This removes the most significant long-term drift mechanism in the
voltage reference. The CHOP_E bits control the behavior of CROSS. The CROSS signal will reverse the
amplifier connection in the voltage reference in order to negate the effects of its offset. On the first CK32
rising edge after the last multiplexer state of its sequence, the multiplexer will wait one additional CK32
cycle before beginning a new frame. At the beginning of this cycle, the value of CROSS will be updated
according to the CHOP_E bits. The extra CK32 cycle allows time for the chopped VREF to settle. During
this cycle, MUXSYNC is held high. The leading edge of MUXSYNC initiates a pass through the CE program sequence. The beginning of the sequence is the serial readout of the four RTM words.
CHOP_E has four states: positive, reverse and two toggle states. In the positive state, CHOP_E = 01,
CROSS and CHOP_CLK are held low. In the reverse state, CHOP_E = 10, CROSS and CHOP_CLK are
held high. In the first toggle state, CHOP_E = 00, CROSS is automatically toggled near the end of each
multiplexer frame and an ALT frame is forced during the last multiplexer frame in each SUM cycle. It is
desirable that CROSS take on alternate values during each ALT frame. For this reason, if CHOP_E = 00,
CROSS will not toggle at the end of the multiplexer frame immediately preceding the ALT frame in each
accumulation interval.
Accumulation interval n
1
2
3
4
Multiplexer frames
Alternative MUX cycle
Accumulation interval n+1
2519 2520 1
2
3
4
Multiplexer frames
2519 2520
Alternative MUX cycle
CROSS
CROSS
Figure 4: CROSS Signal with CHOP_E = 00
Figure 4 shows CROSS over two accumulation interval when CHOP_E = 00: At the end of the first interval, CROSS is low, at the end of the second interval, CROSS is high. The offset error for the two temperature measurements taken during the ALT multiplexer frames will be averaged to zero. Note that the
number of multiplexer frames in an accumulation interval is always even. Operation with CHOP_E = 00
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
13
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
does not require control of the chopping mechanism by the MPU while eliminating the offset for temperature measurement.
In the second toggle state, CHOP_E = 11, no ALT frame is forced during the last multiplexer cycle in an
accumulation interval and CROSS always toggles near the end of each multiplexer frame.
The internal bias voltage, VBIAS (typically 1.6 V), is used by the ADC when measuring the temperature
and battery monitor signals.
1.2.6
Temperature Sensor
The 71M6531D/F and 71M6532D/F include an on-chip temperature sensor implemented as a bandgap
reference. It is used to determine the die temperature. The MPU may request an alternate multiplexer
cycle containing the temperature sensor output by asserting MUX_ALT.
The primary use of the temperature data is to determine the magnitude of compensation required to offset
the thermal drift in the system (see Section 3.4 Temperature Compensation).
1.2.7
Battery Monitor
The battery voltage is measured by the ADC during alternative multiplexer frames if the BME (Battery
Measure Enable) bit in the I/O RAM is set. While BME is set, an on-chip 45 kΩ load resistor is applied to
the battery and a scaled fraction of the battery voltage is applied to the ADC input. After each alternative
MUX frame, the result of the ADC conversion is available at XRAM address 0x0B. BME is ignored and
assumed zero when system power is not available (V1 < VBIAS). See Section 5.4.4 Battery Monitor.
1.2.8
AFE Functional Description
The AFE functions as a data acquisition system, controlled by the MPU. The main signals (IA, VA, IB and
VB) are sampled, and the ADC counts obtained are stored in XRAM where they can be accessed by the
CE and, if necessary, by the MPU. Alternate multiplexer cycles are initiated less frequently by the MPU to
gather access to the slow temperature and battery signals.
Figure 5 shows the block diagram of the AFE, with current inputs shown only as differential pair of pins
(for the 71M6531D/F, the current input for phase A is a single pin [IA]).
VREF
∆Σ ADC
CONVERTER
VBIAS
IAP
VADC
VBIAS
FIR
FIR_LEN
22
IAN
MUX
VA
VREF
VREF_CAL
VREF_DIS
IBP
ADC_E
VREF
IBN
VB
VBAT
EQU
MUX_ALT
MUX_DIV
TEMP
SENSOR
Figure 5: AFE Block Diagram (Shown for the 71M6532D/F)
14
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
1.3
Data Sheet 71M6531D/F-71M6532D/F
Digital Computation Engine (CE)
The CE, a dedicated 32-bit signal processor, performs the precision computations necessary to accurately measure energy. The CE calculations and processes include:
•
•
•
•
•
•
•
•
Multiplication of each current sample with its associated voltage sample to obtain the energy per
sample (when multiplied with the constant sample time).
Frequency-insensitive delay cancellation on all four channels (to compensate for the delay between
samples caused by the multiplexing scheme).
90° phase shifter (for VAR calculations).
Pulse generation.
Monitoring of the input signal frequency (for frequency and phase information).
Monitoring of the input signal amplitude (for sag detection).
Scaling of the processed samples based on calibration coefficients.
Scaling of all samples based on temperature compensation information (71M6532D/F only).
The CE program resides in flash memory. Common access to flash memory by CE and MPU is controlled by a memory share circuit. Each CE instruction word is two bytes long. Allocated flash space for
the CE program cannot exceed 4096 16-bit words (8 KB). The CE program counter begins a pass
through the CE code each time multiplexer state 0 begins. The code pass ends when a HALT instruction
is executed. For proper operation, the code pass must be completed before the multiplexer cycle ends
(see Section 2.2 System Timing Summary).
The CE program must begin on a 1-KB boundary of the flash address. The I/O RAM register
CE_LCTN[7:0] defines which 1-KB boundary contains the CE code. Thus, the first CE instruction is located at 1024*CE_LCTN[7:0].
The CE can access up to 4 KB of data RAM (XRAM), or 1024 32-bit data words, starting at RAM address
0x0000.
The XRAM can be accessed by the FIR filter block, the RTM circuit, the CE, and the MPU. Assigned time
slots are reserved for FIR, and MPU, respectively, to prevent bus contention for XRAM data access.
The MPU can read and write the XRAM as the primary means of data communication between the two
processors. Table 4 shows the CE addresses in XRAM allocated to analog inputs from the AFE.
Table 4: XRAM Locations for ADC Results
Address (HEX)
0x00
0x01
0x02
0x03
0x04...0x09
0x0A
0x0B
Name
IA
VA
IB
VB
–
TEMP
VBAT
Description
Phase A current
Phase A voltage
Phase B current
Phase B voltage
Not used
Temperature
Battery Voltage
The CE is aided by support hardware to facilitate implementation of equations, pulse counters and accumulators. This hardware is controlled through I/O RAM locations EQU (equation assist), DIO_PV and
DIO_PW (pulse count assist) and PRE_SAMPS and SUM_CYCLES (accumulation assist).
PRE_SAMPS and SUM_CYCLES support a dual level accumulation scheme where the first accumulator
accumulates results from PRE_SAMPS samples and the second accumulator accumulates up to
SUM_CYCLES of the first accumulator results. The integration time for each energy output is PRE_SAMPS
* SUM_CYCLES/2520.6 (with MUX_DIV = 1). The CE hardware issues the XFER_BUSY interrupt when
the accumulation is complete.
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
15
Data Sheet 71M6531D/F-71M6532D/F
1.3.1
FDS 6531/6532 005
Meter Equations
The 71M6531D/F and 71M6532D/F provide hardware assistance to the CE in order to support various
meter equations. This assistance is controlled through I/O RAM location EQU (equation assist). The
Compute Engine (CE) firmware for residential configurations implements the equations listed in Table 5.
EQU specifies the equation to be used based on the number of phases used for metering.
Table 5: Meter Equations
Watt and VAR Formula
EQU
Description
0
1
1 element, 2 W, 1φ with
neutral current sense
1 element, 3 W, 1φ
2
2 element, 3 W, 3φ Delta
1.3.2
Element 0
Element 1
Element
2
VA · IA
VA · IB
N/A
VA(IA-IB)/2
N/A
N/A
VA · IA
VB · IB
N/A
Mux
Sequence
ALT Mux Sequence
Sequence is
programmable
with
SLOTn_SEL
Sequence is
programmable
with
SLOTn_ALTSEL
Real-Time Monitor
The CE contains a Real-Time Monitor (RTM), which can be programmed to monitor four selectable XRAM
locations at full sample rate. The four monitored locations are serially output to the TMUXOUT pin via the
digital output multiplexer at the beginning of each CE code pass. The RTM can be enabled and disabled
with RTM_E. The RTM output is clocked by CKTEST (pin SEG19/CKTEST), with the clock output enabled
by setting CKOUT_E = 1. Each RTM word is clocked out in 35 cycles and contains a leading flag bit. See
Figure 20 for the RTM output format. RTM is low when not in use.
1.3.3
Pulse Generators
The 71M6531D/F and 71M6532D/F provide four pulse generators, RPULSE, WPULSE, XPULSE and
YPULSE, as well as increased hardware support for the two original pulse generators (RPULSE and
WPULSE). The pulse generators can be used to output CE status indicators, SAG for example, to DIO
pins.
The polarity of the pulses may be inverted with PLS_INV. When this bit is set, the pulses are active high,
rather than the more usual active low. PLS_INV inverts all the pulse outputs.
XPULSE and YPULSE
The CE sign bit may be exported to the XPULSE and YPULSE pulse generator DFFs using the XPULSE
and YPULSE CE instructions. The DFF outputs are called XPULSE and YPULSE and may be brought
out on DIO8 and DIO9. Generally, the XPULSE and YPULSE DFF outputs are updated once on each
pass of the CE code, resulting in a maximum pulse frequency of 1260 Hz (assuming a multiplexer frame
is 13 CK32 cycles).
The YPULSE pin can be used by the CE code to generate interrupts based on sag events. This method
is faster than checking the sag bits by the MPU at every CE_BUSY interrupt. See Section 4.3.6 CE Status and Control for details.
RPULSE and WPULSE
During each CE code pass, the hardware stores exported WPULSE AND RPULSE sign bits in an 8-bit
FIFO and outputs them at a specified interval. This permits the CE code to calculate the RPULSE AND
WPULSE outputs at the beginning of its code pass and to rely on hardware to spread them over the MUX
frame. The FIFO is reset at the beginning of each MUX frame. PLS_INTERVAL[7:0] controls the delay to
the first pulse update and the interval between subsequent updates. Its LSB is 4 CK_FIR cycles. If zero,
the FIFO is deactivated and the DFFs are updated immediately. Thus, NINTERVAL is 4*PLS_INTERVAL.
Since the FIFO resets at the beginning of each MUX frame, the user must specify PLS_INTERVAL so that
all of the pulse updates are output before the MUX frame completes. For instance, if the CE code outputs
5 updates per MUX interval and if the MUX interval is 1950 cycles long, the ideal value for the interval is
1950/5/4 = 97.5. If PLS_INTERVAL = 98, the fifth output will occur too late and be lost. In this case, the
proper value for PLS_INTERVAL is 97.
16
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
Hardware also provides a maximum pulse width feature. PLS_MAXWIDTH[7:0] selects a maximum negative pulse width to be Nmax updates according to the formula: Nmax = (2*PLS_MAXWIDTH+1). If
PLS_MAXWIDTH=255, no width checking is performed.
The WPULSE and RPULSE pulse generator outputs are available on DIO6 and DIO7, respectively. They
can also be output on OPT_TX (see OPT_TXE[1:0] for details).
1.3.4
Data RAM (XRAM)
The CE and MPU use a single general-purpose Data RAM (also referred to as XRAM). The Data RAM is
1024 32-bit words, shared between the CE and the MPU using a time-multiplex method. This reduces
MPU wait states when accessing CE data. When the MPU and CE are clocking at maximum frequency
(10 MHz), the DRAM will make up to four accesses during each 100 ns interval. These consist of two
MPU accesses, one CE access and one SPI access.
The Data RAM is 32 bits wide and uses an external multiplexer so as to appear byte-wide to the MPU.
The Data RAM hardware will convert an MPU byte write operation into a read-modify-write operation that
requires two Data RAM accesses. The second access is guaranteed to be available because the MPU
cannot access the XRAM on two consecutive instructions unless it is using the same address.
In addition to the reduction of wait states, this arrangement permits the MPU to easily use unneeded CE
data memory. Likewise, the amount of memory the CE uses is not limited by the size of a dedicated CE
data RAM.
1.3.5
CE Functional Overview
The ADC processes one sample per channel per multiplexer cycle. Figure 6 shows the timing of the
samples taken during one multiplexer cycle.
The number of samples processed during one accumulation cycle is controlled by the I/O RAM registers
PRE_SAMPS (0x2001[7:6]) and SUM_CYCLES (0x2001[5:0]). The integration time for each energy output
is:
PRE_SAMPS * SUM_CYCLES / 2520.6, where 2520.6 is the sample rate [Hz]
For example, PRE_SAMPS = 42 and SUM_CYCLES = 50 will establish 2100 samples per accumulation
cycle. PRE_SAMPS = 100 and SUM_CYCLES = 21 will result in the exact same accumulation cycle of 2100
samples or 833 ms. After an accumulation cycle is completed, the XFER_BUSY interrupt signals to the
MPU that accumulated data are available.
1/32768Hz =
30.518µs
IB
VB
IA
VA
13/32768Hz = 397µs
per mux cycle
Figure 6: Samples from Multiplexer Cycle
The end of each multiplexer cycle is signaled to the MPU by the CE_BUSY interrupt. At the end of each
multiplexer cycle status information, such as sag data and the digitized input signal, is available to the MPU.
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
17
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
833ms
20ms
XFER_BUSY
Interrupt to MPU
Figure 7: Accumulation Interval
Figure 7 shows the accumulation interval resulting from PRE_SAMPS = 42 and SUM_CYCLES = 50, consisting of 2100 samples of 397µs each, followed by the XFER_BUSY interrupt. The sampling in this example is applied to a 50 Hz signal.
There is no correlation between the line signal frequency and the choice of PRE_SAMPS or SUM_CYCLES
(even though when SUM_CYCLES = 42 one set of SUM_CYCLES happens to sample a period of 16.6 ms).
Furthermore, sampling does not have to start when the line voltage crosses the zero line and the length
of the accumulation interval need not be an integer multiple of the signal cycles.
18
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
1.4
Data Sheet 71M6531D/F-71M6532D/F
80515 MPU Core
The 71M6531D/F and 71M6532D/F include an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one clock cycle. Using a 10-MHz clock results in a processing throughput of 10 MIPS. The
80515 architecture eliminates redundant bus states and implements parallel execution of fetch and execution phases. Normally, a machine cycle is aligned with a memory fetch, therefore, most of the 1-byte instructions are performed in a single machine cycle (MPU clock cycle). This leads to an 8x average performance improvement (in terms of MIPS) over the Intel 8051 device running at the same clock frequency.
Table 6 shows the CKMPU frequency as a function of the allowed combinations of the MPU clock divider
MPU_DIV[2:0] and the MCK divider registers M40MHZ and M26MHZ. Actual processor clocking speed
can be adjusted to the total processing demand of the application (metering calculations, AMR management, memory management, LCD driver management and I/O management) using the I/O RAM register
MPU_DIV[2:0] and the MCK divider registers M40MHZ and M26MHZ, as shown in Table 6.
Table 6: CKMPU Clock Frequencies
MPU_DIV [2:0]
000
001
010
011
100
101
110
111
[M40MHZ, M26MHZ] Values
[1,0]
[0,1]
[0,0]
10 MHz
6.6 MHz
5 MHz
5 MHz
3.3 MHz
2.5 MHz
2.5 MHz
1.65 MHz
1.25 MHz
1.25 MHz
825 kHz
625 kHz
625 kHz
412.5 kHz
312.5 kHz
312.5 kHz
206.25 kHz
156.25 kHz
156.25 kHz
103.13 kHz
78.13 kHz
156.25 kHz
103.13 kHz
78.13 kHz
Typical measurement and metering functions based on the results provided by the internal 32-bit compute engine (CE) are available for the MPU as part of Teridian’s standard library. A standard ANSI C
80515 application programming interface library is available to help reduce design cycle.
1.4.1
Memory Organization and Addressing
The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces. Memory organization in the 80515 is similar to that of the industry standard 8051. There are four memory
areas: Program memory (Flash, shared by MPU and CE), external RAM (Data RAM, shared by the CE
and MPU), Configuration RAM and internal data memory (Internal RAM). Table 7 shows the memory
map.
Program Memory
The 80515 can address up to 64 KB of program memory space from 0x0000 to 0xFFFF. Program memory is read when the MPU fetches instructions or performs a MOVC operation. Access to program memory
above 0x7FFF is controlled by the FL_BANK[2:0] register (SFR 0xB6).
After reset, the MPU starts program execution from program memory location 0x0000. The lower part of
the program memory includes reset and interrupt vectors. The interrupt vectors are spaced at 8-byte intervals, starting from 0x0003.
MPU External Data Memory (XRAM)
Both internal and external memory is physically located on the 71M6531 device. The external memory
referred to in this documentation is only external to the 80515 MPU core.
4 KB of RAM starting at address 0x0000 is shared by the CE and MPU. The CE normally uses the first
1 KB, leaving 3 KB for the MPU. Different versions of the CE code use varying amounts. Consult the
documentation for the specific code version being used for the exact limit.
If the MPU overwrites the CE’s working RAM, the CE’s output may be corrupted. If the CE is disabled,
the first 0x40 bytes of RAM are still unusable because the 71M6531 ADC writes to these locations.
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
19
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
The 80515 writes into external data memory when the MPU executes a MOVX @Ri,A or MOVX
@DPTR,A instruction. The MPU reads external data memory by executing a MOVX A,@Ri or MOVX
A,@DPTR instruction (SFR PDATA provides the upper 8 bytes for the MOVX A,@Ri instruction).
Internal and External Memory Map
Table 7 shows the address, type, use and size of the various memory components.
Only the memory ranges shown in Table 7 contain physical memory.
Table 7: Memory Map
Address
Memory
Memory
(hex)
Technology
Type
00000-1FFFF/ Flash Memo- Non-volatile
00000-3FFFF
ry
on 1K boundary
Flash Memo- Non-volatile
ry
Name
Typical Usage
Program memory
MPU Program and
non-volatile data
Memory Size
(bytes)
128 KB/
256 KB
Program memory
CE program
8 KB max.
0000-0FFF
Static RAM
Volatile
External RAM
(XRAM)
Shared by CE and
MPU
4 KB
2000-20BF,
20C8-20FF
Static RAM
Volatile
Configuration RAM,
I/O RAM
Hardware control
256
20C0-20C7
Static RAM
Non-volatile
(battery)
Configuration RAM,
I/O RAM
Battery-buffered
memory
8
0000-00FF
Static RAM
Volatile
Internal RAM
Part of 80515 Core
256
MOVX Addressing
There are two types of instructions differing in whether they provide an 8-bit or 16-bit indirect address to
the external data RAM.
In the first type, MOVX A,@Ri, the contents of R0 or R1 in the current register bank provide the eight
lower-ordered bits of address. The eight high-ordered bits of the address are specified with the PDATA
SFR. This method allows the user paged access (256 pages of 256 bytes each) to all ranges of the
external data RAM.
In the second type of MOVX instruction, MOVX A,@DPTR, the data pointer generates a 16-bit address.
This form is faster and more efficient when accessing very large data arrays (up to 64 KB), since no
additional instructions are needed to set up the eight high ordered bits of the address.
It is possible to mix the two MOVX types. This provides the user with four separate data pointers, two
with direct access and two with paged access, to the entire 64 KB of external memory range.
Dual Data Pointer
The Dual Data Pointer accelerates the block moves of data. The standard DPTR is a 16-bit register that
is used to address external memory or peripherals. In the 80515 core, the standard data pointer is called
DPTR, the second data pointer is called DPTR1. The data pointer select bit, located in the LSB of the DPS
register (DPS[0]), chooses the active pointer. DPTR is selected when DPS[0] = 0 and DPTR1 is selected
when DPS[0] = 1.
The user switches between pointers by toggling the LSB of the DPS register. The values in the data pointers are not affected by the LSB of the DPS register. All DPTR related instructions use the currently selected DPTR for any activity.
The second data pointer may not be supported by certain compilers.
DPTR1 is useful for copy routines, where it can make the inner loop of the routine two instructions faster compared to the reloading of DPTR from registers. Any interrupt routine using DPTR1 must save
and restore DPS, DPTR and DPTR1, which increases stack usage and slows down interrupt latency.
20
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
By selecting the Evatronics R80515 core in the Keil compiler project settings and by using the compiler
directive “MODC2”, dual data pointers are enabled in certain library routines.
An alternative data pointer is available in the form of the PDATA register (SFR 0xBF, sometimes referred
to as USR2). It defines the high byte of a 16-bit address when reading or writing XDATA with the instruction MOVX A,@Ri or MOVX @Ri,A.
Internal Data Memory Map and Access
The Internal data memory provides 256 bytes (0x00 to 0xFF) of data memory. The internal data memory
address is always 1 byte wide. Table 8 shows the internal data memory map.
The Special Function Registers (SFR) occupy the upper 128 bytes. The SFR area of internal data memory is available only by direct addressing. Indirect addressing of this area accesses the upper 128 bytes of
Internal RAM. The lower 128 bytes contain working registers and bit addressable memory. The lower 32
bytes form four banks of eight registers (R0-R7). Two bits on the program memory status word (PSW)
select which bank is in use. The next 16 bytes form a block of bit addressable memory space at bit addresses 0x00-0x7F. All of the bytes in the lower 128 bytes are accessible through direct or indirect addressing.
Table 8: Internal Data Memory Map
Address
0xFF
0x80
0x7F
0x30
0x2F
0x20
0x1F
0x00
1.4.2
Direct addressing
Indirect addressing
Special Function Registers (SFRs)
RAM
Byte addressable area
Bit addressable area
Register banks R0…R7
Special Function Registers (SFRs)
A map of the Special Function Registers is shown in Table 9.
Only a few addresses in the SFR memory space are occupied, the others are not implemented. A read
access to unimplemented addresses will return undefined data, while a write access will have no effect.
SFRs specific to the 71M6531D/F and 71M6532D/F are shown in bold print on a gray field. The registers
at 0x80, 0x88, 0x90, etc., are bit addressable, all others are byte addressable.
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
21
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
Table 9: Special Function Register Map
Bit
Hex/ Addressable
Bin
X000
X001
F8
INTBITS
B
F0
E8
IFLAGS
A
E0
WDCON
D8
PSW
D0
T2CON
C8
IRCON
C0
IEN1
IP1
B8
B0
P3
IEN0
IP0
A8
A0
P2
DIR2
S0CON
S0BUF
98
90
P1
DIR1
TCON
TMOD
88
P0
SP
80
1.4.3
Byte Addressable
X010
X011
S0RELH
FLSHCTL
S0RELL
DIR0
IEN2
DPS
TL0
DPL
X100
X101
X110
S1RELH
S1CON
TL1
DPH
S1BUF
ERASE
TH0
DPL1
X111
FL_BANK
PDATA
PGADR
S1RELL
EEDATA
EECTRL
TH1
DPH1
CKCON
PCON
Bin/
Hex
FF
F7
EF
E7
DF
D7
CF
C7
BF
B7
AF
A7
9F
97
8F
87
Generic 80515 Special Function Registers
Table 10 shows the location, description and reset or power-up value of the generic 80515 SFRs. Additional descriptions of the registers can be found at the page numbers listed in the table.
Table 10: Generic 80515 SFRs - Location and Reset Values
Name
P0
SP
DPL
DPH
DPL1
DPH1
PCON
TCON
TMOD
TL0
TL1
TH0
TH1
CKCON
DPS
S0CON
S0BUF
IEN2
S1CON
S1BUF
22
Address
(Hex)
0x80
0x81
0x82
0x83
0x84
0x85
0x87
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0x8E
0x92
0x98
0x99
0x9A
0x9B
0x9C
Reset value
(Hex)
0xFF
0x07
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x01
0x00
0x00
0x00
0x00
0x00
0x00
Description
Port 0
Stack Pointer
Data Pointer Low 0
Data Pointer High 0
Data Pointer Low 1
Data Pointer High 1
UART Speed Control, Idle and Stop mode Control
Timer/Counter Control
Timer Mode Control
Timer 0, low byte
Timer 1, high byte
Timer 0, low byte
Timer 1, high byte
Clock Control (Stretch=1)
Data Pointer select Register
Serial Port 0, Control Register
Serial Port 0, Data Buffer
Interrupt Enable Register 2
Serial Port 1, Control Register
Serial Port 1, Data Buffer
© 2005-2009 TERIDIAN Semiconductor Corporation
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32
30
29
29
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20
28
26
31
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v1.2
FDS 6531/6532 005
Name
S1RELL
IEN0
IP0
S0RELL
IEN1
IP1
S0RELH
S1RELH
PDATA
IRCON
T2CON
PSW
WDCON
A
B
Address
(Hex)
0x9D
0xA8
0xA9
0xAA
0xB8
0xB9
0xBA
0xBB
0xBF
0xC0
0xC8
0xD0
0xD8
0xE0
0xF0
Data Sheet 71M6531D/F-71M6532D/F
Reset value
(Hex)
0x00
0x00
0x00
0xD9
0x00
0x00
0x03
0x03
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Description
Page
Serial Port 1, Reload Register, low byte
Interrupt Enable Register 0
Interrupt Priority Register 0
Serial Port 0, Reload Register, low byte
Interrupt Enable Register 1
Interrupt Priority Register 1
Serial Port 0, Reload Register, high byte
Serial Port 1, Reload Register, high byte
High address byte for [email protected] - also called USR2
Interrupt Request Control Register
Polarity for INT2 and INT3
Program Status Word
Baud Rate Control Register (only WDCON[7] bit used)
Accumulator
B Register
27
31
34
27
31
34
27
27
20
32
32
23
26
23
23
Accumulator (ACC, A):
ACC is the accumulator register. Most instructions use the accumulator to hold the operand. The mnemonics for accumulator-specific instructions refer to accumulator as A, not ACC.
B Register:
The B register is used during multiply and divide instructions. It can also be used as a scratch-pad register to hold temporary data.
Program Status Word (PSW):
This register contains various flags and control bits for the selection of the register banks (see Table 11).
Table 11: PSW Bit Functions (SFR 0xD0)
PSW Bit
7
6
5
Symbol
CV
AC
F0
Function
Carry flag.
Auxiliary Carry flag for BCD operations.
General-purpose Flag 0 available for user.
F0 is not to be confused with the F0 flag in the CESTATUS register.
v1.2
4
RS1
3
RS0
2
1
0
OV
P
Register bank select control bits. The contents of RS1 and RS0 select the
working register bank:
RS1/RS0
Bank selected
Location
00
Bank 0
0x00 – 0x07
01
Bank 1
0x08 – 0x0F
10
Bank 2
0x10 – 0x17
11
Bank 3
0x18 – 0x1F
Overflow flag.
User defined flag.
Parity flag, affected by hardware to indicate odd or even number of one bits in
the Accumulator, i.e. even parity.
© 2005-2009 TERIDIAN Semiconductor Corporation
23
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
Stack Pointer (SP):
The stack pointer is a 1-byte register initialized to 0x07 after reset. This register is incremented before
PUSH and CALL instructions, causing the stack to begin at location 0x08.
Data Pointer:
The data pointer (DPTR) is 2 bytes wide. The lower part is DPL and the highest is DPH. It can be loaded
as two registers (e.g. MOV DPL,#data8). It is generally used to access external code or data space (e.g.
MOVC A,@A+DPTR or MOVX A,@DPTR respectively).
Program Counter:
The program counter (PC) is 2 bytes wide and initialized to 0x0000 after reset. This register is incremented when fetching operation code or when operating on data from program memory.
Port Registers:
The I/O ports are controlled by Special Function Registers P0, P1 and P2. The contents of the SFR can
be observed on corresponding pins on the chip. Writing a 1 to any of the ports (see Table 12) causes the
corresponding pin to be at high level (V3P3). Writing a 0 causes the corresponding pin to be held at a
low level (GND). The data direction registers DIR0, DIR1 and DIR2 define individual pins as input or output pins (see Sections 1.5.7 Digital I/O – 71M6531D/F or 1.5.8 Digital I/O – 71M6532D/F).
Table 12: Port Registers
Register
P0
DIR0
P1
DIR1
P2
DIR2
SFR AdR/W
Description
dress
0x80
R/W Register for port 0 read and write operations.
0xA2
R/W Data direction register for port 0. Setting a bit to 1 means that the corresponding pin is an output.
0x90
R/W Register for port 1 read and write operations.
0x91
R/W Data direction register for port 1.
0xA0
R/W Register for port 2 read and write operations.
0xA1
R/W Data direction register for port 2.
All DIO ports on the chip are bi-directional. Each of them consists of a Latch (SFR P0 to P2), an output
driver and an input buffer, therefore the MPU can output or read data through any of these ports. Even if
a DIO pin is configured as an output, the state of the pin can still be read by the MPU, for example when
counting pulses issued via DIO pins that are under CE control.
The technique of reading the status of or generating interrupts based on DIO pins configured as
outputs can be used to implement pulse counting.
Clock Stretching (CKCON)
The three low order bits of the CKCON register define the stretch memory cycles that could be used for
MOVX instructions when accessing slow external peripherals. The practical value of this register is to
guarantee access to XRAM between CE, MPU, and SPI. The default setting of CKCON (001) should not
be changed.
Table 13 shows how the signals of the External Memory Interface change when stretch values are set
from 0 to 7. The widths of the signals are counted in MPU clock cycles. The post-reset state of the
CKCON register (001), which is shown in bold in the table, performs the MOVX instructions with a stretch
value equal to 1.
24
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
Table 13: Stretch Memory Cycle Width
1.4.4
CKCON[2:0]
Stretch
Value
000
001
010
011
100
101
110
111
0
1
2
3
4
5
6
7
Read signal width
memaddr
memrd
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
Write signal width
memaddr
memwr
2
1
3
1
4
2
5
3
6
4
7
5
8
6
9
7
Special Function Registers (SFRs) Specific to the 71M6531D/F and 71M6532D/F
Table 14 shows the location and description of the SFRs specific to the 71M6531D/F and 71M6532D/F.
Table 14: 71M6531D/F and 71M6532D/F Specific SFRs
Register
(Alternate
Name)
EEDATA
EECTRL
SFR
Address
Bit Field
Name
R/W
Description
0x9E
0x9F
R/W
R/W
ERASE
(FLSH_ERASE)
0x94
W
FL_BANK
PGADDR
(FLSH_PGADR)
0xB6[2:0]
0xB7
FLSHCRL
0xB2[0]
FLSH_PWE
0xB2[1]
FLSH_MEEN
0xB2[6]
SECURE
0xB2[7]
PREBOOT
I2C EEPROM interface data register.
I2C EEPROM interface control register. See
Section 1.5.14 EEPROM Interface for a description of the command and status bits available
for EECTRL.
This register is used to initiate either the Flash
Mass Erase cycle or the Flash Page Erase cycle.
See the Flash Memory section for details.
Flash Bank Selection.
Flash Page Erase Address register. Contains
the flash memory page address (page 0 through
page 127) that will be erased during the Page
Erase cycle (default = 0x00).
Must be re-written for each new Page Erase
cycle.
Program Write Enable:
0: MOVX commands refer to XRAM Space,
normal operation (default).
1: MOVX @DPTR,A moves A to Program
Space (Flash) @ DPTR.
Mass Erase Enable:
0: Mass Erase disabled (default).
1: Mass Erase enabled.
Must be re-written for each new Mass Erase
cycle.
Enables security provisions that prevent external reading of flash memory and CE program
RAM. This bit is reset on chip reset and may
only be set. Attempts to write zero are ignored.
Indicates that the preboot sequence is active.
v1.2
R/W
R/W
R/W
W
R/W
R
© 2005-2009 TERIDIAN Semiconductor Corporation
25
Data Sheet 71M6531D/F-71M6532D/F
Register
(Alternate
Name)
IFLAGS
IFLAGS (cont.)
INTBITS
(INT0 … INT6)
SFR
Address
Bit Field
Name
FDS 6531/6532 005
R/W
Description
This flag monitors the XFER_BUSY interrupt. It
is set by hardware and must be cleared by the
interrupt handler.
This flag monitors the RTC_1SEC interrupt. It
is set by hardware and must be cleared by the
interrupt handler.
This flag indicates that a flash write was attempted while the CE was busy.
This flag indicates that a flash write was in progress when the CE was attempting to begin a
code pass.
This flag indicates that the wake-up pushbutton
was pressed.
This flag indicates that the MPU was awakened
by the autowake timer.
PLL_RISE Interrupt Flag:
Write 0 to clear the PLL_RISE interrupt flag.
PLL_FALL Interrupt Flag:
Write 0 to clear the PLL_FALL interrupt flag.
Interrupt inputs. The MPU may read these bits
to see the status of external interrupts INT0 up
to INT6. These bits do not have any memory
and are primarily intended for debug use.
The WDT is reset when a 1 is written to this bit.
0xE8[0]
IE_XFER
R/W
0xE8[1]
IE_RTC
R/W
0xE8[2]
FW_COL0
R/W
0xE8[3]
FW_COL1
R/W
0xE8[4]
IE_PB
R/W
0xE8[5]
IE_WAKE
R/W
0xE8[6]
PLL_RISE
R/W
0xE8[7]
PLL_FALL
R/W
0xF8[6:0]
INT6 … INT0
R
0xF8[7]
WD_RST
W
Only byte operations on the entire INTBITS register should be used when
writing. The byte must have all bits set except the bits that are to be cleared.
1.4.5
Instruction Set
All instructions of the generic 8051 microcontroller are supported. A complete list of the instruction set
and of the associated op-codes is contained in the 71M653X Software User’s Guide (SUG).
1.4.6
UARTs
The 71M6531D/F and 71M6532D/F includes a UART (UART0) that can be programmed to communicate
with a variety of AMR modules. A second UART (UART1) is connected to the optical port, as described
in Section 1.5.6 Optical Interface.
The UARTs are dedicated 2-wire serial interfaces, which can communicate with an external host processor at up to 38,400 bits/s (with MPU clock = 1.2288 MHz). The operation of the RX and TX UART0
pins is as follows:
•
•
UART0 RX: Serial input data are applied at this pin. Conforming to RS-232 standard, the bytes are
input LSB first.
UART0 TX: This pin is used to output the serial data. The bytes are output LSB first.
The 71M6531D/F and 71M6532D/F have several UART-related registers for the control and buffering of
serial data.
The serial buffers consist of sets of two separate registers (one set for each UART), a transmit buffer
(S0BUF, S1BUF) and a receive buffer (R0BUF, R1BUF). Writing data to the transmit buffer starts the
transmission by the associated UART. Received data are available by reading from the receive buffer.
Both UARTs can simultaneously transmit and receive data.
26
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
WDCON[7] selects whether timer 1 or the internal baud rate generator is used. All UART transfers are
programmable for parity enable, parity, 2 stop bits/1 stop bit and XON/XOFF options for variable communication baud rates from 300 to 38400 bps. Table 15 shows how the baud rates are calculated. Table 16
shows the selectable UART operation modes.
Table 15: Baud Rate Generation
UART0
Using Timer 1
(WDCON[7] = 0)
2smod * fCKMPU/ (384 * (256-TH1))
Using Internal Baud Rate Generator
(WDCON[7] = 1)
2smod * fCKMPU/(64 * (210-S0REL))
UART1
N/A
fCKMPU/(32 * (210-S1REL))
S0REL and S1REL are 10-bit values derived by combining bits from the respective timer reload registers.
SMOD is the SMOD bit in the SFR PCON register. TH1 is the high byte of timer 1.
Table 16: UART Modes
UART 0
Mode 0
Mode 1
Mode 2
Mode 3
N/A
Start bit, 8 data bits, stop bit, variable
baud rate (internal baud rate generator
or timer 1)
Start bit, 8 data bits, parity, stop bit,
fixed baud rate 1/32 or 1/64 of fCKMPU
Start bit, 8 data bits, parity, stop bit, variable baud rate (internal baud rate generator or timer 1)
UART 1
Start bit, 8 data bits, parity, stop bit, variable
baud rate (internal baud rate generator)
Start bit, 8 data bits, stop bit, variable baud
rate (internal baud rate generator)
N/A
N/A
Parity of serial data is available through the P flag of the accumulator. 7-bit serial modes with
parity, such as those used by the FLAG protocol, can be simulated by setting and reading bit 7 of
8-bit output data. 7-bit serial modes without parity can be simulated by setting bit 7 to a constant
1. 8-bit serial modes with parity can be simulated by setting and reading the 9th bit, using the
control bits TB80 (S0CON[3]) and TB81 (S1CON[3]) in the S0CON and S1CON SFRs for transmit
and RB81 (S1CON[2]) for receive operations.
The feature of receiving 9 bits (Mode 3 for UART0, Mode A for UART1) can be used as handshake signals for inter-processor communication in multi-processor systems. In this case, the slave processors
have bit SM20 (S0CON[5]) for UART0, or SM21 (S1CON[5] for UART1, set to 1. When the master processor outputs the slave’s address, it sets the 9th bit to 1, causing a serial port receive interrupt in all the
slaves. The slave processors compare the received byte with their address. If there is a match, the addressed slave will clear SM20 or SM21 and receive the rest of the message. All other slaves will ignore
the message. After addressing the slave, the host outputs the rest of the message with the 9th bit set to 0,
so no additional serial port receive interrupts will be generated.
UART Control Registers:
The functions of UART0 and UART1 depend on the setting of the Serial Port Control Registers S0CON
and S1CON shown in Table 17 and
Table 18, respectively and the PCON register shown in Table 19.
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
27
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
Table 17: The S0CON (UART0) Register (SFR 0x98)
Bit
S0CON[7]
Symbol
SM0
S0CON[6]
SM1
S0CON[5]
S0CON[4]
S0CON[3]
SM20
REN0
TB80
S0CON[2]
RB80
S0CON[1]
TI0
S0CON[0]
RI0
Function
The SM0 and SM1 bits set the UART0 mode:
Mode
Description
SM0
SM1
0
N/A
0
0
1
8-bit UART
0
1
2
9-bit UART
1
0
3
9-bit UART
1
1
Enables the inter-processor communication feature.
If set, enables serial reception. Cleared by software to disable reception.
The 9th transmitted data bit in Modes 2 and 3. Set or cleared by the
MPU, depending on the function it performs (parity check, multiprocessor
communication etc.)
In Modes 2 and 3 it is the 9th data bit received. In Mode 1, SM20 is 0,
RB80 is the stop bit. In mode 0, this bit is not used. Must be cleared by
software.
Transmit interrupt flag; set by hardware after completion of a serial transfer. Must be cleared by software.
Receive interrupt flag; set by hardware after completion of a serial reception. Must be cleared by software.
Table 18: The S1CON (UART1) register (SFR 0x9B)
Bit
S1CON[7]
Symbol
SM
S1CON[5]
S1CON[4]
S1CON[3]
SM21
REN1
TB81
S1CON[2]
RB81
S1CON[1]
TI1
S1CON[0]
RI1
Function
Sets the baud rate and mode for UART1.
SM
Mode
Description
Baud Rate
0
A
9-bit UART
variable
1
B
8-bit UART
variable
Enables the inter-processor communication feature.
If set, enables serial reception. Cleared by software to disable reception.
The 9th transmitted data bit in Mode A. Set or cleared by the MPU, depending on the function it performs (parity check, multiprocessor communication etc.)
In Modes A and B, it is the 9th data bit received. In Mode B, if SM21 is 0,
RB81 is the stop bit. Must be cleared by software
Transmit interrupt flag, set by hardware after completion of a serial transfer. Must be cleared by software.
Receive interrupt flag, set by hardware after completion of a serial reception. Must be cleared by software.
Table 19: PCON Register Bit Description (SFR 0x87)
Bit
Symbol
Function
PCON[7]
SMOD
The SMOD bit doubles the baud rate when set
PCON[6:2]
–
Not used.
PCON[1]
STOP
Stops MPU flash access and MPU peripherals including timers and
UARTs when set until an external interrupt is received.
PCON[0]
IDLE
Stops MPU flash access when set until an internal interrupt is received.
28
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
1.4.7
Data Sheet 71M6531D/F-71M6532D/F
Timers and Counters
The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be configured for counter or timer operations.
In timer mode, the register is incremented every machine cycle, i.e. it counts up once for every 12 periods
of the MPU clock. In counter mode, the register is incremented when the falling edge is observed at the
corresponding input signal T0 or T1 (T0 and T1 are the timer gating inputs derived from certain DIO pins,
see Section 1.5.7 Digital I/O). Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum
input count rate is 1/2 of the clock frequency (CKMPU). There are no restrictions on the duty cycle, however to ensure proper recognition of the 0 or 1 state, an input should be stable for at least 1 machine
cycle.
Four operating modes can be selected for Timer 0 and Timer 1, as shown in Table 20 and Table 21. The
TMOD Register, shown in Table 22, is used to select the appropriate mode. The timer/counter operation
is controlled by the TCON Register, which is shown in Table 23. Bits TR1 (TCON[6]) and TR0 (TCON[4]) in
the TCON register start their associated timers when set.
Table 20: Timers/Counters Mode Description
M1
0
M0
0
0
1
1
0
M1
1
M0
1
Mode
Function
Mode 0 13-bit Counter/Timer mode with 5 lower bits in the TL0 or TL1 register and
the remaining 8 bits in the TH0 or TH1 register (for Timer 0 and Timer 1,
respectively). The 3 high order bits of TL0 and TL1 are held at zero.
Mode 1 16-bit Counter/Timer mode.
Mode 2 8-bit auto-reload Counter/Timer. The reload value is kept in TH0 or TH1,
while TL0 or TL1 is incremented every machine cycle. When TL(x) overflows, a value from TH(x) is copied to TL(x) (where x is 0 for counter/timer 0 or 1 for counter/timer 1.
Mode
Function
Mode 3 If Timer 1 M1 and M0 bits are set to 1, Timer 1 stops.
If Timer 0 M1 and M0 bits are set to 1, Timer 0 acts as two independent
8-bit Timer/Counters.
In Mode 3, TL0 is affected by TR0 and gate control bits and sets the TF0 flag on overflow, while TH0
is affected by the TR1 bit and the TF1 flag is set on overflow.
Table 21 specifies the combinations of operation modes allowed for Timer 0 and Timer 1.
Table 21: Allowed Timer/Counter Mode Combinations
Timer 0 - mode 0
Timer 0 - mode 1
Timer 0 - mode 2
v1.2
Mode 0
YES
YES
Not allowed
Timer 1
Mode 1
YES
YES
Not allowed
Mode 2
YES
YES
YES
© 2005-2009 TERIDIAN Semiconductor Corporation
29
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
Table 22: TMOD Register Bit Description (SFR 0x89)
Bit
Symbol
Timer/Counter 1:
Gate
TMOD[7]
TMOD[6]
C/T
TMOD[5:4]
M1:M0
Timer/Counter 0:
TMOD[3]
Gate
TMOD[2]
C/T
TMOD[1:0]
M1:M0
Function
If set, enables external gate control (pin INT1). When INT1 is high and
the TR1 bit is set (see the TCON register), a counter is incremented every
falling edge on T1 input pin
Selects timer or counter operation. When set to 1, a counter operation is
performed. When cleared to 0, the corresponding register will function as a
timer.
Selects the mode for Timer/Counter 0 as shown in Table 20.
If set, enables external gate control (pin INT0). When INT0 is high and
the TR0 bit is set (see the TCON register), a counter is incremented every
falling edge on T0 input pin.
Selects timer or counter operation. When set to 1, a counter operation is
performed. When cleared to 0, the corresponding register will function as
a timer.
Selects the mode for Timer/Counter 1, as shown in Table 20.
Table 23: The TCON Register Bit Functions (SFR 0x88)
Bit
TCON[7]
Symbol
TF1
TCON[6]
TCON[5]
TR1
TF0
TCON[4]
TCON[3]
TR0
IE1
TCON[2]
IT1
TCON[1]
IE0
TCON[0]
IT0
1.4.8
Function
The Timer 1 overflow flag is set by hardware when Timer 1 overflows.
This flag can be cleared by software and is automatically cleared when
an interrupt is processed.
Timer 1 run control bit. If cleared, Timer 1 stops.
Timer 0 overflow flag set by hardware when Timer 0 overflows. This
flag can be cleared by software and is automatically cleared when an
interrupt is processed.
Timer 0 Run control bit. If cleared, Timer 0 stops.
Interrupt 1 edge flag is set by hardware when the falling edge on external pin int1 is observed. Cleared when an interrupt is processed.
Interrupt 1 type control bit. Selects either the falling edge or low level
on input pin to cause an interrupt.
Interrupt 0 edge flag is set by hardware when the falling edge on external pin int0 is observed. Cleared when an interrupt is processed.
Interrupt 0 type control bit. Selects either the falling edge or low level
on input pin to cause interrupt.
WD Timer (Software Watchdog Timer)
There is no internal software watchdog timer. Use the standard watchdog timer instead (see 1.5.16
Hardware Watchdog Timer).
1.4.9
Interrupts
The 80515 MPU provides 11 interrupt sources with four priority levels. Each source has its own request
flag(s) located in a special function register (TCON, IRCON and SCON). Each interrupt requested by the
corresponding flag can be individually enabled or disabled by the enable bits in SFRs IEN0, IEN1 and
IEN2. Figure 8 shows the device interrupt structure.
30
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
Interrupt Overview
When an interrupt occurs, the MPU will vector to the predetermined address as shown in Table 36. Once
the interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service is terminated by a return from instruction, RETI. When an RETI is performed, the processor will return to the instruction that would have been next when the interrupt occurred.
When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. This bit is
set regardless of whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per
machine cycle, after that, samples are polled by the hardware. If the sample indicates a pending interrupt
when the interrupt is enabled, then the interrupt request flag is set. On the next instruction cycle, the interrupt will be acknowledged by hardware forcing an LCALL to the appropriate vector address, if the following conditions are met:
• No interrupt of equal or higher priority is already in progress.
• An instruction is currently being executed and is not completed.
• The instruction in progress is not RETI or any write access to the registers IEN0, IEN1, IEN2, IP0 or IP1.
Special Function Registers for Interrupts
The following SFR registers control the interrupt functions:
•
•
•
•
The interrupt enable registers: IEN0, IEN1 and IEN2 (see Table 24, Table 25 and Table 26.
The Timer/Counter control registers, TCON and T2CON (see Table 27 and Table 28).
The interrupt request register, IRCON (see Table 29).
The interrupt priority registers: IP0 and IP1 (see Table 34).
Table 24: The IEN0 Bit Functions (SFR 0xA8)
Bit
IEN0[7]
IEN0[6]
IEN0[5]
IEN0[4]
IEN0[3]
IEN0[2]
IEN0[1]
IEN0[0]
Symbol
EAL
WDT
–
ES0
ET1
EX1
ET0
EX0
Function
EAL = 0 disables all interrupts.
Not used for interrupt control.
Not Used.
ES0 = 0 disables serial channel 0 interrupt.
ET1 = 0 disables timer 1 overflow interrupt.
EX1 = 0 disables external interrupt 1.
ET0 = 0 disables timer 0 overflow interrupt.
EX0 = 0 disables external interrupt 0.
Table 25: The IEN1 Bit Functions (SFR 0xB8)
Bit
IEN1[7]
Symbol
–
Not used.
Function
IEN1[6]
–
Not used.
IEN1[5]
IEN1[4]
IEN1[3]
IEN1[2]
IEN1[1]
IEN1[0]
EX6
EX5
EX4
EX3
EX2
–
EX6 = 0 disables external interrupt 6.
EX5 = 0 disables external interrupt 5.
EX4 = 0 disables external interrupt 4.
EX3 = 0 disables external interrupt 3.
EX2 = 0 disables external interrupt 2.
Not Used.
Table 26: The IEN2 Bit Functions (SFR 0x9A)
Bit
IEN2[0]
v1.2
Symbol
ES1
Function
ES1 = 0 disables the serial channel 1 interrupt.
© 2005-2009 TERIDIAN Semiconductor Corporation
31
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
Table 27: TCON Bit Functions (SFR 0x88)
Bit
TCON[7]
TCON[6]
TCON[5]
TCON[4]
TCON[3]
TCON[2]
Symbol
TF1
TR1
TF0
TR0
IE1
IT1
TCON[1]
TCON[0]
IE0
IT0
Function
Timer 1 overflow flag.
Not used for interrupt control.
Timer 0 overflow flag.
Not used for interrupt control.
External interrupt 1 flag.
External interrupt 1 type control bit:
0 = interrupt on low level.
1 = interrupt on falling edge.
External interrupt 0 flag
External interrupt 0 type control bit:
0 = interrupt on low level.
1 = interrupt on falling edge.
Table 28: The T2CON Bit Functions (SFR 0xC8)
Bit
T2CON[7]
T2CON[6]
Symbol
–
I3FR
T2CON[5]
I2FR
T2CON[4:0]
–
Function
Not used.
Polarity control for INT3:
0 = falling edge.
1 = rising edge.
Polarity control for INT2:
0 = falling edge.
1 = rising edge.
Not used.
Table 29: The IRCON Bit Functions (SFR 0xC0)
Bit
IRCON[7]
Symbol
–
Function
Not used
IRCON[6]
–
Not used
IRCON[5]
IRCON[4]
IRCON[3]
IRCON[2]
IRCON[1]
IRCON[0]
IEX6
IEX5
IEX4
IEX3
IEX2
–
1 = External interrupt 6 occurred and has not been cleared.
1 = External interrupt 5 occurred and has not been cleared.
1 = External interrupt 4 occurred and has not been cleared.
1 = External interrupt 3 occurred and has not been cleared.
1 = External interrupt 2 occurred and has not been cleared.
Not used.
TF0 and TF1 (Timer 0 and Timer 1 overflow flags) will be automatically cleared by hardware when
the service routine is called (Signals T0ACK and T1ACK – port ISR – active high when the service
routine is called).
External MPU Interrupts
External interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of
the 71M6531D/F or 71M6532D/F, for example the CE, DIO, RTC, EEPROM interface.
32
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
The 71M6531D/F and 71M6532D/F MPU allows seven external interrupts. These are connected as
shown in Table 30. The polarity of interrupts 2 and 3 is programmable in the MPU via the I3FR and I2FR
bits in T2CON. Interrupts 2 and 3 should be programmed for falling sensitivity (I3FR = I2FR = 0). The generic 8051 MPU literature states that interrupts 4 through 6 are defined as rising-edge sensitive. Thus,
the hardware signals attached to interrupts 5 and 6 are inverted to achieve the edge polarity shown in
Table 30.
Table 30: External MPU Interrupts
External
Interrupt
0
1
2
3
4
5
6
Connection
Polarity
Digital I/O High Priority
Digital I/O Low Priority
FWCOL0, FWCOL1, SPI
CE_BUSY
PLL_OK (rising), PLL_OK (falling)
EEPROM busy
XFER_BUSY, RTC_1SEC or WD_NROVF
see Section 1.5.7
see Section 1.5.7
falling
falling
rising
falling
falling
Flag Reset
automatic
automatic
automatic
automatic
automatic
automatic
manual
External interrupt 0 and 1 can be mapped to pins on the device using DIO resource maps. See Section
1.5.7 Digital I/O for more information.
FWCOLx interrupts occur when the CE collides with a flash write attempt. See the flash write description
in the Flash Memory section for more detail.
SFR enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its
own flag bit, which is set by the interrupt hardware, and reset by the MPU interrupt handler.
XFER_BUSY, RTC_1SEC, WD_NROVF, FWCOL0, FWCOL1, SPI, PLLRISE and PLLFALL have their
own enable and flag bits in addition to the interrupt 6, 4 and enable and flag bits (see Table 31).
IE0 through IEX6 are cleared automatically when the hardware vectors to the interrupt handler. The other
flags, IE_XFER through IE_PB, are cleared by writing a zero to them.
Since these bits are in an SFR bit addressable byte, common practice would be to clear them
with a bit operation, but this must be avoided. The hardware implements bit operations as a
byte-wide read-modify-write hardware macro. If an interrupt occurs after the read, but before
the write, its flag will be cleared unintentionally.
The proper way to clear the flag bits is to write a byte mask consisting of all ones except for a zero in the
location of the bit to be cleared. The flag bits are configured in hardware to ignore ones written to them.
Table 31: Interrupt Enable and Flag Bits
Interrupt Enable
Name
Location
EX0
SFR A8[0]
EX1
SFR A8[2]
EX2
SFR B8[1]
EX3
SFR B8[2]
EX4
SFR B8[3]
EX5
SFR B8[4]
EX6
SFR B8[5]
EX_XFER
2002[0]
EX_RTC
2002[1]
IEN_WD_NROVF 20B0[0]
IEN_SPI
20B0[4]
EX_FWCOL
2007[4]
v1.2
Interrupt Flag
Name
Location
IE0
SFR 88[1]
IE1
SFR 88[3]
IEX2
SFR C0[1]
IEX3
SFR C0[2]
IEX4
SFR C0[3]
IEX5
SFR C0[4]
IEX6
SFR C0[5]
IE_XFER
SFR E8[0]
IE_RTC
SFR E8[1]
WD_NROVF_FLAG 20B1[0]
SPI_FLAG
20B1[4]
IE_FWCOL0
SFR E8[3]
Interrupt Description
External interrupt 0
External interrupt 1
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
XFER_BUSY interrupt (INT 6)
RTC_1SEC interrupt (INT 6)
WDT near overflow (INT 6)
SPI Interface (INT2)
FWCOL0 interrupt (INT 2)
© 2005-2009 TERIDIAN Semiconductor Corporation
33
Data Sheet 71M6531D/F-71M6532D/F
Interrupt Enable
Name
Location
Interrupt Flag
Name
Location
IE_FWCOL1
SFR E8[2]
IE_PLLRISE
SFR E8[6]
IE_PLLFALL
SFR E8[7]
IE_WAKE
SFR E8[5]
IE_PB
SFR E8[4]
2007[5]
EX_PLL
FDS 6531/6532 005
Interrupt Description
FWCOL1 interrupt (INT 2)
PLL_OK rise interrupt (INT 4)
PLL_OK fall interrupt (INT 4)
AUTOWAKE flag
PB flag
The AUTOWAKE and PB flag bits are shown in Table 31 because they behave similarly to interrupt flags,
even though they are not actually related to an interrupt. These bits are set by hardware when the MPU
wakes from a push button or wake timeout. The bits are reset by writing a zero. Note that the PB flag is
set whenever the PB is pushed, even if the part is already awake.
Interrupt Priority Level Structure
All interrupt sources are combined in groups, as shown in Table 32:
Table 32: Interrupt Priority Level Groups
Group
0
1
External interrupt 0
Timer 0 interrupt
2
External interrupt 1
–
External interrupt 3
3
Timer 1 interrupt
–
External interrupt 4
4
Serial channel 0 interrupt
–
External interrupt 5
–
External interrupt 6
5
Group Members
Serial channel 1 interrupt
–
–
External interrupt 2
–
Each group of interrupt sources can be programmed individually to one of four priority levels (as shown in
Table 33) by setting or clearing one bit in the SFR interrupt priority register IP0 and one in IP1(Table 34).
If requests of the same priority level are received simultaneously, an internal polling sequence as shown
in Table 35 determines which request is serviced first.
Changing interrupt priorities while interrupts are enabled can easily cause software defects. It is best
to set the interrupt priority registers only once during initialization before interrupts are enabled.
Table 33: Interrupt Priority Levels
IP1[x]
0
0
1
1
IP0[x]
0
1
0
1
Priority Level
Level 0 (lowest)
Level 1
Level 2
Level 3 (highest)
Table 34: Interrupt Priority Registers (IP0 and IP1)
Register
Address
IP0
IP1
34
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
SFR 0xA9
Bit 7
(MSB)
–
–
IP0[5]
IP0[4]
IP0[3]
IP0[2]
IP0[1]
Bit 0
(LSB)
IP0[0]
SFR 0xB9
–
–
IP1[5]
IP1[4]
IP1[3]
IP1[2]
IP1[1]
IP1[0]
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
External interrupt 0
Serial channel 1 interrupt
Timer 0 interrupt
External interrupt 2
External interrupt 1
External interrupt 3
Timer 1 interrupt
External interrupt 4
Serial channel 0 interrupt
External interrupt 5
External interrupt 6
Polling sequence
Table 35: Interrupt Polling Sequence
Interrupt Sources and Vectors
Table 36 shows the interrupts with their associated flags and vector addresses.
Table 36: Interrupt Vectors
Interrupt Request Flag
IE0
TF0
IE1
TF1
RI0/TI0
RI1/TI1
IEX2
IEX3
IEX4
IEX5
IEX6
v1.2
Description
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial channel 0 interrupt
Serial channel 1 interrupt
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
Interrupt Vector
Address
0x0003
0x000B
0x0013
0x001B
0x0023
0x0083
0x004B
0x0053
0x005B
0x0063
0x006B
© 2005-2009 TERIDIAN Semiconductor Corporation
35
Data Sheet 71M6531D/F-71M6532D/F
No.
0
FDS 6531/6532 005
External
Source
Internal
Source
Individual
Enable Bits
Individual Flags
DIO
DIO status
changed
DIO_Rn
TCON.1 (IE0)
byte received
UART1
(optical)
Logic and Polarity
Selection
Interrupt
Flags
Interrupt Enable
IEN0.7
(EAL)
IEN0.0
(EX0)
Priority
Assignment
IT0
IEN2.0
(ES1)
S1CON.0 (RI1)
IP1.0/
IP0.0
>=1
byte transmitted
S1CON.1 (TI1)
IEN0.1
(ET0)
SPI I/F
2
Write attempt, CE
Flash
busy
Write
CE code start,
Collision
overflow occurred
TCON.5 (TF0)
IEN_SPI
SPI_FLAG
>=1
1
3
DIO
CE_BUSY
4
PLL OK
PLL status
changed
IRCON.1
(IEX2)
EX_FWCOL
DIO_Rn
I3FR
overflow occurred
IEN0.3
(ET1)
TCON.7 (TF1)
IEN1.3
(EX4)
IE_PLLRISE
EX_PLL
IE_PLLFALL
UART0
byte transmitted
BUSY fell
EX_EEX
>=1
IEN0.4
(ES0)
>=1
>=1
EX_SPI
IE_SPI
XFER_BUSY
accumulation
cycle completed
EX_XFER
IE_XFER
EX_RTC
IE_RTC
IEN_NR_
WDOVF
WD_NROVF_FLAG
NR_OVF
MPU-external
sources
IEN1.4
(EX5)
IE_EEX
I2C
RTC_1S
every second
WDT near
overflow
IP1.3/
IP0.3
IRCON.3
(IEX4)
S0CON.0 (TI0)
command
received
6
IP1.2/
IP0.2
IRCON.2
(IEX3)
S0CON.0 (RI0)
EEPROM
IEN0.2
(EX1)
IEN1.2
(EX3)
TCON.3 (IE1)
byte received
5
IP1.1/
IP0.1
IE_FWCOL1
CE completed code run and
has new status information
Timer 1
I2FR
IE_FWCOL0
flash write busy
DIO status
changed
IEN1.1
(EX2)
Polling Sequence
Timer 0
IRCON.4
(IEX5)
IEN1.5
(EX6)
>=1
IP1.5/
IP0.5
IRCON.5
(IEX6)
Flag=1 means
that an interrupt has occurred and
has not been
cleared
MPU-internal
sources
IP1.4/
IP0.4
EX0 – EX6 are cleared
automatically when the
hardware vectors to the
interrupt handler
Interrupt
Vector
2/2/2009
Figure 8: Interrupt Structure
36
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
1.5
On-Chip Resources
1.5.1
Oscillator
The oscillator of the 71M6531D/F and 71M6532D/F drives a standard 32.768 kHz watch crystal. These
crystals are accurate and do not require a high-current oscillator circuit. The oscillator of the 71M6531D/F
and 71M6532D/F has been designed specifically to handle these crystals and is compatible with their
high impedance and limited power handling capability.
Oscillator calibration can improve the accuracy of both the RTC and metering. Refer to Section
1.5.3 Real-Time Clock (RTC) for more information.
The oscillator is powered directly and only from VBAT, which therefore must be connected to a DC voltage source. The oscillator requires approximately 100 nA, which is negligible compared to the internal
leakage of a battery.
The oscillator may appear to work when VBAT is not connected, but this mode of operation is not recommended.
If VBAT is connected to a drained battery or disconnected, a battery test that sets BME may drain
VBAT’s supply and cause the oscillator to stop. A stopped oscillator may force the device to reset.
Therefore, an unexpected reset during a battery test should be interpreted as a battery failure.
1.5.2
Internal Clocks
Timing for the device is derived from the 32.768 kHz crystal oscillator output. On-chip timing functions
include:
• The MPU clock (CKMPU)
• The emulator clock (2 x CKMPU)
• The clock for the CE (CKCE)
• The clock driving the delta-sigma ADC along with the FIR (CKADC, CKFIR)
• A real time clock (RTC).
The two general-purpose counter/timers contained in the MPU are controlled by CKMPU (see Section
1.4.7 Timers and Counters). Table 37 provides a summary of the available clock functions.
Table 37: Clock System Summary
Clock
Derived
From
MCK Divider / [M40MHZ, M26MHZ]
÷2 / [1,0]
80 MHz
40 MHz
5 MHz † 10 MHz †
5 MHz
10 MHz***
32 kHz
÷3 / [0,1]
80 MHz
26 MHz
6.6 MHz
6.6 MHz
6.6 MHz ***
32 kHz
÷4** / [0,0]
80 MHz
20 MHz
5 MHz
5 MHz
5 MHz ***
32 kHz
Brownout
Mode
CKPLL
Crystal
off
MCK
CKPLL
112 kHz
CKCE
MCK
off
CKADC / CKFIR
MCK
28 kHz
CKMPU maximum MCK
28 kHz
CK32
MCK
**
Default state at power-up
***
This is the maximum CKMPU frequency. CKMPU can be reduced from this rate using MPU_DIV.
†
CKCE = 10 MHz when CE10MHZ is set, 5 MHz otherwise.
The master clock, MCK, is generated by an on-chip PLL that multiplies the oscillator output frequency
(CK32) by 2400 to provide 80 MHz (78.6432 MHz). A divider controlled by the I/O RAM registers
M40MHZ and M26MHZ permits scaling of MCK by ½, ⅓ and ¼. All other clocks are derived from this
scaled MCK output (making them multiples of 32768 Hz), and the clock skew is matched so that the rising
edges of CKADC, CKCE, CK32 and CKMPU are aligned.
The PLL generates a 2x emulator clock which is controlled by ECK_DIS. Since clock noise from this feature may disturb the ADC, it is recommended that this option be avoided when possible.
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
37
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
The MPU clock frequency CKMPU is determined by another divider controlled by the I/O RAM register
MPU_DIV and can be set to MCK/2(MPU_DIV+2) Hz where MPU_DIV varies from 0 to 6. The circuit also generates the 2 x CKMPU clock for use by the emulator. The emulator clock is not generated when
ECK_DIS is asserted.
During a power-on reset, [M40MHZ, M26MHZ] defaults to [0,0] and the MCK divider is set to divide by 4.
When [M40MHZ, M26MHZ] = [1,0], the CE clock frequency may be set to 5 MHz or 10 MHz, using the I/O
RAM register CE10MHZ. In this mode, the ADC and FIR clock frequencies remain at 5 MHz. When
[M40MHZ, M26MHZ] = [0,1], the CE, ADC, FIR and MPU clock frequencies are shifted to 6.6 MHz. This
increases the ADC sample rate by 33%. In sleep mode, the M40MHZ and M26MHZ inputs to the clock
generator are forced low.
In brownout mode, the clocks are derived from the crystal oscillator and the clock frequencies are scaled
by 7/8.
1.5.3
Real-Time Clock (RTC)
The RTC is driven directly by the crystal oscillator. It is powered by the net RTC_NV (battery-backed up
supply). The RTC consists of a counter chain and output registers. The counter chain consists of registers for seconds, minutes, hours, day of week, day of month, month and year. The RTC is capable of
processing leap years. Each counter has its own output register. Whenever the MPU reads the seconds
register, all other output registers are automatically updated. Since the RTC clock (RTCLK) is not coherent to the MPU clock, the MPU must read the seconds register until two consecutive reads are the same
(this requires either 2 or 3 reads). At this point, all RTC output registers will have the correct time. Regardless of the MPU clock speed, RTC reads require one wait state.
RTC time is set by writing to the registers RTC_SEC through RTC_YR. Each write operation must be preceded by a write operation to the WE register in I/O RAM. The value written to the WE register is unimportant.
Time adjustments are written to the RTCA_ADJ, PREG and QREG registers. Updates to PREG and QREG
must occur after the one second interrupt and must be finished before reaching the next one second
boundary. The new values are loaded into the counters at the next one second boundary.
PREG and QREG are separate registers in the device hardware, but the bits are 16-bit contiguous so the
MPU firmware can treat them as a single register. A single binary number can be calculated and then
loaded into them at the same time.
The 71M6531D/F and 71M6532D/F have two rate adjustment mechanisms. The first is an analog rate
adjustment, using RTCA_ADJ[6:0], which trims the crystal load capacitance. Setting RTCA_ADJ[6:0] to 00
minimizes the load capacitance, maximizing the oscillator frequency. Setting RTCA_ADJ[6:0] to 0x7F
maximizes the load capacitance, minimizing the oscillator frequency. The adjustable capacitance is approximately:
C ADJ =
RTCA _ ADJ
⋅ 16.5 pF
128
The maximum adjustment range is approximately-12 ppm to +22ppm. The precise amount of adjustment
will depend on the crystal properties. The adjustment may occur at any time and the resulting clock frequency can be measured over a one-second interval.
The second rate adjustment is a digital rate adjust using PREG and QREG, which can be used to adjust
the clock rate up to ± 988 ppm, with a resolution of 1.9 ppm. Updates must occur after a one second interrupt and must finish before the next one second boundary. The rate adjustment will be implemented
starting at the next one second boundary. Since the LSB results in an adjustment every four seconds,
the frequency should be measured over an interval that is a multiple of four seconds.
To adjust the clock rate using the digital rate adjust, the appropriate values must be written to PREG[16:0]
and QREG[1:0]. The default frequency is 32,768 RTCLK cycles per second. To shift the clock frequency
by ∆ ppm, calculate PREG and QREG using the following equation:
 32768 ⋅ 8

+ 0.5 
4 ⋅ PREG + QREG = floor 
−6
 1 + ∆ ⋅ 10

38
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
For example, for a shift of -988 ppm, 4⋅PREG + QREG = 262403 = 0x40103. PREG = 0x10040 and
QREG = 0x03. The default values of PREG and QREG, corresponding to zero adjustment, are 0x10000
and 0x0, respectively.
Default values for RTC_ADJ, PREG and QREG should be nominal values, at the center of the adjustment range. Extreme values (zero for example) can cause incorrect operation.
If the crystal temperature coefficient is known, the MPU can integrate temperature and correct the RTC
time as necessary.
The sub-second register of the RTC, SUBSEC, can be read by the MPU after the one second interrupt and
before reaching the next one second boundary. SUBSEC contains the count remaining, in 1/256 second
nominal clock periods, until the next one second boundary. When the RST_SUBSEC bit is written, the
SUBSEC counter is restarted. Reading and resetting the sub-second counter can be used as part of an
algorithm to accurately set the RTC.
1.5.4
Temperature Sensor
The device includes an on-chip temperature sensor for determining the temperature of the bandgap reference. If automatic temperature measurement is not performed by selecting CHOP_E = 00, the MPU
may request an alternate multiplexer frame containing the temperature sensor output by asserting
MUX_ALT. The primary use of the temperature data is to determine the magnitude of compensation required to offset the thermal drift in the system (see Section 3.4 Temperature Compensation).
1.5.5
Physical Memory
Flash Memory
The 71M6531D and 71M6532D include 128 KB of on-chip flash memory. The 71M6531F and 71M6532F
offer 256 KB of flash memory. The flash memory primarily contains MPU and CE program code. It also
contains images of the CE and MPU data in RAM, as well as of I/O RAM. On power-up, before enabling
the CE, the MPU copies these images to their respective locations.
The flash memory is segmented into individually erasable pages that contain 1024 bytes.
Flash space allocated for the CE program is limited to 4096 16-bit words (8 KB). The CE program must
begin on a 1-KB boundary of the flash address space. The CE_LCTN[7:0] word defines which 1-KB
boundary contains the CE code. Thus, the first CE instruction is located at 1024*CE_LCTN[7:0].
Flash Write Procedures
The MPU may write to the flash memory. This is one of the non-volatile storage options available to the
user in addition to external EEPROM.
FLSH_PWE (flash program write enable) differentiates 80515 data store instructions ([email protected],A)
between Flash and XRAM write operations. This bit must be cleared by the MPU after each byte write
operation. Write operations to this bit are inhibited when interrupts are enabled.
The MPU cannot write to flash while the CE is executing its code from flash. Two interrupts warn of collisions between the MPU firmware and the CE timing. If a flash write operation is attempted while the CE
is busy, the flash write will not execute and the FW_COL0 interrupt will be issued. If a flash write is still in
progress when the CE would otherwise begin a code pass, the code pass is skipped, the write operation
is completed, and the FW_COL1 interrupt is issued.
The simplest flash write procedure disables the CE during the write operation and interpolates the metering measurements. However, this results in the loss of at least one second of data, because the CE has
to resynchronize with the mains voltage.
There is a brief guaranteed interval (typically 1/32768 s) between CE executions which occurs 2520 times
per second. The start of the interval can be detected with the CE_BUSY interrupt which occurs on the
falling edge of CE_BUSY (an internal signal measurable from TMUXOUT). However, this guaranteed idle
time (30.5 µs) is too short to write a byte which takes 42 µs or to erase a page of flash memory which
takes at least 20 ms. Some CE code has substantially longer idle times, but in those cases, firmware interrupt latencies can easily consume the available write time. If a flash write fails in this scheme, the failure can be detected with the FWCOL0 or FWCOL1 interrupt and the write can be retried.
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
39
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
It is practical to pre-erase pages, disable interrupts and poll the CE_BUSY interrupt flag, IRCON[2]. This
method avoids problems with interrupt latency, but can still result in a write failure if the CE code takes to
much time. As mentioned above, polling FWCOL0 and FWCOL1 can detect write failures. However, the
speed in a polling write is only 2520 bytes per second and the firmware cannot respond to interrupts.
As an alternative to using flash, a small EEPROM can store data without compromises. EEPROM interfaces are included in the device.
Updating Individual Bytes in Flash Memory
The original state of a flash byte is 0xFF (all ones). Once a value other than 0xFF is written to a flash
memory cell, overwriting with a different value usually requires that the cell be erased first. Since cells
cannot be erased individually, the page has to be copied to RAM, followed by a page erase. After this,
the page can be updated in RAM and then written back to the flash memory.
Flash Erase Procedures
Flash erasure is initiated by writing a specific data pattern to specific SFR registers in the proper sequence.
These special pattern/sequence requirements prevent inadvertent erasure of the flash memory.
The mass erase sequence is:
1. Write 1 to the FLSH_MEEN bit (SFR address 0xB2[1].
2. Write pattern 0xAA to FLSH_ERASE (SFR address 0x94).
The mass erase cycle can only be initiated when the ICE port is enabled.
The page erase sequence is:
1. Write the page address to FLSH_PGADR (SFR address 0xB7[7:1].
2. Write pattern 0x55 to FLSH_ERASE (SFR address 0x94).
Bank-Switching:
The program memory of the 71M6531 consists of a fixed lower bank of 32 KB addressable at 0x0000 to
0x7FFF plus an upper bank area of 32 KB, addressable at 0x8000 to 0xFFFF. The upper 32 KB space is
banked using the I/O RAM FL_BANK register as follows:
•
•
The 71M6531D provides 4 banks of 32 KB each selected by FL_BANK[1:0]. Note that when
FL_BANK[1:0] = 00, the upper bank is the same as the lower bank.
The 71M6531F and 71M6532D/F provide 8 banks of 32 KB each selected by FL_BANK[2:0].
Table 38 illustrates the bank switching mechanism.
Table 38: Bank Switching with FL_BANK[2:0]
FL_BANK Address Range for Lower
[1:0] / [2:0]
Bank (0x000-0x7FFF)
000
0x0000-0x7FFF
001
0x0000-0x7FFF
010
0x0000-0x7FFF
011
0x0000-0x7FFF
100
0x0000-0x7FFF
101
0x0000-0x7FFF
110
0x0000-0x7FFF
111
0x0000-0x7FFF
Address Range for Upper
Bank (0x8000-0xFFFF)
0x0000-0x7FFF
0x8000-0xFFFF
0x10000-0x17FFF
0x18000-0x1FFFF
0x20000-0x217FF
0x28000-0x2FFFF
0x30000-0x37FFF
0x38000-0x3FFFF
Available for
71M653XD
X
X
X
X
Available for
71M6531XF
X
X
X
X
X
X
X
X
Program Security
When enabled, the security feature limits the ICE to global flash erase operations only. All other ICE operations are blocked. This guarantees the security of the user’s MPU and CE program code. Security
40
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
should be enabled by MPU code that is executed during the pre-boot interval (60 CKMPU cycles before
the primary boot sequence begins). Once security is enabled, the only way to disable it is to perform a
global erase of the flash, followed by a chip reset.
The first 60 cycles of the MPU boot code are called the pre-boot phase because during this phase the
ICE is inhibited. A read-only status bit, PREBOOT, identifies these cycles to the MPU. Upon completion
of pre-boot, the ICE can be enabled and is permitted to take control of the MPU.
The security enable bit, SECURE, is reset whenever the chip is reset. Hardware associated with the bit
permits only ones to be written to it. Thus, pre-boot code may set SECURE to enable the security feature
but may not reset it. Once SECURE is set, the pre-boot code is protected and no external read of program
code is possible
Specifically, when SECURE is set, the following applies:
•
•
•
The ICE is limited to bulk flash erase only.
Page zero of flash memory, the preferred location for the user’s pre-boot code, may not be
page-erased by either MPU or ICE. Page zero may only be erased with global flash erase.
Write operations to page zero, whether by MPU or ICE are inhibited.
MPU/CE RAM:
The 71M6531D/F and 71M6532D/F include 4 KB of static RAM memory on-chip (XRAM) plus 256-bytes
of internal RAM in the MPU core. The 4 KB of static RAM are used for data storage for MPU and CE operations.
1.5.6
Optical Interface
The device includes an interface to implement an IR/optical port. The pin OPT_TX is designed to directly
drive an external LED for transmitting data on an optical link. The pin OPT_RX has the same threshold
as the RX pin, but can also be used to sense the input from an external photo detector used as the receiver for the optical link. OPT_TX and OPT_RX are connected to a dedicated UART port (UART1).
The OPT_TX and OPT_RX pins can be inverted with configuration bits OPT_TXINV and OPT_RXINV, respectively. Additionally, the OPT_TX output may be modulated at 38 kHz. Modulation is available when
system power is present (i.e. not in BROWNOUT mode). The OPT_TXMOD bit enables modulation. Duty
cycle is controlled by OPT_FDC[1:0], which can select 50%, 25%, 12.5% and 6.25% duty cycle. 6.25% duty
cycle means OPT_TX is low for 6.25% of the period. Figure 9 illustrates the OPT_TX generator.
When not needed for the optical UART, the OPT_TX pin can alternatively be configured as DIO2,
WPULSE, or VARPULSE. The configuration bits are OPT_TXE[1:0]. Likewise, OPT_RX can alternately
be configured as DIO1. Its control is OPT_RXDIS.
VARPULSE
from
OPT_TX UART
OPT_TXINV
3
2
1
V3P3
Internal
WPULSE
DIO2
MOD
A
B
0
EN DUTY
OPT_TXE[1:0]
OPT_TXMOD
OPT_FDC
2
OPT_TX
OPT_TXMOD = 1,
OPT_FDC = 2 (25%)
OPT_TXMOD = 0
A
A
B
B
1/38kHz
Figure 9: Optical Interface
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
41
Data Sheet 71M6531D/F-71M6532D/F
1.5.7
FDS 6531/6532 005
Digital I/O – 71M6531D/F
The 71M6531D/F includes up to 22 pins of general-purpose digital I/O. These pins are compatible with 5V inputs (no current limiting resistors are needed). The Digital I/O pins can be categorized as follows:
• Dedicated DIO pins (1 pin): PB
• DIO/LCD segment pins (a total of 19 pins):
o DIO4/SEG24 - DIO15/SEG35 (12 pins)
o DIO17/SEG37 (1 pin)
o DIO28/SEG48 – DIO29/SEG49 (2 pins)
o DIO43/SEG63 - DIO46/SEG66 (4 pins)
• DIO pins combined with other functions (2 pins): DIO2/OPT_TX, DIO1/OPT_RX
The pins DIO4/SEG24 through DIO29/SEG49 are configured by the LCD_MAP DIO registers to be DIO or
segment pins. A one in LCD_MAP defines the pin as a LCD segment output, a zero makes the pin a DIO
pin. Pins configured as LCD pins are controlled with the LCD_SEGnn registers. Pins configured as DIO
can be defined independently as an input or output with the DIO_DIR bits (see Table 41).
Write operations to a disabled DIO are not ignored. Write operations are registered, but do not
affect the pin, or the result of a read operation on the pin, until it becomes a DIO output.
DIO2/OPT_TX will be an active TX output pin at power up (OPT_TXE[1:0] = 00).
A 3-bit configuration word, I/O RAM register DIO_Rx (0x2009[2:0] through 0x200E[6:4], can be used for
certain pins (when configured as DIO) to individually assign an internal resource such as an interrupt or a
timer control (see Table 42 for DIO pins available for this option). This way, DIO pins can be tracked
even if they are configured as outputs.
Table 39 lists the direction registers and configurability associated with each group of DIO pins.
Table 39: Data/Direction Registers and Internal Resources for DIO Pins (71M6531D/F)
1
–
2
–
–
4
5
6
7
8
9
10
11
12
13
14
15
LCD Segment
PB
–
–
24
25
26
27
28
29
30
31
32
33
34
35
Pin number
65
60
3
–
39
40
41
42
43
44
45
46
68
30
21
22
–
–
–
–
0
1
2
3
4
5
6
7
0
1
2
3
DIO
Configuration (DIO
or LCD segment)
Data Register
Direction Register
Internal Resources
Configurable
42
0
–
–
LCD_MAP[31:24]
1
2
–
4
5
6
7
DIO0 = P0 (SFR 0x80)
1
2
–
4
5
6
7
DIO_DIR0 (SFR 0xA2)
LCD_MAP[31:24] LCD_MAP[39:32]
0
1
2
3
4
5
6
7
DIO1 = P1 (SFR 0x90)
0
1
2
3
4
5
6
7
DIO_DIR1 (SFR 0x91)
–
Y
–
–
Y
Y
Y
Y
Y
Y
© 2005-2009 TERIDIAN Semiconductor Corporation
Y
–
–
–
–
v1.2
FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
DIO
–
17
–
–
–
–
–
–
–
–
–
–
28
29
–
–
LCD Segment
–
37
–
–
–
–
–
–
–
–
–
–
48
49
–
–
Pin number
–
13
–
–
–
–
–
–
–
–
–
–
47
24
–
–
–
5
–
–
–
–
–
–
–
–
–
–
0
1
–
–
LCD_MAP[39:32]
–
–
1 –
–
–
–
–
–
–
–
–
LCD_MAP[55:48]
–
4
5 –
DIO2 = P2 (SFR 0xA0)
–
–
–
–
1 –
–
–
Direction Register
0 = input, 1 = output
DIO3 = P3 (SFR 0xB0)
DIO_DIR2 (SFR 0xA1)
DIO
–
–
–
43
44
45
46
–
LCD Segment
–
–
–
63
64
65
66
–
Pin number
–
–
–
29
23
28
5
–
Configuration (DIO
or LCD segment)
–
–
–
7
0
1
2
–
Direction Register
0 = input, 1 = output
–
–
–
LCD_SEG66[3] LCD_SEG66[0]
–
LCD_SEG65[3] LCD_SEG65[0]
–
LCD_SEG64[3] LCD_SEG64[0]
–
LCD_SEG63[3] LCD_SEG63[0]
LCD_BITMAP[63:56] LCD_BITMAP[64:71]
Data Register
1.5.8
LCD_SEG49[3]
Data Register
LCD_SEG48[3]
Configuration (DIO
or LCD segment)
–
–
Digital I/O – 71M6532D/F
The 71M6532D/F includes up to 43 pins of general-purpose digital I/O. These pins are compatible with 5V inputs (no current limiting resistors are needed). The Digital I/O pins can be categorized as follows:
• Dedicated DIO pins (4 pins):
o DIO3
o DIO56 – DIO58 (3 pins)
• DIO/LCD segment pins (a total of 37 pins):
o DIO4/SEG24 – DIO27/SEG47 (24 pins)
o DIO29/SEG49, DIO30/SEG50 (2 pins)
o DIO40/SEG60 – DIO45/SEG65 (6 pins)
o DIO47/SEG67 – DIO51/SEG71 (5 pins)
• DIO pins combined with other functions (2 pins): DIO2/OPT_TX, DIO1/OPT_RX
On reset or power-up, all DIO pins are inputs until they are configured for the desired direction under
MPU control. The pin function can be configured by the I/O RAM registers LCD_BITMAPn. Setting
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© 2005-2009 TERIDIAN Semiconductor Corporation
43
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
LCD_BITMAPn = 1 configures the pin for LCD, setting LCD_BITMAPn = 0 configures it for DIO. Once a
pin is configured as DIO, it can be configured independently as an input or output with the DIO_DIR bits
or the LCD_SEGn registers. Input and output data are written to or read from the pins using SFR registers
P0, P1, and P2. Table 40 shows all the DIO pins with their configuration, direction control and data registers.
Table 40: Data/Direction Registers and Internal Resources for DIO Pins (71M6532D/F)
Configuration (DIO or
LCD segment)
Data Register
Direction Register
0 = input, 1 = output
Internal Resources
Configurable
DIO
LCD Segment
Pin number
Configuration (DIO or
LCD segment)
Data Register
1
–
87
2
–
3
3
–
17
Always DIO
0
–
Y
4
24
60
0
5
25
61
1
1
2
3
4
5
DIO0 = P0 (SFR 0x80)
1
2
3
4
5
DIO_DIR0 (SFR 0xA2)
Y
Y
Y
Y
Y
16
17 18 19 20
21
36
37 18 39 40
41
33
12 13 64 65
66
4
5
6
7
0
1
LCD_BITMAP[39:32]
0
1
2
3
4
5
DIO2 = P2 (SFR 0xA0)
-1
-3
4
5
Direction Register
0 = input, 1 = output
6
7
8
9
26 27 28 29
62 63 67 68
2
3
4
5
LCD_BITMAP[31:24]
6
7
0
1
10
30
69
6
11
31
70
7
12
32
13 14 15
33 34 35
100
44 29 30
0
1
2
3
LCD_BITMAP[39:32]
2
3
4
5
6
7
DIO1 = P1 (SFR 0x90)
2
3
4
5
6
7
DIO_DIR1 (SFR 0x91)
–
6
7
0
1
Y
Y
Y
Y
Y
Y
22 23 24 25
42 43 44 45
93 54 46 43
2
3
--LCD_BITMAP[47:40]
6
7
0
1
26
46
42
--
27
47
41
--
--
--
–
--
Pin number
95
97
98
40
31
38
--
22
23
24
25
50
Configuration (DIO or
LCD segment)
4
5
6
7
LCD_BITMAP[63:56]
0
1
-3
4
5
LCD_BITMAP[71:64]
6
7
Data Register
LCD_SEG61[0]
LCD_SEG62[0]
LCD_SEG63[0]
LCD_SEG64[0]
Direction Register
0 = input, 1 = output
LCD_SEG61[0]
LCD_SEG62[0]
LCD_SEG63[0]
LCD_SEG64[3]
--
LCD_SEG71[0]
51
71
--
LCD_SEG71[3]
50
70
LCD_SEG70[0]
49
69
LCD_SEG70[3]
48
68
LCD_SEG69[0]
47
67
LCD_SEG69[3]
---
LCD_SEG68[0]
45
65
LCD_SEG68[3]
44
64
LCD_SEG67[0]
43
63
LCD_SEG67[3]
42
62
LCD_SEG65[0]
41
61
LCD_SEG65[3]
40
60
LCD_SEG60[0]
--
LCD_SEG60[0]
--
DIO
LCD Segment
44
–
–
-29 30
--49 50
--32 35
-1
2
-LCD_BITMAP[55:48]
2
3
–
5
6
-DIO3 = P3 (SFR 0xB0)
--
DIO_DIR2 (SFR 0xA1)
–
© 2005-2009 TERIDIAN Semiconductor Corporation
LCD_SEG50[3]
PB
–
92
LCD_SEG49[3]
DIO
LCD Segment
Pin number
--
v1.2
FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
DIO24 and higher do not have SFR registers for direction control. DIO40 and higher do not have SFR registers for data access. The direction control of these pins is achieved with the LCD_SEGn[3] registers
and data access is controlled with the LCD_SEGn[0] registers in I/O RAM.
DIO56 through DIO58 are dedicated DIO pins. They are controlled with DIO_DIR56[7] through
DIO_DIR58[7] and with DIO_56[4] through DIO_58[4] in I/O RAM.
1.5.9
Digital IO – Common Characteristics for 71M6531D/F and 71M6532D/F
On reset or power-up, all DIO pins are inputs until they are configured for the desired direction under
MPU control. The pin function can be configured by the I/O RAM registers LCD_BITMAPn. Setting
LCD_BITMAPn = 1 configures the pin for LCD, setting LCD_BITMAPn = 0 configures it for DIO. Once a
pin is configured as DIO, it can be configured independently as an input or output with the DIO_DIR bits
or the LCD_SEGn registers. Input and output data are written to or read from the pins using SFR registers
P0, P1, and P2.
DIO24 and higher do not have SFR registers for direction control. DIO41 and higher do not have SFR
registers for data access. The direction control of these pins is achieved with the LCD_SEGn[3] registers
and data access is controlled with the LCD_SEGn[0] registers in I/O RAM.
Since the control for DIO_24 through DIO_53 is shared with the control for LCD segments, the firmware
must take care not to disturb the DIO pins when accessing the LCD segments and vice versa. Usually,
this requires reading the I/O RAM register, applying a mask and writing back the modified byte.
Table 41: DIO_DIR Control Bit
DIO_DIR [n]
0
1
DIO Pin n Function
Input
Output
Table 42: Selectable Controls using the
DIO_DIR Bits
DIO_R
Value
0
1
2
3
4
5
6
7
Resource Selected for DIO Pin
None
Reserved
T0 (counter 0 clock)
T1 (counter 1 clock)
High priority I/O interrupt (INT0 rising)
Low priority I/O interrupt (INT1 rising)
High priority I/O interrupt (INT0 falling)
Low priority I/O interrupt (INT1 falling)
Additionally, if DIO6 and DIO7 are configured as DIO and defined as outputs, they can be used as dedicated pulse outputs (WPULSE = DIO6, VARPULSE = DIO7) using the DIO_PW and DIO_PV registers. In
this case, DIO6 and DIO7 are under CE control. DIO4 and DIO5 can be configured to implement the
EEPROM Interface.
The PB pin is a dedicated digital input. In addition, if the optical UART is not used, OPT_TX and
OPT_RX can be configured as dedicated DIO pins, DIO1 and DIO2, respectively (see Section 1.5.6 Optical
Interface).
The internal control resources selectable for the DIO pins are listed in Table 42. If more than one input is
connected to the same resource, the resources are combined using a logical OR.
Tracking DIO pins configured as outputs is useful for pulse counting without external hardware.
Either the interrupts or the counter/timer clocks can be used to count pulses on the pulse outputs
or interrupts on the CE’s power failure output.
When driving LEDs, relay coils etc., the DIO pins should sink the current into GNDD (as shown in
Figure 10, right), not source it from V3P3D (as shown in Figure 10, left). This is due to the resistance of the internal switch that connects V3P3D to either V3P3SYS or VBAT.
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
45
Data Sheet 71M6531D/F-71M6532D/F
71M6531
FDS 6531/6532 005
71M6531
V3P3SYS
VBAT
V3P3D
3.3V
3.3V
V3P3SYS
VBAT
V3P3D
LED
DIO1
DIO1
R
R
LED
DGND
DGND
Not recommended
Recommended
Figure 10: Connecting an External Load to DIO Pins
1.5.10 LCD Drivers – 71M6531D/F
The 71M6531 contains a total of 39 dedicated and multiplexed LCD drivers which are grouped as follows:
• 11 dedicated LCD segment drivers – always available
• 3 drivers multiplexed with the ICE interface (E_TCLK, E_RST, E_RXTX) – available in normal operation mode (when not emulating)
• 2 driver multiplexed with auxiliary signals MUX_SYNC and CKTEST (SEG7, SEG19) – available
when not used for test
• 4 drivers multiplexed with the SPI port (PCLK, PSDO, PCSZ, PSDI)
• 19 multi-use pins described above in the 1.5.7 Digital I/O – 71M6531D/F section.
• 4 common drivers for multiplexing (25%, 33%, 50%, or 100% duty cycle) – always available
With a minimum of 16 driver pins always available and a total of 39 driver pins in the maximum configuration, the device is capable of driving between 64 to 156 pixels of LCD display with 25% duty cycle. At
eight pixels per digit, this corresponds to 8 to 19 digits. At 33% duty cycle, 48 to 117 pixels can be driven.
For each multi-use pin, the corresponding LCD_BITMAP[] register (as described in Section 1.5.7 Digital I/O
– 71M6531D/F) is used to select the pin for DIO or LCD operation. The mapping of the LCD_BITMAP[]
registers is specified in Section 4.1 (I/O RAM registers). The LCD drivers are supported by the four
common pins (COM0 – COM3).
1.5.11 LCD Drivers – 71M6532D/F
The 71M6532D/F contains a total of 67 dedicated and multiplexed LCD drivers, which are grouped as
follows:
•
•
•
•
•
15 dedicated LCD segment drivers (SEG0 to SEG2, SEG8, SEG12 - SEG18, SEG20 – SEG23)
4 drivers multiplexed with the SPI port (SEG3 to SEG6)
2 drivers multiplexed with MUX_SYNC (SEG7) or CKTEST (SEG19)
3 drivers multiplexed with the ICE interface (SEG9 to SEG11)
43 multi-use LCD/DIO pins described in Section 1.5.8 Digital I/O – 71M6532D/F.
With a minimum of 15 driver pins always available and a total of 67 driver pins in the maximum configuration, the device is capable of driving between 60 to 268 pixels of an LCD display with 25% duty
cycle. At eight pixels per digit, this corresponds to 7.5 to 33.5 digits.
For each multi-use pin, the corresponding LCD_BITMAP[ ] register (as described in Section 1.5.8 Digital I/O
– 71M6532D/F) is used to select the pin for DIO or LCD operation. The mapping of the LCD_BITMAP[ ]
registers is specified in Section 4.1 I/O RAM and SFR Map – Functional Order. The LCD drivers are supported by the four common pins (COM0 – COM3).
46
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
1.5.12 LCD Drivers – Common Characteristics for 71M6531D/F and 71M6532D/F
The LCD interface is flexible and can drive 7-segment digits, 14-segment digits or enunciator symbols.
The LCD bias may be compensated for temperature using the LCD_DAC bits in I/O RAM. The bias may
be adjusted from 1.4 V below the 3.3 V supply (V3P3SYS in mission mode and brownout modes, VBAT
in LCD mode). When the LCD_DAC bits are set to 000, the DAC is bypassed and powered down. This
can be used to reduce current in LCD mode.
Segment drivers SEG18 and SEG19 can be configured to blink at either 0.5 Hz or 1 Hz. The blink rate is
controlled by LCD_Y. There can be up to four pixels/segments connected to each of these drivers.
LCD_BLKMAP18[3:0] and LCD_BLKMAP19[3:0] identify which pixels, if any, are to blink. The most significant bit corresponds to COM3, the least significant to COM0.
1.5.13 Battery Monitor
The battery voltage is measured by the ADC during alternative MUX frames if the BME (Battery Measure
Enable) bit is set. While BME is set, an on-chip 45 kΩ load resistor is applied to the battery and a scaled
fraction of the battery voltage is applied to the ADC input. After each alternative MUX frame, the result of
the ADC conversion is available at RAM address 0x07. BME is ignored and assumed zero when system
power is not available.
If VBAT is connected to a drained battery or disconnected, a battery test that sets BME may drain
VBAT’s supply and cause the oscillator to stop. A stopped oscillator may force the device to reset.
Therefore, an unexpected reset during a battery test should be interpreted as a battery failure.
Battery measurement is not very linear but is very reproducible if properly calibrated. The best way to
perform the calibration is to set the battery input to the desired failure voltage and then have the MPU
firmware record that measurement. After this, the battery measurement logic may use the recorded value
as the battery failure limit. The same value can also be a calibration offset for any battery voltage display.
See Section 5.4.4 Battery Monitor for details regarding the ADC LSB size and the conversion accuracy.
1.5.14 EEPROM Interface
The 71M6531D/F and 71M6532D/F provide hardware support for either a two-pin or a three-wire (µ-wire)
type of EEPROM interface. The interfaces use the EECTRL and EEDATA registers for communication.
Two-Pin EEPROM Interface
The dedicated 2-pin serial interface communicates with external EEPROM devices. The interface is multiplexed onto the DIO4 (SCK) and DIO5 (SDA) pins and is selected by setting DIO_EEX = 01. The MPU
communicates with the interface through the SFR registers EEDATA and EECTRL. If the MPU wishes to
write a byte of data to the EEPROM, it places the data in EEDATA and then writes the Transmit code to
EECTRL. This initiates the transmit operation which is finished when the BUSY bit falls. INT5 is also asserted when BUSY falls. The MPU can then check the RX_ACK bit to see if the EEPROM acknowledged
the transmission.
A byte is read by writing the Receive command to EECTRL and waiting for the BUSY bit to fall. Upon
completion, the received data is in EEDATA. The serial transmit and receive clock is 78 kHz during each
transmission and then holds in a high state until the next transmission. The EECTRL bits when the twopin interface is selected are shown in Table 43.
Table 43: EECTRL Bits for 2-pin Interface
Status
Bit
Name
Read/
Write
Reset
State
Polarity
Description
7
6
5
4
ERROR
BUSY
RX_ACK
TX_ACK
R
R
R
R
0
0
1
1
Positive
Positive
Negative
Negative
1 when an illegal command is received.
1 when serial data bus is busy.
0 indicates that the EEPROM sent an ACK bit.
0 indicates when an ACK bit has been sent to the
EEPROM.
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
47
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
Status
Bit
Name
Read/
Write
Reset
State
Polarity
3:0
CMD[3:0]
W
0000
Positive
Description
CMD[3:0]
0000
0010
0011
0101
0110
1001
Others
Operation
No-op command. Stops the I2C
clock (SCK, DIO4). If not issued,
SCK keeps toggling.
Receive a byte from the EEPROM
and send ACK.
Transmit a byte to the EEPROM.
Issue a STOP sequence.
Receive the last byte from the
EEPROM and do not send ACK.
Issue a START sequence.
No operation, set the ERROR bit.
The EEPROM interface can also be operated by controlling the DIO4 and DIO5 pins directly. In
this case, a resistor has to be used in series with SDA to avoid data collisions due to limits in the
speed at which the SDA pin can be switched from output to input. Controlling DIO4 and DIO5 directly is discouraged, because it may tie up the MPU to the point where it may become too busy to process interrupts.
Three-Wire (µ-Wire) EEPROM Interface
A 500 kHz three-wire interface, using SDATA, SCK and a DIO pin for CS is available. The interface is
selected by setting DIO_EEX = 2 (b10). The EECTRL bits when the three-wire interface is selected are
shown in Table 44. When EECTRL is written, up to 8 bits from EEDATA are either written to the EEPROM
or read from the EEPROM, depending on the values of the EECTRL bits.
The µ-Wire EEPROM interface is only functional when MPU_DIV[2:0] = 000.
Table 44: EECTRL Bits for the 3-Wire Interface
Control
Bit
7
WFR
Read/
Write
W
6
BUSY
R
5
HiZ
W
4
3:0
RD
CNT[3:0]
W
W
Name
Description
Wait for Ready. If this bit is set, the trailing edge of BUSY will be delayed until a rising edge is seen on the data line. This bit can be used
during the last byte of a Write command to cause the INT5 interrupt to
occur when the EEPROM has finished its internal write sequence. This
bit is ignored if HiZ = 0.
Asserted while the serial data bus is busy. When the BUSY bit falls, an
INT5 interrupt occurs.
Indicates that the SD signal is to be floated to high impedance immediately after the last SCK rising edge.
Indicates that EEDATA is to be filled with data from EEPROM.
Specifies the number of clocks to be issued. Allowed values are 0
through 8. If RD=1, CNT bits of data will be read MSB first and right
justified into the low order bits of EEDATA. If RD=0, CNT bits will be
sent MSB first to the EEPROM, shifted out of the MSB of EEDATA. If
CNT[3:0] is zero, SDATA will simply obey the HiZ bit.
The timing diagrams in Figure 11 through Figure 15 describe the 3-wire EEPROM interface behavior. All
commands begin when the EECTRL register is written. Transactions start by first raising the DIO pin that
is connected to CS. Multiple 8-bit or less commands such as those shown in Figure 11 through Figure 15
are then sent via EECTRL and EEDATA.
48
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
When the transaction is finished, CS must be lowered. At the end of a Read transaction, the EEPROM
will be driving SDATA, but will transition to HiZ (high impedance) when CS falls. The firmware should
then immediately issue a write command with CNT=0 and HiZ=0 to take control of SDATA and force it to
a low-Z state.
EECTRL Byte Written
INT5
CNT Cycles (6 shown)
Write -- No HiZ
SCLK (output)
SDATA (output)
D7
D6
D5
SDATA output Z
D4
D3
D2
(LoZ)
BUSY (bit)
Figure 11: 3-Wire Interface. Write Command, HiZ=0.
EECTRL Byte Written
INT5
CNT Cycles (6 shown)
Write -- With HiZ
SCLK (output)
SDATA (output)
D7
D6
D5
SDATA output Z
D4
D3
D2
(LoZ)
(HiZ)
BUSY (bit)
Figure 12: 3-Wire Interface. Write Command, HiZ=1
EECTRL Byte Written
INT5
CNT Cycles (8 shown)
READ
SCLK (output)
SDATA (input)
D7
SDATA output Z
D6
D5
D4
D3
D2
D1
D0
(HiZ)
BUSY (bit)
Figure 13: 3-Wire Interface. Read Command.
EECTRL Byte Written
Write -- No HiZ
INT5 not issued
CNT Cycles (0 shown)
SDATA output Z
BUSY (bit)
Write -- HiZ
INT5 not issued
CNT Cycles (0 shown)
SCLK (output)
SCLK (output)
SDATA (output)
EECTRL Byte Written
SDATA (output)
D7
(LoZ)
SDATA output Z
(HiZ)
BUSY (bit)
Figure 14: 3-Wire Interface. Write Command when CNT=0
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
49
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
EECTRL Byte Written
INT5
CNT Cycles (6 shown)
Write -- With HiZ and WFR
SCLK (output)
SDATA (out/in)
D7
D6
D5
D4
D3
D2
(From 6520)
SDATA output Z
(LoZ)
BUSY
READY
(From EEPROM)
(HiZ)
BUSY (bit)
Figure 15: 3-Wire Interface. Write Command when HiZ=1 and WFR=1.
1.5.15 SPI Slave Port
The slave SPI port communicates directly with the MPU data bus and is able to read and write Data RAM
locations. It is also able to send commands to the MPU. The interface to the slave port consists of the
PCSZ, PCLK, PSDI and PSDO pins. These pins are multiplexed with the LCD segment driver pins SEG3
to SEG6. The port pins default to LCD driver pins. The port is enabled by setting the SPE bit.
Access to I/O RAM (Configuration RAM) should not be attempted via the SPI Port.
A typical SPI transaction is as follows. While PCSZ is high, the port is held in an initialized/reset state.
During this state, PSDO is held in HiZ state and all transitions on PCLK and PSDI are ignored. When
PCSZ falls, the port will begin the transaction on the first rising edge of PCLK. A transaction consists of
an 8-bit command, a 16-bit address and then one or more bytes of data. The transaction ends when
PCSZ is raised. Some transactions may consist of a command only.
The last SPI command and address (if part of the command) are available to the MPU in registers
SP_CMD and SP_ADDR.
The SPI port supports data transfers at 1 Mb/s in mission mode and 16 kb/s in brownout mode. The SPI
commands are described in Table 45 and in Figure 16 illustrate the SPI Interface read and write timing.
Table 45: SPI Command Description
Command
11xx xxxx ADDR Byte0 ... ByteN
10xx xxxx ADDR Byte0 ... ByteN
50
Description
Read data starting at ADDR. The ADDR will auto-increment until PCSZ
is raised. Upon completion:
SP__CMD=11xx xxxx, SP_ADDR=ADDR+N+1.
No MPU interrupt is generated if the command is 1100 0000. Otherwise, an SPI interrupt is generated.
Write data starting at ADDR. The ADDR will auto-increment until PCSZ
is raised. Upon completion:
SP_CMD=10xx xxxx, SP_ADDR=ADDR+N+1.
No MPU interrupt is generated if the command is 1000 0000. Otherwise, an SPI interrupt is generated.
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
SERIAL READ
8 bit CMD
DATA[ADDR]
16 bit Address
DATA[ADDR+1]
PCSZ
Extended Read . . .
0
7
8
C0
A15
23
24
A0
x
31
32
D0
D7
39
PSCK
(From Host) PSDI
x
C7
C6
C5
A14
A1
HI Z
(From 6531) PSDO
SERIAL WRITE
D7
8 bit CMD
D6
D1
DATA[ADDR]
16 bit Address
D6
D1
D0
DATA[ADDR+1]
PCSZ
Extended Write . . .
0
7
8
C0
A15
23
24
A0
D7
31
32
D0
D7
39
PSCK
(From Host) PSDI
x
C7
C6
C5
A14
A1
D6
D1
D6
D1
D0
x
HI Z
(From 6531) PSDO
Figure 16: SPI Slave Port: Typical Read and Write operations
Possible applications for the SPI interface are:
1) An external host reads data from CE locations to obtain metering information. This can be used
in applications where the 71M6531D/F or 71M6532D/F function as smart front-ends with preprocessing capability. Since the addresses are in 16-bit format, any type of XRAM data can be accessed: CE, MPU, I/O RAM, but not SFRs or the 80515-internal register bank.
2) A communication link can be established via the SPI interface: By writing into MPU memory locations, the external host can initiate and control processes in the MPU of the 71M6531D/F or
71M6532D/F. Writing to a CE or MPU location normally generates an interrupt, a function that
can be used to signal to the MPU that the byte that had just been written by the external host
must be read and processed. Data can also be inserted by the external host without generating
an interrupt.
3) An external DSP can access front-end data generated by the ADC. This mode of operation uses
the 71M6531D/F or 71M6532D/F as an analog front-end (AFE).
1.5.16 Hardware Watchdog Timer
V1
V3P3
V3P3 - 10mV
WDT disabled
V3P3 400mV
Normal
operation,
WDT
enabled
VBIAS
Battery
modes
An independent, robust, fixed-duration, watchdog timer (WDT) is included
in the 71M6531D/F and 71M6532D/F. It uses the RTC crystal oscillator as
its time base and must be refreshed by the MPU firmware at least every
1.5 seconds. When not refreshed on time, the WDT overflows and the part
is reset as if the RESET pin were pulled high, except that the I/O RAM bits
will be in the same state as after a wake-up from SLEEP or LCD modes
(see the I/O RAM description in Section 4.2 for a list of I/O RAM bit states
after RESET and wake-up). 4100 oscillator cycles (or 125 ms) after the
WDT overflow, the MPU will be launched from program address 0x0000.
A status bit, WD_OVF, is set when the WDT overflow occurs. This bit is
powered by the nonvolatile supply and can be read by the MPU when
WAKE rises to determine if the part is initializing after a WDT overflow
event or after a power-up. After it is read, the MPU firmware must clear
WD_OVF. The WD_OVF bit is also cleared by the RESET pin.
There is no internal digital state that deactivates the WDT.
0V
Figure 17: Functions defined by V1
The WDT can be disabled by tying the V1 pin to V3P3 (see Figure 17). Of course, this also deactivates
V1 power fault detection. Since there is no method in firmware to disable the crystal oscillator or the
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
51
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
WDT, it is guaranteed that whatever state the part might find itself in, upon watchdog overflow, the part
will be reset to a known state.
Asserting ICE_E will also deactivate the WDT. This is the only method that will work in BROWNOUT
mode. In normal operation, the WDT is reset by periodically writing a one to the WDT_RST bit. The
watchdog timer is also reset when the internal signal WAKE=0 (see Section 2.5 Wake-Up Behavior).
If enabled with the IEN_WD_NROVF register in I/O RAM, an interrupt occurs roughly 1 ms before the WDT
resets the chip. This can be used to determine the cause of a WDT reset since it allows the code to log
its state (e.g. the current PC value, loop counters, flags, etc.) before a WDT reset occurs.
1.5.17 Test Ports (TMUXOUT pin)
One of the digital or analog signals listed in Table 46 can be selected to be output on the TMUXOUT pin.
The function of the multiplexer is controlled with the I/O RAM register TMUX (0x20AA[4:0]), as shown in
Table 46.
Table 46: TMUX[4:0] Selections
TMUX[4:0]
0
1
2
3
4
5
6
7
8 - 0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16 – 0x17
0x18
0x19
0x1A
0x1B
0x1C
0X1D
Mode
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
–
Digital
Digital
–
Digital
Digital
Digital
–
Digital
Digital
–
Digital
Digital
Digital
0X1E
0X1F
Digital
Digital
Function
DGND
Reserved
DGND
Reserved
PLL_2P5
Output of the 2.5 V low-power regulator
Internal VBIAS voltage (nominally 1.6V)
Not used
Reserved
RTC 1-second output
RTC 4-second output
Not used
V1_OK comparator output
Real-time output (RTM) from the CE
WDTR_EN (Comparator 1 Output AND V1LT3)
Not used
RXD (from Optical interface, w/ optional inversion)
MUX_SYNC
Not used
CKMPU (MPU clock)
Pulse output
RTCLK (output of the oscillator circuit, nominally
32,786Hz)
CE_BUSY (busy interrupt generated by CE, 396µs)
XFER_BUSY (transfer busy interrupt generated by the
CE, nominally every 999.7ms)
The TMUXOUT pin may be used for diagnosis purposes or in production test. The RTC 1-second output
may be used to calibrate the crystal oscillator. The RTC 4-second output provides even higher precision.
52
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
2
Functional Description
2.1
Theory of Operation
The energy delivered by a power source into a load can be expressed as:
t
E = ∫ V (t ) I (t )dt
0
Assuming phase angles are constant, the following formulae apply:


P = Real Energy [Wh] = V * A * cos φ* t

S = Apparent Energy [VAh] =
Q = Reactive Energy [VARh] = V * A * sin φ * t
P2 + Q2
For a practical meter, not only voltage and current amplitudes, but also phase angles and harmonic content may change constantly. Thus, simple RMS measurements are inherently inaccurate. A modern solid-state electricity meter IC such as the Teridian 71M6531 functions by emulating the integral operation
above, i.e. it processes current and voltage samples through an ADC at a constant frequency. As long as
the ADC resolution is high enough and the sample frequency is beyond the harmonic range of interest,
the current and voltage samples, multiplied with the time period of sampling will yield an accurate quantity
for the momentary energy. Summing up the momentary energy quantities over time will result in accumulated energy.
500
400
300
200
100
0
0
5
10
15
20
-100
-200
Current [A]
-300
Voltage [V]
Energy per Interval [Ws]
-400
Accumulated Energy [Ws]
-500
Figure 18: Voltage, Current, Momentary and Accumulated Energy
Figure 18 shows the shapes of V(t), I(t), the momentary power and the accumulated power, resulting from
50 samples of the voltage and current signals over a period of 20 ms. The application of 240 VAC and
100 A results in an accumulation of 480 Ws (= 0.133 Wh) over the 20 ms period, as indicated by the accumulated power curve. The described sampling method works reliably, even in the presence of dynamic
phase shift and harmonic distortion.
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Data Sheet 71M6531D/F-71M6532D/F
2.2
FDS 6531/6532 005
System Timing Summary
Figure 19 summarizes the timing relationships between the input MUX states, the CE_BUSY signal and
the two serial output streams. In this example, MUX_DIV=4 and FIR_LEN=2 (384 CE cycles, 3 CK32
cycles per conversion), resulting in 13 CK32 cycles per multiplexer frame. Generally, the duration of each
MUX frame is:
•
•
•
1 + MUX_DIV * 1, if FIR_LEN=0 (138 CE cycles)
1 + MUX_DIV * 2, if FIR_LEN=1 (288 CE cycles)
1 + MUX_DIV * 3, if FIR_LEN=2 (384 CE cycles).
An ADC conversion will always consume an integer number of CK32 clocks. Following this is a single
CK32 cycle where the bandgap voltage is allowed to recover from the change in CROSS.
ADC MUX Frame
ADC TIMING
Settle
MUX_DIV=4 (4 conversions) is shown
CK32
150
MUX_SYNC
MUX STATE
0
S
1
2
S
3
ADC EXECUTION
ADC0
CE TIMING
0
ADC1
450
ADC2
900
ADC3
1350
1800
CE_EXECUTION
MAX CK COUNT
CK COUNT = CE_CYCLES + floor((CE_CYCLES + 2) / 5)
CE_BUSY
XFER_BUSY
INITIATED BY A CE OPCODE AT END OF SUMMATION INTERVAL
NOTES:
1. ALL DIMENSIONS ARE 5MHZ CK COUNTS.
2. THE PRECISE FREQUENCY OF CK IS 150*CRYSTAL FREQUENCY = 4.9152MHz.
3. XFER_BUSY OCCURS ONCE EVERY (PRE_SAMPS * SUM_CYCLES) CODE PASSES.
Figure 19: Timing Relationship between ADC MUX, Compute Engine
Each CE program pass begins when the ADC0 conversion (for IA) begins. Depending on the length of
the CE program, it may continue running until the end of the last conversion (ADC3). CE opcodes are
constructed to ensure that all CE code passes consume exactly the same number of cycles. The result of
each ADC conversion is inserted into the RAM when the conversion is complete. The CE code is written
to tolerate sudden changes in ADC data. The exact clock count when each ADC value is loaded into
RAM is shown in Figure 19.
Figure 20 shows that the serial data stream, RTM, begins transmitting at the beginning of state S. RTM,
consisting of 140 CK cycles, will always finish before the next code pass starts.
CK32
MUX_SYNC
CKTEST
30
0
31
1
30
0
31
1
30
31
FLAG
SIGN
FLAG
SIGN
1
FLAG
LSB
0
31
LSB
30
SIGN
1
LSB
RTM DATA 0 (32 bits)
RTM DATA 1 (32 bits)
RTM DATA 2 (32 bits)
RTM DATA 3 (32 bits)
LSB
FLAG
SIGN
0
TMUXOUT/RTM
Figure 20: RTM Output Format
2.3
Battery Modes
Shortly after system power (V3P3SYS) is applied, the part will be in MISSION mode. MISSION mode
means that the part is operating with system power and that the internal PLL is stable. This mode is the
normal operation mode where the part is capable of measuring energy.
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Data Sheet 71M6531D/F-71M6532D/F
When system power is not available (i.e. when V1<VBIAS), the 71M6531 will be in one of three battery
modes: BROWNOUT, LCD, or SLEEP mode. Figure 21 shows a state diagram of the various operation
modes, with the possible transitions between modes. For information on the timing of mode transitions
refer to Figure 22 through Figure 24.
RESET
MISSION
V3P3SYS
falls
IE_PLLRISE
-> 1
V3P3SYS
rises
V1 > VBIAS
V1 <= VBIAS
IE_PLLFALL
-> 1
V3P3SYS
rises
LCD_ONLY
BROWNOUT
V3P3SYS
rises
RESET &
VBAT_OK
IE_PB -> 1
IE_WAKE ->
1
PB
SLEEP or
VBAT_OK
timer
LCD
timer
PB
VBAT_OK
VBAT_OK
RESET &
VBAT_OK
SLEEP
Figure 21: Operation Modes State Diagram
When V1 falls below VBIAS or the part wakes up under battery power, the part will automatically enter
BROWNOUT mode (see Section 2.5 Wake-Up Behavior). From BROWNOUT mode, the part may enter
either LCD mode or SLEEP mode, as controlled by the MPU via the I/O RAM bits LCD_ONLY and SLEEP.
The transition from MISSION mode to BROWNOUT mode is signaled by the IE_PLLFALL interrupt flag
(SFR 0xE8[7]). The transition in the other direction is signaled by the IE_PLLRISE interrupt flag (SFR
0xE8[6]), when the PLL becomes stable.
Meters that do not require functionality in the battery modes, e.g. meters that only use the SLEEP
mode to maintain the RTC, still need to contain code that brings the chip from BROWNOUT
mode to SLEEP mode. Otherwise, the chip remains in BROWNOUT mode, once the system
power is missing, and consumes more current than intended.
Similarly, meters equipped with batteries need to contain code that transitions the chip to SLEEP
mode as soon as the battery is attached in production. Otherwise, remaining in BROWNOUT
mode would add unnecessary drain to the battery.
Transitions from both LCD and SLEEP mode are initiated by wake-up timer timeout conditions or pushbutton events. When the PB pin is pulled high (pushbutton is pressed), the IE_PB interrupt flag (SFR
0xE8[4]) is set, and when the wake-up timer times out, the IE_WAKE interrupt flag (SFR 0xE8[5]) is set.
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Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
In the absence of system power, if the voltage margin for the LDO regulator providing 2.5 V to the internal
circuitry becomes too low to be safe, the part automatically enters sleep mode (BAT_OK false). The battery voltage must stay above 3 V to ensure that BAT_OK remains true. Under this condition, the
71M6531 stays in SLEEP mode, even if the voltage margin for the LDO improves (BAT_OK true). Table
47 shows the circuit functions available in each operating mode.
Table 47: Available Circuit Functions
Circuit Function
CE
System Power
MISSION
Yes
Battery Power (Nonvolatile Supply)
BROWNOUT
LCD
SLEEP
–
–
–
–
–
Yes
Yes
–
–
–
Analog circuits
Yes
–
–
–
MPU clock rate
From PLL, as
defined by
MPU_DIV
Yes
28.672 kHz
(7/8 of 32768 Hz)
–
–
–
–
–
ICE
Yes
Yes
–
–
DIO Pins
Yes
Yes
–
–
Watchdog Timer
Yes
Yes
–
–
LCD
EEPROM Interface (2-wire)
Yes
Yes
Yes
Yes (8 kb/s)
Yes
–
–
–
EEPROM Interface (3-wire)
Yes
Yes (16 kb/s)
–
–
UART
Yes
300 bd
–
–
Optical TX modulation
Yes
–
–
–
Flash Read
Yes
Yes
–
–
Flash Page Erase
Yes
Yes
–
–
Flash Write
Yes
–
–
–
RAM Read and Write
Yes
Yes
–
–
Wakeup Timer
OSC and RTC
XRAM data preservation
Yes
Yes
Yes
Yes
Yes
Yes
Yes
–
Yes
Yes
–
V3P3D voltage output pin
Yes
–
–
GPO – GP7 registers
Yes
Yes
Yes
Yes
Yes
CE Data RAM
Yes
FIR
MPU_DIV
Yes
-- indicates not active
2.3.1
BROWNOUT Mode
In BROWNOUT mode, most non-metering digital functions are active (as shown in Table 47), including
ICE, UART, EEPROM, LCD and RTC. In BROWNOUT mode, a low bias current regulator will provide
2.5 Volts to V2P5 and V2P5NV. The regulator has an output called BAT_OK to indicate that it has sufficient overhead. When BAT_OK = 0, the part will enter SLEEP mode. From BROWNOUT mode, the processor can voluntarily enter LCD or SLEEP modes. When system power is restored, the part will automatically transition from any of the battery modes to MISSION mode, once the PLL has settled.
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The MPU will run at 7/8 of the crystal clock rate. This permits the UARTs to be operated at 300 bd. In
this mode, the MPU clock has substantial short-term jitter.
The value of MPU_DIV will be remembered (not changed) as the part enters and exits BROWNOUT.
MPU_DIV will be ignored during BROWNOUT.
While PLL_OK = 0, the I/O RAM bits ADC_E and CE_E are held in the zero state disabling both the ADC
and the CE. When PLL_OK falls, the CE program counter is cleared immediately and all FIR processing
halts.
2.3.2
LCD Mode
In LCD mode, the data contained in the LCD_SEG registers is displayed. Up to four LCD segments each
connected to pins SEG18 and SEG19 can be made to blink without the involvement of the MPU, which is
disabled in LCD mode. To minimize power, only segments that might be used should be enabled.
LCD mode can be exited only by system power up, a timeout of the wake-up timer, or a push button.
When the IC exits LCD mode, the MPU can discover the event that caused the exit by reading the interrupt flags and interpret them as follows:
• IE_WAKE = 1 indicates that the wake timer has expired.
• IE_PB =1 indicates that the pushbutton input (PB) was activated.
• COMPSTAT = 0 indicates that a reset occurred but that main power is not yet available.
• If none of the above conditions applies, system power (V3P3SYS) must have been restored
After the transition from LCD mode to MISSION or BROWNOUT mode, the PC will be at 0x0000, the
XRAM is in an undefined state and the I/O RAM is only partially preserved (see the description of I/O
RAM states in Section 4.2). The GP0[7:0] through GP7[7:0] registers are preserved unless RESET goes
high.
2.3.3
SLEEP Mode
In SLEEP mode, the battery current is minimized and only the Oscillator and RTC functions are active.
This mode can be exited only by system power-up, a timeout of the wake-up timer, or a push button
event.
When the IC exits SLEEP mode, the MPU can discover the event that caused the exit by reading the interrupt flags and interpret them as follows:
•
•
•
•
IE_WAKE = 1 indicates that the wake timer has expired.
IE_PB =1 indicates that the pushbutton input (PB) was activated.
COMPSTAT = 0 indicates that a reset occurred but that main power is not yet available.
If none of the above conditions applies, system power (V3P3SYS) must have been restored
After the transition from SLEEP mode to MISSION or BROWNOUT mode the PC will be at 0x0000, the
XRAM is in an undefined state and the I/O RAM is only partially preserved (see the description of I/O
RAM states in Section 4.2). The GP0[7:0] through GP7[7:0] registers are preserved unless RESET goes
high.
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Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
System
Power
(V3P3SYS)
V1_OK
Battery
Current
MPU Mode
300nA
BROWNOUT
PLL_OK
MISSION
13..14 CK
cycles
WAKE
MPU Clock
Source
Transition
PLL
(4.2MHz/MUX_DIV)
Xtal
2048...4096
CK32 cycles
time
Figure 22: Transition from BROWNOUT to MISSION Mode when System Power Returns
V3P3SYS
and VBAT
V1_OK
Battery
Current
MPU Mode
MPU Clock
Source
WAKE
PLL_OK
Internal
RESETZ
300nA
BROWNOUT
Xtal
MISSION
PLL
(4.2MHz)
14.5 CK32
cycles
4096 CK32
cycles
1024 CK32
cycles
time
Figure 23: Power-Up Timing with V3P3SYS and VBAT tied together
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Data Sheet 71M6531D/F-71M6532D/F
VBAT
Battery
Current
BROWNOUT
MPU Mode
Xtal
MPU Clock
Source
14.5 CK32
cycles
WAKE
PLL_OK
Internal
RESETZ
1024 CK32
cycles
VBAT_OK
time
Figure 24: Power-Up Timing with VBAT only
2.4
Fault and Reset Behavior
2.4.1
Reset Mode
When the RESET pin is pulled high, all digital activity stops. The oscillator and RTC module continue to
run. Additionally, all I/O RAM bits are set to their default states. As long as V1, the input voltage at the
power fault block, is greater than VBIAS, the internal 2.5 V regulator will continue to provide power to the
digital section.
Once initiated, the reset mode will persist until the reset timer times out, signified by WAKE rising. This
will occur in 4100 cycles of the real time clock after RESET goes low, at which time the MPU will begin
executing it’s pre-boot and boot sequences from address 00. See the Program Security description in the
Flash Memory section for additional descriptions of pre-boot and boot.
If system power is not present, the reset timer duration will be 2 cycles of the crystal clock at which time
the MPU will begin executing in BROWNOUT mode, starting at address 00.
2.4.2
Power Fault Circuit
The 71M6531D/F and 71M6532D/F include a comparator to monitor system power fault conditions.
When the output of the comparator falls (V1<VBIAS), the I/O RAM bits PLL_OK are zeroed and the part
switches to BROWNOUT mode if a battery is present. Once system power returns, the MPU remains in
reset and does not transition to MISSION mode until 2048 to 4096 CK32 clock cycles later, when
PLL_OK rises. If a battery is not present, as indicated by BAT_OK=0, WAKE will fall and the part will enter SLEEP mode.
There are several conditions the device could be in as system power returns. If the part is in BROWNOUT mode, it will automatically switch to MISSION mode when PLL_OK rises. It will receive an interrupt
indicating this. No configuration bits will be reset or reconfigured during this transition.
If the part is in LCD or SLEEP mode when system power returns, it will also switch to MISSION mode
when PLL_OK rises. In this case, all configuration bits will be in the reset state due to WAKE having
been zero. The RTC clock will not be disturbed, but the MPU RAM must be re-initialized. The hardware
watchdog timer will become active when the part enters MISSION mode.
If there is no battery when system power returns, the part will switch to MISSION mode when PLL_OK
rises. All configuration bits will be in reset state and RTC and MPU RAM data will be unknown and must
be initialized by the MPU.
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Data Sheet 71M6531D/F-71M6532D/F
2.5
FDS 6531/6532 005
Wake-Up Behavior
As described above, the part will always wake up in MISSION mode when system power is restored. Additionally, the part will wake up in BROWNOUT mode when PB rises (push button is pressed) or when a
timeout of the wake-up timer occurs.
2.5.1
Wake on PB
If the part is in SLEEP or LCD mode, it can be awakened by a rising edge on the PB pin. This pin is normally pulled to GND and can be pulled high by a push button depression. Before the PB signal rises, the
MPU is in reset due to WAKE being low. When PB rises, WAKE rises and within three crystal cycles, the
MPU begins to execute. The MPU can determine whether the PB signal woke it up by checking the
IE_PB flag. Figure 25 shows the Wake Up timing.
For debouncing, the PB pin is monitored by a state machine operating from a 32 Hz clock. This circuit
will reject between 31 ms and 62 ms of noise. Detection hardware will ignore all transitions after the initial
rising edge. This will continue until the MPU clears the IE_PB bit.
System
Power
(V3P3SYS)
PB or wakeup timer
15 CK32
cycles
WAKE
MPU Mode
LCD
BROWNOUT
PLL_OK
time
Figure 25: Wake Up Timing
2.5.2
Wake on Timer
If the part is in SLEEP or LCD mode, it can be awakened by the wake-up timer. Until this timer times out,
the MPU is in reset due to WAKE being low. When the wake-up timer times out, the WAKE signal rises
and within three crystal cycles, the MPU begins to execute. The MPU can determine whether the timer
woke it by checking the AUTOWAKE interrupt flag (IE_WAKE).
The wake-up timer begins timing when the part enters LCD or SLEEP mode. Its duration is controlled by
WAKE_PRD[2:0] and WAKE_RES. WAKE_RES selects a timer LSB of either 1 minute (WAKE_RES = 1) or
2.5 seconds (WAKE_RES = 0). WAKE_PRD[2:0] selects a duration of from 1 to 7 LSBs.
The timer is armed by WAKE_ARM = 1. It must be armed at least three RTC cycles before SLEEP or
LCD_ONLY is initiated. Setting WAKE_ARM presets the timer with the values in WAKE_RES and
WAKE_PRD and readies the timer to start when the processor writes to SLEEP or LCD_ONLY. The timer is
reset and disarmed whenever the processor is awake. Thus, if it is desired to wake the MPU periodically
(every 5 seconds, for example) the timer must be rearmed every time the MPU is awakened.
2.6
Data Flow
The data flow between the Compute Engine (CE) and the MPU is shown in Figure 26. In a typical application, the 32-bit CE sequentially processes the samples from the voltage inputs on pins IA, VA, IB and
VB, performing calculations to measure active power (Wh), reactive power (VARh), A2h and V2h for fourquadrant metering. These measurements are then accessed by the MPU, processed further and output
using the peripheral devices available to the MPU. Figure 26 illustrates the CE/MPU data flow.
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Data Sheet 71M6531D/F-71M6532D/F
Pulses
IRQ
Samples
CE
PreProcessor
Processed
Metering
Data
MPU
Data
Post Processor
I/O RAM (Configuration RAM)
Figure 26: MPU/CE Data Flow
2.7
CE/MPU Communication
Figure 27 shows the functional relationships between the CE and the MPU. The CE is controlled by the
MPU via shared registers in the I/O RAM and in RAM.
The CE outputs two interrupt signals to the MPU: CE_BUSY and XFER_BUSY, which are connected to
the MPU interrupt service inputs as external interrupts. CE_BUSY indicates that the CE is actively
processing data. This signal will occur once every multiplexer cycle. XFER_BUSY indicates that the CE
is updating data to the output region of the RAM. This will occur whenever the CE has finished generating a sum by completing an accumulation interval determined by SUM_CYCLES * PRE_SAMPS samples.
Interrupts to the MPU occur on the falling edges of the XFER_BUSY and CE_BUSY signals.
Refer to Section 4.3 CE Interface Description for additional information on setting up the device using the
MPU firmware.
WSUM
PULSES
W (DIO6)
VARSUM
VAR
(DIO7)
APULSEW
APULSER
EXT PULSE
SAG CONTROL
ADC
SAMPLES
CE
Mux Control
DISPLAY (Memory
mapped LCD
segments)
SERIAL
(UART0/1)
MPU
DATA
EEPROM
(I2C)
CE BUSY
XFER BUSY
DIO
INTERRUPTS
I/O RAM (Configuration RAM)
Figure 27: MPU/CE Communication
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Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
3
Application Information
3.1
Connection of Sensors
Figure 28 through Figure 30 show how resistive dividers, current transformers, Rogowski coils and resistive shunts are connected to the voltage and current inputs of the 71M6531.
VA = Vin * Rout/(Rout + Rin)
VA
Rin
Vin
Rout
Figure 28: Resistive Voltage Divider
Iin
Iout
IA
IIN
IOUT
InP
VDIFF
VOUT
Vout
R
R
V3P3A
V3P3
1/N
InN
1/N
Filter
Figure 29: CT with Single Ended (Left) and Differential Input (Right) Connection
Iin
IA
R
Vout
Iin
1/N
Vout = dIin /dt
IA
R
Vout
V3P3
VC
V3P3
Figure 30: Resistive Shunt (Left) and Rogowski Sensor (Right) Connection
3.2
Connecting 5-V Devices
All digital input pins of the 71M6531D/F and 71M6532D/F are compatible with external 5-V devices. I/O
pins configured as inputs do not require current-limiting resistors when they are connected to external 5-V
devices.
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3.3
Data Sheet 71M6531D/F-71M6532D/F
Temperature Measurement
Measurement of absolute temperature uses the on-chip temperature sensor and applying the following
formula:
T=
( N (T ) − N n )
+ Tn
Sn
In the above formula, T is the temperature in °C, N(T) is the ADC count at temperature T, Nn is the ADC
count at 25°C, Sn is the sensitivity in LSB/°C as stated in the Electrical Specifications and Tn is +25 °C.
It is recommended that temperature measurements be based on TEMP_RAW_X which is the sum of two
consecutive temperature readings, thus being higher by a factor of two than the raw sensor readings.
3.4
Temperature Compensation
3.4.1
Temperature Coefficients:
The internal voltage reference VREF is calibrated during device manufacture.
The temperature coefficient TC2 is given as a constant that represents typical component behavior (in
µV/°C2). TC1 (µV/°C) can be calculated for the individual chip from the contents of the TRIMT[7:0] I/O
RAM register. TC1 and TC2 allow compensation for variations of the reference voltage to within ±40
PPM/°C.
Since TC1 and TC2 are given in µV/°C and µV/°C2, respectively, the value of the VREF voltage
(1.195V) has to be taken into account when transitioning to PPM/°C and PPM/°C2. This means
that PPMC = 26.84*TC1/1.195 and PPMC2 = 1374*TC2/1.195).
3.4.2
Temperature Compensation for VREF
The bandgap temperature is used to digitally compensate the power outputs for the temperature dependence of VREF, using the CE register GAIN_ADJ. Since the band gap amplifier is chopper-stabilized via
the CHOP_E bits, the most significant long-term drift mechanism in the voltage reference is removed.
The following formula is used to determine the GAIN_ADJ value of the CE. In this formula, TEMP_X is the
deviation from nominal or calibration temperature expressed in multiples of 0.1 °C:
GAIN _ ADJ = 16385 +
3.4.3
TEMP _ X ⋅ PPMC TEMP _ X 2 ⋅ PPMC 2
+
214
2 23
System Temperature Compensation
In a production electricity meter, the 71M6531 or 71M6532D/F is not the only component contributing to
temperature dependency. A whole range of components (e.g. current transformers, resistor dividers,
power sources, filter capacitors) will contribute temperature effects.
Since the output of the on-chip temperature sensor is accessible to the MPU, temperature compensation
mechanisms with great flexibility are possible. MPU access to GAIN_ADJ permits a system-wide temperature correction over the entire meter rather than local to the chip.
3.4.4
Temperature Compensation for the RTC
In order to obtain accurate readings from the RTC, the following procedure is recommended:
1. At the time of meter calibration, the crystal oscillator is calibrated using the RTC_ADJ register in I/O
RAM to be as close to 32768 Hz as possible. The recommended procedure is to connect a highprecision frequency counter to the TMUXOUT pin and select 0x11 for TMUX[4:0]. This will generate
a 4-second pulse at TMUXOUT that can be used to trim RTC_ADJ to the best value.
2. When the meter is in service, the MPU takes frequent temperature readings. If the temperature characteristics of the crystal are known, the temperature readings can be used to modify the settings for
the I/O RAM registers PREG[16:0] and QREG[1:0] in order to keep the crystal frequency close to
32768 Hz.
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Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
3. After periods of operation under battery power, the temperature for the time the meter was not powered can be estimated by averaging the temperatures before and after battery operation. Based on
this, the overall correction for the RTC time can be calculated and applied to the RTC after main
power returns to the meter.
3.5
Connecting LCDs
The 71M6531D/F and 71M6532D/F have an on-chip LCD controller capable of controlling static or multiplexed LCDs. Figure 31 shows the basic connection for an LCD.
The following dedicated and multi-use pins can be assigned as LCD segment pins for the 71M6531D/F:
•
•
•
12 dedicated LCD segment pins: SEG0 to SEG2, SEG7, SEG8, SEG12 to SEG18.
7 dual-function pins: SEG3/PCLK, SEG4/PSDO, SEG5/PCSZ, SEG6/PSDI, E_RXTX/SEG9,
E_TCLK/SEG10, and E_RST/SEG11.
14 combined DIO and segment pins: SEG24/DIO4 to SEG35/DIO15, SEG37/DIO17, SEG48/DIO28,
SEG49/DIO29 and SEG63/DIO43 to SEG66/DIO46.
The following dedicated and multi-use pins can be assigned as LCD segments for the 71M6532D/F:
•
•
•
15 dedicated LCD segment pins: SEG0 to SEG2, SEG8, SEG12 - SEG18, SEG20 - SEG23.
9 dual-function pins: MUX_SYNC/SEG7, E_RXTX/SEG9, E_TCLK/SEG10, E_RST/SEG11,
SEG3/PCLK, SEG4/PSDO, SEG5/PCSZ, SEG6/PSDI.
43 combined DIO and segment pins, as described in section 1.5.8.
71M6531D/F or 71M6532D/F
LCD
segments
commons
.
Figure 31: Connecting LCDs
3.6
Connecting I2C EEPROMs
I2C EEPROMs or other I2C compatible devices should be connected to the DIO pins DIO4 and DIO5, as
shown in Figure 32.
Pull-up resistors of roughly 10 kΩ to V3P3D (to ensure operation in BROWNOUT mode) should be used
for both SCL and SDA signals. The DIO_EEX register in I/O RAM must be set to 01 in order to convert
the DIO pins DIO4 and DIO5 to I2C pins SCL and SDA.
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Data Sheet 71M6531D/F-71M6532D/F
71M6531D/F
71M6532D/F 10 kΩ
V3P3D
10 kΩ
EEPROM
DIO4
SCL
DIO5
SDA
Figure 32: I2C EEPROM Connection
3.7
Connecting Three-Wire EEPROMs
µWire EEPROMs and other compatible devices should be connected to the DIO pins DIO4 and DIO5, as
shown in Figure 33 and described below:
•
•
•
•
•
DIO5 connects to both the DI and DO pins of the three-wire device.
The CS pin must be connected to a vacant DIO pin of the 71M6531.
In order to prevent bus contention, a 10 kΩ to resistor is used to separate the DI and DO signals.
The CS and CLK pins should be pulled down with resistors to prevent operation of the three-wire device on power-up, before the 71M6531 can establish a stable signal for CS and CLK.
The DIO_EEX register in I/O RAM must be set to 2 (b10) in order to convert the DIO pins DIO4 and
DIO5 to µWire pins.
The µ-Wire EEPROM interface is only functional when MPU_DIV[2:0] = 000.
71M653X
EEPROM
V3P3D
VCC
DIO4
CLK
10 kΩ
DIO5
DIOn
DI
DO
CS
100 kΩ
100 kΩ
Figure 33: Three-Wire EEPROM Connection
3.8
UART0 (TX/RX)
The UART0 RX pin should be pulled down by a 10 kΩ resistor and additionally protected by a 100 pF ceramic capacitor, as shown in Figure 34.
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
65
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
71M6531D/F, 71M6532D/F
RX
100 pF 10 k Ω
TX
RX
TX
Figure 34: Connections for UART0
3.9
Optical Interface (UART1)
The OPT_TX and OPT_RX pins can be used for a regular serial interface (by connecting a RS-232 transceiver for example), or they can be used to directly operate optical components (for example, an infrared
diode and phototransistor implementing a FLAG interface). Figure 35 shows the basic connections for
UART1. The OPT_TX pin becomes active when the I/O RAM register OPT_TXE is set to 00.
The polarity of the OPT_TX and OPT_RX pins can be inverted with the configuration bits, OPT_TXINV
and OPT_RXINV, respectively.
The OPT_TX output may be modulated at 38 kHz when system power is present. Modulation is not
available in BROWNOUT mode. The OPT_TXMOD bit enables modulation. The duty cycle is controlled
by OPT_FDC[1:0], which can select 50%, 25%, 12.5% and 6.25% duty cycle. A 6.25% duty cycle means
OPT_TX is low for 6.25% of the period. The OPT_RX pin uses digital signal thresholds. It may need an
analog filter when receiving modulated optical signals.
With modulation, an optical emitter can be operated at higher current than nominal, enabling it to
increase the distance along the optical path.
If operation in BROWNOUT mode is desired, the external components should be connected to V3P3D.
V3P3SYS
R1
71M6531D/F or 71M6532D/F
OPT_RX
100 pF
10 kΩ
Phototransistor
V3P3SYS
R2
LED
OPT_TX
Figure 35: Connection for Optical Components
66
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
3.10
Data Sheet 71M6531D/F-71M6532D/F
Connecting the V1 Pin
A voltage divider should be used to establish that V1 is in a safe range when the meter is in MISSION
mode (see Figure 36). V1 must be lower than 2.9 V in all cases in order to keep the hardware watchdog
timer enabled. The resistor divider ratio must be chosen so that V1 crosses the VBIAS threshold when
V3P3 is near the minimum supply voltage (3.0 VDC). A series resistor (R3) provides additional hysteresis, and a capacitor to ground (C1) is added for enhanced EMC immunity.
The amount of hysteresis depends on the choice of R1 and R3: If V1 < VBIAS, approximately 1 µA will
flow into the on-chip V1 comparator causing a voltage drop. If V1 ≥ VBIAS, almost no current will flow
into the comparator. The voltage drop will require V3P3 to be slightly higher for V1 to cross the VBIAS
threshold when V3P3 is rising as compared to when V3P3 is falling. Maintaining sufficient hysteresis
helps to eliminate rapid mode changes which may occur in cases where the power supply is unstable with
V1 close to the VBIAS threshold point.
R3
R1
V3P3
16.9kΩ
R2
20kΩ
C1
100pF
V1
GND
Figure 36: Voltage Divider for V1
3.11
Connecting the Reset Pin
Even though a functional meter will not necessarily need a reset switch, it is useful to have a reset pushbutton for prototyping as shown in Figure 37, left side. The RESET signal may be sourced from
V3P3SYS (functional in MISSION mode only), V3P3D (MISSION and BROWNOUT modes), or VBAT (all
modes, if a battery is present), or from a combination of these sources, depending on the application.
For a production meter, the RESET pin should be protected by the by the external components shown in
Figure 37, right side. R1 should be in the range of 100 Ω and mounted as closely as possible to the IC.
VBAT/
V3P3D
V3P3D
R2
1k Ω
71M6533
71M6531D/F
71M6532D/F
71M6531D/F
71M6532D/F
Reset
Switch
RESET
RESET
0.1µF
100Ω
R1
10k Ω
R1
DGND
DGND
Figure 37: External Components for the RESET Pin: Push-button (Left), Production Circuit (Right)
Since the 71M6531 generates its own power-on reset, a reset button or circuitry, as shown in Figure 37,
is only required for test units and prototypes.
3.12
Connecting the Emulator Port Pins
Even when the emulator is not used, small shunt capacitors to ground (22 pF) should be used for protection from EMI as illustrated in Figure 38. Production boards should have the ICE_E pin connected to
ground.
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
67
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
LCD Segments
(optional)
V3P3D
ICE_E
62 Ω
E_RST
62 Ω
E_RXT
E_TCLK
62 Ω
22 pF 22 pF 22 pF
71M6531D/F
71M6532D/F
Figure 38: External Components for the Emulator Interface
3.13
Connecting a Battery
It is important that a valid voltage is connected to the VBAT pin at all times. For meters without a battery,
VBAT should be connected directly to V3P3SYS. Designs for meters with batteries need to ensure that
the meter functions even when the battery voltage decreases below the specified voltage for VBAT. This
can be achieved by connecting a diode from V3P3SYS to VBAT. However, the battery test will yield inaccurate results if that technique is used, since the voltage at V3P3SYS will feed current to the VBAT pin.
A better solution is shown in Figure 39: During the battery test, a DIO pin is activated as an output and
applies a low voltage to the anode of the diode. This prevents the voltage at the power supply to influence
the voltage at the VBAT pin.
Power
Supply
V3P3SYS
V3P3A
DIO
VBAT
Battery or
Super-Cap
+
71M6531/71M6532
Figure 39: Connecting a Battery
As mentioned in section 2.3, meters equipped with batteries need to contain code that transitions
the chip to SLEEP mode as soon as the battery is attached in production. Otherwise, remaining in
BROWNOUT mode would add unnecessary drain to the battery.
3.14
Flash Programming
Operational or test code can be programmed into the flash memory using either an in-circuit emulator or
the Flash Programmer Module (TFP2) available from Teridian. The flash programming procedure uses
the E_RST, E_RXTX and E_TCLK pins. The FL_BANK[2:0] register must be set to the value corresponding to the bank that is being programmed.
68
© 2005-2009 TERIDIAN Semiconductor Corporation
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FDS 6531/6532 005
3.15
Data Sheet 71M6531D/F-71M6532D/F
MPU Firmware Library
All application-specific MPU functions mentioned in the Application Information section are available from
Teridian as a standard ANSI C library and as ANSI C source code. The code is available as part of the
Demonstration Kit for the 71M6531D/F and 71M6532D/F. The Demonstration Kits come with the
71M6531D/F or 71M6532D/F preprogrammed with demo firmware and mounted on a functional sample
meter Demo Board. The Demo Boards allow for quick and efficient evaluation of the IC without having to
write firmware or having to supply an in-circuit emulator (ICE).
3.16
Crystal Oscillator
The oscillator drives a standard 32.768 kHz watch crystal. The oscillator has been designed specifically
to handle these crystals and is compatible with their high impedance and limited power handling capability. The oscillator power dissipation is very low to maximize the lifetime of any battery backup device attached to VBAT.
Board layouts with minimum capacitance from XIN to XOUT will require less battery current. Good
layouts will have XIN and XOUT shielded from each other.
Since the oscillator is self-biasing, an external resistor must not be connected across the crystal.
3.17
Meter Calibration
Once the Teridian 71M6531D/F or 71M6532D/F energy meter device has been installed in a meter system, it must be calibrated. A complete calibration includes the following:
•
•
•
•
Calibration of the metrology section, i.e. calibration for tolerances of the current sensors, voltage dividers and signal conditioning components as well as of the internal reference voltage (VREF).
Establishment of the reference temperature (Section 3.3) for temperature measurement and temperature compensation (Section 3.4).
Calibration of the battery voltage measurement (Section 1.5.13).
Calibration of the oscillator frequency (Section 1.5.3) and temperature compensation for the RTC
(Section 3.4.4).
The metrology section can be calibrated using the gain and phase adjustment factors accessible to the
CE. The gain adjustment is used to compensate for tolerances of components used for signal conditioning, especially the resistive components. Phase adjustment is provided to compensate for phase shifts
introduced by the current sensors or by the effects of reactive power supplies.
Due to the flexibility of the MPU firmware, any calibration method, such as calibration based on energy, or
current and voltage can be implemented. It is also possible to implement segment-wise calibration (depending on current range).
The 71M6531D/F and 71M6532D/F support common industry standard calibration techniques, such as singlepoint (energy-only), multi-point (energy, Vrms, Irms) and auto-calibration.
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
69
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
4
Firmware Interface
4.1
I/O RAM and SFR Map – Functional Order
Unused bits are labeled as “Not Used” and grayed out. These bits contain no memory and are read by the MPU as zero. Bits labeled as “Reserved” may be in use and should not be changed from the values given in parentheses. This table lists only the SFR registers that are not generic 8051 SFR registers. Bits marked with † apply to the 71M6531D/F only, bits marked with ‡ apply to the 71M6532D/F only and should be 0 for
the other device.
Table 48: I/O RAM Map in Functional Order
Name
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Configuration:
CE0
EQU[2:0]
CE_E
CE10MHZ
Not Used
2000
CE1
PRE_SAMPS[1:0]
SUM_CYCLES[5:0]
2001
CE2
CHOP_E[1:0]
RTM_E
WD_OVF
EX_RTC
EX_XFR
Not Used
2002
COMP0
PLL_OK
COMP_STAT
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
2003
CONFIG0
VREF_CAL
PLS_INV
CKOUT_E
VREF_DIS
MPU_DIV[2:0]
Not Used
2004
CONFIG1
ECK_DIS
M26MHZ
ADC_E
MUX_ALT
M40MHZ
Not Used
Not Used
Not Used
2005
VERSION
VERSION[7:0]
2006
CONFIG2
OPT_TXE[1:0]
EX_PLL
EX_FWCOL
FIR_LEN[1:0]
OPT_FDC[1:0]
2007
CE3
MUX_DIV[3:0]
Not Used
209D
CE4
BOOT_SIZE[7:0]
20A7
CE5
CE_LCTN[7:0]
20A8
WAKE
WAKE_ARM
SLEEP
LCD_ONLY
WAKE_RES
WAKE_PRD[2:0]
Not Used
20A9
TMUX
TMUX[4:0]
Not Used
20AA
ANACTRL
LCD_DAC[2:0]
CHOP_I_EN‡
Reserved (0000)
20AB
CONFIG3
SEL_IBN‡
CHOP_IB‡
SEL_IAN‡
CHOP_IA‡
20AC
Not Used
Not Used
CONFIG4
Reserved (0) Reserved (0)
Not Used
Reserved (0) Reserved (0)
20AD
Not Used
Interrupts and WD Timer:
INTBITS
WD_RST
INT6
INT5
INT4
INT3
INT2
INT1
INT0
SFR F8
IFLAGS
IE_WAKE
IE_PB
IE_FWCOL1 IE_FWCOL0
IE_RTC
IE_XFER
SFR E8 IE_PLLFALL IE_PLLRISE
Flash Memory:
ERASE
FLSH_ERASE[7:0]
SFR 94
FLSHCTL SFR B2
PREBOOT
SECURE
WRPROT_BT WRPROT_CE
FLSH_MEEN
FLSH_PWE
Not Used
FL_BANK SFR B6
FLBANK[2:0]
Not Used
PGADR
FLSH_PGADR[5:0]
Not Used
SFR B7
70
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
Name
Digital I/O:
Addr
Data Sheet 71M6531D/F-71M6532D/F
Bit 7
Bit 6
DIO7
DIO8
DIO9
DIO10
20AF
2008
2009
200A
200B
200C
200D
200E
200F
SFR 80
SFR A2
SFR 90
SFR 91
DIO11
SFR A0
DIO12
SFR A1 DIO_DIR2[7] ‡
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
DIO6
DIO13
SFR B0
Real Time Clock:
RTCCTRL
2010
RTCA_ADJ
2011
SUBSEC1
2014
RTC0
2015
RTC1
2016
RTC2
2017
RTC3
2018
RTC4
2019
RTC5
201A
RTC6
201B
RTCADJ_H 201C
RTCADJ_M 201D
RTCADJ_L
201E
WE
201F
v1.2
Bit 5
Bit 4
Bit 3
Bit 2
Not Used
DIO_EEX[1:0]
OPT_RXDIS
OPT_RXINV
DIO_PW
DIO_R1[2:0]†
Not Used
Not Used
Not Used
Not Used
Not Used
DIO_R5[2:0]
Not Used
Not Used
DIO_R7[2:0]
Not Used
Not Used
DIO_R9[2:0]
Not Used
Not Used
DIO_R11[2:0]
Not Used
Not Used
DIO_PX
Reserved(0) Reserved (0)
Not Used
DIO_0[7:1]
DIO_DIR0[7:1]
DIO_1[7:0] (Port 1)
DIO_DIR1[7:0]
DIO_2[7]‡
Reserved(0)
DIO_PV
DIO_PY
DIO_2[6]‡
DIO_2[5]‡
DIO_2[4] ‡
DIO_2[3] ‡
DIO_2[2] ‡
DIO_DIR2[6]
DIO_DIR2[5]
DIO_DIR2[4]
DIO_DIR2[3]
DIO_DIR2[2]
‡
‡
‡
‡
‡
DIO_3[6]‡
DIO_3[5]
DIO_3[4]†
DIO_3[3] ‡
DIO_3[2] ‡
Bit 1
Bit 0
DIO_RRX[2:0]
OPT_TXMOD OPT_TXINV
DI_RPB[2:0]
DIO_R2[2:0]
DIO_R4[2:0]
DIO_R6[2:0]
DIO_R8[2:0]
DIO_R10[2:0]
Not Used
DIO_0[0]†
DIO_DIR0[0]†
DIO_2[1]
DIO_2[0]‡
DIO_DIR2[1]
DIO_DIR2[0] ‡
DIO_3[1] ‡
DIO_3[0] ‡
Not Used
Not Used
RST_SUBSEC
RTCA_ADJ[6:0]
SUBSEC[7:0]
RTC_SEC[5:0]
RTC_MIN[5:0]
RTC_HR[4:0]
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
RTC_DAY[2:0]
RTC_DATE[2:0]
RTC_MO[3:0]
RTC_YR[7:0]
Not Used
PREG[16:14]
PREG[13:6]
PREG[5:0]
RTC write protect register
© 2005-2009 TERIDIAN Semiconductor Corporation
QREG[1:0]
71
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
Name
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LCD Display Interface:
MUX_SYNC_E
LCDX
BME
Reserved (0) Reserved (0)
Not Used
2020
LCDY
LCD_Y
LCD_E
LCD_MODE[2:0]
LCD_CLK[1:0]
Not Used
2021
LCD_MAP0 2023
LCD_BITMAP[31:24]
LCD_MAP1 2024
LCD_BITMAP LCD_BITMAP LCD_BITMAP LCD_BITMAP LCD_BITMAP LCD_BITMAP LCD_BITMAP LCD_BITMAP
[39]‡
[38]‡
[37]
[36]‡
[35]
[34]
[33]
[32]
LCD_MAP2 2025
LCD_BITMAP[47:40]‡
LCD_MAP3 2026
LCD_BITMAP LCD_BITMAP LCD_BITMAP
Not Used
[50]‡
[49]
[48]†
LCD_MAP4 2027
LCD_BITMAP LCD_BITMAP LCD_BITMAP LCD_BITMAP
Not Used
[63]
[62]‡
[61]‡
[60]‡
LCD_MAP5 2028
LCD_BITMAP LCD_BITMAP LCD_BITMAP LCD_BITMAP LCD_BITMAP LCD_BITMAP LCD_BITMAP LCD_BITMAP
[71]‡
[70]‡
[69]‡
[68]‡
[67]‡
[66]†
[65]
[64]
LCD_MAP6 2029
Not Used
LCD0
LCD_SEG42[3:0]‡
LCD_SEG0[3:0]
2030
2031
LCD1
LCD_SEG43[3:0]‡
LCD_SEG1[3:0]
2032
LCD2
LCD_SEG2[3:0]
Not Used
2033
LCD3
LCD_SEG45[3:0]‡
LCD_SEG3[3:0]
2034
LCD4
LCD_SEG46[3:0]‡
LCD_SEG4[3:0]
LCD5
LCD_SEG47[3:0]‡
LCD_SEG5[3:0]
2035
LCD6
LCD_SEG48[3:0]†
LCD_SEG6[3:0]†
2036
LCD7
LCD_SEG49[3:0]
LCD_SEG7[3:0]
2037
LCD8
LCD_SEG50[3:0]‡
LCD_SEG8[3:0]
2038
LCD9
2039
LCD_SEG9[3:0]
Not Used
…
…
…
…
LCD17
LCD_SEG17[3:0]
Not Used
2041
LCD18
LCD_SEG60[3:0]‡
LCD_SEG18[3:0]
2042
LCD19
LCD_SEG61[3:0]‡
LCD_SEG19[3:0]
2043
LCD20
LCD_SEG62[3:0]‡
LCD_SEG20[3:0]‡
2044
LCD21
LCD_SEG63[3:0]
LCD_SEG21[3:0]‡
2045
LCD22
LCD_SEG64[3:0]
LCD_SEG22[3:0]‡
2046
LCD23
LCD_SEG65[3:0]
LCD_SEG23[3:0]‡
2047
LCD24
LCD_SEG66[3:0]†
LCD_SEG24[3:0]
2048
LCD25
LCD_SEG67[3:0]‡
LCD_SEG25[3:0]
2049
LCD26
204A
LCD_SEG68[3:0]‡
LCD_SEG26[3:0]
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v1.2
FDS 6531/6532 005
Name
Addr
LCD27
204B
LCD28
204C
LCD29
204D
LCD30
204E
…
…
LCD33
2053
LCD36
2054
LCD37
2055
LCD38
2056
…
…
LCD41
2059
LCD_BLNK 205A
RTM:
RTM0H
2060
RTM0L
2061
RTM1H
2062
RTM1L
2063
RTM2H
2064
RTM2L
2065
RTM3H
2066
RTM3L
2067
SPI Interface:
SPI…
2070
SP_CMD
2071
SP_ADH
2072
SP_ADL
2073
Pulse Generator:
PLS_W
2080
PLS_I
2081
v1.2
Data Sheet 71M6531D/F-71M6532D/F
Bit 7
Bit 6
Bit 5
LCD_SEG69[3:0]‡
LCD_SEG70[3:0]‡
LCD_SEG71[3:0]‡
Not Used
…
Not Used
Not Used
Not Used
Not Used
…
Not Used
LCD_BLKMAP19[3:0]
Bit 4
Bit 3
Not Used
Bit 2
Bit 1
LCD_SEG27[3:0]†
LCD_SEG28[3:0]
LCD_SEG29[3:0]
LCD_SEG30[3:0]
…
LCD_SEG35[3:0]
LCD_SEG36[3:0]‡
LCD_SEG37[3:0]
LCD_SEG38[3:0]‡
…
LCD_SEG41[3:0]‡
LCD_BLKMAP18[3:0]
Bit 0
RTM0[9:8]
RTM0[7:0]
Not Used
RTM1[9:8]
RTM1[7:0]
Not Used
RTM2[9:8]
RTM2[7:0]
Not Used
RTM3[9:8]
RTM3[7:0]
SPE
Not Used
SP_CMD[7:0]
SP_ADDR[15:8]
SP_ADDR[7:0]
PLS_MAXWIDTH[7:0]
PLS_INTERVAL[7:0]
© 2005-2009 TERIDIAN Semiconductor Corporation
73
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
ADC MUX:
SLOT0
SLOT1_SEL
2090
SLOT1
SLOT3_SEL
2091
SLOT2
2092
Reserved
SLOT3
Reserved
2093
SLOT4
2094
Reserved
SLOT5
SLOT1_ALTSEL
2096
SLOT6
SLOT3_ALTSEL
2097
SLOT7
2098
Reserved
SLOT8
2099
Reserved
SLOT9
Reserved
209A
SPI Interrupt:
SPI0
20B0
Not Used
SPI1
20B1
Not Used
General-Purpose Nonvolatile Registers:
GP0
20C0
…
…
GP7
20C7
VERSION 20C8
Serial EEPROM:
EEDATA
SFR 9E
EECTRL
SFR 9F
† 71M6531D/F only
SLOT0_SEL
SLOT2_SEL
Reserved
Reserved
Reserved
SLOT0_ALTSEL
SLOT2_ALTSEL
Reserved
Reserved
Reserved
IEN_SPI
SPI_FLAG
Not Used
Not Used
IEN_WD_NROVF
WD_NROVF_FLAG
GPO[7:0]
…
GP7[7:0]
VERSION[7:0]
EEDATA[7:0]
EECTRL[7:0]
‡ 71M6532D/F only
74
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
4.2
Data Sheet 71M6531D/F-71M6532D/F
I/O RAM Description – Alphabetical Order
The following conventions apply to the descriptions in this table:
•
•
•
•
Bits with a W (write) direction are written by the MPU into configuration RAM. Typically, they are initially stored in flash memory and copied to
the configuration RAM by the MPU. Some of the more frequently programmed bits are mapped to the MPU SFR memory space. The remaining bits are mapped to 2xxx.
Bits with a R (read) direction can be read by the MPU.
Columns labeled Reset and Wake describe the bit values upon reset and wake, respectively. “NV” in the Wake column means the bit is powered by the nonvolatile supply and is not initialized. LCD-related registers labeled “L” retain data upon transition from LCD mode to
BROWNOUT mode and vice versa, but do not retain data in SLEEP mode. “–“ means that the value is undefined.
Write-only bits will return zero when they are read.
Table 49: I/O RAM Description - Alphabetical
Name
ADC_E
BME
Location
2005[3]
2020[6]
Reset
0
0
Wake
0
–
Dir
R/W
R/W
BOOT_SIZE[7:0]
20A7[7:0]
01
01
R/W
CE10MHZ
2000[3]
0
0
R/W
CE_E
CE_LCTN[7:0]
CHOP_E[1:0]
2000[4]
20A8[4:0]
2002[5:4]
0
31
0
0
31
0
R/W
R/W
R/W
CHOP_IA*
20AC[0]
0
0
R/W
CHOP_IB*
20AC[4]
0
0
R/W
CHOP_I_E*
20AB[0]
0
0
R/W
v1.2
Description
Enables ADC and VREF. When disabled, removes bias current.
Battery Measure Enable. When set, a load current is immediately applied to the battery and it is connected to the ADC to be measured on Alternative Mux Cycles. See
the MUX_ALT bit.
End of space reserved for boot program. The ending address of the boot region is
1024*BOOT_SIZE.
CE clock select. When set, the CE is clocked at 10 MHz. Otherwise, the CE clock
frequency is 5 MHz.
CE enable.
CE program location. The starting address for the CE program is 1024*CE_LCTN.
Chop enable for the reference bandgap circuit. The value of CHOP will change on the
rising edge of MUXSYNC according to the value in CHOP_E:
00 = toggle, except at the mux sync edge at the end of SUMCYCLE, an alternative
MUX frame is automatically inserted at the end of each accumulation interval.
01 = positive.
10 = reversed.
11 = toggle, no alternative MUX frame is inserted
This bit enables chop mode for the IA current channel (71M6532D/F only). CHOP_I_E
must be set also.
This bit enables chop mode for the IB current channel (71M6532D/F only). CHOP_I_E
must be set also.
This bit must be set to enable chop mode for the current channels (71M6532D/F only).
© 2005-2009 TERIDIAN Semiconductor Corporation
75
Data Sheet 71M6531D/F-71M6532D/F
Name
CKOUT_E
Location
2004[4]
COMP_STAT[0]
FDS 6531/6532 005
Reset
0
Wake
0
Dir
R/W
2003[0]
–
–
R
DI_RPB[2:0]
DIO_R1[2:0]
DIO_R2[2:0]
DIO_R4[2:0]
DIO_R5[2:0]
DIO_R6[2:0]
DIO_R7[2:0]
DIO_R8[2:0]
DIO_R9[2:0]
DIO_R10[2:0]
DIO_R11[2:0]
DIO_RRX[2:0]
2009[2:0]
2009[6:4]
200A[2:0]
200B[2:0]
200B[6:4]
200C[2:0]
200C[6:4]
200D[2:0]
200D[6:4]
200E[2:0]
200E[6:4]
20AF[2:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
DIO_DIR0[7:1]
SFR A2
[7:1]
0
–
R/W
DIO_DIR1[7:0]
SFR 91
0
–
R/W
DIO_DIR2[1]
SFR A1[1]
0
–
R/W
DIO_0[7:0]
DIO_1[7:0]
DIO_2[1]
DIO_3[5:4]
SFR 80
SFR 90
SFR A0[1]
SFR B0[5:4]
0
0
0
0
–
–
–
–
R/W
R/W
R/W
R/W
76
Description
Control bit for the SEG19/CKOUT pin:
0: The pin is the SEG19 LCD driver
1: The pin is the CK_FIR output (5 MHz in mission mode, 32 kHz in brownout mode)
Status bit for the V1 comparator (same as V1_OK, see TMUXOUT)
Connects dedicated I/O pins DIO2 and DIO4 through DIO11 as well as input pins PB,
DIO1 and RX to internal resources. If more than one input is connected to the same
resource, the Multiple column in the table below specifies how they are combined.
Resource
Multiple
NONE
–
Reserved
OR
T0 (Counter /Timer 0 clock or gate)
OR
T1 (Counter /Timer 1 clock or gate)
OR
High priority IO interrupt (int0 rising)
OR
Low priority IO interrupt (int1 rising)
OR
High priority IO interrupt (int0 fall110
OR
ing)
111
Low priority IO interrupt (int1 falling)
OR
Programs the direction of DIO pins 7 through 1. 1 indicates an output. The bits are
ignored if the pin is not configured as DIO. See DIO_PV and DIO_PW for special options for DIO6 and DIO7. See DIO_EEX for special options for DIO4 and DIO5.
Programs the direction of DIO pins 15 through 8. 1 indicates an output. The bits are
ignored if the pin is not configured as I/O. See DIO_PX and DIO_PW for special options for the DIO8 and DIO9 outputs.
Programs the direction of DIO17.
DIO_Rx[2:0]
000
001
010
011
100
101
The value on the DIO pins. Pins configured as LCD will read zero. When written, changes
data on pins configured as outputs. Pins configured as LCD or input will ignore writes.
DIO_0[7:1] corresponds to DIO7 through DIO1. PB is read on DIO_0[0].
DIO_1[7:0] corresponds to DIO15 through DIO8.
DIO_2[1] corresponds to DIO17.
DIO_3[5:4] corresponds to DIO28 and DIO29.
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
Name
DIO_EEX[1:0]
Location
2008[7:6]
Data Sheet 71M6531D/F-71M6532D/F
Reset
0
Wake
0
Dir
R/W
Description
When set, converts DIO4 and DIO5 to interface with external EEPROM. DIO4 becomes SDCK and DIO5 becomes bi-directional SDATA.
DIO_EEX[1:0]
00
01
10
11
DIO_PV
DIO_PW
DIO_PX
DIO_PY
EEDATA[7:0]
EECTRL[7:0]
ECK_DIS
2008[2]
2008[3]
200F[3]
200F[2]
SFR 9E
SFR 9F
2005[5]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Disable EEPROM interface
2-Wire EEPROM interface
3-Wire EEPROM interface
not used
Causes VARPULSE to be output on DIO7.
Causes WPULSE to be output on DIO6.
Causes XPULSE to be output on DIO8.
Causes YPULSE to be output on DIO9.
Serial EEPROM interface data.
Serial EEPROM interface control.
Emulator clock disable. When ECK_DIS = 1, the emulator clock is disabled.
If ECK_DIS is set, the emulator and programming devices will be unable to
erase or program the device.
EQU[2:0]
EX_XFR
EX_RTC
EX_FWCOL
EX_PLL
FIR_LEN[1:0]
2000[7:5]
2002[0]
2002[1]
2007[4]
2007[5]
2007[3:2]
0
0
0
0
0
1
0
0
0
0
0
1
R/W
R/W
Specifies the power equation to be used by the CE.
Interrupt enable bits. These bits enable the XFER_BUSY, the RTC_1SEC, the FirmWareCollision (FWCOL) and PLL interrupts. Note that if one of these interrupts is to
be enabled, its corresponding MPU EX enable must also be set. See Section 1.4.9
Interrupts for details.
R/W
FIR_LEN[1:0] controls the length of the ADC decimation FIR filter and therefore controls the time taken for each conversion.
Resulting FIR
Resulting
Resulting
Filter Cycles
CK32 Cycles DC Gain
[00], [10], or [11]
00
138
1
0.110017
01
288
2
1.000
10
384
3
2.37037
[01]
00
186
1
0.113644
01
384
2
1.000
10
588
3
3.590363
Flash bank. Memory above 32 KB is mapped to the MPU address space from 0x8000
to 0xFFFF in 32 KB banks. When MPU address[15] = 1, the address in flash is
mapped to FL_BANK[2:0], MPU Address[14:0]. FL_BANK is reset by the erase cycle.
[M40MHZ, M26MHZ]
FL_BANK[2:0]
v1.2
SFR B6[2:0]
1
1
R/W
FIR_LEN
© 2005-2009 TERIDIAN Semiconductor Corporation
77
Data Sheet 71M6531D/F-71M6532D/F
Name
FLSH_ERASE
[7:0]
Location
SFR 94[7:0]
FLSH_MEEN
FDS 6531/6532 005
Reset
0
Wake
0
Dir
W
SFR B2[1]
0
0
W
FLSH_PGADR
[5:0]
SFR B7 [7:2]
0
0
W
FLSH_PWE
SFR B2[0]
0
0
R/W
GP0
…
GP7
IE_FWCOL0
IE_FWCOL1
IE_PB
20C0
…
20C7
SFR E8[2]
SFR E8[3]
SFR E8[4]
0
…
0
0
0
0
NV
…
NV
0
0
–
R/W
R/W
R/W
R/W
IE_PLLRISE
SFR E8[6]
0
0
R/W
IE_PLLFALL
SFR E8[7]
0
0
R/W
IEN_SPI
20B0[4]
0
–
R/W
78
Description
Flash Erase Initiate. (Default = 0x00). FLSH_ERASE is used to initiate either the Flash
Mass Erase cycle or the Flash Page Erase cycle. Specific patterns are expected for
FLSH_ERASE in order to initiate the appropriate Erase cycle.
0x55 = Initiate Flash Page Erase cycle. Must be proceeded by a write to
FLSH_PGADR @ SFR 0xB7.
0xAA = Initiate Flash Mass Erase cycle. Must be proceeded by a write to
FLSH_MEEN @ SFR 0xB2 and the debug (CC) port must be enabled.
Any other pattern written to FLSH_ERASE will have no effect. The erase cycle is not
completed until 0x00 is written to FLSH_ERASE.
Mass Erase Enable.
0 = Mass Erase disabled (default).
1 = Mass Erase enabled.
Must be re-written for each new Mass Erase cycle.
Flash Page Erase Address. (Default = 0x00)
FLSH_PGADR[5:0] with FL_BANK[2:0], sets the Flash Page Address (page 0 through
127) that will be erased during the Page Erase cycle.
Must be re-written for each new Page Erase cycle.
Program Write Enable. This bit must be cleared by the MPU after each byte write operation. Write operations to this bit are inhibited when interrupts are enabled.
0 = MOVX commands refer to XRAM Space, normal operation (default).
1 = MOVX @DPTR,A moves A to Program Space (Flash) @ DPTR.
Non-volatile general-purpose registers powered by the RTC supply. These registers
maintain their value in all power modes, but will be cleared on reset. The values of
GP0…GP7 will be undefined if VBAT drops below the minimum value.
Interrupt flags for Firmware Collision Interrupt. See the Flash Memory section for details.
PB flag. Indicates that a rising edge occurred on PB. Firmware must write a zero to
this bit to clear it. The bit is also cleared when the MPU requests SLEEP or LCD
mode. On bootup, the MPU can read this bit to determine if the part was woken with
the PB (DIO0[0]).
Indicates that the MPU was woken or interrupted (INT4) by system power becoming
available, or more precisely, by PLL_OK rising. The firmware must write a zero to this
bit to clear it.
Indicates that the MPU has entered BROWNOUT mode because system power has
become unavailable (INT4), or more precisely, because PLL_OK fell. This bit will not
be set if the part wakes into BROWNOUT mode because of PB or the WAKE timer.
The firmware must write a zero to this bit to clear it.
SPI interrupt enable.
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
Name
IEN_WD_NROVF
IE_XFER
IE_RTC
IE_WAKE
Location
20B0[0]
SFR E8[0]
SFR E8[1]
SFR E8[5]
INTBITS
Data Sheet 71M6531D/F-71M6532D/F
Reset
0
0
0
0
Wake
0
0
0
–
SFR
F8[6:0]
–
–
R/W
LCD_BITMAP
[31:24]
2023
0
L
R/W
LCD_BITMAP
[39:32]
2024
0
L
R/W
LCD_BITMAP
[55:48]
2026
0
L
R/W
LCD_BITMAP
[63:56]
2027
0
L
R/W
LCD_BITMAP
[71:64]
2028
0
L
R/W
0
L
R/W
0
L
R/W
LCD_BLKMAP19 205A[7:4]
[3:0]
LCD_BLKMAP18 205A[3:0]
[3:0]
LCD_CLK[1:0]
2021[1:0]
v1.2
Dir
R/W
R/W
R/W
Description
Active high watchdog near overflow interrupt enable.
Interrupt flags. These flags monitor the XFER_BUSY interrupt and the RTC_1SEC
interrupt. The flags are set by hardware and clear automatically.
Indicates that the MPU was awakened by the autowake timer. This bit is typically read
by the MPU on bootup. The firmware must write a zero to this bit to clear it.
Interrupt inputs. The MPU may read these bits to see the status of external interrupts
INT0, INT1 up to INT6. These bits do not have any memory and are primarily intended
for debug use.
Configuration for DIO11/SEG31 through DIO4/SEG24. Unused bits should be set to zero.
1 = LCD pin, 0 = DIO pin. Check Table 48 for bit availability.
Bitmap of DIO19/SEG39 through DIO12/SEG32. Unused bits should be set to zero.
1 = LCD pin, 0 = DIO pin. Check Table 48 for bit availability.
Bitmap of DIO28/SEG48 through DIO35/SEG55. Unused bits should be set to zero.
1 = LCD pin, 0 = DIO pin. Check Table 48 for bit availability.
Bitmap of DIO36/SEG56 through DIO43/SEG63. Unused bits should be set to zero.
1 = LCD pin, 0 = DIO pin. Check Table 48 for bit availability.
Bitmap of DIO44/SEG64 through DIO51/SEG71. Unused bits should be set to zero.
1 = LCD pin, 0 = DIO pin. Check Table 48 for bit availability.
Identifies which segments connected to SEG18 and SEG19 should blink. 1 means
blink. The most significant bit corresponds to COM3, the least significant bit to COM0.
Sets the LCD clock frequency for COM/SEG pins (not frame rate) according to the following (fw = 32768 Hz):
00 = fw/29
01 = fw/28
10 = fw/27
11 = fw/26
© 2005-2009 TERIDIAN Semiconductor Corporation
79
Data Sheet 71M6531D/F-71M6532D/F
Name
LCD_DAC[2:0]
Location
20AB[3:1]
Reset
0
FDS 6531/6532 005
Wake
L
Dir
R/W
Description
LCD contrast control DAC. Adjusts the LCD voltage in steps of 0.2 V from V3P3SYS
(mission mode) or VBAT (brownout/LCD modes).
LCD_DAC[2:0]
000
001
010
011
100
101
110
111
LCD_E
2021[5]
LCD_MODE[2:0] 2021[4:2]
0
L
R/W
0
L
R/W
Resulting LCD Voltage
V3P3 or VBAT
V3P3 or VBAT – 0.2V
V3P3 or VBAT – 0.4V
V3P3 or VBAT – 0.6V
V3P3 or VBAT – 0.8V
V3P3 or VBAT – 1.0V
V3P3 or VBAT – 1.2V
V3P3 or VBAT – 1.4V
Enables the LCD display. When disabled, VLC2, VLC1 and VLC0 are ground as are
the COM and SEG outputs.
The LCD bias mode. Use the LCD DAC in ANACTRL to reduce saturation. The number of states is the number of commons which are driven to multiplex the LCD.
LCD_MODE[2:0]
Function
Notes
000
4 states, ⅓ bias
⅓ bias modes can drive 3.3 V LCDs.
001
3 states, ⅓ bias
010
2 states, ½ bias
½ bias and static modes can drive
both 3.3 V and 5 V LCDs.
011
3 states, ½ bias
100
static display
Puts the part to sleep, but with the LCD display still active. LCD_ONLY is ignored if
system power is present. While in SLEEP mode, the device will wake up on reset,
when the autowake timer times out, when the push button is pushed, or when system
power returns.
LCD Segment Data. Each word contains information for 1 to 4 time divisions of each
segment. Some addresses are used to address two segments.
LCD_ONLY
20A9[5]
0
0
W
LCD_SEG0[3:0]
…
LCD_SEG19[3:0]
LCD_SEG24[3:0]
…
LCD_SEG31[3:0]
2030[3:0]
…
2043[3:0]
0
…
0
R/W
…
R/W
2048[3:0]
…
204F[3:0]
0
…
0
L
…
L
L
…
L
R/W
…
R/W
In each word, bit 0 corresponds to COM0, bit 1 to COM1, bit 2 to COM2 and bit 3 to
COM3 of the first segment. Bits 4 through 7 correspond to COM0 to COM3, respectively, of the second segment.
LCD_SEG32[3:0] 2050[3:0]
0
L
R/W
Care should be taken when writing to LCD_SEG locations since some of them control
DIO pins.
80
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
Name
LCD_SEG33[3:0]
…
LCD_SEG35[3:0]
LCD_SEG37[3:0]
LCD_SEG39[3:0]
…
LCD_SEG41[3:0]
Data Sheet 71M6531D/F-71M6532D/F
LCD_SEG48[7:4]
…
LCD_SEG49[7:4]
Location
2051[3:0]
…
2053[3:0]
2055[3:0]
2057[3:0]
…
2059[3:0]
2036[7:4]
…
2037[7:4]
LCD_SEG63[7:4]
…
LCD_SEG66[7:4]
2045[7:4]
…
2048[7:4]
LCD_SEG71[7:4]
…
LCD_SEG73[7:4]
204D[7:4]
…
204F[7:4]
LCD_Y
2021[6]
Reset
0
…
0
0
0
…
0
0
…
0
0
…
0
0
…
0
0
Wake
L
…
L
L
L
…
L
L
…
L
L
…
L
L
…
L
L
Dir
R/W
…
R/W
R/W
R/W
…
R/W
M26MHZ
M40MHZ
2005[4]
2005[0]
0
0
0
0
R/W
R/W
MPU_DIV[2:0]
2004[2:0]
0
0
R/W
Description
R/W
…
R/W
R/W
…
R/W
R/W
…
R/W
R/W
LCD Blink Frequency (ignored if blink is disabled or if the segment is off).
0 = 1 Hz (500 ms ON, 500 ms OFF)
1 = 0.5 Hz (1 s ON, 1 s OFF)
M26MHZ and M40MHZ set the master clock (MCK) frequency. These bits are reset on
chip reset and may only be set. Attempts to write zeroes to M40MHZ and M26MHZ.are
ignored.
The MPU clock divider (from MCK). These bits may be programmed by MPU without
risk of losing control.
MPU_DIV[2:0]
000
001
010
011
100
101
110
111
v1.2
Resulting Clock Frequency
MCK/22
MCK/23
MCK/24
MCK/25
MCK/26
MCK/27
MCK/28
MCK/28
© 2005-2009 TERIDIAN Semiconductor Corporation
81
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
Name
MUX_ALT
Location
2005[2]
Reset
0
Wake
0
Dir
R/W
MUX_DIV[3:0]
MUX_SYNC_E
OPT_FDC[1:0]
209D[3:0]
2020[7]
2007[1:0]
0
0
0
0
0
0
R/W
R/W
R/W
Description
The MPU asserts this bit when it wishes the MUX to perform ADC conversions on an
alternate set of inputs.
If CHOP_E is 00, MUX_ALT is automatically asserted once per sumcycle, when
XFER_BUSY falls.
The number of states in the input multiplexer.
When set, SEG7 outputs MUX_SYNC. Otherwise, SEG7 is an LCD pin.
Selects the modulation duty cycle for OPT_TX.
OPT_FDC[1:0]
00
01
10
11
Function
50% Low
25% Low
12.5% Low
6.25% Low
OPT_RXDIS
2008[5]
0
0
R/W
Configures OPT_RX to an analog input to the optical UART comparator or as a digital
input/output, DIO1: 0 = OPT_RX, 1 = DIO1.
OPT_RXINV
2008[4]
0
0
R/W
OPT_TXE[1:0]
2007[7:6]
00
00
R/W
Inverts the result from the OPT_RX comparator when 1. Affects only the UART input.
Has no effect when OPT_RX is used as a DIO input.
Configures the OPT_TX output pin.
OPT_TXE[1:0]
00
01
10
11
OPT_TXINV
OPT_TXMOD
2008[0]
2008[1]
PLL_OK
2003[6]
PLS_MAXWIDTH 2080[7:0]
[7:0]
PLS_INTERVAL
[7:0]
82
2081[7:0]
0
0
0
0
R/W
R/W
0
FF
0
FF
R
R/W
0
0
R/W
Function
OPT_TX
DIO2
WPULSE
RPULSE
Inverts OPT_TX when 1. This inversion occurs before modulation.
Enables modulation of OPT_TX. When OPT_TXMOD is set, OPT_TX is modulated
when it would otherwise have been zero. The modulation is applied after any inversion caused by OPT_TXINV.
Indicates that system power is present and the clock generation PLL is settled.
Determines the maximum width of the pulse (low going pulse).
The maximum pulse width is (2*PLS_MAXWIDTH + 1)*TI. Where TI is PLS_INTERVAL.
If PLS_INTERVAL = 0, TI is the sample time (397 µs). If set to 255, pulse width control
is disabled and pulses are output with a 50% duty cycle.
For PULSE_W and PULSE_V only: If the FIFO is used, PLS_INTERVAL must be set to
81. If PLS_INTERVAL = 0, the FIFO is not used and pulses are output as soon as the
CE issues them.
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
Name
PLS_INV
Location
2004[6]
Reset
0
Wake
0
Dir
R/W
PREBOOT
SFRB2[7]
–
–
R
PREG[16:0]
201C[2:0]
201D[7:0]
201E[7:2]
4
0
0
4
0
0
R/W
R/W
R/W
PRE_SAMPS[1:0] 2001[7:6]
0
0
R/W
Description
Inverts the polarity of the pulse outputs. Normally, these pulses are active low. When
inverted, they become active high.
Indicates that the preboot sequence is active.
RTC adjust. See Section 1.5.3 Real-Time Clock (RTC) for additional details.
0x0FFBF ≤ PREG[16:0] ≤ 0x10040
PREG[16:0] and QREG[1:0] are separate in hardware but can be programmed with a
single number calculated by the MPU.
The duration of the pre-summer, in samples.
PRE_SAMPS[1:0]
00
01
10
11
QREG[1:0]
RST_SUBSEC
RTCA_ADJ[6:0]
RTC_SEC[5:0
RTC_MIN[5:0]
RTC_HR[4:0]
RTC_DAY[2:0]
RTC_DATE[4:0]
RTC_MO[3:0]
RTC_YR[7:0]
201E[1:0]
2010[0]
2011[6:0]
2015
2016
2017
2018
2019
201A
201B
0
0
40
*
*
*
*
*
*
*
0
0
–
NV
NV
NV
NV
NV
NV
NV
R/W
R/W
R/W
R/W
RTM_E
RTM0[7:0]
2002[3]
2060[9:8]
2061[7:0]
2062[9:8]
2063[7:0]
2064[9:8]
2064[7:0]
2065[9:8]
2066[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
RTM1[7:0]
RTM2[7:0]
RTM3[7:0]
v1.2
Pre-summer Duration
42
50
84
100
RTC adjust. See Section 1.5.3 Real-Time Clock (RTC) for additional details.
The sub-second counter is restarted when a 1 is written to this bit.
Analog RTC adjust. See Section 1.5.3 Real-Time Clock (RTC) for additional details.
These are the year, month, day, hour, minute and second parameters of the RTC.
Writing to these registers sets the time. Each write operation to one of these registers
must be preceded by a write to 0x201F (WE). Valid values for each parameter are:
SEC: 00 to 59, MIN: 00 to 59, HR: 00 to 23 (00 = Midnight)
DAY: 01 to 07 (01 = Sunday), DATE: 01 to 31, MO: 01 to 12
YR: 00 to 99 (00 and all others divisible by 4 are leap years)
Values in the RTC registers are undefined when the IC powers up without a battery but
are maintained through mission and battery modes when a sufficient voltage is maintained at the VBAT pin.
* no change of value at reset.
Real Time Monitor (RTM) enable. When 0, the RTM output is low.
The four RTM probes. Before each CE code pass, the values of these registers are
serially output on the RTM pin. The RTM registers are ignored when RTM_E = 0.
© 2005-2009 TERIDIAN Semiconductor Corporation
83
Data Sheet 71M6531D/F-71M6532D/F
Name
SECURE
Location
SFRB2[6]
SEL_IAN*
FDS 6531/6532 005
Reset
0
Wake
–
Dir
R/W
20AC[1]
0
0
R/W
SEL_IBN*
20AC[5]
0
0
R/W
SLEEP
20A9[6]
0
0
W
SLOT0_SEL[3:0]
SLOT1_SEL[3:0]
SLOT2_SEL[3:0]
SLOT3_SEL[3:0]
SLOT0_ALTSEL
[3:0]
SLOT1_ALTSEL
[3:0]
SLOT2_ALTSEL
[3:0]
SLOT3_ALTSEL
[3:0]
SP_ADDR[15:8]
SP_ADDR[7:0]
SP_CMD
SPE
SPI_FLAG
2090[3:0]
2090[7:4]
2091[3:0]
2091[7:4]
2096[3:0]
0
1
2
3
A
0
1
2
3
A
R/W
2096[7:4]
1
1
2097[3:0]
2
B
2097[7:4]
3
3
2072[7:0]
2073[7:0]
2071
2070[7]
20B1[4]
0
0
0
0
1
SUBSEC[7:0]
2014[7:0]
SUM_CYCLES
[5:0]
TMUX[4:0]
84
Description
When set, enables security provisions that prevent external reading of the flash memory (zeros will be returned if the flash is read). SECURE should be set during the preboot phase, i.e. while PREBOOT is set. SECURE is cleared when the flash is masserased and when the chip is reset. The bit may only be set, attempts to write zero are
ignored.
When set to 1, selects differential mode for the current input (IAP, IAN). When 0, the
input remains single-ended (71M6532D/F only).
When set to 1, selects differential mode for the current input (IBP, IBN). When 0, the
input remains single-ended (71M6532D/F only).
Puts the 71M6531 into SLEEP mode. This bit is ignored if system power is present.
The 71M6531 will wake when the autowake timer times out, when the push button is
pushed, when system power returns, or when RESET goes high.
Primary multiplexer frame analog input selection. These bits map the selected input,
0-3 to the multiplexer state. The ADC output is always written to the memory location
corresponding to the input, regardless of which multiplexer state an input is mapped to
(see Section 1.2 Analog Front End (AFE)).
R/W
Alternate multiplexer frame analog input selection. Maps the selected input to the multiplexer state.
The additional inputs, 10 and 11 in the alternate frame are:
10 = TEMP
11 = VBAT
0
0
0
0
1
R
R
R
R/W
R/W
SPI Address. 16-bit address from the bus master.
–
–
R
2001[5:0]
0
0
R/W
20AA[4:0]
2
–
R/W
SPI command. 8-bit command from the bus master.
SPI port enable. Enables the SPI interface on pins SEG3 through SEG5.
SPI interrupt flag. The flag is set by the hardware and is cleared by the firmware writing a 0. Firmware using this interrupt should clear the spurious interrupt indication during initialization.
The remaining count, in terms of 1/256 RTC cycles, to the next one second boundary.
SUBSEC may be read by the MPU after the one second interrupt and before reaching
the next one second boundary. Setting RST_SUBSEC will clear SUBSEC.
The number of pre-summer outputs summed in the final summing stage of the CE.
Selects one of 32 signals for TMUXOUT. For details, see Section 1.5.17 Test Ports
(TMUXOUT pin).
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
Name
TRIM[7:0]
TRIMSEL[3:0]
Location
20FF
20FD[3:0]
Data Sheet 71M6531D/F-71M6532D/F
Reset
0
0
Wake
0
0
Dir
R/W
R/W
Description
Contains fuse information, depending on the value written to TRIMSEL[3:0].
Selects the trim fuse to be read with the TRIM register:
TRIMSEL[3:0]
1
VERSION[7:0]
2006
20C8
–
–
–
–
R
R
2004[7]
2004[3]
20A9[7]
WAKE_PRD
20A9[2:0]
WAKE_RES
Purpose
Trim for the magnitude of VREF
The device version index. This word may be read by the firmware to determine the
silicon version.
VERSION[7:0]
0001 0101
VREF_CAL
VREF_DIS
WAKE_ARM
Trim Fuse
TRIMT[7:0]
Silicon Version
A05
0
0
0
0
0
–
R/W
R/W
W
001
–
R/W
Brings VREF to the VREF pad. This feature is disabled when VREF_DIS =1.
Disables the internal voltage reference.
Arm the autowake timer. Writing a 1 to this bit arms the autowake timer and presets it
with the values presently in WAKE_PRD and WAKE_RES. The autowake timer is reset
and disarmed whenever the IC is in MISSION or BROWNOUT mode. The timer must
be armed at least three RTC cycles before the SLEEP or LCD-ONLY mode is commanded.
Sleep time. Time = WAKE_PRD[2:0]*WAKE_RES. Default = 001. Maximum value is 7.
20A9[3]
0
–
R/W
Resolution of WAKE timer: 1 = 1 minute, 0 = 2.5 seconds.
WD_NROVF_
FLAG
WD_RST
20B1[0]
–
0
R/W
SFR F8[7]
0
0
W
WD_OVF
2002[2]
0
0
R/W
WE
201F[7:0]
–
–
W
This flag is set approximately 1 ms before the watchdog timer overflows. It is cleared
by writing a 0 or on the falling edge of WAKE.
WD timer bit. This bit must be accessed with byte operations. Operations possible for
this bit are: Write 0xFF: Resets the WDT.
The WD overflow status bit. This bit is set when the WD timer overflows. It is powered
by the nonvolatile supply and at bootup will indicate if the part is recovering from a WD
overflow or a power fault. This bit should be cleared by the MPU on bootup. It is also
automatically cleared when RESET is high.
An 8-bit value has to be written to this address prior to accessing the RTC registers.
WRPROT_BT
SFR B2[5]
0
0
WRPROT_CE
SFR B2[4]
0
0
v1.2
When set, this bit protects flash addresses from 0 to BOOT_SIZE*1024 from flash page
erase.
When set, this bit protects flash addresses from CE_LCTN*1024 to the end of memory
from flash page erase.
© 2005-2009 TERIDIAN Semiconductor Corporation
85
Data Sheet 71M6531D/F-71M6532D/F
4.3
CE Interface Description
4.3.1
CE Program
FDS 6531/6532 005
The CE performs the precision computations necessary to accurately measure energy. Different code
variations are used for EQU = 0 and EQU = 1 or 2. The computations include offset cancellation, products, product smoothing, product summation, frequency detection, VAR calculation, sag detection, peak
detection and voltage phase measurement. All data computed by the CE is dependent on the selected
meter equation as given by EQU (in I/O RAM). Although EQU = 0 and EQU = 2 have the same element
mapping, the MPU code can use the value of EQU to decide if element 2 is used for tamper detection
(typically done by connecting VB to VA) or as a second independent element.
The CE program is supplied by Teridian as a data image that can be merged with the MPU operational
code for meter applications. Typically, the CE program covers most applications and does not need to be
modified. Other variations of CE code may be available from TERIDIAN. The description in this section
applies to CE code revision CE31A04 (for EQU = 0). Deviations for code revision CE31A03 (for EQU = 1
or 2) are noted where applicable.
4.3.2
CE Data Format
All CE words are 4 bytes. Unless specified otherwise, they are in 32-bit two’s complement format
(-1 = 0xFFFFFFFF). Calibration parameters are defined in flash memory (or external EEPROM) and
must be copied to CE data memory by the MPU before enabling the CE. Internal variables are used in
internal CE calculations. Input variables allow the MPU to control the behavior of the CE code. Output
variables are outputs of the CE calculations. The corresponding MPU address for the most significant
byte is given by 0x0000 + 4 x CE_address and by 0x0003 + 4 x CE_address for the least significant byte.
4.3.3
Constants
Constants used in the CE Data Memory tables are:
•
•
•
•
•
•
•
•
•
FS = 32768 Hz/13 = 2520.62 Hz.
F0 is the fundamental frequency.
IMAX is the external rms current corresponding to 250 mV pk at the inputs IA and IB.
VMAX is the external rms voltage corresponding to 250 mV pk at the VA and VB inputs.
NACC, the accumulation count for energy measurements is PRE_SAMPS*SUM_CYCLES.
The duration of the accumulation interval for energy measurements is PRE_SAMPS*SUM_CYCLES/FS
ln_8 is a gain constant of the current channel, n. Its value is 8 or 1 and is controlled by In_SHUNT.
X is a gain constant of the pulse generators. Its value is determined by PULSE_FAST and PULSE_SLOW.
Voltage LSB for sag detection = VMAX * 7.8798*10-6 V.
The system constants IMAX and VMAX are used by the MPU to convert internal quantities (as used by
the CE) to external, i.e. metering quantities. Their values are determined by the off-chip scaling of the
voltage and current sensors used in an actual meter. The LSB values used in this document relate digital
quantities at the CE or MPU interface to external meter input quantities. For example, if a SAG threshold
of 80 V peak is desired at the meter input, the digital value that should be programmed into SAG_THR
would be 80/SAG_THRLSB, where SAG_THRLSB is the LSB value in the description of SAG_THR.
The parameters EQU, CE_E, PRE_SAMPS and SUM_CYCLES essential to the function of the CE are stored
in I/O RAM (see Section 4.2 I/O RAM Description – Alphabetical Order).
4.3.4
Environment
Before starting the CE using the CE_E bit, the MPU has to establish the proper environment for the CE by
implementing the following steps:
•
•
•
•
•
•
86
Load the CE data into RAM.
Establish the equation to be applied in EQU.
Establish the accumulation period and number of samples in PRE_SAMPS and SUM_CYCLES.
Establish the number of cycles per ADC multiplexer frame (MUX_DIV).
Set PLS_INTERVAL[7:0] to 81.
Select the proper values for FIR_LEN (2) and MUX_DIV (4).
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
•
•
•
Data Sheet 71M6531D/F-71M6532D/F
Apply proper values to SLOTn_SEL and SLOTn_ALTSEL.
Set CHOP_E = 00.
Initialize any MPU interrupts, such as CE_BUSY, XFER_BUSY, or a power failure detection interrupt.
Typically, there are thirteen 32768 Hz cycles per ADC multiplexer frame (see Figure 19). This means that
the product of the number of cycles per frame and the number of conversions per frame must be 12 (allowing for one settling cycle).
During operation, CHOP_E = 00 enables the automatic chopping mode and forces an alternate multiplexer sequence at regular intervals. This enables accurate temperature measurement.
4.3.5
CE Calculations
Table 50: CE EQU Equations and Element Input Mapping
EQU
VA IA (1 element, 2W 1φ)
with tamper detection
VA*(IA-IB)/2
(1 element, 3W 1φ)
VA*IA + VB*IB
(2 element, 4W 2φ)
0
1
2
4.3.6
Watt & VAR Formula
(WSUM/VARSUM)
Element Input Mapping
W0SUM/
VAR0SUM
W1SUM/
VAR1SUM
I0SQSUM
I1SQSUM
VA*IA
VA*IB
IA
IB
VA*(IA-IB)/2
(VA * IB)/2
IA-IB
IB
VA*IA
VB*IB
IA
IB
CE Status and Control
The CESTATUS register provides information about the status of voltage and input AC signal frequency,
which are useful for generating early power fail warnings, e.g. to initiate necessary data storage. It contains sag warning flags for VA and VB as well as F0, the derived clock operating at the fundamental input
frequency. CESTATUS represents the status flags for the preceding CE code pass (CE busy interrupt).
Sag alarms are not remembered from one code pass to the next. The CE Status word is refreshed at
every CE_BUSY interrupt. The significance of the bits in CESTATUS is shown in Table 51.
CE Address
0x80
Name
CESTATUS
Description
See description of CESTATUS bits in Table 51.
Since the CE_BUSY interrupt typically occurs at 2520.6 Hz, it is desirable to minimize the computation
required in the interrupt handler of the MPU. Rather than reading the CE status word at every CE_BUSY
interrupt and interpret the sag bits, it is recommended that the MPU activate the YPULSE output to generate interrupts when a sag occurs (see the description of the CECONFIG register)
Table 51: CESTATUS Bit Definitions
CESTATUS
[bit]
31:29
28
27
26
Not Used
F0
Reserved
SAG_B
25
SAG_A
24:0
Not Used
v1.2
Name
Description
These unused bits will always be zero.
F0 is a square wave at the exact fundamental input frequency.
Normally zero. Becomes one when VB remains below SAG_THR for
SAG_CNT samples. Will not return to zero until VB rises above SAG_THR.
Normally zero. Becomes one when VA remains below SAG_THR for
SAG_CNT samples. Will not return to zero until VA rises above SAG_THR.
These unused bits will always be zero.
© 2005-2009 TERIDIAN Semiconductor Corporation
87
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
The CE is initialized and its functions are controlled by the MPU using CECONFIG. This register contains
in packed form SAG_CNT, FREQSEL, EXT_PULSE, I0_SHUNT, I1_SHUNT, PULSE_SLOW and PULSE_FAST.
The CECONFIG bit definitions are given in Table 52.
CE Address
Name
0x20
CECONFIG
Data
0x5020
Description
See description of the CECONFIG bits in Table 52.
IA_SHUNT and/or IB_SHUNT can configure their respective current inputs to accept shunt resistor sensors. In this case the CE provides an additional gain of 8 to the selected current input. WRATE may need
to be adjusted based on the values of IA_SHUNT and IB_SHUNT. Whenever IA_SHUNT or IB_SHUNT are
set to 1, In_8 (in the equation for Kh) is assigned a value of 8.
The CE pulse generator can be controlled by either the MPU (external) or CE (internal) variables. Control
is by the MPU if EXT_PULSE = 1. In this case, the MPU controls the pulse rate by placing values into
APULSEW, APULSER, APULSE2 and APULSE3. By setting EXT_PULSE = 0, the CE controls the pulse rate
based on W0SUM_X and VAR0SUM_X (EQU = 0) or WSUM_X (EQU = 2).
If EXT_PULSE = 1 and EQU = 2, the pulse inputs are W0SUM_X + W1SUM_X and VAR0SUM_X +
VAR1SUM_X. In this case, creep cannot be controlled since creep is an MPU function.
If EXT_PULSE = 1 and EQU = 0, the pulse inputs are W0SUM_X if I0SQSUM_X > I1SQSUM_X and
W1SUM_X, if I1SQSUM_X > I0SQSUM_X.
The 71M6531 Demo Code creep function halts both internal and external pulse generation.
The EXT_TEMP bit controls the temperature compensation mode:
•
When EXT_TEMP = 0 (internal compensation), the CE will control the gain using GAIN_ADJ (see Table 54)
based on PPMC, PPMC2 and TEMP_X, the difference between die temperature and the reference/calibration temperature TEMP_NOM. Since PPMC and PPMC2 reflect the typical behavior of the
reference voltage over temperature, the internal temperature compensation eliminates the effects of
temperature-related errors of VREF only.
•
When EXT_TEMP = 1 (external compensation), the MPU is allowed to control the CE gain using
GAIN_ADJ, based on any algorithm implemented in MPU code.
The FREQSEL1 and FREQSEL0 bits select the phase used to control the CE-internal PLL. CE accuracy
depends on the channel selected by the FREQSEL1 and FREQSEL0 bits receiving a clean voltage signal.
Table 52: CECONFIG Bit Definitions
CECONFIG
[bit]
[19]
[18]
[17]
Name
Default
SAG_MASK1
SAG_MASK0
SAG_INT
0
0
0
[16]
EXT_TEMP
0
[15:8]
SAG_CNT
80
(0x50)
[7]
[6]
FREQSEL1
FREQSEL0
0
0
88
Description
Sets the sag control of phase B.
Sets the sag control of phase A.
When set, enables the sag interrupt to be output on the
YPULSE pin.
When set, enables the control of GAIN_ADJ by the MPU.
When 0, enables the control of GAIN_ADJ by the CE.
The number of consecutive voltage samples below SAG_THR
before a sag alarm is declared. The maximum value is 255.
SAG_THR is at address 0x24.
Selects the phase to be used for the frequency monitor.
FREQSEL1/FREQSEL0 = 0/0: Phase A
FREQSEL1/FREQSEL0 = 0/1: Phase B
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
[5]
EXT_PULSE
1
[4]
–
0
[3]
IB_SHUNT
0
[2]
[1]
IA_SHUNT
PULSE_FAST
0
0
[0]
PULSE_SLOW
When zero, causes the pulse generators to respond to internal
data (PULSE0 = WSUM_X, PULSE1 = VARSUM_X., PULSE2 =
VASUM_X). Otherwise, the generators respond to values the
MPU places in APULSEW and APULSER.
Unused.
When 1, the current gain of channel B is increased by 8. The
gain factor controlled by In_SHUNT is referred to as In_8
throughout this document.
When 1, the current gain of channel A is increased by 8.
When PULSE_FAST = 1, the pulse generator input is increased
16x. When PULSE_SLOW = 1, the pulse generator input is
reduced by a factor of 64. These two bits control the pulse
gain factor X (see table below). Default is 0 for both (X = 6).
PULSE_SLOW PULSE_FAST
X
0
0
1.5 * 22 = 6
0
1
1.5 * 26 = 96
1
0
1.5 * 2-4 = 0.09375
1
1
Do not use
0
Table 53: Sag Threshold Control
CE Address
Name
Default
Description
0x24
SAG_THR
443000
The threshold for sag warnings. The default value is
equivalent to 80 V RMS if VMAX = 600 V. The LSB value
is VMAX * 4.255*10-7 V (peak).
Table 54: Gain Adjust Control
CE Address
Name
Default
Description
0x40
GAIN_ADJ
16384
This register scales all voltage and current channels. The
default value is equivalent unity gain (1.000).
4.3.7
CE Transfer Variables
When the MPU receives the XFER_BUSY interrupt, it knows that fresh data is available in the transfer
variables. The transfer variables can be categorized as:
1. Fundamental energy measurement variables
2. Instantaneous (RMS) values
3. Other measurement parameters
Fundamental Energy Measurement Variables
Table 55 describes each transfer variable for fundamental energy measurement. All variables are signed
32-bit integers. Accumulated variables such as WSUM are internally scaled so they have at least 2x
margin before overflow when the integration time is one second. Additionally, the hardware will not permit output values to fold back upon overflow.
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
89
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
Table 55: CE Transfer Variables
CE Address
0x85
Name
Description
WSUM_X
0x86
0x87
W0SUM_X
W1SUM_X
0x8A
VARSUM_X
0x8B
0x8C
VAR0SUM_X
VAR1SUM_X
For EQU = 2, this register holds the calculated sum of Wh samples
from each wattmeter element (In_8 is the gain of 1 or 8 configured by
IA_SHUNT or IB_SHUNT).
LSB = 6.6952*10-13 VMAX IMAX / In_8 Wh.
The sum of Wh samples from each wattmeter element (In_8 is the gain
of 1 or 8 configured by IA_SHUNT or IB_SHUNT).
LSB = 6.6952*10-13 VMAX IMAX / In_8 Wh.
For EQU = 2, this register holds the calculated sum of VARh samples
from each element (In_8 is the gain of 1 or 8 configured by IA_SHUNT
or IB_SHUNT).
LSB = 6.6952*10-13 VMAX IMAX / In_8 VARh.
The sum of VARh samples from each element (In_8 is the gain 1 or 8
configured by IA_SHUNT or IB_SHUNT).
LSB = 6.6952*10-13 VMAX IMAX / In_8 VARh.
WxSUM_X is the Wh value accumulated for element X in the last accumulation interval and can be computed based on the specified LSB value.
For example, with VMAX = 600 V and IMAX = 208 A, the LSB for WxSUM_X is 0.08356 µWh.
Instantaneous Measurement Variables
Table 56 contains various measurement results. The Frequency measurement is computed for the phase
selected with FREQSELn bits in the CECONFIG register.
IxSQSUM_X and VxSQSUM are the squared current and voltage samples acquired during the last accumulation interval. They can be used to calculate RMS voltages and currents. INSQSUM_X can be used for
computing the neutral current.
Table 56: CE Energy Measurement Variables
CE Address
0x82
Name
FREQ_X
Description
Fundamental frequency.
LSB ≡
0x8F
90
I0SQSUM_X
0x90
I1SQSUM_X
0x93
V0SQSUM_X
0x94
V1SQSUM_X
0x45
WSUM_ACCUM
0x46
VSUM_ACCUM
0x47
SUM3_ACCUM
0x48
SUM4_ACCUM
0x99
I0SQRES_X
0x9A
I1SQRES_X
FS
≈ 0.587 ⋅ 10 −6 Hz
32
2
The sum of squared current samples from each element.
LSBI = 6.6952*10-13 IMAX2 / In_82 A2h
The sum of squared voltage samples from each element.
LSBV= 6.6952*10-13 VMAX2 V2h
These registers contain roll-over accumulators for WPULSE and
VPULSE respectively.
These registers contain roll-over accumulators for pulse outputs
XPULSE and YPULSE respectively.
These registers hold residual current measurements with doubleprecision accuracy. The exact current is:
ISQn = InSQSUM_X + InSQRES_X
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
The RMS values can be computed by the MPU from the squared current and voltage samples as follows:
Ix RMS =
IxSQSUM ⋅ LSBI ⋅ 3600 ⋅ FS
N ACC
VxRMS =
VxSQSUM ⋅ LSBV ⋅ 3600 ⋅ FS
N ACC
Other Measurement Parameters
Table 57 describes the CE measurement parameters listed below:
•
•
•
•
MAINEDGE_X: Useful for implementing a real-time clock based on the input AC signal. MAINEDGE_X
is the number of half-cycles accounted for in the last accumulated interval for the AC signal.
TEMP_RAW: May be used by the MPU to monitor the chip temperature or to implement temperature
compensation.
GAIN_ADJ: A scaling factor for measurements based on the temperature. GAIN_ADJ can be controlled by the MPU for temperature compensation.
VBAT_SUM_X: This result can be used to calculate the measured battery voltage (VBAT).
Table 57: Useful CE Measurement Parameters
CE Address
0x83
Name
Default
Description
MAINEDGE_X
N/A
0x81
0x9D
TEMP_RAW_X
TEMP_X
N/A
N/A
0x40
GAIN_ADJ
16384
0x84
VBAT_SUM_X
N/A
The number of zero crossings of the voltage selected with
FREQSELn in the previous accumulation interval. Zero
crossings are either direction and are debounced.
The filtered, un-scaled reading from the temperature sensor.
This register contains the difference between the die temperature and the reference/calibration temperature as established in the TEMP_NOM register, measured in 0.1°C.
Scales all voltage and current inputs. A value of 16384 provides unity gain. This register is used by the CE or by the
MPU to implement temperature compensation.
The result of the battery voltage measurement.
4.3.8
Pulse Generation
Table 58 describes the CE pulse generation parameters WRATE, APULSEW, APULSER, APULSE2 and
APULSE3.
WRATE controls the number of pulses that are generated per measured Wh and VARh quantities. The
lower WRATE is the slower the pulse rate for measured energy quantity. The metering constant Kh is derived from WRATE as the amount of energy measured for each pulse. That is, if Kh = 1 Wh/pulse, a power applied to the meter of 120 V and 30 A (3,600 W) results in one pulse per second. If the load is 240 V
at 150 A (36,000 W), ten pulses per second will be generated.
The maximum pulse rate is 7.5 kHz for APULSEW and APULSER and 1.2 kHz for APULSE2 and APULSE3.
The maximum time jitter is 67 µs and is independent of the number of pulses measured. Thus, if the pulse
generator is monitored for one second, the peak jitter is 67 ppm. After 10 seconds, the peak jitter is 6.7 ppm.
The average jitter is always zero. If it is attempted to drive either pulse generator faster than its maximum
rate, it will simply output at its maximum rate without exhibiting any rollover characteristics. The actual
pulse rate, using WSUM as an example, is:
RATE =
WRATE ⋅ WSUM ⋅ FS ⋅ X
Hz ,
2 46
where FS = sampling frequency (2520.6 Hz) and X = Pulse speed factor (as defined in the CECONFIG
register with the PULSE_FAST and PULSE_SLOW bits).
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
91
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
Table 58: CE Pulse Generation Parameters
CE Address
0x21
Name
Default
Description
WRATE
827
0x41
APULSEW
0
0x42
APULSER
0
0x43
APULSE2
0
0x44
APULSE3
0
0x38
PULSE
WIDTH
12
Kh = VMAX*IMAX*47.1132 / (In_8*WRATE*NACC*X) Wh/pulse. The
default value results in a Kh of 1.0 Wh/pulse when 2520 samples
are taken in each accumulation interval (and VMAX=600,
IMAX = 442 [for 400µΩ shunt], In_8 = 1, X = 6).
Maximum value = 215 -1.
Watt pulse generator input (see DIO_PW bit). The output pulse
rate is: APULSEW * FS * 2-32 * WRATE * X * 2-14. This input is buffered and can be loaded during a computation interval. The
change will take effect at the beginning of the next interval.
VAR pulse generator input (see DIO_PV bit). The output pulse rate
is: APULSER * FS*2-32 * WRATE * X * 2-14. This input is buffered and
can be loaded during a computation interval. The change will take
effect at the beginning of the next interval.
Third pulse generator input (see DIO_PV bit). The output pulse
rate is: APULSE2 * FS*2-32 * WRATE * X * 2-14. This input is buffered
and can be loaded during a computation interval. The change will
take effect at the beginning of the next interval.
Fourth pulse generator input (see DIO_PV bit). The output pulse
rate is: APULSE3 * FS*2-32 * WRATE * X * 2-14. This input is buffered
and can be loaded during a computation interval. The change will
take effect at the beginning of the next interval.
Register for pulse width control of XPULSE and YPULSE. The maximum pulse width is (2*PULSEWIDTH+1)*(1/FS). The default value
will generate pulses of 10 ms width at FS = 2520.62 Hz.
4.3.9
CE Calibration Parameters
Table 59 lists the parameters that are typically entered to effect calibration of meter accuracy.
Table 59: CE Calibration Parameters
CE Address
0x10
0x11
0x12
0x13
0x18
Name
Default
Description
CAL_IA
CAL_VA
CAL_IB
CAL_VB
PHADJ_A
16384
16384
16384
16384
0
0x19
PHADJ_B
0
These constants control the gain of their respective channels. The
nominal value for each parameter is 214 = 16384. The gain of
each channel is directly proportional to its gain constant. Thus, if
the gain of the IA channel is 1% slow, CAL_IA should be scaled by
1/(1 – 0.01) and the resulting value is 16549.
These two constants control the CT phase compensation. No compensation occurs when PHADJ_X = 0. As PHADJ_X is increased,
more compensation (lag) is introduced. Range: ± 215 – 1. If it is
desired to delay the current by the angle Φ, the equations are:
0.02229 ⋅ TANΦ
at 60Hz
PHADJ _ X = 2 20
0.1487 − 0.0131 ⋅ TANΦ
0.0155 ⋅ TANΦ
at 50Hz
0.1241 − 0.009695 ⋅ TANΦ
This register contains the anchor or reference point for the temperature measurement. At calibration temperature, the value read
at TEMP_RAW_X should be written to TEMP_NOM. The CE will
calculate the chip temperature TEMP_X relative to the reference
temperature.
The scale factor for the temperature calculation. It is not necessary
to use values other than the default value.
PHADJ _ X = 2 20
92
0x1F
TEMP_NOM
0
0x39
DEGSCALE
9174
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
4.3.10 Other CE Parameters
Table 60 shows the CE parameters used for suppression of noise due to scaling and truncation effects.
The table also includes the parameter which indicates the CE Code version.
Table 60: CE Parameters for Noise Suppression and Code Version
CE Address
0x22
Name
Default
KVAR
6448
0x26
QUANT_A
0
0x27
QUANT_B
0
0x2A
QUANT_VARA
0
0x2B
QUANT_VARB
0
0x2E
QUANT_IA
0
0x2F
QUANT_IB
0
0x35
0x63653331
0x36
0x61303463
0x37
0x00000000
Description
This is the scale factor for the VAR calculation. No value
other than the default value should be applied.
These parameters are added to the Watt calculation for element 0 and 1 to compensate for input noise and truncation.
LSB = (VMAX*IMAX / In_8) *7.4162*10-10 W
These parameters are added to the VAR calculation for element A and B to compensate for input noise and truncation.
LSB = (VMAX*IMAX / In_8) * 7.4162*10-10 W
These parameters are added to compensate for input noise
and truncation in their respective channels in the squaring
calculations for I2 and V2.
LSB = VMAX2*7.4162*10-10 V2 and
LSB = (IMAX2/In_82)*7.4162*10-10 A2
Text strings holding the CE version information as supplied
by the CE data associated with the CE code. For example,
the words 0x63653331 and 0x61303463 form the text string
“ce31a04c”.
These locations are overwritten in operation.
4.3.11 CE Flow Diagrams
Figure 40 through Figure 42 show the data flow through the CE in simplified form. Functions not shown
include delay compensation, sample interpolation, scaling and processing of meter equations.
Figure 40: CE Data Flow: Multiplexer and ADC
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
93
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
Figure 41: CE Data Flow: Scaling, Gain Control, Intermediate Variables
Figure 42: CE Data Flow: Squaring and Summation Stages
94
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
5
Electrical Specifications
5.1
Absolute Maximum Ratings
Table 61 shows the absolute maximum ranges for the device. Stresses beyond Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation
at these or any other conditions beyond those indicated under recommended operating conditions (Section 5.3) is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability. All voltages are with respect to GNDA.
Table 61: Absolute Maximum Ratings
Voltage and Current
Supplies and Ground Pins
V3P3SYS, V3P3A
VBAT
GNDD
Analog Output Pins
V3P3D
VREF
V2P5
Analog Input Pins
IA, VA, IB, VB, V1
−0.5 V to 4.6 V
-0.5 V to 4.6 V
-0.5 V to +0.5 V
-10 mA to 10 mA,
-0.5 V to 4.6 V
-10 mA to +10 mA,
-0.5 V to V3P3A+0.5 V
-10 mA to +10 mA,
-0.5 V to 3.0 V
-10 mA to +10 mA
-0.5 V to V3P3A+0.5 V
-10 mA to +10 mA
-0.5 V to 3.0 V
XIN, XOUT
All Other Pins
Configured as SEG or COM drivers
Configured as Digital Inputs
Configured as Digital Outputs
-1 mA to +1 mA,
-0.5 to V3P3D+0.5
-10 mA to +10 mA,
-0.5 to 6 V
-15 mA to +15 mA,
-0.5 V to V3P3D+0.5 V
All other pins
−0.5 V to V3P3D+0.5 V
Temperature and ESD Stress
Operating junction temperature (peak, 100ms)
Operating junction temperature (continuous)
Storage temperature
140 °C
125 °C
Solder temperature – 10 second duration
ESD stress on all pins
v1.2
−45 °C to +165 °C
250 °C
4 kV
© 2005-2009 TERIDIAN Semiconductor Corporation
95
Data Sheet 71M6531D/F-71M6532D/F
5.2
FDS 6531/6532 005
Recommended External Components
Table 62: Recommended External Components
Name
C1
C2
CSYS
C2P5
From
V3P3A
V3P3D
V3P3SYS
V2P5
AGND
DGND
DGND
DGND
Bypass capacitor for 3.3 V supply
Bypass capacitor for 3.3 V output
Bypass capacitor for V3P3SYS
Bypass capacitor for V2P5
XTAL
XIN
XOUT
CXS
XIN
AGND
CXL
XOUT
AGND
32.768 kHz crystal – electrically similar to
ECS .327-12.5-17X or Vishay XT26T,
load capacitance 12.5 pF
Load capacitor for crystal (depends on
crystal specs and board parasitics).
Load capacitor for crystal (depends on
crystal specs and board parasitics).
To
Function
Value
Unit
≥0.1 ±20%
≥0.1 ±20% †
≥1.0 ±30%
0.1 ±20%
32.768
µF
µF
µF
µF
kHz
33 ±10%
pF
15 ±10%
pF
†
Notes:
1. AGND and DGND should be connected together.
2. V3P3SYS and V3P3A should be connected together.
†
For accuracy and EMI rejection, C1 + C2 should be 470 µF or higher.
5.3
Recommended Operating Conditions
Table 63: Recommended Operating Conditions
Parameter
V3P3SYS, V3P3A: 3.3 V Supply Voltage
V3P3A and V3P3SYS must be at the
same voltage
VBAT
Operating Temperature
96
Condition
Normal Operation
Battery Backup
Min
3.0
0
Typ
3.3
Max
3.6
3.6
Unit
V
V
No Battery
Battery Backup:
BRN and LCD modes
SLEEP mode
Externally Connect to V3P3SYS
3.0
2.0
3.8
3.8
V
V
-40
+85
ºC
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
5.4
Performance Specifications
5.4.1
Input Logic Levels
Table 64: Input Logic Levels
Parameter
Digital high-level input voltagea, VIH
Digital low-level input voltagea, VIL
Input pull-up current, IIL
E_RXTX,
E_RST, CKTEST
Other digital inputs
Input pull down current, IIH
ICE_E
RESET
PB
Other digital inputs
a
Condition
Min
2
Typ
Max
0.8
Unit
V
V
0
100
100
1
µA
µA
µA
0
0
100
100
1
1
µA
µA
µA
µA
VIN=0 V, ICE_E=1
10
10
-1
VIN = V3P3D
10
10
-1
-1
In battery powered modes, digital inputs should be below 0.3 V or above 2.5 V to minimize battery current.
5.4.2
Output Logic Levels
Table 65: Output Logic Levels
Parameter
Digital high-level output voltage VOH
Digital low-level output voltage VOL
OPT_TX VOH (V3P3D-OPT_TX)
OPT_TX VOL
5.4.3
Condition
ILOAD = 1 mA
ILOAD = 15 mA
ILOAD = 1 mA
ILOAD = 15 mA
ISOURCE=1 mA
ISINK=20 mA
Min
V3P3D–0.4
V3P3D-0.6
0
Typ
Max
0.4
0.8
0.4
0.7
Unit
V
V
V
V
V
V
Power-Fault Comparator
Table 66: Power-Fault Comparator Performance Specifications
Parameter
Offset Voltage: V1-VBIAS
Hysteresis Current: V1
Response Time: V1
Condition
Vin = VBIAS – 100 mV
+100 mV overdrive
Voltage at V1 rising
Voltage at V1 falling
WDT Disable Threshold: V1-V3P3A
5.4.4
Min
-20
0.8
Typ
Max
+15
1.2
Unit
mV
μA
8
37
100
100
-10
µs
μs
mV
Typ
45
-48.7
-5.35
-2.26
-19.8
-2.26
-0.63
Max
63
(+10%)
0
+100
Unit
kΩ
μV
μV
μV
μV
μV
μV
mV
10
-400
Battery Monitor
Table 67: Battery Monitor Performance Specifications (BME= 1)
Parameter
Load Resistor
Condition
[M40MHZ, M26MHZ]
= [00], [10], or [11]
LSB Value
Offset Error
v1.2
[M40MHZ, M26MHZ]
= [01]
FIR_LEN=0
FIR_LEN=1
FIR_LEN=2
FIR_LEN=0
FIR_LEN=1
FIR_LEN=2
(L=138)
(L=288)
(L=384)
(L=186)
(L=384)
(L=588)
Min
27
(-10%)
(-10%)
-200
© 2005-2009 TERIDIAN Semiconductor Corporation
(+10%)
97
Data Sheet 71M6531D/F-71M6532D/F
5.4.5
FDS 6531/6532 005
Supply Current
Table 68: Supply Current Performance Specifications
Parameter
V3P3SYS current (CE off)
V3P3SYS current (CE on)
V3P3A current
VBAT current
V3P3SYS current,
Write Flash
VBAT current
5.4.6
Condition
Normal Operation,
V3P3A = V3P3SYS = 3.3 V
CKMPU = 614 kHz
No Flash Memory write
RTM_E=0, ECK_DIS=1,
ADC_E=1, ICE_E=0
Normal Operation as above, except write Flash at maximum rate,
CE_E = 0, ADC_ E = 0
Min
Typ
4.2
Max
6.35
Unit
mA
8.4
9.6
mA
3.3
3.8
mA
+400
nA
9.1
12
mA
52
82
250
250
µA
µA
11
21
0.7
40
46
1.5
µA
µA
µA
Max
15
50
Unit
Ω
Ω
Max
2.7
40
470
Unit
V
mV
mV
+2
mV/V
-400
VBAT=3.6V
BROWNOUT mode
71M6531D/F
71M6532D/F
LCD Mode
LCD DAC off
LCD DAC on
SLEEP Mode
V3P3D Switch
Table 69: V3P3D Switch Performance Specifications
Parameter
On resistance – V3P3SYS to V3P3D
On resistance – VBAT to V3P3D
5.4.7
Condition
| IV3P3D | ≤ 1 mA
| IV3P3D | ≤ 1 mA
Min
Typ
9
32
2.5 V Voltage Regulator
Table 70: 2.5 V Voltage Regulator Performance Specifications
Parameter
V2P5
V2P5 load regulation
Voltage overhead V3P3-V2P5
PSSR ∆V2P5/∆V3P3
5.4.8
Condition
Iload = 0
Iload = 0 mA to 5 mA
Iload = 5 mA, reduce V3P3
until V2P5 drops 200 mV
RESET=0, iload=0
Min
2.3
Typ
2.5
-2
Low-Power Voltage Regulator
Unless otherwise specified, V3P3SYS = V3P3A = 0, PB=GND (BROWNOUT).
Table 71: Low-Power Voltage Regulator Performance Specifications
Parameter
V2P5
V2P5 load regulation
Condition
VBAT voltage requirement
PSRR ΔV2P5/ΔVBAT
98
ILOAD = 0
ILOAD = 0 mA to 1 mA
ILOAD = 1 mA, reduce VBAT
until REG_LP_OK = 0
ILOAD = 0
Min
2.3
-50
© 2005-2009 TERIDIAN Semiconductor Corporation
Typ
2.5
Max
2.7
30
3.0
Unit
V
mV
V
50
mV/V
v1.2
FDS 6531/6532 005
5.4.9
Data Sheet 71M6531D/F-71M6532D/F
Crystal Oscillator
Table 72: Crystal Oscillator Performance Specifications
Parameter
Maximum Output Power to Crystal 4
XIN to XOUT Capacitance 1
Capacitance to DGND 1
XIN
XOUT
Condition
Crystal connected
Min
Typ
Max
1
3
Unit
μW
pF
5
5
pF
pF
Max
+10
Unit
%
RTCA_ADJ = 0
5.4.10 LCD DAC
Table 73: LCD DAC Performance Specifications
Parameter
Condition
VLCD Voltage
1 ≤ LCD_DAC ≤ 7
VLCD = V3P3 ⋅ (1 − 0.059 ⋅ LCD_DAC) − 0.019V
Min
-10
Typ
5.4.11 LCD Drivers
The information in Table 74 applies to all COM and SEG pins with LCD_DAC[2:0] = 000.
Table 74: LCD Driver Performance Specifications
Parameter
VLC2 Voltage
VLC1 Voltage†,
⅓ bias
½ bias
½ bias, minimum output level
VLC0 Voltage,
⅓ bias
VLC1 Impedance
VLC0 Impedance
Condition
With respect to VLCD1
Min
-0.1
Typ
Max
+0.1
Unit
V
With respect to 2*VLC2/3
With respect to VLC2/2
-3
-3
+2
+2
1.0
% VLC2
% VLC2
V
With respect to VLC2/3
∆ILOAD = 100 µA (Isink)
∆ILOAD = -100 µA (Isource)
∆ILOAD = 100 µA (Isink)
∆ILOAD = -100 µA (Isource)
-4
+1
15
15
15
15
%
9
9
9
9
kΩ
kΩ
1
VLCD is V3P3SYS in MISSION mode and VBAT in BROWNOUT and LCD modes.
Specified as percentage of VLC2, the maximum LCD voltage.
†
5.4.12 Optical Interface
Table 75: Optical Interface Performance Specifications
Parameter
OPT_TX VOH (V3P3D-OPT_TX)
OPT_TX VOL
v1.2
Condition
ISOURCE =1 mA
ISINK = 20 mA
Min
© 2005-2009 TERIDIAN Semiconductor Corporation
Typ
Max
0.4
0.7
Unit
V
V
99
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
5.4.13 Temperature Sensor
Table 76 shows the performance for the temperature sensor. The LSB values do not include the 8-bit left
shift at CE input.
Table 76: Temperature Sensor Performance Specifications
Parameter
Condition
Nominal relationship: N(T) = Sn*(T-Tn) + Nn, Tn = 25ºC
Nominal Sensitivity (Sn)4
L
S n = −0.00109 ⋅  
3
FIR_LEN=0
FIR_LEN=1
FIR_LEN=2
(L=138)
(L=288)
(L=384)
[M40MHZ, M26MHZ] =
[01]
FIR_LEN=0
FIR_LEN=1
FIR_LEN=2
(L=186)
(L=384)
(L=588)
FIR_LEN=0
FIR_LEN=1
FIR_LEN=2
FIR_LEN=0
FIR_LEN=1
FIR_LEN=2
(L=138)
(L=288)
(L=384)
(L=186)
(L=384)
(L=588)
3
NominalOffset
(Nn) 4
L
N n = 0.508 ⋅  
3
[M40MHZ, M26MH] =
[00], [10], or [11]
[M40MHZ, M26MHZ] =
[00], [10], or [11]
3
[M40MHZ, M26MHZ] =
[01]
Min
Typ
Max
-106
-964
-2286
-260
-2286
-8207
49447
449446
Unit
LSB/ºC
LSB
1065353
121071
1065353
3825004
Temperature Error 1
Tn = 25°C,
T = -40ºC to +85ºC
 ( N (T ) − N n ) 
ERR = T − 

Sn


-10
10
ºC
Nn is measured at Tn during meter calibration and is stored in MPU or CE for use in temperature calculations.
5.4.14 VREF
Table 77 shows the performance specifications for VREF. Unless otherwise specified, VREF_DIS = 0.
Table 77: VREF Performance Specifications
Parameter
VREF output voltage, VREF(22)
VREF chop step
VREF power supply sensitivity
ΔVREF / ΔV3P3A
VREF input impedance
VREF output impedance
VNOM temperature coefficients:
TC1
TC2
VREF(T) deviation from VNOM(T)
VREF (T ) − VNOM (T )
10 6
VNOM (T )
max( T − 22 ,40)
a
V3P3A = 3.0 to 3.6 V
VREF_DIS = 1,
VREF = 1.3 to 1.7 V
CAL =1,
ILOAD = 10 µA, -10 µA
Min
1.193
Typ
1.195
-1.5
Max
1.197
40
Unit
V
mV
1.5
mV/V
kΩ
100
2.5
VNOM (T ) = VREF (22) + (T − 22)TC1 ⋅ 10 −6 + (T − 22) 2 TC 2 ⋅ 10 −6
VNOM definitiona
VREF aging
Condition
Ta = 22ºC
3.18·(52.46-TRIMT)
-0.444
-40
+40
±25
kΩ
V
µV/ºC
µV/°C2
PPM/ºC
PPM/
year
This relationship describes the nominal behavior of VREF at different temperatures.
100
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
5.4.15 ADC Converter, V3P3A Referenced
Table 78 shows the performance specifications for the ADC converter, V3P3A referenced. For this data,
FIR_LEN=0, VREF_DIS=0 and LSB values do not include the 8-bit left shift at the CE input.
Table 78: ADC Converter Performance Specifications
Parameter
Recommended Input Range
(Vin-V3P3A)
Voltage to Current Crosstalk
6
10 *Vcrosstalk
cos(∠Vin − ∠Vcrosstalk )
Vin
THD (First 10 harmonics) 1:
250 mV-pk
20 mV-pk
Input Impedance
Temperature coefficient of Input Impedance
LSB size
[M40MHZ,
3
1.25  3  M26MHZ] =
VLSB = VREF ⋅
⋅ 
4.75  L  [00], [10], or [11]
L = FIR length
[M40MHZ,
M26MHZ] =
[01]
Digital Full Scale [M40MHZ,
3
M26MHZ] =
 L
 
[00], [10], or [11]
 3
L = FIR length
[M40MHZ,
M26MHZ] =
[01]
ADC Gain Error versus
%Power Supply Variation
10 6 ∆Nout PK 357 nV / VIN
100 ∆V 3P3 A / 3.3
Input Offset (Vin-V3P3A)
v1.2
Condition
Min
-250
Vin = 200 mV peak,
65 Hz, on VA.
Vcrosstalk = largest
measurement on IA or IB
Vin=65 Hz,
64 kpts FFT, BlackmanHarris window
CKCE = 5 MHz
Vin = 65 Hz
Vin = 65 Hz
-10
Typ
40
Max
250
Unit
mV
peak
10
μV/V
-75
-90
dB
dB
90
kΩ
Ω/°C
1.7
FIR_LEN=0
FIR_LEN=1
FIR_LEN=2
FIR_LEN=0
FIR_LEN=1
FIR_LEN=2
3231
355
150
1319
150
42
nV/
LSB
FIR_LEN=0
FIR_LEN=1
FIR_LEN=2
±97336
±884736
±2097152
LSB
FIR_LEN=0
FIR_LEN=1
FIR_LEN=2
±238328
±2097152
±7529536
LSB
Vin=200 mV pk, 65 Hz
V3P3A=3.0 V, 3.6 V
-10
© 2005-2009 TERIDIAN Semiconductor Corporation
nV/
LSB
50
ppm/%
10
mV
101
Data Sheet 71M6531D/F-71M6532D/F
5.5
Timing Specifications
5.5.1
Flash Memory
FDS 6531/6532 005
Table 79: Flash Memory Timing Specifications
Parameter
Flash Read Pulse Width
Condition
V3P3A = V3P3SYS = 0
(BROWNOUT Mode)
Flash write cycles
-40°C to +85°C
Flash data retention
Flash data retention
Flash byte write operations between
page or mass erase operations
Write Time per Byte
Page Erase (1024 bytes)
Mass Erase
25°C
85°C
5.5.2
Min
30
Typ
Max
100
Unit
ns
2
Cycle
s
Years
Years
Cycle
s
µs
ms
ms
20,000
100
10
42
20
200
EEPROM Interface
Table 80: EEPROM Interface Timing
Parameter
Write Clock frequency (I2C)
Write Clock frequency (3-wire)
5.5.3
Condition
CKMPU = 4.9 MHz,
Using interrupts
CKMPU = 4.9 MHz,
bit-banging DIO4/5
CKMPU=4.9 MHz
Min
Typ
78
Max
Unit
kHz
150
kHz
500
kHz
RESET
Table 81: RESET Timing
Parameter
Reset pulse width
Reset pulse fall time
5.5.4
Min
5
Typ
Max
1
Unit
µs
µs
Max
2255
Unit
year
RTC
Parameter
Range for date
102
Condition
Condition
Min
2000
Typ
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
5.5.5
Data Sheet 71M6531D/F-71M6532D/F
SPI Slave Port (MISSION Mode)
Table 82: SPI Slave Port (MISSION Mode) Timing
Parameter
tSPIcyc PCLK cycle time
tSPILead Enable lead time
tSPILag Enable lag time
tSPIW
PCLK pulse width:
High
Low
tSPISCK PCSZ to first PCLK fall
tSPIDIS
tSPIEV
tSPISU
tSPIH
Condition
Min
1
15
0
Typ
Max
40
40
2
Ignore if PCLK is low
when PCSZ falls.
Disable time
PCLK to Data Out
Data input setup time
Data input hold time
Unit
µs
ns
ns
ns
ns
ns
0
15
10
5
ns
ns
ns
ns
PCSZ
tSPIcyc
tSPILead
tSPILag
PCLK
PSDO
tSPISCK
tSPIW
MSB OUT
tSPIEV
tSPIW
LSB OUT
tSPIDIS
tSPIH
PSDI
MSB IN
LSB IN
Figure 43: SPI Slave Port (MISSION Mode) Timing
Electrical Specification Footnotes
1. This spec will be guaranteed and verified in production samples, but will not be measured in production.
2. This spec will be guaranteed and verified in production samples, but will be measured in production
only at DC.
3. This spec will be measured in production at the limits of the specified operating temperature.
4. This spec defines a nominal relationship rather than a measured parameter. Correct circuit operation
will be verified with other specs that use this nominal relationship as a reference.
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
103
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
5.6
Typical Performance Data
5.6.1
Accuracy over Current
Figure 44 shows accuracy over current for various load angles at room temperature.
6531 Wh, All Phases, 50 Hz, 240 V
1
0.75
0.5
0.25
0 Degree
% Error
60 Degree
0
300 Degree
180 Degree
-0.25
-0.5
-0.75
-1
0.1
1
10
100
1000
I (A rms)
Figure 44: Wh Accuracy, 0.1 A to 200 A at 240 V/50 Hz and Room Temperature
5.6.2
Accuracy over Temperature
With digital temperature compensation enabled, the temperature characteristics of the reference voltage
(VREF) are compensated to within ±40 PPM/°C.
104
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
5.7
71M6531D/F Package
5.7.1
Package Outline
68
8.000 ±0.050
1
2
PIN #1 DOT
BY
MARKING
8.000 ±0.050
TOP VIEW
0.850 ±0.050
0.000 ±0.050
SIDE VIEW
0.203 REF
Figure 45: QFN-68 Package Outline, Top and Side View
6.300 ±0.100
Exp. pad
0.400 ±0.050
0.400 BSC
6.300 ±0.100
Exp. pad
0.200 ±0.050
2
1
PIN #1 ID R0.20, or
CHAMFER 0.500 x 45°
68
6.400 REF.
BOTTOM
VIEW
Figure 46: QFN-68 Package Outline, Bottom View
*
Pin length is nominally 0.4 mm (min = 0.3 mm, max = 0.4 mm).
Exposed pad is internally connected to GNDD.
***
Pin 1 is marked on bottom with notch or chamfered corner in the exposed pad next to pin 1.
**
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
105
Data Sheet 71M6531D/F-71M6532D/F
71M6531D/F Pinout (QFN-68)
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
SEG32/DIO12
SEG10/E_TCLK
SEG11/E_RST
PB
XOUT
TEST
XIN
GNDD
DIO1/OPT_RX
V1
VREF
IA
IB
VB
VA
V3P3A
GNDA
5.7.2
FDS 6531/6532 005
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
TERIDIAN
71M6531D-IM
71M6531F-IM
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
RESET
V2P5
VBAT
RX
SEG48/DIO28
SEG31/DIO11
SEG30/DIO10
SEG29/DIO9/YPULSE
SEG28/DIO8/XPULSE
SEG27/DIO7/RPULSE
SEG26/DIO6/WPULSE
SEG25/DIO5/SDATA
SEG24/DIO4/SDCK
ICE_E
SEG18
SEG17
SEG16
SEG0/TEST0
SEG1/TEST1
SEG2/TEST2
SEG34/DIO14
SEG35/DIO15
SEG64/DIO44
SEG49/DIO29
SEG6/PSDI
SEG7/MUX_SYNC
SEG8
SEG65/DIO45
SEG63/DIO43
SEG33/DIO13
SEG12
SEG13
SEG14
SEG15
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
GNDD
SEG9/E_RXTX
DIO2/OPT_TX
TMUXOUT
SEG66/DIO46
TX
SEG3/PCLK
V3P3D
SEG19/CKTEST
V3P3SYS
SEG4/PSDO
SEG5/PCSZ
SEG37/DIO17
COM0
COM1
COM2
COM3
Figure 47: Pinout for QFN-68 Package
106
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
5.7.3
Data Sheet 71M6531D/F-71M6532D/F
Recommended PCB Land Pattern for the QFN-68 Package
Figure 48: PCB Land Pattern for QFN 68 Package
Table 83: Recommended PCB Land Pattern Dimensions
Symbol
e
x
y
d
A
G
Description
Lead pitch
Pad width
Pad length, see note 3
See note 1
Typical Dimension
0.4mm
0.23mm
0.8mm
6.3mm
6.63mm
7.2mm
Notes:
1. Do not place unmasked vias in the region denoted by dimension d.
2. Soldering of bottom internal pad is not required for proper operation.
3. The y dimension has been elongated to allow for hand soldering and reworking. Production assembly may allow this dimension to be reduced as long as the G dimension is maintained.
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
107
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
71M6532D/F Package
5.8.1
71M6532D/F Pinout (LQFP-100)
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
SEG32/DIO12
SEG10/E_TCLK
SEG62/DIO42
SEG61/DIO41
SEG60/DIO40
SEG11/E_RST
SEG42/DIO22/MRX
PB
NC
XOUT
TEST
XIN
GNDD
DIO1/OPT_RX
V1
VREF
IAP
IAN
IBP
IBN
VB
VA
VX
V3P3A
GNDA
5.8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Teridian
71M6532D
71M6532F
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
GNDD
RESET
V2P5
VBAT
RX
SEG31/DIO11
SEG30/DIO10
SEG29/DIO9/YPULSE
SEG28/DIO8/XPULSE
SEG41/DIO21
SEG40/DIO20
SEG39/DIO19
SEG27/DIO7/RPULSE
SEG26/DIO6/WPULSE
SEG25/DIO5/SDATA
SEG24/DIO4/SDCK
SEG23
SEG22
SEG21
SEG20
ICE_E
SEG43/DIO23
SEG18
SEG17
SEG16
SEG0/TEST0
SEG1/TEST1
SEG2/TEST2
SEG34/DIO14
SEG35/DIO15
SEG64/DIO44
SEG49/DIO29
SEG36/DIO16
SEG6/PSDI
SEG50/DIO30
SEG7/MUX_SYNC
SEG8
SEG65/DIO45
GNDD
SEG63/DIO43
SEG47/DIO27
SEG46/DIO26
SEG45/DIO25
SEG33/DIO13
SEG12
SEG44/DIO24
SEG13
SEG14
SEG15
SEG71/DIO51
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
GNDD
SEG9/E_RXTX
DIO2/OPT_TX
TMUXOUT
TX
SEG3/PCLK
V3P3D
SEG19/CKTEST
V3P3SYS
SEG4/PSDO
SEG5/PCSZ
SEG37/DIO17
SEG38/DIO18/MTX
DIO56
DIO57
DIO58
DIO3
COM0
COM1
COM2
COM3
SEG67/DIO47
SEG68/DIO48
SEG69/DIO49
SEG70/DIO50
Figure 49: PCB Land Pattern for LQFP-100 Package
108
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
5.8.2
Data Sheet 71M6531D/F-71M6532D/F
LQFP-100 Mechanical Drawing
15.7(0.618)
16.3(0.641)
1
15.7(0.618)
16.3(0.641)
Top View
14.000 +/- 0.200
MAX. 1.600
1.50 +/- 0.10
0.225 +/- 0.045
0.50 TYP.
0.10 +/- 0.10
0.60 TYP>
Side View
Figure 50: LQFP-100 Package, Mechanical Drawing
(Dimensions are in mm.)
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
109
Data Sheet 71M6531D/F-71M6532D/F
5.9
Pin Descriptions
5.9.1
Power and Ground Pins
FDS 6531/6532 005
Table 84: Power and Ground Pins
Name
GNDA
Type
P
Circuit
–
GNDD
P
–
V3P3A
P
–
V3P3SYS
P
–
V3P3D
O
13
VBAT
P
12
V2P5
O
10
5.9.2
Description
Analog ground: This pin should be connected directly to the ground
plane.
Digital ground: This pin should be connected directly to the ground plane.
Analog power supply: A 3.3 V power supply should be connected to this
pin, must be the same voltage as V3P3SYS.
System 3.3 V supply. This pin should be connected to a 3.3 V power
supply.
Auxiliary voltage output of the chip, controlled by the internal 3.3 V selection switch. In mission mode, this pin is internally connected to
V3P3SYS. In BROWNOUT mode, it is internally connected to VBAT.
This pin is floating in LCD and sleep mode. A bypass capacitor to ground
should not exceed 0.1 µF.
Battery backup and oscillator power supply. A battery or super-capacitor
is to be connected between VBAT and GNDD. If no battery is used, connect VBAT to V3P3SYS.
Output of the internal 2.5 V regulator. A 0.1 µF capacitor to GNDA
should be connected to this pin.
Analog Pins
Table 85: Analog Pins
Name
IA, IB
IAP/IAN,
IBP/IBN
Type
I
Circuit
6
I
6
Description
Line Current Sense Inputs: These pins are voltage inputs to the internal
A/D converter. Typically, they are connected to the outputs of current sensors. Unused pins must be tied to V3P3A.
1)
Line Voltage Sense Inputs: These pins are voltage inputs to the internal
A/D converter. Typically, they are connected to the outputs of resistor dividers. Unused pins must be tied to V3P3A.
The VX pin is not supported by standard CE code.
V1
I
7
Comparator Input: This pin is a voltage input to the internal comparator.
The voltage applied to the pin is compared to the internal BIAS voltage
(1.6 V). If the input voltage is above VBIAS, the comparator output will be
high (1). If the comparator output is low, a voltage fault will occur. A series resistor should be connected from V1 to the resistor divider to provide
hysteresis.
VREF
O
9
Voltage Reference for the ADC. Normally disabled and left unconnected.
If enabled, a 0.1 µF capacitor to V3P3A should be connected to this pin.
XIN
I
8
Crystal Inputs: A 32 kHz crystal should be connected across these pins.
Typically,
a 33 pF capacitor is also connected from XIN to GNDA and a
XOUT
15 pF capacitor is connected from XOUT to GNDA. It is important to minimize the capacitance between these pins. See the crystal manufacturer
datasheet for details.
If an external clock is used, a 150 mV (p-p) clock signal should be applied
to XIN, and XOUT should be left unconnected.
1)
Differential pin pairs IAP/IAN and IBP/IBN, as well as single-ended VX pin used on 71M6532D/F only.
Pin types: P = Power, O = Output, I = Input, I/O = Input/Output
The circuit number denotes the equivalent circuit, as specified under Section 5.9.4 I/O Equivalent Circuits.
VA, VB,
VX 1)
110
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
5.9.3
Data Sheet 71M6531D/F-71M6532D/F
Digital Pins
Table 86: Digital Pins
Name
COM3,COM2,
COM1,COM0
SEG0…SEG2,
SEG7, SEG8
SEG12…SEG18
SEG20…SEG23
SEG24/DIO4…
SEG35/DIO15,
SEG37/DIO17,
SEG48/DIO28,
SEG49/DIO29,
SEG63/DIO43…
SEG66/DIO46
SEG3/PCLK
SEG4/PSDO
SEG5/PCSZ
SEG6/PSDI
E_RXTX/SEG9
E_RST/SEG11
E_TCLK/SEG10
ICE_E
Type Circuit
Description
O
5
LCD Common Outputs: These 4 pins provide the select signals for
the LCD display.
Dedicated LCD Segment Output pins.
O
5
O
I/O
Dedicated LCD Segment Output pins (71M6532D/F only).
5
3, 4, 5 Multi-use pins, configurable as either LCD SEG driver or DIO.
(DIO4 = SCK, DIO5 = SDA when configured as EEPROM interface;
WPULSE = DIO6, VARPULSE = DIO7 when configured as pulse
outputs). Unused pins must be configured as outputs or terminated to V3P3/GNDD.
1)
I/O
3, 4, 5 Multi-use pins, configurable as either LCD SEG driver or SPI PORT.
1, 4, 5 Multi-use pins, configurable as either emulator port pins (when ICE_E
1, 4, 5 pulled high) or LCD SEG drivers (when ICE_E tied to GND).
4, 5
ICE enable. When zero, E_RST, E_TCLK and E_RXTX become
2
SEG32, SEG33 and SEG38 respectively. For production units, this
pin should be pulled to GND to disable the emulator port.
CKTEST/SEG19,
O
4, 5
Multi-use pins, configurable as either multiplexer/clock output or LCD
MUXSYNC/SEG7
segment driver using the I/O RAM registers CKOUT_E or
MUX_SYNC_E.
Digital output test multiplexer. Controlled by TMUX[3:0].
TMUXOUT
O
4
OPT_RX/DIO1
I/O
3, 4, 7 Multi-use pin, configurable as Optical Receive Input or general DIO.
When configured as OPT_RX, this pin receives a signal from an external
photo-detector used in an IR serial interface. If this pin is unused it
must be configured as an output or terminated to V3P3D or GNDD.
Multi-use pin, configurable as either optical LED transmit output,
OPT_TX/DIO2
I/O
3, 4
WPULSE, RPULSE, or general DIO. When configured as OPT_TX,
this pin is capable of directly driving an LED for transmitting data in
an IR serial interface.
Chip reset: This input pin is used to reset the chip into a known state.
RESET
I
2
For normal operation, this pin is pulled low. To reset the chip, this pin
should be pulled high. This pin has an internal 30 μA (nominal) current source pull-down. No external reset circuitry is necessary.
UART input. If this pin is unused it must be configured as an
RX
I
3
output or terminated to V3P3D or GNDD.
UART output.
TX
O
4
TEST
I
7
Enables Production Test. This pin must be grounded in normal
operation.
Push button input. This pin must be at GNDD when not active. A
PB
I
3
rising edge sets the IE_PB flag. It also causes the part to wake up if it
is in SLEEP or LCD mode. PB does not have an internal pull-up or
pull-down.
1)
Not all pins available on the 71M6531D/F or 71M6532D/F.
Pin types: P = Power, O = Output, I = Input, I/O = Input/Output.
The circuit number denotes the equivalent circuit, as specified in Section 5.9.4. I/O Equivalent Circuits.
v1.2
I/O
I/O
O
I
© 2005-2009 TERIDIAN Semiconductor Corporation
111
Data Sheet 71M6531D/F-71M6532D/F
5.9.4
FDS 6531/6532 005
I/O Equivalent Circuits
V3P3D
V3P3A
V3P3D
110K
Digital
Input
Pin
CMOS
Input
from
internal
reference
LCD SEG
Output
Pin
LCD
Driver
VREF
Pin
GNDD
GNDA
GNDD
LCD Output Equivalent Circuit
Type 5:
LCD SEG or
pin configured as LCD SEG
Digital Input Equivalent Circuit
Type 1:
Standard Digital Input or
pin configured as DIO Input
with Internal Pull-Up
VREF Equivalent Circuit
Type 9:
VREF
V3P3A
V3P3D
V3P3D
Digital
Input
Pin
CMOS
Input
Analog
Input
Pin
GNDD
GNDD
Analog Input Equivalent Circuit
Type 6:
ADC Input
Digital Input
Type 2:
Pin configured as DIO Input
with Internal Pull-Down
V2P5 Equivalent Circuit
Type 10:
V2P5
V3P3A
V3P3D
Comparator
Input
Pin
To
Comparator
VLCD
Pin
LCD
Drivers
GNDA
Digital
Input
Pin
V2P5
Pin
GNDA
110K
GNDD
from
internal
reference
To
MUX
CMOS
Input
GNDD
Comparator Input Equivalent
Circuit Type 7:
Comparator Input
VLCD Equivalent Circuit
Type 11:
VLCD Power
GNDD
Oscillator
Pin
Digital Input Type 3:
Standard Digital Input or
pin configured as DIO Input
To
Oscillator
Power
Down
Circuits
VBAT
Pin
GNDD
GNDD
V3P3D
Oscillator Equivalent Circuit
Type 8:
Oscillator I/O
V3P3D
10
Digital
Output
Pin
CMOS
Output
VBAT Equivalent Circuit
Type 12:
VBAT Power
from
V3P3SYS
V3P3D
Pin
GNDD
40
from
VBAT
GNDD
Digital Output Equivalent Circuit
Type 4:
Standard Digital Output or
pin configured as DIO Output
V3P3D Equivalent Circuit
Type 13:
V3P3D
Figure 51: I/O Equivalent Circuits
112
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
6
Data Sheet 71M6531D/F-71M6532D/F
Ordering Information
Part
71M6531D
71M6531D
71M6531F
71M6531F
71M6532D
71M6532D
71M6532F
71M6532F
7
Part Description
(Package)
68-pin QFN,
lead free
100-pin LQFP,
lead free
Flash
Size
128 KB
128 KB
256 KB
256 KB
Bulk
Tape and reel
Bulk
Tape and reel
71M6531D-IM/F
71M6531D-IMR/F
71M6531F-IM/F
71M6531F-IMR/F
Package Marking
71M6531D-IM
71M6531D-IM
71M6531F-IM
71M6531F-IM
128 KB
128 KB
256 KB
256 KB
Bulk
Tape and reel
Bulk
Tape and reel
71M6532D-IGT/F
71M6532D-IGTR/F
71M6532F-IGT/F
71M6532F-IGTR/F
71M6532D-IGT
71M6532D-IGT
71M6532F-IGT
71M6532F-IGT
Packaging
Order Number
Related Information
The following documents applicable to the 71M6531D/F and 71M6532D/F are available from Teridian
Semiconductor Corporation:
•
71M653X Software User’s Guide (SUG_653X)
•
Demo Board User’s Guide (DBUM_6531)
•
Application Note on Migration from the 6521 to the 6531 (AN_6531_001)
8
Contact Information
For more information about Teridian Semiconductor products or to check the availability of the
71M6531D/F or 71M6532D/F, contact us at:
6440 Oak Canyon Road
Suite 100
Irvine, CA 92618-5201
USA
Telephone: (714) 508-8800
FAX: (714) 508-8878
Email: [email protected]
For a complete list of worldwide sales offices, go to http://www.teridian.com.
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
113
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
Appendix A: Acronyms
AMR
ANSI
CE
DIO
ICE
IEC
MPU
PLL
RMS
SFR
SOC
TOU
UART
114
Automatic Meter Reading
American National Standards Institute
Compute Engine
Digital I /O
In-Circuit Emulator
International Electrotechnical Commission
Microprocessor Unit (CPU)
Phase-locked loop
Root Mean Square
Special Function Register
System on Chip
Time of Use
Universal Asynchronous Receiver/Transmitter
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
Appendix B: Revision History
Revision
1.0
Date
February 27,
2009
1.1
July 27, 2009
1.2
October 21, 2009
Description
Initial release. Changes with respect to PDS v1.3:
1) Corrected Timer/Counter 0/1 label in Table 22.
2) Corrected entries for DIO29 and DIO43 in Table 39.
3) Updated unused/reserved bits in I/O RAM tables, added description for WE register.
4) Documented blink capability for both SEG18 and SEG19.
5) Changed package for 71M6532D/F to LQFP-100, updated all pin
tables and I/O RAM tables accordingly.
6) Replaced graph showing system performance specification over
temperature with specification on accuracy of VREF compensation.
7) Added explanation for hysteresis at the V1 pin in Applications
Section.
8) Added note on recommended bypass capacitors C1 and C2 in
Electrical Specification.
9) Removed access to I/O RAM from SPI Port description.
10) Updated numerous parameters in Electrical Specification (temperature sensor, supply current for mission and battery modes).
11) Corrected number of pre-boot cycles in Flash Memory Section.
12) Updated entries in I/O RAM table under “Wake” column.
Updated mechanical drawing for QFN-68 package.
Replaced Figure 19 with single-phase example.
Corrected LQFP-100 package drawing (Figure 50).
Applied minor corrections and enhancements to diagrams.
Updated number range for RTC_ADJ to 0 – 0x7F and tolerance for exposed pad in Figure 46 to 0.1 mm. Corrected bit range for CE_LCTN
to [7:0] and functional description for TMOD[7] and TMOD[3] in Table
22. Added maximum value for WRATE and text stating that registers
RTC_SEC to RTC_YR do not change at reset. Added V LSB entry for
sag detection in CE Interface Description, text regarding hysteresis at
section 3.10, note that VX pin is not supported by standard CE code,
and description of STOP and IDLE bits in PCON register. Changed
value for Wh accuracy percentage on title page (value stated for
room temperature).
© 2008 Teridian Semiconductor Corporation. All rights Reserved.
Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation.
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Simplifying System Integration is a trademark of Teridian Semiconductor Corporation.
Intel is a registered trademark of Intel Corporation.
All other trademarks are the property of their respective owners.
Teridian Semiconductor Corporation makes no warranty for the use of its products, other than expressly
contained in the Company’s warranty detailed in the Teridian Semiconductor Corporation standard Terms
and Conditions. The company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice and
does not make any commitment to update the information contained herein. Accordingly, the reader is
cautioned to verify that this document is current by comparing it to the latest version on
http://www.teridian.com or by checking with your sales representative.
Teridian Semiconductor Corp., 6440 Oak Canyon, Suite 100, Irvine, CA 92618
TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
115