SN74LVC138A-EP www.ti.com....................................................................................................................................... SCAS734D – NOVEMBER 2003 – REVISED NOVEMBER 2008 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER FEATURES 1 • • • • • • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Operates From 2 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 5.8 ns at 3.3 V Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C xxx D OR PW PACKAGE (TOP VIEW) A B C G2A G2B G1 Y7 GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS • • • • • • • (1) Controlled Baseline One Assembly/Test Site One Fabrication Site Available in Military (–55°C/125°C) Temperature Range (1) Extended Product Life Cycle Extended Product-Change Notification Product Traceability Custom temperature ranges available DESCRIPTION/ORDERING INFORMATION The SN74LVC138A 3-line to 8-line decoder/demultiplexer is designed for 2.7-V to 3.6-V VCC operation. The device is designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder minimizes the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, delay times of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low enable inputs and one active-high enable input reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2008, Texas Instruments Incorporated SN74LVC138A-EP SCAS734D – NOVEMBER 2003 – REVISED NOVEMBER 2008....................................................................................................................................... www.ti.com ORDERING INFORMATION (1) PACKAGE (2) TA -40°C to 125°C –55°C to 125°C (1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING SOIC - D Reel of 2500 SN74LVC138AQDREP C138AEP TSSOP - PW Reel of 2000 SN74LVC138AQPWREP C138AEP TSSOP – PW Reel of 250 SN74LVC138AMPWTEP C138AME For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE 2 ENABLE INPUTS SELECT INPUTS OUTPUTS G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X H X X X X H H H H H H H H X X H X X X H H H H H H H H L X X X X X H H H H H H H H H L L L L L L H H H H H H H H L L L L H H L H H H H H H H L L L H L H H L H H H H H H L L L H H H H H L H H H H H L L H L L H H H H L H H H H L L H L H H H H H H L H H H L L H H L H H H H H H L H H L L H H H H H H H H H H L Submit Documentation Feedback Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVC138A-EP SN74LVC138A-EP www.ti.com....................................................................................................................................... SCAS734D – NOVEMBER 2003 – REVISED NOVEMBER 2008 LOGIC DIAGRAM (POSITIVE LOGIC) 15 A 1 14 Select Inputs B C 13 3 12 10 Enable Inputs 6 9 4 7 G2A G2B Y1 2 11 G1 Y0 Y2 Y3 Data Outputs Y4 Y5 Y6 Y7 5 Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVC138A-EP Submit Documentation Feedback 3 SN74LVC138A-EP SCAS734D – NOVEMBER 2003 – REVISED NOVEMBER 2008....................................................................................................................................... www.ti.com Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V –0.5 VCC + 0.5 (2) (3) UNIT VO Output voltage range IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through VCC or GND θJA Package thermal impedance (4) Tstg Storage temperature range (5) (1) (2) (3) (4) (5) D package V 73 PW package °C/W 108 –65 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging. Recommended Operating Conditions (1) Operating MIN MAX 2 3.6 UNIT VCC Supply voltage VIH High-level input voltage VCC = 2.7 V to 3.6 V VIL Low-level input voltage VCC = 2.7 V to 3.6 V 0.8 V VI Input voltage 0 5.5 V VO Output voltage 0 VCC V IOH High-level output current IOL Low-level output current Δt/Δv Input transition rise or fall rate TA Operating free-air temperature (1) 4 Data retention only 1.5 2 V VCC = 2.7 V –12 VCC = 3 V –24 VCC = 2.7 V 12 VCC = 3 V 24 –55 V mA mA 10 ns/V 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVC138A-EP SN74LVC138A-EP www.ti.com....................................................................................................................................... SCAS734D – NOVEMBER 2003 – REVISED NOVEMBER 2008 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 µA VOH 2.2 3V 2.4 IOH = –24 mA 3V 2.2 IOL = 100 µA 2.7 V to 3.6 V IOL = 12 mA 2.7 V 0.4 IOL = 24 mA 3V 0.55 VI = 5.5 V or GND ICC VI = VCC or GND, IO = 0 One input at VCC – 0.6 V, Other inputs at VCC or GND Ci MAX UNIT VCC – 0.2 2.7 V II ΔICC (1) 2.7 V to 3.6 V IOH = –12 mA VOL MIN TYP (1) VCC V 0.2 V ±5 µA 3.6 V 10 µA 2.7 V to 3.6 V 500 µA 3.6 V VI = VCC or GND 3.3 V 5 pF All typical values are at VCC = 3.3 V, TA = 25°C. Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) FROM (INPUT) PARAMETER TO (OUTPUT) VCC = 2.7 V MIN MAX MIN MAX 7.9 1 6.7 7.4 1 6.5 6.4 1 5.8 A or B or C tpd G2A or G2B VCC = 3.3 V ＝ 0.3 V Y G1 UNIT ns Operating Characteristics TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS VCC = 2.5 V VCC = 3.3 V TYP TYP f = 10 MHz 26 27 Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVC138A-EP Submit Documentation Feedback UNIT pF 5 SN74LVC138A-EP SCAS734D – NOVEMBER 2003 – REVISED NOVEMBER 2008....................................................................................................................................... www.ti.com PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 2.7 V 3.3 V ± 0.3 V VI tr/tf 2.7 V 2.7 V ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ 1.5 V 1.5 V 6V 6V 50 pF 50 pF 500 Ω 500 Ω 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VM VM VOL tPHL VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPLZ VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VOH Output VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VM VOH - V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 Submit Documentation Feedback Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVC138A-EP PACKAGE OPTION ADDENDUM www.ti.com 11-Nov-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LVC138AMPWTEP ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC138AQDREP ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC138AQPWREP ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/04657-01XE ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/04657-01YE ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/04657-02YE ACTIVE TSSOP PW 16 250 CU NIPDAU Level-1-260C-UNLIM Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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OTHER QUALIFIED VERSIONS OF SN74LVC138A-EP : SN74LVC138A • Catalog: SN74LVC138A-Q1 • Automotive: • Military: SN54LVC138A NOTE: Qualified Version Definitions: - TI's standard catalog product • Catalog Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects • Military - QML certified for Military and Defense Applications • Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74LVC138AMPWTEP Package Package Pins Type Drawing TSSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LVC138AQDREP SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74LVC138AQPWREP TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC138AMPWTEP TSSOP PW SN74LVC138AQDREP SOIC D 16 250 367.0 367.0 35.0 16 2500 333.2 345.9 28.6 SN74LVC138AQPWREP TSSOP PW 16 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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