SN74LVC1G00-EP SINGLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES450D – DECEMBER 2003 – REVISED SEPTEMBER 2006 FEATURES • • • • • • • • • (1) • Controlled Baseline – One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree (1) Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 3.8 ns at 3.3 V Low Power Consumption, 10-µA Max ICC ±24-mA Output Drive at 3.3 V • • Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DBV OR DCK PACKAGE (TOP VIEW) A B GND Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. 1 5 VCC 4 Y 2 3 DESCRIPTION/ORDERING INFORMATION This single 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G00 performs the Boolean function Y = A • B or Y = A + B in positive logic. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION PACKAGE (1) TA –40°C to 85°C –55°C to 125°C (1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING (2) SOP (SC-70) – DCK Reel of 3000 SN74LVC1G00IDCKREP CAO SOP – DBV Reel of 3000 SN74LVC1G00MDBVREP SBFM SOP (SC-70) – DCK Reel of 3000 SN74LVC1G00MDCKREP BYA Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. The actual top-side marking has one additional character that designates the assembly/test site. FUNCTION TABLE INPUTS A B OUTPUT Y H H L L X H X L H LOGIC DIAGRAM (POSITIVE LOGIC) A B 1 2 4 Y Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2006, Texas Instruments Incorporated SN74LVC1G00-EP SINGLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES450D – DECEMBER 2003 – REVISED SEPTEMBER 2006 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V –0.5 6.5 V –0.5 VCC + 0.5 state (2) VO Voltage range applied to any output in the high-impedance or power-off VO Voltage range applied to any output in the high or low state (2) (3) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through VCC or GND θJA Package thermal impedance (4) Tstg Storage temperature range (1) (2) (3) (4) 2 UNIT DBV package 324.1 DCK package 252 –65 150 V °C/W °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback SN74LVC1G00-EP SINGLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES450D – DECEMBER 2003 – REVISED SEPTEMBER 2006 Recommended Operating Conditions VCC Supply voltage (1) Operating Data retention only High-level input voltage MAX 1.65 5.5 1.5 VCC = 2.3 V to 2.7 V 1.7 VCC = 3 V to 3.6 V 0.7 × VCC 0.35 × VCC VCC = 1.65 V to 1.95 V Low-level input voltage V V 2 VCC = 4.5 V to 5.5 V VIL UNIT 0.65 × VCC VCC = 1.65 V to 1.95 V VIH MIN VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 V 0.3 × VCC VCC = 4.5 V to 5.5 V VI Input voltage 0 5.5 V VO Output voltage 0 VCC V VCC = 1.65 V –4 VCC = 2.3 V IOH High-level output current VCC = 3 V –8 2.4-V Min VOH –16 2.3-V Min VOH –24 VCC = 4.5 V –32 VCC = 1.65 V 4 VCC = 2.3 V IOL Low-level output current ∆t/∆v Input transition rise or fall rate VCC = 3 V 8 0.4-V Max VOL 16 0.55-V Max VOL 24 VCC = 4.5 V 32 VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20 VCC = 3.3 V ± 0.3 V 10 VCC = 5 V ± 0.5 V TA (1) Operating free-air temperature mA mA ns/V 5 SN74LVC1G00IDCKREP –40 85 SN74LVC1G00MDBVREP –55 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback 3 SN74LVC1G00-EP SINGLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES450D – DECEMBER 2003 – REVISED SEPTEMBER 2006 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = –100 µA VOH 1.65 V to 5.5 V 1.65 V 1.2 IOH = –8 mA 2.3 V 1.9 4.5 V 1.65 V to 5.5 V 0.1 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.3 0.4 ICC VI = 5.5 V or GND, IO = 0 ∆ICC One input at VCC – 0.6 V, Other inputs at VCC or GND Ci VI = VCC or GND 0.55 0 to 5.5 V ±5 µA 0 ±10 µA 1.65 V to 5.5 V 10 µA 3 V to 5.5 V 500 µA VI = 5.5 V or GND VI or VO = 5.5 V V 0.55 4.5 V Ioff (1) 3.8 3V IOL = 32 mA A or B inputs 2.3 IOL = 100 µA IOL = 24 mA UNIT V IOH = –32 mA IOL = 16 mA II MAX 2.4 3V IOH = –24 mA TYP (1) VCC – 0.1 IOH = –4 mA IOH = –16 mA VOL MIN 3.3 V 4 pF All typical values are at VCC = 3.3 V, TA = 25°C. Switching Characteristics over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) A or B Y tpd VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V MIN MAX MIN MAX 2.2 7.2 0.9 4.4 MIN MAX 0.8 3.8 VCC = 5 V ± 0.5 V UNIT MIN MAX 0.8 3.4 ns Switching Characteristics over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A or B Y VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V MIN MAX MIN MAX MIN MAX MIN MAX SN74LVC1G00M 3.1 9 1.3 7.0 1 6.3 1 5 SN74LVC1G00I 3.1 9 1.3 5.5 1 4.7 1 4 DEVICE UNIT ns Operating Characteristics TA = 25°C Cpd 4 PARAMETER TEST CONDITIONS Power dissipation capacitance f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP 22 22 23 25 Submit Documentation Feedback UNIT pF SN74LVC1G00-EP SINGLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES450D – DECEMBER 2003 – REVISED SEPTEMBER 2006 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 15 pF 15 pF 15 pF 15 pF 1 MΩ 1 MΩ 1 MΩ 1 MΩ 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VM VM VOL tPHL VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPLZ VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VOH Output VI Output Control VM VOL Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + V∆ VOL tPHZ VM VOH – V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms Submit Documentation Feedback 5 SN74LVC1G00-EP SINGLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES450D – DECEMBER 2003 – REVISED SEPTEMBER 2006 PARAMETER MEASUREMENT INFORMATION (continued) VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VM VM VOL tPHL VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPLZ VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VOH Output VI Output Control VM VOL Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + V∆ VOL tPHZ VM VOH – V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms 6 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 2-Feb-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LVC1G00IDCKREP ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G00MDBVREP ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G00MDCKREP ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/04732-01XE ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/04732-02XE ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/04732-02YE ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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OTHER QUALIFIED VERSIONS OF SN74LVC1G00-EP : • Catalog: SN74LVC1G00 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74LVC1G00IDCKREP Package Package Pins Type Drawing SC70 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DCK 5 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 SN74LVC1G00MDBVREP SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 SN74LVC1G00MDCKREP DCK 5 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 SC70 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC1G00IDCKREP SC70 DCK 5 3000 203.0 203.0 35.0 SN74LVC1G00MDBVREP SOT-23 DBV 5 3000 203.0 203.0 35.0 SN74LVC1G00MDCKREP SC70 DCK 5 3000 203.0 203.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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