W925E/C240 8-BIT CID MICROCONTROLLER Table of Contents1. GENERAL DESCRIPTION ......................................................................................................... 2 2. FEATURES ................................................................................................................................. 2 3. PIN CONFIGURATION ............................................................................................................... 4 4. PIN DESCRIPTION..................................................................................................................... 5 5. BLOCK DIAGRAM ...................................................................................................................... 7 6. FUNCTIONAL DESCRIPTION.................................................................................................... 8 6.1 Memory Organization ..................................................................................................... 9 6.2 Special Function Registers ........................................................................................... 12 6.3 Initial State of Registers................................................................................................ 32 6.4 Instruction ..................................................................................................................... 33 6.5 Power Management...................................................................................................... 37 6.6 Reset............................................................................................................................. 38 6.7 Interrupt......................................................................................................................... 38 6.8 Programmable Timers/Counters................................................................................... 41 6.9 Serial Port 1 .................................................................................................................. 45 6.10 Comparator ................................................................................................................... 47 6.11 DTMF Generator........................................................................................................... 47 6.12 FSK Generator.............................................................................................................. 48 6.13 I/O Ports........................................................................................................................ 50 6.14 Divider........................................................................................................................... 50 6.15 Calling Identity Delivery (CID)....................................................................................... 51 7. APPLICATION CIRCUIT........................................................................................................... 60 8. ELECTRICAL CHARACTERISTICS......................................................................................... 66 8.1 Absolute Maximum Ratings*......................................................................................... 66 8.2 Recommended Operating Conditions .......................................................................... 66 8.3 DC Characteristics ........................................................................................................ 67 8.4 Electrical Characteristics - Gain Control OP-Amplifier ................................................. 68 8.5 AC Characteristics ........................................................................................................ 69 9. PACKAGE DIMENSION ........................................................................................................... 72 10. REVISION HISTORY ................................................................................................................ 73 -1- Publication Release Date: July 12, 2005 Revision A10 W925E/C240 1. GENERAL DESCRIPTION The W925E/C240 is an all in one single 8-bit micro-controller with widely used Calling Identity Delivery (CID) function. The 8-bit CPU core is based on the 8051 family; therefore, all the instructions are compatible to the Turbo 8051 series. The CID part consisted of FSK decoder, DTMF receiver, CPE* Alert Signal (CAS) detector and Ring detector. Also built-in DTMF generator and FSK generator with baud rate 1200 bps (bits/sec). Using W925E/C240 can easily implement the CID adjunct box and the feature phone or Short Message Service (SMS) phone with CID function. The main features are listed in the next section. 2. FEATURES • APPLICATION: The SMS phone with CID function and CID adjunct box. • CPU: 8-bit micro-controller is similar to the 8051 family. − EEPROM type(E version) operating voltage: µC: Depend on the operating vol. option. Either 2.4 to 3.6V or 3.0 to 5.5V for operating. If 2.4 to 3.6V be selected, the µC operating range is from 2.4 to 3.6V, else if 3.0 to 5.5V be selected, the µC operating range is from 3.0 to 5.5V. CID: 3.0 to 5.5V. − MASK type(C version) operating voltage: µC: 2.2 to 5.5V. CID: 3.0 to 5.5V. • Dual-clock operation: − Main oscillator: 3.58MHz crystal for CID and DTMF function. And built-in RC oscillator. − Sub oscillator: 32768Hz crystal. − Main and sub oscillators are enable/disable by bit control individually. • ROM: 256K bytes internal flash EEPROM/MASK ROM type. − Up 128K bytes for program ROM. − Total 256K bytes for look-up table ROM. − Separate 256K into 4 pages, each page is 64K addressable. • RAM: − 256 bytes on chip scratch-pad RAM. − 8K bytes on chip RAM for MOVX instruction. • CID − Compatible with Bellcore TR-NWT-000030 & SR-TSV-002476, British Telecom(BT) SIN227, U.K. Cable Communication Association(CCA) specification. − FSK modulator/demodulator: for Bell 202 and ITU-T V.23 FSK with 1200-baud rate. − CAS detector: for dual tones of Bellcore CAS and BT Idle State and Loop State Dual Tone Alert Signal (DTAS). − DTMF generator/receiver; − Ring detector: for line reversal for BT, ring burst for CCA or ring signal for Bellcore. − Two independent OP amps with adjustable gain for Tip/Ring and Telephone Hybrid connections. -2- W925E/C240 • I/O: 40 I/O pins. − P0: Bit and byte addressable. I/O mode can be bit controlled. Open drain type. − P1~P3: Bit and byte addressable. Pull high and I/O mode can be bit controlled. − P4: Byte addressable. Pull high and I/O mode can be bit controlled. Note: ”CPE*” Customer Premises Equipment • Power mode: − Dual-clock slow operation mode: System is operated by the sub-oscillator (Fosc=Fs and Fm is stopped) − Idle mode: CPU hold. The clock to the CPU is halted, but the interrupt, timer and watchdog timer block work normally but CID function is disabled. − Power down mode: All activity is completely stopped and power consumption is less than 1 µA. • Timer: 2 13/16-bit timers, or 8-bit auto-reload timers, that are Timer0 and Timer1. • Watchdog timer: WDT can be programmed by the user to serve as a system monitor. • Interrupt: 11 interrupt sources with two levels of priority. − 4 interrupts from INT0, INT1, INT2 and INT3. − 2 interrupts from Timer0, Timer1. − 1 interrupt from Serial port. − 1 interrupt from CID. − 1 interrupt from 13/14-bit Divider. − 1 interrupt from Comparator. − 1 interrupt from Watch Dog Timer. • Divider: 13/14 bit divider, clock source from sub-oscillator, therefore, DIVF set every 0.25/0.5 second. • Comparator: − Comparator: 1 analog inputs from VNEG pin, 2 reference input pins, one is from VPOS pin and another is from internal regulator output. • Serial port: − An 8-bit serial transceiver with SCLK and SDATA. • Package: − 100pin LQFP: The part numbers are W925E240 & W925C240 − Lead free 100pin LQFP: The part numbers are W925E240FG & W925G240 -3- Publication Release Date: July 12, 2005 Revision A10 W925E/C240 3. PIN CONFIGURATION W925E/C240 P44/VPOS P43 P42/VNEG P41 P40 DTMF/FSK RNGDI RNGRC NC NC INP2 INN2 GCFB2 VAS VAD GCFB1 INN1 INP1 VREF CAP NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC XOUT2 XIN2 VDD RESET/VPP XIN1 XOUT1 VSS P00 P01 P02 P03 P04 P05 P06 P07 NC NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 EA/DATA BUZ TEST/MODE P17 P16 P15 P14 P13 P12 P11 P10 P27 P26 P25 P24 P23 P22 P21 P20 P37 P36 P35 P34 P33 P32 P31 P30 P47 P46 P45 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 Figure 3-1 shows the pin assignment. The package type is 100pin QFP. Figure 3-1 W925E/C240 Pin Configuration -4- 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 W925E/C240 4. PIN DESCRIPTION NAME I/O DESCRIPTION TEST/MODE I/O TEST pin. In E version (EEPROM type), it works as a Mode pin to select programming mode. In C version (Mask type), this pin with internal pulllow resistor. EA /DATA I, I/O Set high for normal function. In E version, it works as a Data pin. In C version, this pin with internal pull-high resistor. RESET /VPP I RESET pin. A low pulse causes the whole chip reset. In E version, this pin works as a VPP pin, which is a supply programming voltage. In C version, this pin with internal pull-high resistor. RNGDI I Ring Detect Input (Schmitt trigger input). Used for ring detection and line reversal detection. Must maintain a voltage between VAD and VAS. RNGRC O Ring RC (Open drain output and Schmitt trigger input). Used to set the time interval from the end of RNGDI pin to the inactive condition of the RNGON pin. An external resistor must connected to VAD and a capacitor connected to VSS, the time interval is the RC time constant. CAP O Must be connected 0.1µF capacitor to VSS. VREF O Reference Voltage. Nominally, VDD/2 is used to bias the input of the gain control op-amp. GCFB1 O Op-amp1 Feed-back Gain Control signal. Select the input gain by connecting this pin and the INN1 pin with feedback resistor. It is recommended that the op-amp1 be set to unity gain. INN1 I Inverting Input of the gain control op-amp1. INP1 I Non-inverting Input of the gain control op-amp1. GCFB2 O Op-amp2 Feed-back Gain Control signal. Select the input gain by connecting this pin and the INN2 pin with feedback resistor. It is recommended that the op-amp2 be set to unity gain. INN2 I Inverting Input of the gain control op-amp2. INP2 I Non-inverting Input of the gain control op-amp2. VAD I Analog voltage supply. VAS I Analog ground. VDD I Digital voltage supply. VSS I Digital ground. XOUT1 O Output pin for main-oscillator. Connected to 3.58MHz crystal for CID function. XIN1 I Input pin for main-oscillator. Connected to 3.58MHz crystal for CID function. -5- Publication Release Date: July 12, 2005 Revision A10 W925E/C240 Pin Description, continued NAME I/O DESCRIPTION XOUT2 O Output pin for sub-oscillator. Connected to 32.768KHz crystal only. Suggest to add an external capacitor about 10~30pF to ground(VSS) for the accuracy of the oscillator. XIN2 I Input pin for sub-oscillator. Connected to 32.768KHz crystal only. Suggest to add an external capacitor about 10~30pF to ground(VSS) for the accuracy of the oscillator. DTMF/FSK O BUZ O Buzzer output pin. If buzzer function is disabled, BUZ pin is in floating state. P00-P07 I/O Input/output port0. Port0 data can be bit controlled. The I/O mode is controlled by P0IO register. Port0 is open drain type when it is configured as output mode. P10-P17 I/O Input/output port1 with pull high resistors. Port1 data can be bit controlled. The I/O mode is controlled by P1IO register. The P10-P13 and P14-P17 indicate the external interrupt pins(INT2 and INT3) P20-P27 I/O Input/output port2 with pull high resistors. Port2 data can be bit controlled. The I/O mode is controlled by P2IO register. P30-P37 I/O Input/output port3 with pull high resistors. Port3 data can be bit controlled. The I/O mode is controlled by P3IO register. The special function of port3 is referred to the description of P3 register. P40-P47 I/O VPOS, VNEG I FTE=0, Dual-Tone Multi-Frequency(DTMF) signal output FTE=1, FSK signal output Contents are byte controlled. Pull high and I/O mode can be bit controlled. The special function of P4 is referred to the description of P4 register. The comparator V+, V- analog input pins. Share pin with P4.2 and P4.4 -6- W925E/C240 5. BLOCK DIAGRAM Internal CID and uC interface signal RNGDI RNGRC INP1 INN1 GCFB1 INP2 INN2 GCFB2 VREF CAP FSK,CAS (W91030) P4 DTMFD DTMFPT DTMFAT 8 8 DCLK DATA DTMFH DTMFL RST S/P 8 Fosc D-latch ck 8 8 8-bit µC X O U T 1 X I N 2 DD3~DD0 FM DCLK FDATA FD7~FD0 X I N 1 DTMF RECEIVER DTMFE CASPT CASAT CIDE FSKE CASE P0 P1 P2 P3 RNG ALGO FDR FCD CASH,CASL X V V V V O D S A A U D S D S T 2 RNGF ALGOF FDRF DTMFDF FSF FSK modulator B U Z -7- D T M F / F S K R E S E T / V P P E A / D A T A TEST/MODE Publication Release Date: July 12, 2005 Revision A10 W925E/C240 6. FUNCTIONAL DESCRIPTION The W925E/C240 is an 8-bit micro-controller with CID function. The 8-bit micro-control has the same instruction set as the 8051 family, with one addition: DEC DPTR (op-code A5H, the DPTR is decreased by 1). In addition, the W925E/C240 contains on-chip 8K bytes MOVX RAM. ROM There are 256K bytes EEPROM/MASK ROM. Only 128K bytes EEPROM/MASK ROM is used for program code. The completely 256K bytes EEPROM/MASK ROM can be used for the look-up table memory. On-chip Data RAM The W925E/C240 has 8K normal RAM which address is from 0000H to 1FFFH. It only can be accessed by MOVX instruction; this on-chip RAM is optional under software control. The on-chip data RAM is not used for executable program memory. There is no conflict or overlap among the 256 bytes scratchpad RAM and the 8K Bytes MOVX RAM as they use different addressing modes and separate instructions. CID The CID functions include the FSK decoder, CAS detector, and DTMF decoder and ring detector. FSK Modulator Support ITU-T V.23 and Bellcore 202 FSK transmit modulated signal. DTMF Modulator The W925E/C240 built-in dual tone multi-frequency generator. I/O Ports: The W925E/C240 has five 8-bit I/O ports giving 40 lines. Port0 to Port3 can be used as an 8-bit general I/O port with bit-addressable. The I/O mode of each port is controlled by PxIO registers. Port1 to Port4 have internal pull high resistors enabled/disabled by PxH registers. Port0 is open-drain type in output mode. Serial I/O Port The serial port, through P4.0 (SCLK) and P4.1 (SDATA), is an 8-bit synchronous serial I/O interface. Timers The W925E/C240 has two 13/16-bit timers or an 8 bits auto-reload timers. An independent watchdog timer is used as a system monitor or as a very long time period timer. A divider can produce the divider interrupt in every period of 0.5S or 0.25S. Comparator The W925E/C240 has an internal comparator with one external analog signal input path VNEG and an external path VPOS or a regulator voltage for the reference input REF1. Interrupts The W925E/C240 provides 11 interrupt resources with two priority level, including 4 external interrupt sources, 2 timer interrupts, 1 CID interrupt, 1 divider interrupt, 1 serial port interrupt, 1 comparator interrupt and 1 watchdog timer interrupt. -8- W925E/C240 Power Management The W925E/C240 has IDLE and POWER DOWN modes of operation. In the IDLE mode, the clock to the CPU core is stopped however the functions of the timers, divider, CID and interrupts are active continuously. In the POWER DOWN mode, both of the system clock stop oscillating and the chip operation is completely stopped. POWER DOWN mode is the state of the lowest power consumption. 6.1 Memory Organization The W925E/C240 separates the memory into two separate sections, the Program Memory and the Data Memory. The Program Memory is used to store the instruction op-codes and look-up table data, while the Data Memory is used to store data or for memory mapped devices. Program Memory The Program Memory on the W925E/C240 can be up to 256K bytes that are divided into 4 pages, each page has the size of 64K bytes. The upper 128K bytes are used to store the op-codes and the whole 256K can be used to store look-up table data. Because the op-code is 64K addressable, a PG bit in PAGE register decides which ROM page between page0, page1 is enabled, and the ALU fetches the op-code from the selected ROM page. If PG=0, ALU fetches the op-code from page0. If PG=1, ALU fetches the op-code from page1. When MOVC instruction is executed, ALU fetches the look-up table data according the indication of LT1 and LT0 bits. The value of LT1 and LT0 indicates which ROM page is active for look-up table instruction. 00000 64K Page0 PG=0 LT1,0 =00 64K Page1 PG=1 LT1,0 =01 0FFFF 10000 1FFFF 20000 64K Page2 LT1,0 =10 64K Page3 LT1,0 =11 2FFFF 30000 3FFFF Figure 6-1 Program Memory Map -9- Publication Release Date: July 12, 2005 Revision A10 W925E/C240 Data Memory The W925E/C240 contains on-chip 8K MOVX RAM of Data Memory, which can only be accessed by MOVX instructions from the address 0000H to 1FFFH. In addition, the W925E/C240 has 256 bytes of on-chip scratchpad RAM. This can be accessed either by direct addressing or by indirect addressing. There are also Special Function Registers (SFRs), which can only be accessed by direct addressing. Since the scratchpad RAM is only 256 bytes, it can be used only when data contents are small. In the event that larger data contents are present, the only one selection is on-chip MOVX RAM. The on-chip MOVX RAM can only be accessed by a MOVX instruction. However, the on-chip RAM has the fastest access times. The memory map is shown Figure 6-2 and Figure 6-3 shows the scratched-pad RAM/register addressing. FFH 80H 7FH 00H Indirect Addressing RAM SFRs Direct Addressing only Direct & Indirect Addressing RAM 1FFFH 8K byte SRAM On chip 0000H Figure 6-2 memory map - 10 - W925E/C240 FFh Indirect RAM 80h 7Fh 30h 2Fh 2Eh 2Dh 2Ch 2Bh 2Ah 29h 28h 27h 26h 25h 24h 23h 22h 21h 20h 1Fh 18h 17h 10h 0Fh 08h 07h 00h Direct RAM 7F 77 6F 67 5F 57 4F 47 3F 37 2F 27 1F 17 0F 07 7E 76 6E 66 5E 56 4E 46 3E 36 2E 26 1E 16 0E 06 7D 75 6D 65 5D 55 4D 45 3D 35 2D 25 1D 15 0D 05 7C 74 6C 64 5C 54 4C 44 3C 34 2C 24 1C 14 0C 04 7B 73 6B 63 5B 53 4B 43 3B 33 2B 23 1B 13 0B 03 7A 72 6A 62 5A 52 4A 42 3A 32 2A 22 1A 12 0A 02 79 71 69 61 59 51 49 41 39 31 29 21 19 11 09 01 78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00 Bit Addressable 20H- 2FH Bank 3 Bank 2 Bank 1 Bank 0 Figure 6-3 Scratchpad RAM/Register Addressing - 11 - Publication Release Date: July 12, 2005 Revision A10 W925E/C240 6.2 Special Function Registers The W925E/C240 uses Special Function Registers (SFRs) to control and monitor peripherals and their Modes. The SFRs reside in the register locations 80-FFh and accessed by direct addressing only. Some of the SFRs are bit addressable. This is very useful in cases where one wishes to modify a particular bit without changing the others. The SFRs that are bit addressable are those whose addresses end in 0 or 8. The list of SFRs is as follows. The table is condensed with eight locations per row. Empty locations indicate that there are no registers at these addresses. The content of reserved bits or registers is not guaranteed. Table 1 Special Function Register Location Table F8 EIP F0 B E8 EIE E0 ACC D8 WDCON D0 PSW C8 DIVC C0 SCON1 B8 IP B0 P3 A8 IE A0 P2 CIDGD CIDGA SBUF1 REGVC CIDR PMR STATUS FSKTC FSKTB DTMFG COMPR IRC1 IRC2 CASPT CASAT CIDFG CIDPCR FSKDR DTMFDR DTMFPT DTMFAT P4IO HB P4H P4 98 P1EF P1H P2H P3H 90 P1 EXIF RPAGE P1SR P0IO P1IO P2IO P3IO 88 TCON TMOD TL0 TL1 TH0 TH1 CKCON1 CKCON2 80 P0 SP DPL DPH DPL1 DPH1 DPS PCON Note: The SFRs in the column with dark borders are bit-addressable. A brief description of the SFRs now follows. PORT 0 (initial=FFh, input mode) Bit: 7 6 5 4 3 2 1 0 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 Mnemonic: P0 Address: 80h P0: P0 can be selected as input or output mode by the P0IO register. At initial reset, P0IO is set to FFH, P0 is used as input mode. When P0IO is set to 0, the P0 is used as CMOS open drain mode. - 12 - W925E/C240 STACK POINTER (initial=07H) Bit: 7 6 5 4 3 2 1 0 SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0 Mnemonic: SP SP: Address: 81h The Stack Pointer stores the scratchpad RAM address where the stack begins. In other words, it always points to the top of the stack. DATA POINTER LOW Bit: (initial=00H) 7 6 5 4 3 2 1 0 DPL.7 DPL.6 DPL.5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0 Mnemonic: DPL Address: 82h DPL: This is the low byte of the standard 8052 16-bit data pointer. DATA POINTER HIGH Bit: (initial=00H) 7 6 5 4 3 2 1 0 DPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0 Mnemonic: DPH Address: 83h DPH: This is the high byte of the standard 8052 16-bit data pointer. DATA POINTER LOW1 Bit: (initial=00H) 7 6 5 4 3 2 1 0 DPL1.7 DPL1.6 DPL1.5 DPL1.4 DPL1.3 DPL1.2 DPL1.1 DPL1.0 Mnemonic: DPL1 DPL1: Address: 84h This is the low byte of the new additional 16-bit data pointer. That has been added to the W925E/C240. The user can switch between DPL, DPH and DPL1, DPH1 simply by setting register DPS.0 = 1. The instructions that use DPTR will now access DPL1 and DPH1 in place of DPL and DPH. If they are not required, they can be used as conventional register locations by the user. DATA POINTER HIGH1 Bit: (initial=00H) 7 6 5 4 3 2 1 0 DPH1.7 DPH1.6 DPH1.5 DPH1.4 DPH1.3 DPH1.2 DPH1.1 DPH1.0 Mnemonic: DPH1 DPH1: Address: 85h This is the high byte of the new additional 16-bit data pointer. That has been added to the W925E/C240. The user can switch between DPL, DPH and DPL1, DPH1 simply by setting register DPS = 1. The instructions that use DPTR will now access DPL1 and DPH1 in place of DPL and DPH. If they are not required, they can be used as conventional register locations by the user. - 13 - Publication Release Date: July 12, 2005 Revision A10 W925E/C240 DATA POINTER SELECT Bit: (initial=00H) 7 6 5 4 3 2 1 0 - - - - - - - DPS.0 Mnemonic: DPS DPS.0: Address: 86h This bit is used to select either the DPL,DPH pair or the DPL1,DPH1 pair as the active Data Pointer. When set to 1, DPL1,DPH1 will be selected, otherwise DPL,DPH will be selected. DPS.1-7: These bits are reserved, but will read 0. POWER CONTROL Bit: (initial=00H) 7 6 5 4 3 2 1 0 - - - IDLT GF1 GF0 PD IDL Mnemonic: PCON Address: 87h IDLT: This bit controls the idle mode type. In idle mode when idle mode is released by any interrupt, if IDLT=1 it will not jump to the corresponding interrupt; if IDLT=0 it will jump to the corresponding interrupt. GF1-0: These two bits are general-purpose user flags. PD: Setting this bit causes the W925E/C240 to go into the POWER DOWN mode. In this mode, all the clocks are stopped and program execution is frozen. Power down mode can be released by INT0~INT3 and ring detection of CID interrupt. IDL: Setting this bit causes the W925E/C240 to go into the IDLE mode. The type of idle mode is selected by IDLT. In this mode the clocks to the CPU are stopped, so program execution is frozen. However, the clock path to the timers blocks and interrupt blocks is not stopped, and these blocks continue operating. TIMER CONTROL (initial=00H) Bit: 7 6 5 4 3 2 1 0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Mnemonic: TCON Address: 88h TF1: Timer 1 overflows flag. This bit is set when Timer 1 overflows. It is cleared automatically when the program does a timer 1 interrupt service routine. Software can also set or clear this bit. TR1: Timer 1 runs control. This bit is set or cleared by software to turn timer on or off. TF0: Timer 0 overflows flag. This bit is set when Timer 0 overflows. It is cleared automatically when the program does a timer 0 interrupt service routine. Software can also set or clear this bit. TR0: Timer 0 runs control. This bit is set or cleared by software to turn timer on or off. IE1: Interrupt 1 edge detects: Set by hardware when an edge/level is detected on INT1 . This bit is cleared by hardware when the service routine is vectored to only if the interrupt was edge triggered. Otherwise, it follows the pin. IT1: Interrupt 1 type control: Set/cleared by software to specify falling edge/ low level triggered external inputs. - 14 - W925E/C240 IE0: Interrupt 0 edge detects: Set by hardware when an edge/level is detected on INT0 . This bit is cleared by hardware when the service routine is vectored to only if the interrupt was edge triggered. Otherwise, it follows the pin. IT0: Interrupt 0 type control. Set/cleared by software to specify falling edge/ low level triggered external inputs. TIMER MODE CONTROL Bit: (initial=00H) 7 6 5 4 3 2 1 0 GATE C/ T M1 M0 GATE C/ T M1 M0 Mnemonic: TMOD Address: 89h Bit7~4 control timer 1, bit3~0 control timer0 GATE: Gating control. When this bit is set, Timer x is enabled only while INTx pin is high and TRx control bit is set. When cleared, Timer x is enabled whenever TRx control bit is set. C/ T : Timer or Counter Select. When cleared, the timer is incremented by internal clocks. When set, the timer counts high-to-low edges of the Tx pin. Note: X is either 0 or 1. M1, M0: Mode Select bits: M1 M0 Mode 0 0 Mode 0: 13-bits timer 0 1 Mode 1: 16-bits timer 1 0 Mode 2: 8-bits with auto-reload from Thx 1 1 Reserved TIMER 0 LOW BYTE Bit: (initial=00H) 7 6 5 4 3 2 1 0 TL0.7 TL0.6 TL0.5 TL0.4 TL0.3 TL0.2 TL0.1 TL0.0 Mnemonic: TL0 Address: 8Ah TL0.7-0: Timer 0 low byte register. TIMER 1 LOW BYTE Bit: (initial=00H) 7 6 5 4 3 2 1 0 TL1.7 TL1.6 TL1.5 TL1.4 TL1.3 TL1.2 TL1.1 TL1.0 Mnemonic: TL1 Address: 8Bh TL1.7-0: Timer 1 low byte register. - 15 - Publication Release Date: July 12, 2005 Revision A10 W925E/C240 TIMER 0 HIGH BYTE (initial=00H) Bit: 7 6 5 4 3 2 1 0 TH0.7 TH0.6 TH0.5 TH0.4 TH0.3 TH0.2 TH0.1 TH0.0 Mnemonic: TH0 Address: 8Ch TH0.7-0: Timer 0 high byte register. TIMER 1 HIGH BYTE (initial=00H) Bit: 7 6 5 4 3 2 1 0 TH1.7 TH1.6 TH1.5 TH1.4 TH1.3 TH1.2 TH1.1 TH1.0 Mnemonic: TH1 Address: 8Dh TH1.7-0: Timer 1 high byte register. CLOCK CONTROL1 (initial=00H) Bit: 7 6 5 4 3 2 1 0 WD1 WD0 T1S1 T1S0 T0S1 T0S0 DIVS M /S Mnemonic: CKCON1 Address: 8Eh WD1-0: Watchdog timer mode select bits: These bits determine the time-out period for the watchdog timer. In all four time-out options the reset time-out is 512 clocks more than the interrupt timeout period. WD1 WD0 Interrupt time-out Reset time-out 12 Fosc/212 + 512 0 0 Fosc/2 0 1 Fosc/215 Fosc/215 + 512 1 0 Fosc/218 Fosc/218 + 512 1 1 Fosc/221 Fosc/221 + 512 T0S0-1&T1S0-1: Timer0 & Timer1 clock source mode select bits. These bits determine the timer0 & timer1 clock source. T0S1 (T1S1) T0S0 (T1S0) Prescale Clock Source 0 0 Fosc/22 0 1 Fosc/26 1 0 Fosc/210 1 1 Fs DIVS: Divider clock source control bit 1: DIVS = 0 : Fs/213 DIVS= 1 : Fs/214 - 16 - W925E/C240 M /S: System clock source control bit: M /S = 0 : Fosc = XIN1 ( FM) M /S = 1 : Fosc = XIN2 ( Fs) CLOCK CONTROL2 (initial = 00H) Bit: 7 6 ENBUZ BUZSL 5 4 3 2 1 0 KT1 KT0 - - - - Mnemonic: CKCON2 Address: 8Fh ENBUZ: When ENBUZ=1 the BUZ pin works as buzzer output, otherwise BUZ pin is in floating state. BUZSL: Buzzer output selection. When BUZSL=0 BUZ is the output of octave tone. When BUZZL=1, BUZ is the output of key tone. KT1-0: Key tone frequency sources from divider. When divider is enable, KT1 and KT0 determines the key tone frequency. KT1 KT0 Key tone frequency 0 0 Low 0 1 512Hz 1 0 1024Hz 1 1 2048Hz PORT 1 (initial=FFH,input mode) Bit: 7 6 5 4 3 2 1 0 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 Mnemonic: P1 Address: 90h P1.7-0: P1 can be selected as input or output mode by the P1IO register, at initial reset, P1IO is set to 1, so P1 is used as input mode. When P1IO is set to 0, the P1 is used as CMOS output mode. When P1EF are set and P1IO are set as input mode P1 can be used as external interrupt source. The functions are listed below. P1.0 : INT2.0 P1.1 : INT2.1 P1.2 : INT2.2 P1.3 : INT2.3 P1.4 : INT3.0 P1.5 : INT3.1 P1.6 : INT3.2 P1.7 : INT3.3 External Interrupt 2 External Interrupt 2 External Interrupt 2 External Interrupt 2 External Interrupt 3 External Interrupt 3 External Interrupt 3 External Interrupt 3 - 17 - Publication Release Date: July 12, 2005 Revision A10 W925E/C240 EXTERNAL INTERRUPT FLAG Bit: (initial = 00H) 7 6 5 4 3 2 1 0 - - - COMPF DIVF CIDF IE3 IE2 Mnemonic: EXIF Address: 91h COMPF: Comparator flag. Set by hardware when RESC bit is from low to high. DIVF: Divider overflow flag. CIDF: CID interrupt flag. Set by hardware when at least one of CID flags is set. IE3: External Interrupt 3 flag. Set by hardware when a falling edge is detected on INT3. IE2: External Interrupt 2 flag. Set by hardware when a falling edge is detected on INT2. ROM PAGE POINTER (initial = 00H) Bit: 7 6 5 4 3 2 1 0 - - LT1 LT0 - - - PG Mnemonic: RPAGE Address: 92h LT1 and LT0 determine the ROM page of the instruction MOVC reading the content from ROM. ROM PAGE Rom address (LT1, LT0) = (0, 0) Page 0 00000H-0FFFFH (LT1, LT0) = (0, 1) Page 1 10000H-1FFFFH (LT1, LT0) = (1, 0) Page 2 20000H-2FFFFH (LT1, LT0) = (1, 1) Page 3 30000H-3FFFFH PG = 0 indicates the executing program is in page 0, from 00000H-0FFFFH PG = 1 indicates the executing program is in page 1, from 10000H-1FFFFH P1 PINS STATUS (initial = 00H) Bit: 7 6 5 4 3 2 1 0 P1.7SR P1.6SR P1.5SR P1.4SR P1.3SR P1.2SR P1.1SR P1.0SR Mnemonic: P1SR Address: 93h P1SR: Set when a falling edge is detected on the corresponding P1 pin, clear by software. P0 I/O PORT CONTROL (initial = FFH) Bit: 7 6 5 4 3 2 1 0 P0.7IO P0.6IO P0.5IO P0.4IO P0.3IO P0.2IO P0.1IO P0.0IO Mnemonic: P0IO Address: 94h P0IO: P0 pins I/O control. 1: input mode 0: output mode - 18 - W925E/C240 P1 I/O PORT CONTROL (initial = FFH) Bit: 7 6 5 4 3 2 1 0 P1.7IO P1.6IO P1.5IO P1.4IO P1.3IO P1.2IO P1.1IO P1.0IO Mnemonic: P1IO Address: 95h P1IO: P1 pins I/O control. 1: input mode 0: output mode P2 I/O PORT CONTROL (initial = FFH) Bit: 7 6 5 4 3 2 1 0 P2.7IO P2.6IO P2.5IO P2.4IO P2.3IO P2.2IO P2.1IO P2.0IO Mnemonic: P2IO Address: 96h P2IO: P2 pins I/O control. 1: input mode 0: output mode P3 I/O PORT CONTROL (initial = FFH) Bit: 7 6 5 4 3 2 1 0 P3.7IO P3.6IO P3.5IO P3.4IO P3.3IO P3.2IO P3.1IO P3.0IO Mnemonic: P3IO Address: 97h P3IO: P3 pins I/O control. 1: input mode 0: output mode P1 PINS INTERRUPT EABLE Bit: 7 (initial = 00H) 6 5 4 3 2 1 0 P1.7EF P1.6EF P1.5EF P1.4EF P1.3EF P1.2EF P1.1EF P1.0EF Mnemonic: P1EF Address: 9Bh P1EF: P1 pins interrupt function enabled/disabled register 0: disable 1: enable P1 PULL-HIGH CONTROL Bit: (initial = 00H) 7 6 5 4 3 2 1 0 P1.7H P1.6H P1.5H P1.4H P1.3H P1.2H P1.1H P1.0H Mnemonic: P1H Address: 9Dh - 19 - Publication Release Date: July 12, 2005 Revision A10 W925E/C240 P1H: Port1 pins pull-high resistor enable/disable 1: enable 0: disable P2 PULL-HIGH CONTROL Bit: (initial = 00H) 7 6 5 4 3 2 1 0 P2.7H P2.6H P2.5H P2.4H P2.3H P2.2H P2.1H P2.0H Mnemonic: P2H P2H: Address: 9Eh Port1 pins pull-high resistor enable/disable 1: enable 0: disable P3 PULL-HIGH CONTROL Bit: (initial = 00H) 7 6 5 4 3 2 1 0 P3.7H P3.6H P3.5H P3.4H P3.3H P3.2H P3.1H P3.0H Mnemonic: P3H P3H: Address: 9Fh Port1 pins pull-high resistor enable/disable 1: enable 0: disable PORT 2 (initial = FFH,input mode) Bit: 7 6 5 4 3 2 1 0 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 Mnemonic: P2 Address: A0h P2.7-0: Port 2 is an I/O port with internal pull-high resistor. P2 can be selected as input or output mode by the P2IO register. At initial reset, P2 is used as input mode. When P2IO is set to 0, P2 is used as CMOS output mode. HIGH BYTE REGISTER (initial = 00H) Bit: 7 6 5 4 3 2 1 0 HB.7 HB.6 HB.5 HB.4 HB.3 HB.2 HB.1 HB.0 Mnemonic: HB Address: A1h This register contains the high byte address during execution of " MOVX @Ri, " instructions. P4 PULL-HIGH CONTROL Bit: (initial = 00H) 7 6 5 4 3 2 1 0 P4.7H P4.6H P4.5H P4.4H P4.3H P4.2H P4.1H P4.0H Mnemonic: P4H Address: A2h - 20 - W925E/C240 P4H: Port4 pins pull-high resistor enable/disable 1: enable 0: disable PORT 4 (initial = FFH,input mode) Bit: 7 6 5 4 3 2 1 0 P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 Mnemonic: P4 Address: A6h P4.7-0: Port 4 is an I/O port with internal pull-high resistor. P4 can be selected as input or output mode by the P4IO register. At initial reset, P4IO is set to 0FFh, P4 is used as input mode. When P4IO is set to 00h, P4 is used as CMOS output mode. Special function of P4 is described below. P4.4 VPOS Positive input of the comparator P4.2 VNEG Negative input of the comparator P4.1 SDATA Serial port data I/O P4.0 SCLK Serial port clock I/O with Smith trigger in input path INTERRUPT ENABLE (initial = 00H) Bit: 7 6 5 4 3 2 1 0 EA ES1 - - ET1 EX1 ET0 EX0 Mnemonic: IE EA: ES1: Address: A8h Global enable. Enable/disable all interrupts. Enable Serial port interrupt ET1: Enable Timer 1 interrupt EX1: Enable external interrupt 1 ET0: Enable Timer 0 interrupt EX0: Enable external interrupt 0 P4 I/O PORT CONTROL (initial = FFH) Bit: 7 6 5 4 3 2 1 0 P4.7IO P4.6IO P4.5IO P4.4IO P4.3IO P4.2IO P4.1IO P4.0IO Mnemonic: P4IO Address: AEh P4IO: P4 pins I/O control. 1: input mode 0: output mode - 21 - Publication Release Date: July 12, 2005 Revision A10 W925E/C240 PORT 3 (initial = FFH,input mode) Bit: 7 6 5 4 3 2 1 0 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 Mnemonic: P3 Address: B0h P3.7-0: P3 can be selected as input or output mode by the P3IO register, at initial reset, P3IO is set to 0FFH, P3 is used as input mode. When P3IO is set to 00h, the P3 is used as CMOS output mode. Special function of P3 is described below. P3.5 T1 Timer/Counter 1 external count input P3.4 T0 Timer/Counter 0 external count input P3.3 INT1 External interrupt 1 P3.2 INT0 External interrupt 0 CID REGISTER (initial = 00H,read only) Bit: 7 6 5 4 3 2 1 0 - FCLK FDATA FCD DTMFD FDR ALGO RNG Mnemonic: CIDR Address: B1h This SFR indicates the CID signal immediately. Register data is set or cleared by hardware only. FCLK: FSK serial clock with the baud rate of 1200Hz. FDATA: FSK serial bit data. FCD: Set when FSK carrier is detected. Cleared when FSK carrier is disappeared. DTMFD: Set when DTMF decoded data is ready. Cleared when DTMF signal ends. FDR: Set when FSK 8 bits data is ready. Cleared before next FSK start bit comes ALGO: Dual tone Alert signal Guard time detect signal. Set when a guard time qualified dual tone alert signal has been detected. Cleared when the guard time qualified dual tone alert signal is absent. RNG: Ring detection bit. High to indicate the detection of line reversal and/or ringing. CID FLAG GENERATOR Bit: (initial = 00H) 7 6 5 4 - - - FSF 3 2 DTMFDF FDRF Mnemonic: CIDFG 1 0 ALGOF RNGF Address: B2h FSF: Set when FSK Latch clock low to high. Cleared by software DTMFDF: Set when DTMFD low to high. Cleared by software FDRF: Set when FDR low to high. Cleared by software. ALGOF: Set when ALGO low to high. Cleared by software. RNGF: Set when RNG low to high. Cleared by software. - 22 - W925E/C240 CID POWER CONTROL REGISTER Bit: (initial = 00H) 7 6 5 4 3 2 1 0 - - - CIDE - FSKE CASE DTMFE Mnemonic: CIDPCR Address: B3h CIDE: Global enable CID function. Low to disable all functions of CID parts. FSKE: Enable FSK demodulation circuit. CASE: Enable Dual Tone Alert Signal detection circuit. DTMFE: Enable DTMF demodulation circuit. FSK DATA REGISTER Bit: (initial = XXH) 7 6 5 4 3 2 1 0 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 Mnemonic: FSKDR FD7-0: Address: B4h 8 bits FSK demodulated data. DTMF DATA REGISTER Bit: (initial = XXH) 7 6 CASH CASL 5 4 DTMFH DTMFL 3 2 1 0 DD3 DD2 DD1 DD0 Mnemonic: DTMFDR Address: B5h CASH: Set when Dual Tone Alert Signal high tone is detected. CASL: Set when Dual Tone Alert Signal low tone is detected. DTMFH: Set when DTMF high tone is detected. DTMFL: Set when DTMF low tone is detected. DD3-0: 4 bits DTMF demodulated data. DTMF PRESENT TIME REGISTER Bit: (initial = 19H) 7 6 5 4 3 2 1 0 DPT7 DPT6 DPT5 DPT4 DPT3 DPT2 DPT1 DPT0 Mnemonic: DTMFPT Address: B6h The clock period of guard-time timer is 0.8582mS. The default DTMF present time is 21.45mS. DPT7-0: The pre-set data register for counting DTMF present time. When DTMF is detected(Est, low to high), the guard timer starts to up-count from 00H. As the guard timer is equal to the value of DTMFPT, the exist of the DTMF is accepted. Est changes to low state to stop and reset the counter. - 23 - Publication Release Date: July 12, 2005 Revision A10 W925E/C240 DTMF ABSENT TIME REGISTER Bit: (initial = 19H) 7 6 5 4 3 2 1 0 DAT7 DAT6 DAT5 DAT4 DAT3 DAT2 DAT1 DAT0 Mnemonic: DTMFAT Address: B7h The clock period of guard-time timer is 0.8582mS. The default DTMF absent time is 21.45mS. DAT7-0: The pre-set data register for counting DTMF absent time. When DTMF is absent(Est, high to low), the guard timer starts to up-count from 00H. As the guard timer is equal to the value of DTMFAT, the finish of DTMF is recognized. Est changes to low state to stop and reset the counter. INTERRUPT PRIORITY (initial = 00H) Bit: 7 6 5 4 3 2 1 0 - PS1 - - PT1 PX1 PT0 PX0 Mnemonic: IP Address: B8h IP.7: This bit is un-implemented and will read high. PS1: This bit defines the Serial port interrupt priority. PS1 = 1 sets it to higher priority level PT1: This bit defines the Timer 1 interrupt priority. PT1 = 1 sets it to higher priority level. PX1: This bit defines the External interrupt 1 priority. PX1 = 1 sets it to higher priority level. PT0: This bit defines the Timer 0 interrupt priority. PT0 = 1 sets it to higher priority level. PX0: This bit defines the External interrupt 0 priority. PX0 = 1 sets it to higher priority level. DTMF GENERATOR REGISTER Bit: (initial = 00H) 7 6 5 4 3 2 1 0 - DTGE HE LE L1 L0 H1 H0 Mnemonic: DTMFG Address: BAh L1 L0 H1 H0 Selected tone x x 0 0 1209Hz x x 0 1 1336Hz x x 1 0 1477Hz x x 1 1 1633Hz 0 0 x x 697Hz 0 1 x x 770Hz 1 0 x x 852Hz 1 1 x x 941Hz LE: Enable low group frequency output. HE: Enable high group frequency output. DTGE: Enable dual tone output to DTMF pin. - 24 - W925E/C240 COMPARATOR REGISTER Bit: (initial = 00H) 7 6 5 4 3 2 1 0 - - - - RESC REF - COMPEN Mnemonic: COMPR Address: BBh RESC: Result of the comparator. Set when positive analog input voltage is(VPOS or 1.0v internal regular output) higher than negative analog input voltage(VNEG) RESC is a read only bit. REF: REF = 0 reference input from analog input voltage(VPOS/P4.4) pin. REF = 1 reference input from the internal regulator output. COMPEN: COMPEN = 0 Disable comparator COMPEN = 1 Enable comparator IDLE RELEASED CONDITION REGISTER 1 Bit: (initial = 00H) 7 6 5 4 3 2 1 0 - IRCS1 - - IRCT1 IRCX1 IRCT0 IRCX0 Mnemonic: IRC1 Address: BCh One of the bits of IRC1 and IRC2 will be set by hardware to record the idle released condition when the idle mode is released. IRC1 and IRC2 can be set by hardware and can be R/W by software. IRCS1: Idle mode released by Serial port interrupt flag. IRCT1: Idle mode released by Timer 1 interrupt flag. IRCX1: Idle mode released by external interrupt 1 flag. IRCT0: Idle mode released by Timer 0 interrupt flag. IRCX0: Idle mode released by external interrupt 0 flag. IDLE RELEASED CONDITION REGISTER 2 Bit: 7 6 - - (initial = 00H) 5 4 3 2 IRCWDI IRCCOMP IRCDIV IRCCID Mnemonic: IRC2 1 0 IRCX3 IRCX2 Address: BDh One of the bits of IRC1 and IRC2 will be set by hardware to record the idle released condition when the idle mode is released. IRC1 and IRC2 can be set by hardware and can be R/W by software. IRCWDI: Idle mode released by Watchdog timer interrupt flag. IRCCOMP: Idle mode released by comparator interrupt flag. IRCDIV: Idle mode released by Divider interrupt flag. IRCCID: Idle mode released by CID interrupt flag. IRCX3: Idle mode released by External Interrupt 3 flag. IRCX2: Idle mode released by External Interrupt 2 flag. - 25 - Publication Release Date: July 12, 2005 Revision A10 W925E/C240 CAS TONE PRESENT TIME REGISTER Bit: 7 6 (initial = 0FH) 5 4 3 2 1 0 CASPT7 CASPT6 CASPT5 CASPT4 CASPT3 CASPT2 CASPT1 CASPT0 Mnemonic: CASPT Address: BEh The clock period of guard-time timer is 0.8582mS. The default alert tone present time is 12.87mS. CASPT7-0: The pre-set data register for counting CAS tone present time. When CAS tone is detected (ALGR low to high), the guard timer starts to up-count from 00H. As the guard timer is equal to the value of CASPT, the exist of the CAS tone is accepted. ALGR changes to low state to stop and reset the counter. CAS TONE ABSENT TIME REGISTER Bit: 7 (initial = 0FH) 6 5 4 3 2 1 0 CASAT7 CASAT6 CASAT5 CASAT4 CASAT3 CASAT2 CASAT1 CASAT0 Mnemonic: CASAT Address: BFh The clock period of guard-time timer is 0.8582mS. The default alert tone absent time is 12.87mS. CASAT7-0: The pre-set data register for counting CAS tone absent time. When CAS tone is absent (ALGR high to low), the guard timer starts to up-count from 00H. As the guard timer is equal to the value of CASAT, the finish of CAS tone is recognized. ALGR changes to high state to stop and reset the counter. SERIAL PORT CONTROL Bit: (initial = 00H) 7 6 5 4 3 2 1 0 SF1 - REGON REN1 SFQ SEDG CLKIO SIO Mnemonic: SCON1 Address: C0h SF1: Serial port interrupt flag. When 8-bits data transited completely, SF1 is set by hardware. SF1 is cleared when serial interrupt routine is executed or cleared by software. REGON: Regulator on/off control. 0 to disable regulator, 1 to regulator. REN1: Set REN1 from 0 to 1 to start the serial port to receive 8-bit serial data. SFQ: SFQ = 0 Serial clock output frequency is equal to fOSC /2 SFQ = 1 Serial clock output frequency is equal to fOSC /256 SEDG: SEDG = 0 Serial data latched at falling edge of clock, SCLK = Low initially. SEDG = 1 Serial data latched at rising edge of clock, SCLK = High initially. CLKIO: CLKIO = 0 P4.0(SCLK) work as output mode CLKIO = 1 P4.0(SCLK) work as input mode SIO: SIO = 0 P4.0 & P4.1 work as normal I/O pin SIO = 1 P4.0 & P4.1 work as Serial port1 function - 26 - W925E/C240 SERIAL DATA BUFFER Bit: 7 (initial = 00H) Read Only 6 5 4 3 2 1 0 SBUF1.7 SBUF1.6 SBUF1.5 SBUF1.4 SBUF1.3 SBUF1.2 SBUF1.1 SBUF1.0 Mnemonic: SBUF1 Address: C1h SBUF1.7-0: Serial data on the serial port 1 is read from or written to this location. It actually consists of two separate internal 8-bit registers. One is the receive register, and the other is the transmit buffer. Any read access gets data from the receive data buffer, while write access is to the transmit data buffer. REGULATOR VOLTAGE CONTROL REGISTER Bit: (initial = 00H) 7 6 5 4 - - - - 3 2 1 0 REGVC.3 REGVC.2 REGVC.1 REGVC.0 Mnemonic: REGVC Address: C2h REGVC.3-0: 4 bits to tune the regulator output voltage. POWER MANAGEMENT REGISTER Bit: (initial = XXX00001B) 7 6 5 4 3 2 1 0 XT/ RG RGMD RGSL X2OFF X1OFF - - - Mnemonic: PMR Address: C4h XT/ RG :Crystal/RC Oscillator Select. Setting this bit selects crystal or external clock as system clock source. Clearing this bit selects the on-chip RC oscillator as clock source. X1UP (STATUS.4) must be set to 1 and X1OFF (PMR.3) must be cleared before this bit can be set. Attempts to set this bit without obeying these conditions will be ignored. RGMD: RC Mode Status. This bit indicates the current clock source of micro-controller. When cleared, CPU is operating from the external crystal or oscillator. When set, CPU is operating from the on-chip RC oscillator. RGSL: RC Oscillator Select. This bit selects the clock source following a resume from Power Down Mode. Setting this bit allows device operating from RC oscillator when a resume from Power Down Mode. When this bit is cleared, the device will hold operation until the crystal oscillator has warmed-up following a resume from Power Down Mode. X2OFF: Set to disable sub-oscillator (32KHz oscillator) X1OFF: Crystal Oscillator Disable. Setting this bit disables the external crystal oscillator. This bit can only be set to 1 while the micro-controller is operating from the RC oscillator. Clearing this bit restarts the crystal oscillator, the X1UP (STATUS.4) bit will be set after crystal oscillator warmed-up has completed. ※Please insert at least 5 instructions NOP after X2UP = ”1”& Fsys = Fs (CKCON1.0 = “1”, M/S). - 27 - Publication Release Date: July 12, 2005 Revision A10 W925E/C240 STATUS REGISTER Bit: (initial=00H) 7 6 5 4 3 2 1 0 X2UP HIP LIP X1UP - - - - Mnemonic: STATUS Address: C5h X2UP:Sub-crystal oscillator warm-up status. When set, this bit indicates the crystal oscillator has completed the warm-up delay. When X2OFF bit is set, hardware will clear this bit. There are two options which is selected by option code for warm-up delay, one is 1024 clocks warm-up delay, other is 65536 clocks warm-up delay. HIP: High Priority Interrupt Status. When set, it indicates that software is servicing a high priority interrupt. This bit will be cleared when the program executes the corresponding RETI instruction. LIP: Low Priority Interrupt Status. When set, it indicates that software is servicing a low priority interrupt. This bit will be cleared when the program executes the corresponding RETI instruction. X1UP:Crystal Oscillator Warm-up Status. when set, this bit indicates the crystal oscillator has completed the 65536 clocks warm-up delay. Each time the crystal oscillator is restarted by exit from power down mode or the X1OFF bit is set, hardware will clear this bit. This bit is set to 1 after a power-on reset. When this bit is cleared, it prevents software from setting the XT/ RG bit to enable CPU operation from crystal oscillator. There are two options which is selected by option code for warm-up delay, one is 4096 clocks warm-up delay, other is 65536 clocks warmup delay. FSK TRANSIMT CONTROL REGISTER Bit: (initial = 00H) 7 6 5 4 3 2 1 0 FTE FTM FDS - - - LO1 LO0 Mnemonic: FSKTC Address: C6h FTE: FSK transmit Enable; Enable:1, Disable = 0 FTM: FSK signal Standard; Bellcore:1, V.23 = 0 FDS: FSK data sending status LO0, LO1: FSK transmit level option FSK Output Level LO1 LO0 150 mV 0 0 120 mV 0 1 95 mV 1 0 75 mV 1 1 FSK TRANSMIT DATA BUFFER Bit: 7 (initial = 00H) 6 5 4 3 2 1 0 FSKTB.7 FSKTB.6 FSKTB.5 FSKTB.4 FSKTB.3 FSKTB.2 FSKTB.1 FSKTB.0 Mnemonic: FSKTB Address: C7h FSKTB.0:Only this bit will be latched and send out as FSK signal - 28 - W925E/C240 DIVIDER CONTROL (initial = 01H) Bit: 7 6 5 4 3 2 1 0 - - - - - - - DIVA Mnemonic: DIVC Address: C8h DIVA: Divider available control bit. This bit is set or cleared by software to enable/disable divider. DIVA = 1 to enable the divider. DIVA = 0 to disable the divider. DIVA is reset after reset. PROGRAM STATUS WORD Bit: (initial = 00H) 7 6 5 4 3 2 1 0 CY AC F0 RS1 RS0 OV F1 P Mnemonic: PSW Address: D0h CY: Carry flag. Set for an arithmetic operation, which results in a carry being generated from the ALU. It is also used as the accumulator for the bit operations. AC: Auxiliary carry. Set when the previous operation resulted in a carry from the high order nibble. F0: User flag 0. General-purpose flag that can be set or cleared by the user. RS.1-0: Register bank select bits: RS1 RS0 Register bank Address 0 0 0 00-07h 0 1 1 08-0Fh 1 0 2 10-17h 1 1 3 18-1Fh OV: Overflow flag. Set when a carry was generated from the seventh bit but not from the 8th bit as a result of the previous operation, or vice-versa. F1: User Flag 1. General-purpose flag that can be set or cleared by the user by software. P: Parity flag. Set/cleared by hardware to indicate odd/even number of 1's in the accumulator. WATCHDOG CONTROL Bit: (initial: note) 7 6 5 4 3 2 1 0 - POR - WFS WDIF WTRF EWT RWT Mnemonic: WDCON Address: D8h POR: Power-on reset flag. Hardware will set this flag when system is powered on and this flag is cleared only by software. WFS: Watchdog Timer Frequency Select. Set to select FS as WDT clock input. Clear to select FOSC as WDT clock input. WDIF: Watchdog Timer Interrupt flag. This bit is set whenever the time-out occurs in the watchdog timer. If the Watchdog interrupt is enabled (EIE.5), then an interrupt will occur (if the global interrupt enable is set and other interrupt requirements are met). Software or any reset can clear this bit. - 29 - Publication Release Date: July 12, 2005 Revision A10 W925E/C240 WTRF: Watchdog Timer Reset Flag. Hardware will set this bit when the watchdog timer causes a reset. Software can read it but must clear it manually. A power-fail reset will also clear the bit. This bit helps software in determining the cause of a reset. If EWT = 0, the watchdog timer will have no effect on this bit. EWT: Enable Watchdog timer Reset. Setting this bit will enable the Watchdog timer Reset function. RWT: Reset Watchdog Timer. This bit helps in putting the watchdog timer into a known state. It also helps in resetting the watchdog timer before a time-out occurs. Failing to set the EWT before time-out will cause an interrupt, if EWDI (EIE.5) is set, and 512 clocks after that a watchdog timer reset will be generated if EWT is set. This bit is self-clearing by hardware. Note: The WDCON SFR is set to a 0x000xx0b on an external reset. WTRF is set to a 1 on a Watchdog timer reset, but to a 0 on power on/down resets. WTRF is not altered by an external reset. POR is set to 1 by a power-on reset. EWT is set to 0 on a Power-on reset and unaffected by other resets. ACCUMULATOR (initial = 00H) Bit: 7 6 5 4 3 2 1 0 ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 Mnemonic: ACC Address: E0h ACC.7-0: The ACC register. EXTENDED INTERRUPT ENABLE Bit: (initial = 00H) 7 6 5 4 3 2 1 0 - - EWDI ECOMP EDIV ECID EX3 EX2 Mnemonic: EIE Address: E8h EIE.7-6: Reserved bits. EWDI: Enable Watchdog timer interrupt. ECOMP: Enable comparator interrupt. EDIV: Enable Divider interrupt. ECID: Enable CID interrupt. EX3: External Interrupt 3 Enable. EX2: External Interrupt 2 Enable. B REGISTER (initial = 00H) Bit: 7 6 5 4 3 2 1 0 B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0 Mnemonic: B Address: F0h B.7-0: The B register serves as a second accumulator. - 30 - W925E/C240 EXTENDED INTERRUPT PRIORITY Bit: (initial = 00H) 7 6 5 4 3 2 1 0 - - PWDI PCOMP PDIV PCID PX3 PX2 Mnemonic: EIP Address: F8h PWDI: Watchdog timer interrupt priority. 0 = Low priority, 1 = High priority. PCOMP: Comparator interrupt priority. 0 = Low priority, 1 = High priority. PDIV: Divider Interrupt Priority. 0 = Low priority, 1 = High priority. PCID: CID Interrupt Priority. 0 = Low priority, 1 = High priority. PX3: External Interrupt 3 Priority. 0 = Low priority, 1 = High priority. PX2: External Interrupt 2 Priority. 0 = Low priority, 1 = High priority. CID GAIN CONTROL DATA Bit: (initial = 00H) 7 6 5 4 3 2 1 0 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 Mnemonic: CIDGD Address: F9h CIDGD.7-0: The data value of programmable CID input filter gain and hysteresis. CID GAIN CONTROL ADDRESS Bit: (initial = 00H) 7 6 5 4 3 2 1 0 - - - - BIT3 BIT2 BIT1 BIT0 Mnemonic: CIDGA CIDGA.3: Address: FAh The CIDGD latch control signal. Rising high pulse to latch CIDGD into CID gain control register. CIDGA.2-0: The address to indicate CID input gain control registers. - 31 - Publication Release Date: July 12, 2005 Revision A10 W925E/C240 6.3 Initial State of Registers The following table lists the initial state of registers after different reset functions. SFR ITEM RESET INITIAL VALUE POR WDT RESET ACC, B, STATUS, PSW, 00h 00h 00h SP, 07h 07h 07h PAGE 00h 00h 00h P0, P1, P2, P3, P4, P0IO, P1IO, P2IO, P3IO, P4IO ffh ffh ffh DPL, DPH, DPL1, DPH1, DPS 00h 00h 00h PCON, TCON, TMOD, 00h 00h 00h TL0, TL1, TH0, TH1, 00h 00h 00h CKCON1, CKCON2, SCON1, SBUF1, REGVC, 00h 00h 00h EXIF, IE, HB, IP, EIE, EIP 00h 00h 00h P1SR, P1EF, P1H, P2H, P3H, P4H, 00h 00h 00h CIDR, CIDFG, CIDPCR, CIDGD, CIDGA, 00h 00h 00h FSKDR, DTMFDR, ******** B ******** B ******** B DTMFPT, DTMFAT, 19h 19h 19h DTMFG, COMPR, IRC1, IRC2, FSKTC, FSKTB, 00h 00h 00h CASPT, CASAT, 0fh 0fh 0fh PMR 10000xx1B 10000xx1B uuu00xx1B DIVC, 01h 01h 01h 0u000uu0B 01000000B 0u0001u0B WDCON Notes: x: Un-used u: unchanged *: Depend on circuit detection - 32 - W925E/C240 6.4 Instruction The W925E/C240 executes all the instructions of the standard 8032 family. However, timing of these instructions is different. In the W925E/C240, each machine cycle consists of 4 clock periods, while in the standard 8032 it consists of 12 clock periods. Also, in the W925E/C240 there is only one fetch per machine cycle i.e. 4 clocks per fetch, while in the standard 8032 there can be two fetches per machine cycle, which works out to 6 clocks per fetch. Table 2 Instructions that affect Flag settings INSTRUCTION CARRY OVERFLOW AUXILIARY INSTRUCTION CARRY OVERFLOW AUXILIARY CARRY HEX BYTES OP-CODE MACHINE CYCLES CARRY INC, DEC - - - SETB C 1 ADD X X X CLR C 0 ADDC X X X CPL C X SUBB X X X ANL C, bit X MUL 0 X ANL C, bit X DIV 0 X ORL C, bit X DA A X ORL C, bit X RRC A X MOV C, bit X RLC A X CJNE X A "X" indicates that the modification is as per the result of instruction. A "-" indicates that the flag is not effected by the instruction. Table 3 Instruction Timing for W925E/C240 INSTRUCTION HEX OP-CODE BYTES MACHINE CYCLES INSTRUCTION NOP ADD A, R0 ADD A, R1 ADD A, R2 ADD A, R3 ADD A, R4 ADD A, R5 ADD A, R6 ADD A, R7 ADD A, @R0 ADD A, @R1 ADD A, direct ADD A, #data ADDC A, R0 ADDC A, R1 00 28 29 2A 2B 2C 2D 2E 2F 26 27 25 24 38 39 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 ANL A, R0 ANL A, R1 ANL A, R2 ANL A, R3 ANL A, R4 ANL A, R5 ANL A, R6 ANL A, R7 ANL A, @R0 ANL A, @R1 ANL A, direct ANL A, #data ANL direct, A ANL direct, #data ANL C, bit - 33 - 58 59 5A 5B 5C 5D 5E 5F 56 57 55 54 52 53 82 1 1 1 1 1 1 1 1 1 1 2 2 2 3 2 1 1 1 1 1 1 1 1 1 1 2 2 2 3 2 Publication Release Date: July 12, 2005 Revision A10 W925E/C240 Table 3. Instruction Timing for W925E/C240, continued INSTRUCTION HEX OP-CODE BYTES MACHINE CYCLES ADDC A, R2 ADDC A, R3 ADDC A, R4 3A 3B 3C 1 1 1 1 1 1 ADDC A, R5 3D 1 1 ADDC A, R6 3E 1 1 1 1 1 2 2 ADDC A, R7 ADDC A, @R0 ADDC A, @R1 ADDC A, direct ADDC A, #data 3F 36 37 35 34 71, 91, B1, ACALL addr11 11, 31, 51, D1, F1 01, 21, 41, AJMP ADDR11 61, 81, A1, C1, E1 CJNE R7, #data, BF rel CLR A E4 CPL A F4 CLR C C3 CLR bit C2 CPL C B3 CPL bit B2 DEC A 14 DEC R0 18 DEC R1 19 DEC R2 1A DEC R3 1B DEC R4 1C DEC R5 1D DEC R6 1E DEC R7 1F DEC @R0 16 DEC @R1 17 DEC direct 15 DEC DPTR A5 DIV AB 84 DA A D4 INSTRUCTION 1 1 1 2 2 ANL C, /bit CJNE A, direct, rel CJNE A, #data, rel CJNE @R0, #data, rel CJNE @R1, #data, rel CJNE R0, #data, rel CJNE R1, #data, rel CJNE R2, #data, rel CJNE R3, #data, rel CJNE R4, #data, rel 2 3 2 HEX BYTES OP-CODE MACHINE CYCLES B0 B5 B4 2 3 3 2 4 4 B6 3 4 B7 3 4 B8 B9 BA BB BC 3 3 3 3 3 4 4 4 4 4 CJNE R5, #data, rel BD 3 4 3 CJNE R6, #data, rel BE 3 4 3 4 JC rel 40 2 3 1 1 1 2 1 2 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 2 1 2 1 1 1 1 1 1 1 1 1 1 1 2 2 5 1 JNC rel JB bit, rel JNB bit, rel JBC bit, rel LCALL addr16 LJMP addr16 MUL AB MOV A, R0 MOV A, R1 MOV A, R2 MOV A, R3 MOV A, R4 MOV A, R5 MOV A, R6 MOV A, R7 MOV A, @R0 MOV A, @R1 MOV A, direct MOV A, #data MOV R0, A MOV R1, A 50 20 30 10 12 02 A4 E8 E9 EA EB EC ED EE EF E6 E7 E5 74 F8 F9 2 3 3 3 3 3 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 3 4 4 4 4 4 5 1 1 1 1 1 1 1 1 1 1 2 2 1 1 - 34 - W925E/C240 Table 3. Instruction Timing for W925E/C240, continued INSTRUCTION HEX OP-CODE BYTES MACHINE CYCLES INSTRUCTION DJNZ R0, rel DJNZ R1, rel DJNZ R2, rel DJNZ R3, rel DJNZ R4, rel DJNZ R5, rel DJNZ R6, rel DJNZ R7, rel DJNZ direct, rel INC A INC R0 INC R1 INC R2 INC R3 INC R4 INC R5 INC R6 INC R7 INC @R0 INC @R1 INC direct INC DPTR JMP @A+DPTR JZ rel JNZ rel MOV @R1, direct MOV @R0, #data MOV @R1, #data MOV direct, A MOV direct, R0 MOV direct, R1 MOV direct, R2 MOV direct, R3 MOV direct, R4 MOV direct, R5 MOV direct, R6 MOV direct, R7 MOV direct, @R0 MOV direct, @R1 D8 D9 DA DB DC DD DE DF D5 04 08 09 0A 0B 0C 0D 0E 0F 06 07 05 A3 73 60 70 A7 76 77 F5 88 89 8A 8B 8C 8D 8E 8F 86 87 2 2 2 2 2 2 2 2 3 1 1 1 1 1 1 1 1 1 1 1 2 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 4 1 1 1 1 1 1 1 1 1 1 1 2 2 2 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 MOV R2, A MOV R3, A MOV R4, A MOV R5, A MOV R6, A MOV R7, A MOV R0, direct MOV R1, direct MOV R2, direct MOV R3, direct MOV R4, direct MOV R5, direct MOV R6, direct MOV R7, direct MOV R0, #data MOV R1, #data MOV R2, #data MOV R3, #data MOV R4, #data MOV R5, #data MOV R6, #data MOV R7, #data MOV @R0, A MOV @R1, A MOV @R0, direct RL A RLC A RR A RRC A SETB C SETB bit SWAP A SJMP rel SUBB A, R0 SUBB A, R1 SUBB A, R2 SUBB A, R3 SUBB A, R4 SUBB A, R5 - 35 - HEX BYTES OP-CODE FA FB FC FD FE FF A8 A9 AA AB AC AD AE AF 78 79 7A 7B 7C 7D 7E 7F F6 F7 A6 23 33 03 13 D3 D2 C4 80 98 99 9A 9B 9C 9D 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 2 1 1 1 1 1 2 1 2 1 1 1 1 1 1 MACHINE CYCLES 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 2 1 1 1 1 1 2 1 3 1 1 1 1 1 1 Publication Release Date: July 12, 2005 Revision A10 W925E/C240 Table 3. Instruction Timing for W925E/C240, continued INSTRUCTION MOV direct, direct MOV direct, #data MOV DPTR, #data 16 MOVC A, @A+DPTR MOVC A, @A+PC MOVX A, @R0 MOVX A, @R1 MOVX A, @DPTR MOVX @R0, A MOVX @R1, A MOVX @DPTR, A MOV C, bit MOV bit, C ORL A, R0 ORL A, R1 ORL A, R2 ORL A, R3 ORL A, R4 ORL A, R5 ORL A, R6 ORL A, R7 ORL A, @R0 ORL A, @R1 ORL A, direct ORL A, #data ORL direct, A ORL direct, #data ORL C, bit ORL C, /bit PUSH direct POP direct RET RETI HEX OP-CODE BYTES MACHINE CYCLES INSTRUCTION 85 75 3 3 3 3 SUBB A, R6 SUBB A, R7 9E 9F 1 1 1 1 90 3 3 SUBB A, @R0 96 1 1 93 1 2 SUBB A, @R1 97 1 1 83 E2 E3 E0 F2 F3 F0 A2 92 48 49 4A 4B 4C 4D 4E 4F 46 47 45 44 42 43 72 A0 C0 D0 22 32 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 2 2 2 3 2 2 2 2 1 1 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 2 2 2 3 2 2 2 2 2 2 SUBB A, direct SUBB A, #data XCH A, R0 XCH A, R1 XCH A, R2 XCH A, R3 XCH A, R4 XCH A, R5 XCH A, R6 XCH A, R7 XCH A, @R0 XCH A, @R1 XCHD A, @R0 XCHD A, @R1 XCH A, direct XRL A, R0 XRL A, R1 XRL A, R2 XRL A, R3 XRL A, R4 XRL A, R5 XRL A, R6 XRL A, R7 XRL A, @R0 XRL A, @R1 XRL A, direct XRL A, #data XRL direct, A XRL direct, #data 95 94 C8 C9 CA CB CC CD CE CF C6 C7 D6 D7 C5 68 69 6A 6B 6C 6D 6E 6F 66 67 65 64 62 63 2 2 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 2 2 2 3 2 2 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 2 2 2 3 - 36 - HEX BYTES OP-CODE MACHINE CYCLES W925E/C240 6.5 Power Management The W925E/C240 has 3 operation mode, normal mode, idle mode and power down mode to manage the power consumption. Normal Mode Normal mode is used in the normal operation status. All functions can be worked in the normal mode. Idle Mode The user can put the device into idle mode by writing 1 to the bit PCON.0. The instruction that sets the idle bit is the last instruction that will be executed before the device goes into Idle Mode. In the Idle mode, the clock to the CPU is halted, but not to the Interrupt, Timer, Watchdog timer, Divider, Comparator and CID blocks. This forces the CPU state to be frozen; the Program counter, the Stack Pointer, the Program Status Word, the Accumulator and the other registers hold their contents. The port pins hold the logical states they had at the time Idle was activated. The Idle mode can be terminated in two ways. Since the interrupt controller is still active, the activation of any enabled interrupt can wake up the processor. This will automatically terminate the Idle mode and clear the Idle bit. And if bit IDLT(PCON.4) is cleared the Interrupt Service Routine(ISR) will be executed, else the idle mode is released directly without any execution of ISR. After the ISR, execution of the program will continue from the instruction, which put the device into Idle mode. The Idle mode can also be exited by activating the reset. The device can be put into reset either by applying a low on the external RESET pin or a power on/fail reset condition or a Watchdog timer reset. The external reset pin has to be held low for at least two machine cycles i.e. 8 clock periods to be recognized as a valid reset. In the reset, condition the program counter is reset to 0000h and all the SFRs are set to the reset condition. Since the clock is still running in the period of external reset therefore the instruction is executed immediately. In the Idle mode, the Watchdog timer continues to run, and if enabled, a time-out will cause a watchdog timer interrupt, which will wake up the device. The software must reset the Watchdog timer in order to preempt the reset, which will occur after 512 clock periods of the time-out. Power Down Mode The device can be put into Power Down mode by writing 1 to bit PCON.1. The instruction that does this will be the last instruction to be executed before the device goes into Power Down mode. In the Power Down mode, all the clocks are stopped and the device comes to a halt. All activity is completely stopped and the power consumption is reduced to the lowest possible value. The port pins output the values held by their respective SFRs. The W925E/C240 will exit the Power Down mode by reset or external interrupts or ring detected. An external reset can be used to exit the Power down state. The low on RESET pin terminates the Power Down mode, and restarts the clock. The on-chip hardware will now provide a delay of 65536 clock, which is used to provide time for the oscillator to restart and stabilize. Once this delay is complete, an internal reset is activated and the program execution will restart from 0000h. In the Power down mode, the clock is stopped, so the Watchdog timer cannot be used to provide the reset to exit Power down mode. The W925E/C240 can be woken from the Power Down mode by forcing an external interrupt pin activated and ring detected, provided the corresponding interrupt is enabled, while the global enable(EA) bit is set. While the power down is released, the device will experience a warm-up delay of 65536 clock cycles to ensure the stabilization of oscillation. Then device executes the interrupt service routine for the corresponding external interrupt or CID interrupt. After the interrupt service routine is completed, the program returns to the instruction after the one, which put the device into Power Down - 37 - Publication Release Date: July 12, 2005 Revision A10 W925E/C240 mode and continues from there. When RGSL (PMR.5) bit is set to 1, the CPU will use the internal RC oscillator instead of crystal to exit Power Down mode. The micro-controller will automatically switch from RC oscillator to crystal after a warm-up delay of 65536 crystal clocks. The RC oscillator runs at approximately 2−4 MHz. Using RC oscillator to exit from Power Down mode saves the time for waiting crystal start-up. It is useful in the low power system which usually be awakened from a short operation then returns to Power Down mode. 6.6 Reset The user has several hardware related options for placing the W925E/C240 into reset condition. In general, most register bits go to their reset value irrespective of the reset condition, but there are few flags that initial states are dependant on the source of reset. User can recognize the cause of reset by reading the flags. There are three ways of putting the device into reset state. They are External reset, Power on reset and Watchdog reset. External Reset The device continuously samples the RESET pin at state C4 of every machine cycle. Therefore, the RESET pin must be held for at least 2 machine cycles to ensure detection of a valid RESET low. The reset circuitry then synchronously applies the internal reset signal. Thus, the reset is a synchronous operation and requires the clock to be running to cause an external reset. Once the device is in reset condition, it will remain so as long as RESET is 0. Even after RESET is deactivated, the device will continue to be in reset state for up to two machine cycles, and then begin program execution from 0000h. There is no flag associated with the external reset condition. However, since some flags indicate the cause of other two reset, the external reset can be considered as the default reset if those two flags are cleared. Watchdog Timer Reset The Watchdog timer is a free running timer with programmable time-out intervals. The user can reset the watchdog timer at any time to avoid producing the flag WDIF. If the Watchdog reset is enabled and the flag WDIF is set high, the watchdog timer reset is performed after the additional 512 clocks come. This places the device into the reset condition. The reset condition is maintained by hardware for two machine cycles. Once the reset is removed, the device will begin execution from 0000h. 6.7 Interrupt The W925E/C240 has a two priority levels interrupt structure with 11 interrupt sources. Each of the interrupt sources has an individual priority bit, flag, interrupt vector and enable bit. In addition, the interrupts can be globally enabled or disabled. Interrupt Sources The External Interrupts INT0 and INT1 can be either edge triggered or level triggered, depending on bits IT0 and IT1. The bits IE0 and IE1 in the TCON register are the flags, which are checked to generate the interrupt. In the edge triggered mode of the INT0 and the INT1 inputs are sampled in every machine cycle. If the sample is high in one cycle and low in the next, then a high to low transition is detected and the interrupts request flag IEx in TCON is set. The flag bit requests the interrupt. Since the external interrupts are sampled every machine cycle, they have to be held high or low for at least one complete machine cycle. The IEx flag is automatically cleared when the service routine is called. If the level triggered mode is selected, then the requesting source has to hold the pin low until the interrupt is serviced. The IEx flag will not be cleared by the hardware on entering the - 38 - W925E/C240 service routine. If the interrupt continues to be held low even after the service routine is completed, then the processor may acknowledge another interrupt request from the same source. Note that the external interrupts INT2 to INT3 are edge triggered only. The TF0, TF1 flags generate the Timer 0, 1 Interrupts. These flags are set by the overflow in the Timer 0, Timer 1. The TF0 and TF1 flags are automatically cleared by the hardware when the timer interrupt is serviced. The Watchdog timer can be used as a system monitor or a simple timer. In either case, when the timeout count is reached, the Watchdog timer interrupt flag WDIF (WDCON.3) is set. If the enable bit EIE.5 enables the interrupt, then an interrupt will occur. The Serial block can generate interrupts on reception or transmission. There are one interrupt sources from the Serial block, which are obtained by SF1 in the SCON1. SF1 is cleared automatically when the serial port interrupt is serviced. The divider interrupt is generated by DIVF that is set when divider overflows. DIVF is set by hardware and cleared when divider interrupt is serviced. The divider interrupt is enable/disable if the bit EDIV is high/low. The comparator interrupt is produced by COMPF, which is set when the RESC bit is changed from low to high. RESC, which is the real-time result of comparator, set when the voltage of reference input is higher than the voltage of analog input. The CID interrupt is generated by CIDF. The CIDF is a logic OR output of all CID flags which are set by hardware and cleared by software. The structure of the CID flags is shown in Figure 6-4. Each of the individual interrupts can be enabled or disabled by setting or clearing the corresponding bits in the IE and EIE SFR. A bit EA, which is located in IE.7, is a global control bit to enable/disable the all interrupt. When bit EA is zero all interrupts are disabling and when bit EA is high, each interrupt is enable individually by the corresponding bit. RNGF FDRF ALGOF DTMFDF FSF CIDF D System clock R Clear by software Figure 6-4 The Structure of CID Flags Priority Level Structure There are two priority levels for the interrupts, high and low. The interrupt sources can be individually set to either high or low levels. Naturally, a higher priority interrupt cannot be interrupted by a lower priority interrupt. However there exists a pre-defined hierarchy amongst the interrupts themselves. This hierarchy comes into play when the interrupt controller has to resolve simultaneous requests having the same priority level. This hierarchy is defined as shown below; the interrupts are numbered starting from the highest priority to the lowest. - 39 - Publication Release Date: July 12, 2005 Revision A10 W925E/C240 Table 4 Interrupt table. FLAG NAME FLAG LOCATION EN BIT External interrupt 0 IE0 TCON.1 EX0 IE.0 Timer0 overflow TF0 TCON.5 ET0 IE.1 External interrupt 1 IE1 TCON.3 EX1 Timer1 overflow TF1 TCON.7 Serial port SF1 External interrupt 2 External interrupt 3 INTERRUPT EN BIT FLAG INTERRUPT PRIORITY LOCATION CLEARED BY VECTOR hardware + software 03h 2 hardware + software 0Bh IE.2 3 hardware + software 13h ET1 IE.3 4 hardware + software 1Bh SCON1.7 ES1 IE.6 5 hardware + software 3Bh IE2 EXIF.0 EX2 EIE.0 6 hardware + software 43h IE3 EXIF.1 EX3 EIE.1 7 hardware + software 4Bh CID CIDF EXIF.2 ECID EIE.2 8 software 53h Divider overflow DIVF EXIF.3 EDIV EIE.3 9 hardware + software 5Bh Compare difference COMPF EXIF.4 ECOMP EIE.4 10 hardware + software 63h Watchdog timer WDIF WDCON.3 EWDI EIE.5 11 software 6Bh 1 (higest) (lowest) Ps: The flags marked as the italic font are not bit-addressable. The interrupt flags are sampled every machine cycle. In the same machine cycle, the sampled interrupts are polled and their priority is resolved. If certain conditions are met then the hardware will execute an internally generated LCALL instruction which will vector the process to the appropriate interrupt vector address. The conditions for generating the LCALL are 1. An interrupt of equal or higher priority is not currently being serviced. 2. The current polling cycle is the last machine cycle of the instruction currently being executed. 3. The current instruction does not involve a write to IP, IE, EIP or EIE registers and is not a RETI. If any of these conditions is not met, then the LCALL will not be generated. The polling cycle is repeated every machine cycle, with the interrupts being sampled in the same machine cycle. If an interrupt flag is active in one cycle but not responded to, and is not active when the above conditions are met, the denied interrupt will not be serviced. This means that active interrupts are not remembered. Note that every polling cycle is new. Execution continues from the vectored address until an RETI instruction is executed. On execution of the RETI instruction, the processor pops out the top content of Stack to the PC. The processor is not notified anything if the content of stack was changed. Note that a RET instruction would perform exactly the same process as a RETI instruction, but it would not inform the Interrupt Controller that the interrupt service routine is completed, and would leave the controller still thinking that the service routine is underway. - 40 - W925E/C240 6.8 Programmable Timers/Counters The W925E/C240 has 2 16-bit timer/counters. There are two 8-bit registers to perform a 16-bit counting register in every timer/counter. In timer/counter 0, TH0 is the upper 8 bits register and TL0 is the lower 8 bits register. Similarly, timer/counter 1 have two 8-bit registers, TH1 and TL1. Each timer/counter has 4 kind of clock sources which are Fosc/4, Fosc/64, Fosc/1024 and Fs. There are 3 operating modes in each timer/counter 0 and 1. The operating modes of timer/ counter0 is identical to timer/counter1. The overflow signal of each timer/counter is sampled at phase 2 in every system machine cycle, therefore when the system clock and the timer/counter clock both are from suboscillator, if the overflow frequency is higher than Fs/4 the overflow flag cannot be sampled correctly. Only one overflow flag can be sampled in a machine cycle others will be missed. MODE 0 In Mode 0, the timer/counters act as 13-bit timer/counters. The 13 bits consist of 8 bits of THx and lower 5 bits of TLx. The upper 3 bits of TLx are ignored. The negative edge of the clock causes the content of the TLx register to increase one. When the fifth bit in TLx moves from 1 to 0, then the count in the THx register is incremented. When the count in THx moves from FFh to 00h, then the overflow flag TFx is set. The counted input is enabled only if TRx is set and either GATE=0 or INTx =1. When C/ T is set to 0, then it will count clock cycles, and if C/ T is set to 1, then it will count 1 to 0 transitions on T0 (P3.4) for timer 0 and T1 (P3.5) for timer 1. When the 13-bit count reaches 1FFFh, the next count will cause it to rollover to 0000h. The timer overflow flag TFx of the relevant timer is set and if enabled an interrupts will occur. Note that when they are used as a timer, the bits of the CKCON1 select the time-base. MODE1 Mode 1 is similar to Mode 0 except that the counting register forms a 16-bit counter, rather than a 13 bit counter. TM0=CKCON1.2, CKCON1.3 (TM1=CKCON1.4, CKCON1.5) Fosc/4 Fosc/64 Fosc/1024 Fs T0 = P3.4 (T1 = P3.5) 00 01 10 11 mux M1,M0 = TMOD.1,TMOD.0 (M1,M0 = TMOD.5,TMOD.4) C/T = TMOD.2 (C/T = TMOD.6) 0 00 0 1 4 7 0 01 TL0 (TL1) TR0 = TCON.4 (TR1 = TCON.6) GATE = TMOD.3 (GATE = TMOD.7) INT0 = P3.2 (INT1 = P3.3) TFx PS: Functions of timer1 are shown in brackets 7 TH0 (TH1) Interrupt TF0 (TF1) Figure 6-5 Mode 0 & Mode 1 of Timer/Counter 0 & 1 - 41 - Publication Release Date: July 12, 2005 Revision A10 W925E/C240 MODE 2 Mode 2 is the Auto Reload Mode. In mode 2, TLx acts as an 8-bit count register, while THx holds the reload value. When the TLx register overflows from FFh to 00h, the TFx bit is set and TLx is reloaded with the content of THx, and the counting process continues from the reloaded TLx. The reload operation leaves the content of the THx register unchanged. Counting is controlled by the TRx bit and the proper setting of GATE and INTx pins. BUZZER In mode 2, timer 0 can be use to output an arbitrary frequency to the BUZ pin by programming bit6 and bit7 of CKCON2. BUZ pin can be configured as key tone (KT) output by setting BUZSL to high. When disable buzzer output by clearing ENBUZ to low, the BUZ output is in floating status. In the case where timer 0 clock input is FT, the desired frequency for BUZ output = FT / (255 – preset value + 1) / 2 (HZ). CKCON2.5, CKCON2.4 Low 512Hz TM0=CKCON1.2, CKCON1.3 (TM1=CKCON1.4, CKCON1.5) Fosc/4 Fosc/64 Fosc/1024 Fs T0 = P3.4 (T1 = P3.5) 1024Hz 2048Hz 00 01 10 11 mux 00 10 mux KT 11 Pin BUZ 1/2 C/T = TMOD.2 (C/T = TMOD.6) 0 FT TL0 (TL1) 0 1 CKCON2.6 CKCON2.7 =BUZSL =ENBUZ 01 From TM0 7 floating TFx Interrupt TF0 (TF1) TR0 = TCON.4 (TR1 = TCON.6) GATE = TMOD.3 (GATE = TMOD.7) INT0 = P3.2 (INT1 = P3.3) 0 7 TH0 (TH1) PS: Functions of timer1 are shown in brackets Figure 6-6 Mode 2 of Timer/Counter 0 & 1 When FT equals 32768 Hz, depending on the preset value of TM0, the BUZ pin will output a single tone signal in the tone frequency range from 64 Hz to 16384 Hz. The relation between the tone frequency and the preset value of TM0 is shown in the table below. - 42 - W925E/C240 Table 5 The relation between the tone frequency and the preset value of TM0 3rd octave Tone frequency C T O C D # D E # F F N E 4th octave TM0 preset value & BUZ frequency Tone frequency 5th octave TM0 preset value & BUZ frequency Tone frequency TM0 preset value & BUZ frequency 130.81 83H 131.07 261.63 C1H 260.06 523.25 E1H 528.51 138.59 8AH 138.84 277.18 C5H 277.69 554.37 E3H 564.96 146.83 90H 146.28 293.66 C8H 292.57 587.33 E4H 585.14 155.56 97H 156.03 311.13 CBH 309.13 622.25 E6H 630.15 164.81 9DH 165.49 329.63 CEH 327.68 659.26 E7H 655.36 174.61 A2H 174.30 349.23 D1H 348.58 698.46 E9H 712.34 # 185.00 A7H 184.09 369.99 D4H 372.35 739.99 EAH 744.72 G G# 196.00 ACH 195.04 392.00 D6H 390.08 783.99 EBH 780.19 207.65 B1H 207.39 415.30 D9H 420.10 830.61 ECH 819.20 A A 220.00 B6H 221.40 440.00 DBH 442.81 880.00 EDH 862.84 233.08 BAH 234.05 466.16 DDH 468.11 932.23 EEH 910.22 246.94 BEH 248.24 493.88 DF H 496.48 987.77 EFH 963.76 B # Note: Central tone is DB (440 Hz). WATCHDOG TIMER The Watchdog timer is a free-running timer that can be programmed by the user to serve as a system monitor, a time-base generator or an event timer. It is a set of dividers that divides the system clock. The divider output is selectable and determines the time-out interval. In the condition of the timer-out expiring, the WDT interrupt and WDT reset may be executed if the corresponding enables control bits are set. The interrupt will occur if the individual interrupt enable and the global enable are set. The interrupt and reset functions are independent of each other and may be used separately or together depending on the users software. Fsub Fosc 12 1 WD1,WD0 WDIF WFS(WDCON.4) 13 15 EWDI(EIE.5) 00 01 16 18 10 11 Reset Watchdog 19 21 WTRF Time-out selector RWT (WDCON.0) Interrupt 512 clock delay Reset Enable Watchdog timer reset EWT(WDCON.1) Figure 6-7 Watchdog Timer - 43 - Publication Release Date: July 12, 2005 Revision A10 W925E/C240 The Watchdog timer should first be restarted by using RWT. This ensures that the timer starts from a known state. The RWT bit is used to restart the watchdog timer. This bit is self-clearing, i.e. after writing a 1 to this bit the software will automatically clear it. The watchdog timer will now count clock cycles. The time-out interval is selected by the two bits WD1 and WD0 (CKCON.7 and CKCON.6). When the selected time-out occurs, the Watchdog interrupt flag WDIF (WDCON.3) is set. After the time-out has occurred, the watchdog timer waits for an additional 512 clock cycles. The software must issue a RWT to reset the watchdog before the 512 clocks have elapsed. If the Watchdog Reset EWT (WDCON.1) is enabled, then 512 clocks after the time-out, if there is no RWT, a system reset due to Watchdog timer will occur. This will last for two machine cycles, and the Watchdog timer reset flag WTRF (WDCON.2) will be set. This indicates to the software that the watchdog was the cause of the reset. When used as a simple timer, the reset and interrupt functions are disabled. The timer will set the WDIF flag each time the timer completes the selected time interval. The WDIF flag is polled to detect a time-out and the RWT allows software to restart the timer. The Watchdog timer can also be used as a very long timer. The interrupt feature is enabled in this case. Every time the time-out occurs an interrupt will occur if the global interrupt enable EA is set. Table 6 Time-out values for the Watchdog timer WATCHDOG INTERVAL WD1 WD0 0 0 2 0 1 2 1 0 2 1 1 2 NUMBER OF CLOCKS FOSC = 3.579545 MHZ FOSC = 32768 HZ RESET OF CLOCKS 12 4096 1.14 mS 0.125 S 4608 15 32786 9.15 mS 1S 33280 18 262144 73.23 mS 8S 262656 21 2097152 585.87 mS 64 S 2097664 The Watchdog timer will de disabled by a power-on/fail reset. The Watchdog timer reset does not disable the watchdog timer, but will restart it. In general, software should restart the timer to put it into a known state. The control bits that support the Watchdog timer are discussed below. WATCHDOG CONTROL WDIF: WDCON.3 - Watchdog Timer Interrupt flag. This bit is set whenever the time-out occurs in the watchdog timer. If the Watchdog interrupt is enabled (EIE.5), then an interrupt will occur (if the global interrupt enable is set and other interrupt requirements are met). Software or any reset can clear this bit. WTRF: WDCON.2 - Watchdog Timer Reset flag. This bit is set whenever a watchdog reset occurs. This bit is useful for determined the cause of a reset. Software must read it, and clear it manually. A Power-fail reset will clear this bit. If EWT = 0, then this bit will not be affected by the watchdog timer. EWT: WDCON.1 - Enable Watchdog timer Reset. This bit when set to 1 will enable the Watchdog timer reset function. Setting this bit to 0 will disable the Watchdog timer reset function, but will leave the timer running - 44 - W925E/C240 RWT: WDCON.0 - Reset Watchdog Timer. This bit is used to clear the Watchdog timer and to restart it. This bit is self-clearing, so after the software writes 1 to it the hardware will automatically clear it. If the Watchdog timer reset is enabled, then the RWT has to be set by the user within 512 clocks of the time-out. If this is not done then a Watchdog timer reset will occur. CLOCK CONTROL WD1, WD0: CKCON.7, CKCON.6 - Watchdog Timer Mode select bits. These two bits select the timeout interval for the watchdog timer. The reset time is longer 512 clocks time than the interrupt time-out value. 12 The default Watchdog time-out is 2 clocks, which is the shortest time-out period. The EWT, WDIF and RWT bits are protected by the Timed Access procedure. This prevents software from accidentally enabling or disabling the watchdog timer. More importantly, it makes it highly improbable that errant code can enable or disable the watchdog timer. 6.9 Serial Port 1 The P4.0 and P4.1 can be used as an 8-bit serial input/output port1. P4.0 is the serial port 1 clock I/O pin and P4.1 is the serial port 1 data I/O pin. The serial port 1 is controlled by SCON1 register which is described as below. SF1: Serial port 1 interrupt flag. When an 8-bits data are transit completely, SF1 is set by hardware. SF1 is cleared when serial interrupt1 routine is executed or cleared by software. REN1: Set REN1 from 0 to 1 to start the serial port1 to receive 8-bit serial data. SFQ: SFQ = 0 Serial clock output frequency is equal to fOSC /2 SFQ = 1 Serial clock output frequency is equal to fOSC / 256 SEDG: SEDG = 0 Serial data latched at falling edge of clock, SCLK=Low initially. SEDG = 1 Serial data latched at rising edge of clock, SCLK=High initially. CLKIO: CLKIO = 0 P4.0(SCLK) work as output mode CLKIO = 1 P4.0(SCLK) work as input mode SIO: SIO = 0 P4.0 & P4.1 work as normal I/O pin SIO = 1 P4.0 & P4.1 work as Serial port1 function Any instruction causes a write to SBUF1 will start the transmission of serial port 1. As the REN1 is from 0 to 1, the serial port 1 begins to receive a byte into SBUF1 in the frequency of the serial clock. REN1 could be cleared by software after receive function begins. The LSB is transmitted/ received first. The I/O mode of serial clock pin is controlled by CLKIO. User has to take care the initial state of the serial port pins. - 45 - Publication Release Date: July 12, 2005 Revision A10 W925E/C240 C1 C2 C3 C4 REN1 P4.0 SEDG=1, rising latch P4.0 SEDG=0, falling latch 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 SF1 P4.1 Data Input NOTE: The serial clock frequency is fosc/2 Figure 6-8 Timing of the Serial Port 1 Input Function C1 C2 C3 C4 Ins. serial out instruction P4.0 SEDG=1, falling changed P4.0 SEDG=0, rising changed 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 SF1 P4.1 Data output NOTE: The serial clock frequency is fosc/2 Figure 6-9 Timing of the Serial Port 1 Output Function - 46 - W925E/C240 6.10 Comparator A built-in comparator can compare the analog signal. There is an analog input paths from pin VNEG. Two reference inputs; one is from pin VPOS and other is from regulator output. When the voltage of positive input is higher than the negative input, the comparator output will be high. The RESEC(COMPR.3) is the result of the comparison. An internal rising signal on RESC produces interrupt flag of COMPF (EXIF.4). The flag COMPF is cleared when comparator interrupt routine is executed or cleared by software. Set COMPEN to enable the comparator function. VNEG(P4.2) D C3 VPOS(P4.4) RESC D CK CK EXIF.4 (COMPF) Clr Clr RESET REF1 REF COMPF=0 COMPEN X.XV REGULATOR EN SCON1.5(REGON) Figure 6-10 The Configuration of Comparator The output voltage of the regulator is tunable by 4 bits in regulator voltage control register (REGVC). When REGVC is equal to 0AH, the output voltage is 1.0V. The higher value of REGVC the lower voltage output of regulator. The adjustable voltage range is about from 0.72V to 1.48V. The variation of the voltage depends on the VDD. Following is the table of REGVC vs. regulator voltage. Regvc 00 01 02 03 04 05 06 07 08 09 0ah 0bh 0ch 0dh 0eh 0fh No 1.497 1.4464 1.3941 1.3426 1.2899 1.238 1.186 1.1352 1.081 1.029 0.976 0.924 0.869 0.815 0.762 0.7112 Loading(3V) No 1.500 1.449 Loading(5V) 1.397 1.345 1.292 1.241 1.188 1.137 1.083 1.031 0.978 0.925 0.87 0.816 0.763 0.712 6.11 DTMF Generator W925E/C240 provides a DTMF generator, which outputs the dual tone multi-frequency signal to the DTMF pin. The DTMF generator can work well at the operating frequency of 3.58MHz. A DTMF generator register DTMFG controls the DTMF output and specifies the desired low/high frequency. The tones are divided into two groups (low group and high group). When the generator is disable, the DTMF pin is in tri-state. The relation between the DTMF signal and the corresponding touch-tone keypad is shown in Figure 6-11. - 47 - Publication Release Date: July 12, 2005 Revision A10 W925E/C240 Row/Col Frequency R1 697 Hz R2 770 Hz R3 852 Hz R4 941 Hz C C1 1209 Hz C2 1336 Hz D C3 1477 Hz C4 1633 Hz C1 C2 C3 C4 R1 1 2 3 A R2 4 5 6 B R3 7 8 9 R4 * 0 # Figure 6-11 The Relation Between DTMF and Keypad Bit: 7 6 5 4 3 2 1 0 - DTGE HE LE L1 L0 H1 H0 Mnemonic: DTMFG Address: BAh L1 L0 H1 H0 SELECTED TONE x x x x x x x x 0 0 1 1 0 1 0 1 1209Hz 1336Hz 1477Hz 1633Hz 0 0 1 1 0 1 0 1 x x x x x x x x 697Hz 770Hz 852Hz 941Hz LE: Enable low group frequency output. HE: Enable high group frequency output. DTGE: Enable dual tone output to DTMF pin. 6.12 FSK Generator W925E/C240 provides a FSK generator, which outputs the FSK signal to the DTMF pin. The FSK output share with DTMF output pin. It can out FSK signal with 1200Hz baud rate of ITU-T V.23 or Bellcore 202 signal. A FSK transmit data register (FSKTB) specifies the desired output data. The FSK Transmit Control Register (FSKTC) can control whether the FSK signal will be output or not. The relation timing is shown in Figure 6-12 - 48 - W925E/C240 Enable signal (FTE) Auto clear Latch clock [FSF] Interrupt occur when rising edge Data latch Flag (FDS) Data (FSKTB) bit0 1 0 1 1 0 0 Hi-Z FSK Signal (DTMF pin) Hi-Z 1 0 1 1 0 833us Figure 6-12 FSK Modulator FSK TRANSIMT CONTROL REGISTER Bit: (initial = 00H) 7 6 5 4 3 2 1 0 FTE FTM FDS - - - LO1 LO0 Mnemonic: FSKTC Address: C6h FTE: FSK transmit Enable. Enable = 1, Disable = 0 FTM: FSK signal Standard. Bellcore 202 = 1, V.23 = 0 FDS: FSK data sending status LO0, LO1: FSK transmit level option FSK output level LO1 LO0 150mV 0 0 120mV 0 1 95mV 1 0 75mV 1 1 FSK TRANSMIT DATA BUFFER Bit: 7 (initial=00H) 6 5 4 3 2 1 0 FSKTB.7 FSKTB.6 FSKTB.5 FSKTB.4 FSKTB.3 FSKTB.2 FSKTB.1 FSKTB.0 Mnemonic: FSKTB Address: C7h FSKTB.0:Only this bit will be latched and send out as FSK signal - 49 - Publication Release Date: July 12, 2005 Revision A10 W925E/C240 When FTE enable will set the FDS to high to enable the internal latch clock in 1200Hz. When FDS is in high state, FSKTB bit0 will be sent out by FSK modulator at the rising edge of latch clock. FDS could be cleared by software to inform no more data will be sent out after the last bit is sent completely. If the FDS is cleared then FTE will become low at next rising latch clock to disable FSK modulator and clear FDS by hardware automatically. When FTE is set, FSK modulation flag (FSF) will be set at every rising edge of latch clock to produce an interrupt shared with CID interrupt routine. If a CID interrupt occurs, user can check FSF to know if this interrupt is caused by FSK modulator. The only way to stop FSK signal immediately is to disable FTE by software. 6.13 I/O Ports There are five 8-bits ports named from P0 to P4 in W925E/C240. All ports can be configured as input or output mode. Except P0, every port has pull high resistor enable/disable by PxH register. After reset the initial state of each port is in input mode and the value of the registers from P0 to P3 are FFh. The I/O port is described as below: P0: I/O mode is controlled by P0IO. Only P0 output as open drain mode and without pull high resistor. P1: I/O mode is controlled by P1IO. Pull high is controlled by P1H. P1.0~P1.3 work as INT2, P1.4~P1.7 work as INT3. Falling edge on P1 pins to produce INT2 and INT3 flag. P1 is configured as INT2/INT3 by P1EF register. P2: I/O mode is controlled by P2IO. Pull high is controlled by P2H. P3: I/O mode is controlled by P3IO. Pull high is controlled by P3H. P3.5 T1 Timer/counter 1 external count input P3.4 T0 Timer/counter 0 external count input P3.3 INT1 External interrupt 1 P3.2 INT0 External interrupt 0 P4: I/O mode is controlled by P4IO. Pull high is controlled by P4H. Special function of P4 is described below. P4.7-5 I/O Normal I/O P4.4 VPOS Positive input of the comparator P4.2 VNEG Negative input of the comparator P4.1 SDATA Serial port output P4.0 SCLK Serial port input 6.14 Divider A built-in 13/14-bit binary up counter designed to generate periodic interrupt. The clock source is from sub-oscillator. When the frequency of sub-crystal is 32768Hz, it provides the divider interrupt in the period of 0.25/0.5 second. Bit DIVS controls the degree of divider. When DIVA is high to enable the divided counter, when DIVA is low to reset divider and stop counting. As the divider overflows, the divider interrupt flag DIVF is set. DIVF is clear by software or serving divider interrupt routine. - 50 - W925E/C240 DIVS (CKCON1.1) overflow D ck CR Fs 1 Q DIVF (EXIF.3) 13 14 Executing DIV Int Clear by software DIVA (DIVC.0) Figure 6-13 13/14-bit Divider 6.15 Calling Identity Delivery (CID) W925E/C240 provides type I and type II of CID system. Type I is on-hook calling with CID message and type II is off-hook call on waiting. The CID function includes FSK decoder, dual tone alert signal detector, ring detector and DTMF receiver. The FSK demodulation function can demodulate Bell 202 and ITU-T V.23 Frequency Shift keying (FSK) with 1200-baud rate. The Tone Alert Signal detect function can detect dual tones of Bellcore Customer Premises Equipment(CPE) Tone Alerting Signal(CAS) and BT Idle State and Loop State Tone Alert Signal. The line reversal for BT, ring burst for CCA or ring signal for Bellcore can be detected by ring detector. It is compatible with Bellcore TRNWT-000030 & ST-TSV-002476, British Telecom(BT) SIN227, U.K. Cable Communications Association(CCA) specification. The DTMF receiver can be programmed as DTMF decoder to decode 16 DTMF signals or tone detector to detect the signal which frequency is in DTMF band. The tone detector can be an auxiliary detector to improve the performance of detecting tone-alerting signal(CAS), said as talk down-off, in type II system. The FSK decoder, alert tone detector and DTMF receiver can be enable/disable individually by the bits of FSKE, CASE and DTMFE in FSK DATA REGISTER(FSKDR). CIDE is the global control bit to enable/disable FSK decoder, alert tone detector and DTMF receiver. However, the ring detector is always active. - 51 - Publication Release Date: July 12, 2005 Revision A10 W925E/C240 DTMFE CIDGA CIDGD High Tone PGD <7:4> INP2 INN2 Bandpass Input Pre-processor + - PGAF <3:0> Anti-alias Filter High Tone Detector Filter Guard Time Timer PHAD<3:0> Low Tone PGD <3:0> ESt Decode data and Latch Low Tone Detector Bandpass Filter GCFB2 DTMFD DD3-DD0 DTMFPT/DTMFAT FSKE FDATA FSK Demodulation Circuit FSK Bandpass Filter Input Pre-processor INP1 + INN1 - PGAF <7:4> FSK Data Output Interface FSK Demodulator PHFL<7:4> Anti-alias Filter FSK Carrier Detector CASE FD7-FD0 FDR FCD PHFL<3:0> GCFB1 To internal circuit VREF CAP Bias Voltage Generator Dual Tone Alert Signal Detection Circuit Bandpass High Tone Detector Filter PHAD<7:4> CIDE,RST VADD High Tone Low Tone Bandpass Filter Interrupt Generator Low Tone Detector Clock Driver VASS Guard Time Circuit CASPT/CASAT Ring Detector To internal circuit Fm ALGO RNG RNGDI RNGRC PS: The signals noted in italic and underline type are CID pins on the chip. Figure 6-14 The CID Block Diagram - 52 - W925E/C240 Ring Detector The application circuit in Figure 6-15 illustrates the relationship between the RNGDI, RNGRC and RNG signals. The combination of RNGDI and RNGRC is used to detect an increase of the RNGDI voltage from ground to a level above the Schmitt trigger high going threshold voltage VT+. C1=0.1uF R1=470K Tip/A R3=200K C1=0.1uF RNGDI R4=300K Ring/B R2=470K R5=150K RNGRC RNG C3=0.22uF Allowance minimal ring voltage (peak to peak) is: Vpp (max ring) = 2 (VT+(max) (R1 + R3 + R4) / R4 + 0.7) Tolerance to noise between Tip and Ring and VSS is: Vpeak (max noise) = VT+(min) (R1 + R3 + R4) / R4 + 0.7 R5 from 10K ohm to 500K ohm. C3 from 47 nF to 0.68 uF. Time constant is: T = R5 C3 ln [VDD / (VDD - VT+ )] VT+(min) <= VT+ <= VT+(max) Figure 6-15 Application Circuit of the Ring Detector The RC time constant of the RNGRC pin is used to delayed the output pulse of the RNG flag for a low going edge on RNGDI. This edge goes from above the VT+ voltage to the Schmitt trigger low going threshold voltage VT-. The RC time constant must be greater than the maximum period of the ring signal, to ensure a minimum RNG high interval and to filter the ring signal to get an envelope output. The rising signal of RNG will set the bit RNGF(CIDFG.0) high to cause the CID flag(CIDF) high. The diode bridge shown in Figure 6-15 works for both single ended ring signal and balanced ringing. The R1 and R2 are used to set the maximum loading and must be of equal value to achieve balanced loading at both the tip and ring line. R1, R3 and R4 form a resistor divider to supply a reduced voltage to the RNGDI input. The attenuation value is determined by the detection of minimal ring voltage and maximum noise tolerance between tip/ring and ground. - 53 - Publication Release Date: July 12, 2005 Revision A10 W925E/C240 Input Pre-Processor The input signal is processed by Input Pre-Processor, which is comprised of two OP amps and a bias source(VREF). The gain OP-amps are used to bias the input voltage with the VREF signal voltage. VREF is VAD/2 typically, this pin is recommended to connect a 0.1uF capacitor to VAS. The gain adjustable OP amps are sued to select the input gain by connecting a feedback resistor between GCFB and INN pins. Figure 6-16 shows the differential input configuration and Figure 6-17 shows the single-ended configuration. C1 R3 0.1uF R4 R1 VREF INP INN C2 R2 R5 Differential Input Amplifier C1 = C2 R1 = R2 R3 = (R4 R5) / (R4 + R5) + - GCFB Voltage Gain Av = R5 / R1 Input Impedance 2 2 Zin = 2 R1 + (1 / wC) Figure 6-16 Differential Input Gain Control Circuit 0.1uF C VREF INP R1 22n INN R2 + - GCFB Voltage Gain Av = R2 / R1 Figure 6-17 Single-Ended Input Gain Control Circuit - 54 - W925E/C240 CAS/DTAS Detection In off-hook services (type II), the detection of CAS/DTAS will affect the quality of the call waiting service. When the CAS/DTAS is sent from far end, sometimes the near end user maybe still talking. The CPE must be able to detect the CAS/DTAS successfully in the presence of near end speech. To detect CAS/DTAS from telephone hybrid receiver pair improves the detection. However, in BT’s onhook CID system the CAS/DTAS detection is from Tip/Ring pair. The dual tone alert signal is separated into high and low tones and detected by a high/low tone detector. When the alert tone is recognized by the detector, the bit ALGO will go high and the rising signal will set the bit ALGOF in CIDFG to produce the CID flag(CIDF). Figure 6-18 shows the guard time waveform of detecting alert tone. The total recognition time is tREC=tDP+tGP, where tDP is the tone present detect time and tGP is the tone present guard time. The total absent guard time is tABS=tDA+tGA where tDA is the tone absent detect time and tGA is the tone absent guard time. The tone present/absent guard time is determined by guard-time timer, which the input clock period is 0.858mS. When the alert tone is detected, the internal signal ALGR will be set and the rising edge of ALGR resets the guard-time timer and the timer starts up counting from 00H. As the content of the timer is the same as the register CASPT, the timer stops counting and the bit ALGO will be set and the rising edge of ALGO triggers the flag ALGOF to become high. The counting of tone absent time is similar to the counting of tone present time but the falling edge of ALGR/ ALGO replaces the rising edge and the CASAT replaces the CASPT. The bit ALGO is controlled by hardware only. The flag ALGOF is set by rising edge of ALGO and cleared by software. Vin Dual Alert Tone Signal t DA t DP t DA t DP ALGR* t GA t GP ALGO + ALGOF t REC 1 t ABS 2 3 3 1 1: Guard time timer is reset and starts to up count from 00H. 2: Guard time timer is reset and starts to up count from 00H. 3: The content of the guard-time timer reaches the content of ASPT/ASAT. *ALGR is an internal signal in the uC. + Clear by software. Figure 6-18 Guard Time Waveform of Alert Tone Signal Detection - 55 - Publication Release Date: July 12, 2005 Revision A10 W925E/C240 DTMF Decoder The DTMF decoder shares the same input pre-processor with FSK decoder. The dual tone is separated into low group and high group by two SCFs (switched capacitor filter. The method of DTMF detection is the same as alert tone detection. The present/absent guard time is adjusted by registers DTMFPT/DTMFAT. As the DTMF signal is recognized and decoded, the bit DTMFD will be set and the decoded DTMF data is stored in bit0 to bit3 of register DTMFDR. The rising edge of DTMFD produces the flag DTMFDF. The bit DTMFD is controlled by hardware only. The flag DTMFDF is set by rising edge of DTMFD and cleared by software. Vin (Tip/ring) TONE #n t DA t DP ESt * t GP t GA t REC t ABS DTMFD DTMFDF DTMFDR + Tone #n-1 Tone #n 1 2 3 3 1: Guard time timer is reset and starts to up count from 00H. 2: Guard time timer is reset and starts to up count from 00H. 3: The content of the up counting timer reaches the register DTMFPT/DTMFAT. * ESt is an internal signal in the circuit. + Clear by software. Figure 6-19 The Waveform of DTMF Detection Tone Detector In off-hook state, said type II system, detecting tone alert signal(CAS) is easily interfered by human’s voice or other noise in voice band. Sometimes the interference makes falsely recognizing a noise as a CAS(talk-off), or lost detecting a real CAS(talk-down). The DTMF can be programmed as a tone detector by setting bit 4 of DTMFR2. The frequency band of the tone detector is DTMF frequency from 697Hz to 1633Hz. Once the tone detector gets signals in the band, the bit of DTMFH or DTMFL in register DTMFDR will become high immediately. User can poll these 2 bits to check if the tone exists on the tip/ring. The input gain of tone detector is the same as DTMF receiver. - 56 - W925E/C240 FSK Decoder The FSK carrier detector provides an indication of the present of a signal within the FSK frequency band. If the output amplitude of the FSK band-pass filter is sufficient to be detected continuously for 8 mS, the FSK carrier detected bit FCD will go high and it will be released if the FSK band-pass filter output amplitude is not able to be detected for greater than 8 mS. The 8 mS is the hysteresis of the FSK carrier detector. Figure 6-20 shows the timing of FSK carrier detection. Tip/Ring t FSKE FSKE Analog FSK Signal Note Analog FSK Signal t CA t CP t CA t CP FCD Figure 6-20 FSK Detection Enable and FSK Carrier Present and Absent Timing The FSK demodulation function can demodulate Bell 202 and ITU-T V.23 Frequency Shift keying (FSK) with 1200-baud rate. When the decoder receives the FSK serial data, the serial data will be demodulated into bit FDATA with 1200-baud rate in the mean time the synchronous clock signal is output to the bit FCLK. As the decoder receives one byte, the internal serial-to-parallel circuit sets the bit FDR and converts the 8-bit serial data into the byte register FSKDR. The rising edge of bit FDR will set the flag FDRF to produce CID interrupt but FDRF is cleared by software. User can get the FSK data by reading register FSKDR or sampling the bit FDATA. The timing of FSK demodulation is shown in Figure 6-21. Tip/Ring 1* 1 0 stop 1st byte data start b0 b1 b2 b3 b4 b5 b6 b7 1* 1 0 stop start 2nd byte data start b0 b1 b2 b3 b4 b5 b6 b7 1 0 b0 t IDD 1st byte data start FDATA b0 b1 b2 b3 b4 b5 stop b6 b7 2nd byte data start b0 b1 b2 b3 b4 stop start b5 b6 b7 1/fDCLK0 FCLK tCRD t RH FDR + FDRF FSKDR 1st byte data 2nd byte data * Mark bit or redundant stop bit(s), will be omitted. + Clear by software. Figure 6-21 Serial Data Interface Timing of FSK Demodulation - 57 - Publication Release Date: July 12, 2005 Revision A10 W925E/C240 CID Input Gain Control The CID input gain and input hysteresis are controllable by internal CID gain control registers. CIDGD and CIDGA registers determine the 6 internal CID gain control registers. CID gain control data register (CIDGD) presents the data bus. The lower 3 bits of CID gain control address register (CIDGA) present the address. The rising edge of CIDGA.4 will latch the CIDGD in the corresponding internal CID gain control register. The 6 internal CID gain control registers are addressed as following table. Setting the 6 registers as the suggestion value guarantees the CID spec. ADDRESS (CIDGA.2-0) Ê INTERNAL CID GAIN CONTROL REGISTER SUGGESTION VALUE 000 DTMFR1: DTMF register1 0000 0001B 001 DTMFR2: DTMF register2 011X 0001BÊ 002 PGAF: Programmable gain control alert tone and FSK 99H 003 PGAD: Programmable gain control DTMF A7H 004 PHAD: Programmable hysteresis alert tone and DTMF 35H 005 PHFL: Programmable hysteresis FSK and low pass filter 33H X = 0 DTMF receiver works a DTMF decoder, X=1 DTMF receiver works as a tone detector. The signals to set internal CID gain control registers is shown in Figure 6-22 CIDGA CIDGA<2:0> CIDGD CIDGD CIDGA.3 Rising latch Figure 6-22 Internal CID Gain Control Register Setting Waveform DTMFR1 DTMFR1[7:4] are reserved bits and must be 0000b. BIT3~BIT0 ACCEPTABLE ERROR PERCENTAGE TO SAMPLE 4 PERIOD OF ROW FREQ. 0000 0.6% (default) 0001 2.5% 001X 3.5% 01XX Reserved 1XXX Reserved - 58 - W925E/C240 DTMFR2 BIT3~BIT0 0000 0001 001X 01XX 1XXX ACCEPTABLE ERROR PERCENTAGE TO SAMPLE 4 PERIOD OF COL FREQ. 0.5% (default) 1.5% 2.5% Reserved Reserved The acceptable error percentage may have small variation by different test environments. DTMFR2.4 = 0 DTMFR2.4 = DTMF receiver works as a DTMF receiver DTMF receiver works as a tone detector DTMFR2.5 = 0 DTMF PT counter is up counter type, detected frequency changed does not effect counter DTMF PT counter is up counter type, detected frequency changed resets DTMF PT counter DTMFR2.5 = 1 DTMFR2.6 = 0 DTMFR2.6 = 1 DTMF AT counter is up-down counter type, up counting when no DTMF detected, down counting if DTMF detected again. DTMF AT counter is up counter type, up counting when no DTMF detected, pause counting if DTMF detected again. DTMFR2.7: reserved There are 4 programmable gain arrays, shown in Figure 6-14, are determined by Low/High nibbles of PGxx. The following table lists the input gain corresponding to the value of L/H nibble of PGxx. X 20 LOG((40+15*X)/(230-(40+15*X))) DB X 0 1 2 3 4 5 -13.53 -10.05 -7.18 -4.64 -2.28 0.00 6 7 8 9 10 20 LOG((40+15*X)/(230-(40+15*X))) DB 2.28 4.64 7.18 10.05 13.53 X is the value of L/H nibble of PGxx There are 4 programmable hysteresis input buffer, shown in Figure 6-14, are determined by Low/ High nibbles of PHxx. The hysteresis control formulas are list below. Alert tone hysteresis DTMF hysteresis FSK hysteresis FSK detector hysteresis HAT = 13mv + 3mv*X HDTMF = 6mv + 3mv*X HFSK = 13mv + 3mv*X HFSKD = 13mv + 3mv*X - 59 - X = PHAD<7:4> X = PHAD<3:0> X = PHFL<7:4> X = PHFL<3:0> Publication Release Date: July 12, 2005 Revision A10 W925E/C240 7. APPLICATION CIRCUIT The analog interface circuit of W925E/C240 shown in Figure 7-1 is a typical CPE system. The gain control op-amp is set to unit gain to allow the electrical characteristics to be met in this application circuit. 22nF Tip/A 430K 34K INP2 INN2 22nF Ring/B 430K 464K 34K 60K4 53K6 VREF 0.1uF 0.1uF RNGDI 470K 150K 100K 464K 464K Microphone Tip Ring Tx+ Tx- Speech Network CAP 470K 200K 0.1uF GCFB2 60K4 RNGRC 0.47u 60K4 INP1 22nF INN1 Rx+ RxSpeaker 464K 22nF Resistor must have 1% tolerance Resistor must have 5% tolerance Figure 7-1 Application Circuit of CID - 60 - 464K GCFB1 W925E/C240 Application Environment There are three major timing differences for CID sequences, Bellcore, BT and CCA. Figure 7-2 is the timing diagram for Bellcore on-hook data transmission and Figure 7-3 is the timing diagram for the Bellcore off-hook data transmission. Figure 7-4 is the timing diagram for the BT caller display service on-hook data transmission and Figure 7-5 is the timing diagram for the BT caller display service offhook data transmission. Figure 7-6 is the timing diagram for the CCA caller display service for on-hook data transmission. The CID flag (CIDF) must be cleared by software when each time the CID interrupt routine is serviced. The CID global enable signal (CIDE) must be set high. Tip/Ring 1st Ring A CIDF Ch. seizure B C Mark D Message E ... ... ... ... 2nd Ring F RNG FSKE FCD FDR FCLK FDATA ...101010... Data A = 2 sec typical B = 250-500mS C = 250mS D = 150mS E = depend on data length MAX C+D+E = 2.9 TO 3.7 sec F >= 200mS Figure 7-2 Input and Output Timing of Bellcore On-hook Data Transmission - 61 - Publication Release Date: July 12, 2005 Revision A10 W925E/C240 CPE goes off-hook CPE unmutes handset and enable keypad CPE mutes handset & disables keypad CPE sends Tip/Ring CAS A Mark ACK B C D E Message F G ASE ... CIDF t REC t ABS ALGO FSKE FCD FDR ... FCLK FDATA Data A = 75 - 85mS B = 0 - 100mS C = 55 - 65mS D = 0 - 500mS E = 58 - 75mS F = depends on data length G <= 50mS Figure 7-3 Input and Output Timing of Bellcore Off-hook Data Transmission - 62 - W925E/C240 Line Reversal Alert Signal A/B Wires A Ch. Seizure B C D Mark Message E F Ring G RNGON ASE ... CIDF ALGO TE DC load TE AC load ... t ABS t REC 15 < 120uA 50 - 150 ms 1 ms < 0.5 mA (optiona) Current wetting pulse (Refer to SIN227) 20 5 ms Note 1 Zss (Refer to SIN227) Note 2 FSKE Note 3 FCDN FDRN ... ... DCLK DATA ...101010... Data A >= 100mS B = 88 - 100mS C >= 45mS (up to 5Sec) D = 80 - 262mS E = 45 - 75mS F <= 2.5S (500mS typical) G >= 200mS Figure 7-4 Input and Output Timing of BT Idle State (On-hook) Data Transmission Note: 1. SIN227 specifies that the AC and DC loads should be applied at 20 ± 5mS after the end of the dual tone alert signal. 2. SIN227 specifies that the AC and DC loads should be removed between 50 – 150mS after the end of the FSK signal. 3. The FSKE bit should be set low to disable the FSK decoder when FSK is not expected. The tone alerting signal speech and the DTMF tones are in the same frequency band as the FSK signal. - 63 - Publication Release Date: July 12, 2005 Revision A10 W925E/C240 CPE goes off-hook Start Point Tip/Ring CPE sends ACK CAS A Note 1 CPE unmutes handset and enable keypad CPE mutes handset & disables keypad B D C Mark E F Message G H Note 3 ASE ... CIDF t REC t ABS ALGO FSKE Note 2 Note 5 Note 4 FCD FDR ... FCLK FDATA Data A = 40 - 50mS B = 80 - 85mS C <= 100mS D = 65 - 75mS E = 5 - 100mS F = 40 - 75mS G = depends on data length H <= 100mS Figure 7-5 Input and Output Timing of BT Loop State (Off-hook) Data Transmission Notes: 1. In a CPE where AC power is not available, the designer may choose to switch over to line power when the CPE goes off-hook and use battery power while on-hook. 2. The FSKE bit may be set low to prevent the alert tone, speech or other FSK in-band noise decoded by FSK demodulator and give false data when the dual tone alert signal is expected. If the FSKE pin cannot controlled by microcontroller, the FSKE bit must always placed in high state and the micro controller must give up the FSK decoded data when the FSK signal is not expected. 3. The exchange will have already disabled the speech path to the distant customer in both transmission directions. 4. The FSKE should be set high as soon as the CPE has finished sending the acknowledge signal ACK. 5. The FSKE may be set low after the last byte (check sum) has been decoded or FCD has become inactive. 6. In an unsuccessful attempts where the exchange does not send the FSK signal, the CPE should disable FSKE, un-mute the handset and enable the keypad after this interval. - 64 - W925E/C240 Line Reversal A/B Wires Ring Burst A First Ring Cycle B Ch. Seizure C Mark D Message E F RNG CIDE Note 4 ... CIDF ... 50 - 150 ms TE DC load 250 - 400 ms TE AC load FSKE Note 2 Note 3 Note 1 FCD FDR ... ... FCLK FDATA ...101010... Data A = 200 - 450mS B >= 500mS C = 80 - 262mS D = 45 - 262mS E <= 2.5sec (500ms typical) F >= 200mS Figure 7-6 Input and Output Timing of CCA Caller Display Service Data Transmission Notes: 1. The CPE designer may choose to set FSKE always high while the CPE is on-hook and the FSK signal is expected. 2. TW/P & E/312 specifies that the AC and DC loads should be applied between 250 - 400 mS after the end of the ring burst. 3. TW/P & E/312 specifies that the AC and DC loads should be removed between 50 - 150 ms after the end of the FSK signal. 4. The CID may not be enable up at the first ring cycle after the FSK data had been processed. - 65 - Publication Release Date: July 12, 2005 Revision A10 W925E/C240 8. ELECTRICAL CHARACTERISTICS 8.1 Absolute Maximum Ratings* (Voltage referenced to VSS pin) PARAMETER SYMBOL RATING UNITS VDD -0.3 to 6 V -0.7 to VDD + 0.7 V 0 to 10 MA -65 to 150 °C Supply Voltage with respect to VSS Voltage on any pin other than supplies (note 1) Current at any pin other than supplies Storage Temperature Tst Note: *. Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the lift and reliability of the device. 1. VDD +0.7 should not excess maximum rating of supply voltage. 8.2 Recommended Operating Conditions CHARACTERISTICS Power Supplies (Analog) SYMBOL RATING UNIT VAD 3.0 to 6.0 V Power Supplies (Digital) EEPROM(E) type(Depend on option) VDD MASK(C) type 2.4 to 3.6 or 3.0 to 5.5 2.2 to 6.0 V Main Clock Frequency fOSC 3.579545 MHz Sub Clock Frequency fSUB 32768 Hz Tolerance on Clock Frequency ∆fC -0.1 to +0.1 % Operation Temperature Top 0 to 75 °C - 66 - W925E/C240 8.3 DC Characteristics PARAMETER Operating Current SYM. CONDITION MIN. TYP. MAX. UNIT IOP1 FSK On, dual clock, normal run 2.8 mA IOP2 FSK Off, dual clock, normal run 1.3 mA IOP3 FSK off, slow run, main osc stopped 50 uA IOP4 Idle mode, dual clock 500 uA IOP5 Idle mode, main osc stopped 50 uA IOP6 Power down mode 1 uA I/O Ports Input High Voltage VIH 0.7VDD VDD V I/O Ports Input Low Voltage VIL VSS 0.3VDD V I/O Ports Output High Voltage VOH IOH = 2.0 mA 2.4 - - V I/O Ports Output Low Voltage VOL IOL = 2.0 mA - - 0.4 V BUZ Pin Output High Voltage VBOH IOH = 3.5 mA 2.4 - - V BUZ Pin Output High Voltage VBOL IOL = 3.5mA 0.4 - - V DTMF Output DC Level VTDC RL = 5KΩ, VDD = 2.5-3.8 1.1 - 2.8 V DTMF Distortion DTHD RL = 5KΩ, VDD = 2.5-3.8 - -30 -23 dB VTO Low group, RL = 5KΩ 130 150 170 mV rms 1 2 3 dB DTMF Output Voltage Pre-emphasis FSK Output DC Level FSK Distortion FSK Output Voltage Col/Row VFDC RL = 5KΩ, VDD = 2.5-3.8 1.1 - 2.8 V FTHD RL = 5KΩ, VDD = 2.5-3.8 - - -30 dB 75 150 170 mV rms VFD RL = 5KΩ - 67 - NOTE Publication Release Date: July 12, 2005 Revision A10 W925E/C240 DC Characteristics, continued PARAMETER SYM. CONDITION MIN. TYP. MAX. UNIT 100 360 1000 KΩ Port Pull High Resistor RPH Schmitt Input High Threshold VT+ RNGDI, RNGRC 0.48VAD - 0.68VAD V Schmitt Input High Threshold VT- RNGDI, RNGRC 0.28VAD - 0.48VAD V Schmitt Hysteresis VHYS RNGDI, RNGRC RNGRC Low Sink Current IRNGL RNGRC Input Current IIN 0.2 V 2.5 INPx, INNx, RNGDI mA - - 1 µA Reference Output voltage VREF VREF 0.5VAD –4% - 0.5VAD + 4% V Reference Output Resistance RREF VREF - - 2 KΩ 8.4 NOTE No load Electrical Characteristics - Gain Control OP-Amplifier (Electrical characteristics supersede the recommended operating conditions unless otherwise stated.) PARAMETER SYM. Input Leakage Current IIN Input Resistance RIN Input Offset Voltage VOS Power Supply Rejection Ratio PSRR Maximum Capacitive Load (GCFBx) CL Maximum Resistive Load (GCFBx) RL MIN. TYP‡ MAX. UNITS 1 10 VSS ≤ VIN ≤ VDD MΩ 25 40 mV dB 100 50 µA TEST CONDITIONS 1 kHz 0.1 Vpp ripple on VDD pF kΩ Note: "‡" Typical figure are at VDD = 5V and temperature = 25 ℃ are design aids only, not guaranteed and not subject to production testing. - 68 - W925E/C240 8.5 AC Characteristics (AC timing characteristics supersede the recommended operating conditions unless otherwise stated.) Dual Tone Alert Signal Detection Interface PARAMETER SYMBOL MIN. TYP. MAX. UNITS Low Tone Frequency fL 2130 Hz High Tone Frequency fH 2750 Hz NOTES Frequency Deviation accept 1.1 % 3 Frequency Deviation reject 3.5 % 4 Maximum Input Signal Level a dBm 0.22 Input Sensitivity Per Tone -40 -38 Reject Signal Level Per Tone -48 b Positive and Negative Twist Accept Noise Tolerance SNRTONE dBm 5 dBm 5 7 dB 20 dB 1, 2 Notes: a. dBm = decibels with a reference power of 1 mW into 600 ohms, 0 dBm = 0.7746 Vrms. b. Twist = 20 log (fH amplitude / fL amplitude). 1. Both tones have the same amplitude. Both tones are at the nominal frequencies. 2. Band limited random noise 300 - 3400 Hz. Present only when tone is present. 3. Range within which tones are accepted. 4. Ranges outside of which tones are rejected. 5. These characteristics are at VDD = 5V and temperature = 25 °C. Dual Tone Alert Signal Detection PARAMETER Alert Signal Present Detect Time Alert Signal Absent Detect Time CONDITION ALGR TYP‡ MAX. UNITS NOTES SYM. MIN. tDP 0.5 10 mS tDA 0.1 8 mS "‡" Typical figure are at VDD = 5V and temperature = 25 °C are design aids only, not guaranteed and not subject to production testing. - 69 - Publication Release Date: July 12, 2005 Revision A10 W925E/C240 FSK Detection Interface PARAMETER SYMBOL MIN. TYP MAX. UNITS NOTES Bell 202 Mark (logic 1) fMark 1188 1200 1212 Bell 202 Space (logic 0) fSpace 2178 2200 2222 ITU-T V.23 Mark (logic 1) fMark 1280.5 1300 1319.5 +/- 1.5 % ITU-T V.23 Space (logic 0) fSpace 2068.5 2100 2131.5 +/- 1.5 % Input Frequency Detection Maximum Input Signal Level -5.78 Input Sensitivity -43 Transmission Rate SNRTONE Hz +/- 1 % dBm dBm 1188 Input Noise Tolerance +/- 1 % 1200 1212 20 1, 3 baud dB 1, 2 Notes: 1. Both mark and space have the same amplitude. Both mark and space are at the nominal frequencies. 2. Band limited random noise 300 - 3400 Hz. Present only when FSK signal is present. 3. These characteristics are at VDD = 5V and temperature = 25 °C. FSK Detection PARAMETER UNITS NOTES FSKE tFSK 25 mS tCP 25 mS Input FSK to FCD High Delay FCD Input FSK to FCD Low Delay Data Ready ACK Time FDR Rate DATA Input FSK to DATA Delay Frequency DCLK High Time Low Time DCLK to FDR Delay MAX. SYM. FSK Detection Enable Time DCLK, FDR MIN. TYP‡ CONDITION tCA 8 tDR 415 416 417 US 2 1188 1200 1212 BpS 1 1 5 mS tIDD mS fDCLK 1201.6 1202.8 1204 Hz 2 tCH 415 416 417 US 2 tCL 415 416 417 US 2 tCRD 415 416 417 US 2 Notes: 1. FSK input data rate at 1200 +/- 12 baud. 2. OSCI frequency at 3.579545 MHz +/- 0.1%. "‡" Typical figure are at VDD = 5V and temperature = 25 °C are design aids only, not guaranteed and not subject to production testing. - 70 - W925E/C240 DTMF Decoder PARAMETER SYMBOL MIN. MAX. UNITS NOTES 1 dBm 1, 2 7 dB 1, 2 Frequency Deviation accept 1.5 % 1, 2 Frequency Deviation reject 3.5 % 1, 2 Input Sensitivity per tone TYP. -29 Positive and negative twist accept 3rd Tone Tolerance -16 dB 1, 2, 3 Noise Tolerance -12 dB 1, 2, 3 dB 1, 2, 4 Dial tone Tolerance 22 Notes : 1. signal consists of all DTMF tones. 2. Tone duration is 40 mS at least, tone pause duration is 40 mS at least. 3. Referenced to the lowest level frequency component in DTMF signal. 4. Referenced to the minimum valid accept level. DTMF Detection Interface PARAMETER DTMF present detect time DTMF absent detect time CONDITION Est TYP‡ MAX. UNITS 0.5 8 mS tFA 0.1 8 mS 40 SYM. MIN. tFP DTMF Detected Duration DTMFD = 1 tDD DTMF Signal Ignore Time DTMFD = 0 tDI DTMF Pause Accept Time DTMFD = 1 tDPA mS 20 20 NOTES mS mS "‡" Typical figure are at VDD = 5V and temperature = 25 °C are design aids only, not guaranteed and not subject to production testing. - 71 - Publication Release Date: July 12, 2005 Revision A10 W925E/C240 9. PACKAGE DIMENSION 100L QFP (14 x 20 x 2.75mm footprint 4.8mm) HD D E e H E b c A2 Seating Plane A θ A1 See Detail F L y L Controlling dimension : Millimeters Symbol A A A b c D E e H H L L y θ 1 2 Dimension in inch Min 0.010 Nom Dimension in mm Max Min 0.014 0.018 0.101 0.107 0.113 2.57 0.25 0.008 0.012 0.016 0.004 0.006 0.008 0.547 0.551 0.45 2.87 0.20 0.30 0.40 0.10 0.15 0.20 0.555 13.90 14.00 14.10 19.90 20.00 20.10 0.783 0.787 0.791 0.026 0.032 D 0.746 0.740 0.756 E 0.960 0.976 0.039 0.047 0.498 0.65 0.802 18.40 18.80 19.20 0.992 24.40 24.80 25.20 0.055 1.00 1.20 1.40 2.40 0.064 0.003 0 0.35 Max 2.72 0.020 1 Nom 7 - 72 - 0.08 0 7 1 W925E/C240 10. REVISION HISTORY REVISION DATE A6 _ A7 _ MODIFICATION 1. Add initial state of registers 2. Modify description of WDCON.0 1. Modify the µC’s operating volt in Features and Operating Conditions. 2. Modify the PMR initial data. A8 May 16, 2003 1. Add Fsys Low-speed-clock switch as High-speed-clock application note. A9 Mar 1, 2005 1. Modify MOVX instruction machine cycles data. A10 July 12, 2005 1. Add lead free package part number. 2. Modify EIF to EXIF. Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. Headquarters Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd. No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office Winbond Electronics Corporation Japan Winbond Electronics (H.K.) Ltd. 9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 73 - Publication Release Date: July 12, 2005 Revision A10