Data Sheet 26185.201E 6276 16-BIT SERIAL-INPUT, CONSTANTCURRENT LATCHED LED DRIVER A6276ELW 24 LOG IC S UP P LY 23 R E XT 22 S E R IAL DAT A OUT 21 OUT P UT E NAB LE 20 OUT 15 6 19 OUT 14 OUT 2 7 18 OUT 13 OUT 3 8 17 OUT 12 OUT 4 9 16 OUT 11 OUT 5 10 15 OUT 10 OUT 6 11 14 OUT 9 OUT 7 12 13 OUT 8 V DD G R OUND 1 S E R IAL DAT A IN 2 C LOC K 3 CK LAT C H E NAB LE 4 L OUT 0 5 OUT 1 IO R E G ULATOR OE R E G IS TE R LAT C HE S Dwg. P P -029-11 Note that three packages offered are electrically identical and share a common terminal number assignment. ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD ....................... 7.0 V Output Voltage Range, VO ............................. -0.5 V to +17 V Output Current, IO ........................ 90 mA Ground Current, IGND .............. 1475 mA Input Voltage Range, VI .................... -0.4 V to VDD + 0.4 V Package Power Dissipation, PD ..................................... See Graph Operating Temperature Range, TA ............................. -40°C to +85°C Storage Temperature Range, TS ........................... -55°C to +150°C Caution: These CMOS devices have input static protection (Class 2) but are still susceptible to damage if exposed to extremely high static electrical charges. The A6276 is specifically designed for LED-display applications. Each BiCMOS device includes a 16-bit CMOS shift register, accompanying data latches, and 16 npn constant-current sink drivers. Except for package style and allowable package power dissipation, the device options are identical. The CMOS shift register and latches allow direct interfacing with microprocessor-based systems. With a 5 V logic supply, typical serial data-input rates are up to 20 MHz. The LED drive current is determined by the user’s selection of a single resistor. A CMOS serial data output permits cascade connections in applications requiring additional drive lines. For inter-digit blanking, all output drivers can be disabled with an ENABLE input high. Similar 8-bit devices are available as the A6275EA and A6275ELW. Three package styles are provided: through-hole DIP (suffix A), surface-mount SOIC (suffix LW) and TSSOP with exposed thermal pad (suffix LP). Under normal applications, a copper lead frame and low logic-power dissipation allow the dual in-line package to sink maximum rated current through all outputs continuously over the operating temperature range (90 mA, 0.75 V drop, +85°C). FEATURES ■ ■ ■ ■ ■ To 90 mA Constant-Current Outputs Under-Voltage Lockout Low-Power CMOS Logic and Latches High Data Input Rate Functional Replacement for TB62706BN/BF Selection Guide Part Number Pb-free* Package Packing Ambient Temperature (°C) A6276EA-T Yes 24-pin DIP 15 per tube –40 to 85 A6276ELP-T Yes 24-pin TSSOP 62 per tube –40 to 85 A6276ELPTR-T Yes 24-pin TSSOP 4000 per reel –40 to 85 A6276ELW-T Yes 24-pin SOICW 31 per tube –40 to 85 A6276ELWTR-T Yes 24-pin SOICW 1000 per reel –40 to 85 A6276SLW-T Yes 24-pin SOICW 31 per tube –20 to 85 A6276SLWTR-T Yes 24-pin SOICW 1000 per reel –20 to 85 *Pb-based variants are being phased out of the product line. The variants cited in this footnote are in production but have been determined to be NOT FOR NEW DESIGN. This classification indicates that sale of this device is currently restricted to existing customer applications. The variants should not be purchased for new design applications because obsolescence in the near future is probable. Samples are no longer available. Status change: May 1, 2006. These variants include:A6276EA, A6276ELW, A6276ELWTR, A6276SA, A6276SLW, and A6276SLWTR. 6276 16-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS 4.0 3.5 24-PIN TSSOP*, R θJA = 32°C/W 3.0 24-PIN DIP, RθJA = 50°C/W 2.5 24-LEAD SOIC, RθJA = 85°C/W 2.0 1.5 1.0 0.5 0 25 50 75 100 125 AMBIENT TEMPERATURE IN ° C 150 *Mounted on single-layer, two-sided PCB, with 3.8 in2 copper each side; additional information on Allegro Web site FUNCTIONAL BLOCK DIAGRAM VDD UVLO CLOCK SERIAL DATA IN SERIAL-PARALLEL SHIFT REGISTER LATCH ENABLE LATCHES LOGIC SUPPLY SERIAL DATA OUT OUTPUT ENABLE (ACTIVE LOW) GROUND MOS BIPOLAR IO REGULATOR OUT 0 OUT 1 OUT 2 2 OUT N 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 2000, 2003 Allegro MicroSystems, Inc. R EXT Dwg. FP-013-3 6276 16-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER VDD VDD IN IN Dwg. EP-010-12 Dwg. EP-010-11 OUTPUT ENABLE (active low) LATCH ENABLE VDD VDD OUT IN Dwg. EP-063-6 Dwg. EP-010-13 CLOCK and SERIAL DATA IN SERIAL DATA OUT TRUTH TABLE Serial Shift Register Contents Data Clock Input Input I1 I2 I3 ... IN-1 IN Serial Latch Data Enable Output Input Latch Contents I1 I2 I3 ... IN-1 IN Output Enable Input Output Contents I1 I2 I3 ... IN-1 IN H H R1 R2 ... RN-2 RN-1 RN-1 L L R1 R2 ... RN-2 RN-1 RN-1 X R1 R2 R3 ... RN-1 RN RN X X X L R1 R2 R3 ... RN-1 RN PN H P1 P2 P3 ... PN-1 PN L P1 P2 P3 ... PN-1 PN X X H H H H ... H X X ... P1 P2 P3 ... L = Low Logic (Voltage) Level www.allegromicro.com X PN-1 PN H = High Logic (Voltage) Level X X ... X = Irrelevant X P = Present State H R = Previous State 3 6276 16-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V (unless otherwise noted). Limits Characteristic Symbol Supply Voltage Range VDD Under-Voltage Lockout VDD(UV) Output Current (any single output) IO Output Current Matching ∆IO (difference between any two outputs at same VCE) Test Conditions Min. Typ. Max. Unit Operating 4.5 5.0 5.5 V VDD = 0 → 5 V 3.4 – 4.0 V VCE = 0.7 V, REXT = 250 Ω 64.2 75.5 86.8 mA VCE = 0.7 V, REXT = 470 Ω 34.1 40.0 45.9 mA REXT = 250 Ω – ±1.5 ±6.0 % REXT = 470 Ω – ±1.5 ±6.0 % – 1.0 5.0 µA 0.4 V ≤ VCE(A) = VCE(B) ≤ 0.7 V: Output Leakage Current ICEX Logic Input Voltage VIH 0.7VDD – VDD V VIL GND – 0.3VDD V SERIAL DATA OUT Voltage Input Resistance Supply Current VOH = 15 V VOL IOL = 500 µA – – 0.4 V VOH IOH = -500 µA 4.6 – – V ENABLE Input, Pull Up 150 300 600 kΩ LATCH Input, Pull Down 100 200 400 kΩ REXT = open, VOE = 5 V – 0.8 1.4 mA REXT = 470 Ω, VOE = 5 V 3.5 6.0 8.0 mA REXT = 250 Ω, VOE = 5 V 6.5 11 15 mA REXT = 470 Ω, VOE = 0 V 7.0 13 20 mA REXT = 250 Ω, VOE = 0 V 10 22 32 mA RI IDD(OFF) IDD(ON) Typical Data is at VDD = 5 V and is for design information only. 4 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 6276 16-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER SWITCHING CHARACTERISTICS at TA = 25°C, VDD = VIH = 5 V, VCE = 0.4 V, VIL = 0 V, REXT = 470 Ω, IO = 40 mA, VL = 3 V, RL = 65 Ω, CL = 10.5 pF. Limits Characteristic Propagation Delay Time Propagation Delay Time Symbol tpHL tpLH Test Conditions Min. Typ. Max. Unit CLOCK-OUTn – 350 1000 ns LATCH-OUTn – 350 1000 ns ENABLE-OUTn – 350 1000 ns CLOCK-SERIAL DATA OUT – 40 – ns CLOCK-OUTn – 300 1000 ns LATCH-OUTn – 300 1000 ns ENABLE-OUTn – 300 1000 ns CLOCK-SERIAL DATA OUT – 40 – ns Output Fall Time tf 90% to 10% voltage 150 350 1000 ns Output Rise Time tr 10% to 90% voltage 150 300 600 ns Min. Typ. Max. Unit RECOMMENDED OPERATING CONDITIONS Characteristic Symbol Supply Voltage VDD 4.5 5.0 5.5 V Output Voltage VO – 1.0 4.0 V Output Current IO Continuous, any one output – – 90 mA IOH SERIAL DATA OUT – – -1.0 mA IOL SERIAL DATA OUT – – 1.0 mA VIH 0.7VDD – VDD + 0.3 V VIL -0.3 – 0.3VDD V – – 10 MHz Logic Input Voltage Clock Frequency www.allegromicro.com fCK Conditions Cascade operation 5 6276 16-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER TIMING REQUIREMENTS and SPECIFICATIONS (Logic Levels are VDD and Ground) C 50% CLOCK A SERIAL DATA IN B DATA 50% tp SERIAL DATA OUT DATA 50% D E LATCH ENABLE OUTPUT ENABLE 50% LOW = ALL OUTPUTS ENABLED tp HIGH = OUTPUT OFF DATA 50% OUT N LOW = OUTPUT ON Dwg. WP-029-1 HIGH = ALL OUTPUTS DISABLED (BLANKED) OUTPUT ENABLE 50% t pLH F tf tr 90% OUT N t pHL DATA 50% 10% Dwg. WP-030-1A Serial data present at the input is transferred to the shift register on the logic 0-to-logic 1 transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The serial data must appear at the input prior to the rising edge of the CLOCK input waveform. Information present at any register is transferred to the respective latch when the LATCH ENABLE is high (serial-toparallel conversion). The latches continue to accept new data as 6 A. Data Active Time Before Clock Pulse (Data Set-Up Time), tsu(D) ............................. 50 ns B. Data Active Time After Clock Pulse (Data Hold Time), th(D) ................................. 20 ns C. Clock Pulse Width, tw(CK) .................................. 50 ns D. Time Between Clock Activation and Latch Enable, tsu(L) ............................... 100 ns E. Latch Enable Pulse Width, tw(L) ...................... 100 ns F. Output Enable Pulse Width, tw(OE) ................... 4.5 μs NOTE: Timing is representative of a 10 MHz clock. Significantly higher speeds are attainable. Max. Clock Transition Time, tr or tf ....................... 10 μs long as the LATCH ENABLE is held high. Applications where the latches are bypassed (LATCH ENABLE tied high) will require that the OUTPUT ENABLE input be high during serial data entry. When the OUTPUT ENABLE input is high, the output sink drivers are disabled (OFF). The information stored in the latches is not affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE input low, the outputs are controlled by the state of their respective latches. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 6276 16-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE A6276EA A6276ELW 100 100 80 VCE = 2 V VCE = 3 V 60 VCE = 4 V 40 TA = +25°C VDD = 5 V RθJA = 50°C/W 20 VCE = 0.7 V ALLOWABLE OUTPUT CURRENT IN mA/BIT ALLOWABLE OUTPUT CURRENT IN mA/BIT VCE = 1 V VCE = 1 V 80 VCE = 2 V 60 VCE = 3 V VCE = 4 V 40 TA = +25°C VDD = 5 V RθJA = 75°C/W 20 0 0 0 20 40 60 80 0 100 20 40 60 80 Dwg. GP-062-6 Dwg. GP-062-11 100 100 VCE = 1 V 80 VCE = 2 V VCE = 3 V 60 VCE = 4 V 40 TA = +50°C VDD = 5 V RθJA = 50°C/W 20 0 0 20 40 60 80 100 DUTY CYCLE IN PER CENT 80 VCE = 1 V VCE = 2 V 60 VCE = 3 V 40 VCE = 4 V TA = +50°C VDD = 5 V RθJA = 75°C/W 20 0 0 20 40 60 80 100 DUTY CYCLE IN PER CENT Dwg. GP-062-10 www.allegromicro.com VCE = 0.7 V ALLOWABLE OUTPUT CURRENT IN mA/BIT ALLOWABLE OUTPUT CURRENT IN mA/BIT 100 DUTY CYCLE IN PER CENT DUTY CYCLE IN PER CENT Dwg. GP-062-7 7 6276 16-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE (cont.) A6276EA A6276ELW 100 100 VCE = 0.4 V ALLOWABLE OUTPUT CURRENT IN mA/BIT ALLOWABLE OUTPUT CURRENT IN mA/BIT VCE = 0.7 V VCE = 1 V 80 VCE = 2 V 60 VCE = 3 V 40 VCE = 4 V TA = +85°C VDD = 5 V RθJA = 50°C/W 20 80 VCE = 0.7 V VCE = 1 V 60 VCE = 2 V VCE = 3 V 40 VCE = 4 V TA = +85°C VDD = 5 V RθJA = 75°C/W 20 0 0 0 20 40 60 80 0 100 20 40 DUTY CYCLE IN PER CENT TYPICAL CHARACTERISTICS OUTPUT CURRENT IN mA/BIT 60 40 TA = +25°C REXT = 500 Ω 20 0 0.5 1.0 1.5 2.0 VCE IN VOLTS Dwg. GP-063 8 80 100 Dwg. GP-062-8 Dwg. GP-062-9 0 60 DUTY CYCLE IN PER CENT 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 6276 16-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE (cont.) A6276ELP 100 ALLOWABLE OUTPUT CURRENT IN mA/BIT VCE = 1 V 80 VCE = 2 V VCE = 3 V 60 VCE = 4 V 40 TA = +25ı°C VDD = 5 V RˇθJA = 40ı°C/W 20 0 0 20 40 60 80 100 DUTY CYCLE IN PER CENT 100 ALLOWABLE OUTPUT CURRENT IN mA/BIT VCE = 1 V 80 VCE = 2 V VCE = 3 V 60 VCE = 4 V 40 TA = +50ı°C VDD = 5 V RˇθJA = 40ı°C/W 20 0 0 20 40 60 80 100 DUTY CYCLE IN PER CENT 9 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 6276 16-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER TERMINAL DESCRIPTION Terminal No. Terminal Name Function 1 GND Reference terminal for control logic. 2 SERIAL DATA IN Serial-data input to the shift-register. 3 CLOCK 4 LATCH ENABLE 5-20 OUT0-15 21 OUTPUT ENABLE 22 SERIAL DATA OUT 23 REXT 24 SUPPLY Clock input terminal for data shift on rising edge. Data strobe input terminal; serial data is latched with high-level input. The 16 current-sinking output terminals. When (active) low, the output drivers are enabled; when high, all output drivers are turned OFF (blanked). CMOS serial-data output to the following shift-register. An external resistor at this terminal establishes the output current for all sink drivers. (VDD) The logic supply voltage (typically 5 V). The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. www.allegromicro.com 10 6276 16-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER Applications Information The load current per bit (IO) is set by the external resistor (REXT) as shown in the figure below. diode (VZ), or a series string of diodes (approximately 0.7 V per diode) for a group of drivers. If the available voltage source will cause unacceptable dissipation and series resistors or diode(s) are undesirable, a regulator such as the Sanken Series SAI or Series SI can be used to provide supply voltages as low as 3.3 V. For reference, typical LED forward voltages are: White 3.5 – 4.0 V Blue 3.0 – 4.0 V Green 1.8 – 2.2 V Yellow 2.0 – 2.1 V Amber 1.9 – 2.65 V Red 1.6 – 2.25 V Infrared 1.2 – 1.5 V Package Power Dissipation (PD). The maximum allowable package power dissipation is determined as PD(max) = (150 - TA)/RθJA. The actual package power dissipation is PD(act) = DC • (VCE • IO • 16) + (VDD • IDD) , where DC is the duty cycle. Pattern Layout. This device has a common logicground and power-ground terminal. If ground pattern layout contains large common-mode resistance, and the voltage between the system ground and the LATCH ENABLE or CLOCK terminals exceeds 2.5 V (because of switching noise), these devices may not operate correctly. When the load supply voltage is greater than 3 V to 5 V, considering the package power dissipating limits of these devices, or if PD(act) > PD(max), an external voltage reducer (VDROP) should be used. Load Supply Voltage (VLED). These devices are designed to operate with driver voltage drops (VCE) of 0.4 V to 0.7 V with LED forward voltages (VF) of 1.2 V to 4.0 V. If higher voltages are dropped across the driver, package power dissipation will be increased significantly. To minimize package power dissipation, it is recommended to use the lowest possible load supply voltage or to set any series dropping voltage (VDROP) as VDROP = VLED - VF - VCE with VDROP = Io • RDROP for a single driver, or a Zener 11 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 6276 16-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER A6276EA Dimensions in Inches (controlling dimensions) 24 0.014 0.008 13 0.430 MAX 0.280 0.240 0.300 BSC 1 0.100 0.070 0.045 1.280 1.230 12 BSC 0.005 MIN 0.210 MAX 0.015 0.150 0.115 MIN 0.022 0.014 Dwg. MA-001-24 in Dimensions in Millimeters (for reference only) 0.355 0.204 13 24 10.92 MAX 7.11 6.10 7.62 BSC 1 1.77 1.15 6 7 2.54 32.51 31.24 BSC 12 0.13 MIN 5.33 MAX 0.39 3.81 2.93 MIN 0.558 0.356 NOTES: 1. 2. 3. 4. Dwg. MA-001-24 mm Exact body and lead configuration at vendor’s option within limits shown. Lead spacing tolerance is non-cumulative Lead thickness is measured at seating plane or below. Supplied in standard sticks/tubes of 15 devices. www.allegromicro.com 12 6276 16-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER A6276ELW Dimensions in Inches (for reference only) 24 13 0.0125 0.0091 0.419 0.394 0.2992 0.2914 0.050 0.016 0.020 0.013 1 2 0.050 3 0° TO 8° BSC 0.6141 0.5985 0.0926 0.1043 0.0040 MIN. Dwg. MA-008-24A in Dimensions in Millimeters (controlling dimensions) 24 13 0.32 0.23 10.65 10.00 7.60 7.40 1.27 0.40 0.51 0.33 1 2 1.27 3 15.60 15.20 BSC 0° TO 8° 2.65 2.35 0.10 MIN. Dwg. MA-008-24A mm NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Supplied in standard sticks/tubes of 31 devices or add “TR” to part number for tape and reel. 13 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 6276 16-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER A6276ELP 7.9 7.7 24 .311 .303 8º 0º A B 0.20 .008 0.09 .004 4.5 4.3 B .177 .169 3 .118 NOM 6.6 6.2 A 1 2 1 .039 REF 4.32 .170 NOM 0.25 .010 24X SEATING PLANE 0.10 [.004] C 24X 0.30 .012 0.19 .007 0.65 .026 0.40 .016 REF SEATING PLANE GAUGE PLANE C 1.20 .047 MAX 0.10 [.004] M C A B 2 .079 NOM 0.75 .030 0.45 .018 .260 .244 0.15 .006 0.00 .000 0.45 .018 NOM 24 0.65 .026 NOM 3 .118 NOM C 5.8 .228 NOM Preliminary dimensions, for reference only (reference JEDEC MO-153 ADT) Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Exposed thermal pad (bottom surface) U.S. Customary dimensions controlling C Reference land pattern layout (reference IPC7351 TSOP65P640-24M); adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) 1 2 4.32 .170 NOM 14 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000