September 2006 Advance Information AS7C1024C ® 5V 128K X 8 CMOS SRAM Features • Industrial (-40o to 85oC) temperature • Organization: 131,072 x 8 bits • High speed - 12 ns address access time - 6 ns output enable access time • Low power consumption via chip deselect • Easy memory expansion with CE1, CE2, OE inputs • TTL/LVTTL-compatible, three-state I/O • 32-pin JEDEC standard packages - 300 mil SOJ - 400 mil SOJ • ESD protection ≥ 2000 volts Pin arrangement Logic block diagram GND 131,702 x 8 Array (1,048,576) A9 A10 A11 A12 A13 A14 A15 A16 Address decoder 12/5/06, v. 1.0 I/O7 Sense amp A0 A1 A2 A3 A4 A5 A6 A7 A8 Address decoder Input buffer I/O0 Control circuit NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AS7C1024C 32-pin SOJ (300 mil) 32-pin SOJ (400 mil) VCC 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 WE OE CE1 CE2 Alliance Memory P. 1 of 9 Copyright © Alliance Memory All rights reserved. AS7C1024C ® Functional description The AS7C1024C is a 5V high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 12 ns with output enable access times (tOE) of 6 ns are ideal for high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank systems. When CE1 is high or CE2 is low, the devices enter standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is static, then full standby power is reached (ISB1). A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0 through I/O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) high. The chips drive I/O pins with the data word referenced by the input address. When either chip enable is inactive, output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. Absolute maximum ratings Symbol Min Max Unit Voltage on VCC relative to GND Parameter Vt1 –0.50 +7.0 V Voltage on any pin relative to GND Vt2 –0.50 VCC +0.50 V Power dissipation PD – 1.25 W Storage temperature (plastic) Tstg –55 +125 °C Ambient temperature with VCC applied Tbias –55 +125 °C DC current into outputs (low) IOUT – 50 mA Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE1 CE2 WE OE Data Mode H X X X High Z Standby (ISB, ISB1) X L X X High Z Standby (ISB, ISB1) L H H H High Z Output disable (ICC) L H H L DOUT Read (ICC) L H L X DIN Write (ICC) Key: X = don’t care, L = low, H = high. 12/5/06, v. 1.0 Alliance Memory P. 2 of 9 AS7C1024C ® Recommended operating conditions Parameter Symbol Min Nominal Max Unit VCC 4.5 5.0 5.5 V Supply Voltage Input Voltage VIH 2.2 - VCC + 0.5 V VIL(1) –0.5(1) – 0.8 V TA –40 – 85 °C Ambient operating temperature (Industrial) Note: 1 VIL min = -1.5V for pulse width less than 10ns, once per cycle. DC operating characteristics (over the operating range)1 AS7C1024C-12 Parameter Symbol Test conditions Min Max Unit |ILI| VCC = Max, VIN = GND to VCC – 5 μA Output leakage current |ILO| VCC = Max, CE1 = VIH or CE2 = VIL, VOUT = GND to VCC – 5 μA Operating power supply current ICC VCC = Max, CE1 ≤ VIL, CE2 ≥ VIH, f = fMax, IOUT = 0 mA – 160 mA ISB VCC = Max, CE1 ≥ VIH and/or CE2 ≤ VIL, f = fMax – 40 mA – 10 mA Input leakage current VCC = Max, CE1 ≥ VCC–0.2V Standby power supply current1 and/or CE2 ≤ 0.2V VIN ≤ 0.2V or VIN ≥ VCC – 0.2V, f = 0 ISB1 Output voltage VOL IOL = 8 mA, VCC = Min – 0.4 V VOH IOH = –4 mA, VCC = Min 2.4 – V Capacitance (f = 1 MHz, Ta = 25o C, VCC = NOMINAL)2 Parameter Symbol Signals Test conditions Max Unit Input capacitance CIN A, CE1, CE2, WE, OE VIN = 3dV 7 pF I/O capacitance CI/O I/O VOUT = 3dV 8 pF Note: This parameter is guaranteed by device characterization, but is not production tested. 12/5/06, v. 1.0 Alliance Memory P. 3 of 9 AS7C1024C ® Read cycle (over the operating range)3,9 AS7C1024C-12 Parameter Symbol Min Max Unit tRC 12 – ns Address access time tAA – 12 ns 3 Chip enable (CE1) access time tACE1 – 12 ns 3, 12 Chip enable (CE2) access time tACE2 – 12 ns 3, 12 Output enable (OE) access time tOE – 6 ns Output hold from address change tOH 4 – ns 5 CE1 Low to output in low Z tCLZ1 3 – ns 4, 5, 12 CE2 High to output in low Z tCLZ2 3 – ns 4, 5, 12 CE1 Low to output in high Z tCHZ1 0 6 ns 4, 5, 12 CE2 Low to output in high Z tCHZ2 – 5 ns 4, 5, 12 OE Low to output in low Z tOLZ 0 – ns 4, 5 OE High to output in high Z tOHZ – 5 ns 4, 5 Power up time tPU 0 – ns 4, 5, 12 Power down time tPD – 12 ns 4, 5, 12 Read cycle time Notes Key to switching waveforms Rising input Falling input Undefined/don’t care Read waveform 1 (address controlled)3,6,7,9 tRC Address tAA tOH DOUT Data valid Read waveform 2 (CE1, CE2, and OE controlled)3,6,8,9,12 tRC1 CE1 CE2 tOE OE DOUT Current supply 12/5/06, v. 1.0 tOHZ tCHZ1, tCHZ2 tOLZ tACE1, tACE2 tCLZ1, tCLZ2 tPU Data valid tPD 50% ICC ISB 50% Alliance Memory P. 4 of 9 AS7C1024C ® Write cycle (over the operating range)11 AS7C1024C-12 Parameter Symbol Min Max Unit Notes Write cycle time tWC 12 – ns Chip enable (CE1) to write end tCW1 10 – ns 12 Chip enable (CE2) to write end tCW2 10 – ns 12 Address setup to write end tAW 10 – ns Address setup time tAS 0 – ns Write pulse width tWP 8 – ns Write recovery time tWR 0 – ns Address hold from end of write tAH 0 – ns Data valid to write end tDW 7 – ns Data hold time tDH 0 – ns 4, 5 Write enable to output in high Z tWZ 0 5 ns 4, 5 Output active from write end tOW 3 – ns 4, 5 12 Write waveform 1 (WE controlled)10,11 tWC tAW tWR tAH Address tWP WE tAS tDW DIN tDH Data valid tWZ tOW DOUT Write waveform 2 (CE1 and CE2 controlled)10,11,12 tAW tWC tAH tWR Address tAS tCW1, tCW2 CE1 CE2 tWP WE twz DIN tDW tDH Data valid DOUT 12/5/06, v. 1.0 Alliance Memory P. 5 of 9 AS7C1024C ® AC test conditions – – – – Output load: see Figure B. Input pulse level: GND to 3.0 V. See Figure A. Input rise and fall times: 3 ns. See Figure A. Input and output timing reference levels: 1.5 V. +5 V Thevenin equivalent: 480 Ω +3.0V GND 90% 10% 90% 3 ns 10% Figure A: Input pulse DOUT 255 Ω C13 DOUT 168 Ω +1.728 V GND Figure B: 5 V Output load Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions, Figures A and B. tCLZ and tCHZ are specified with CL = 5 pF, as in Figure B. Transition is measured ±200 mV from steady-state voltage. This parameter is guaranteed, but not 100% tested. WE is high for read cycle. CE and OE are low for read cycle. Address is valid prior to or coincident with CE transition low. All read cycle timings are referenced from the last valid address to the first transitioning address. N/A All write cycle timings are referenced from the last valid address to the first transitioning address. N/A. C = 30 pF, except all high Z and low Z parameters where C = 5 pF. 12/5/06, v. 1.0 Alliance Memory P. 6 of 9 AS7C1024C ® Package dimensions 32-pin SOJ 300 mil A 32-pin SOJ 300/400 mil D e E1 E2 B Pin 1 A A1 c b A2 Seating plane 32-pin SOJ 400 mil Min Max Min Max 0.128 0.145 0.132 0.146 A1 0.025 - 0.025 - A2 0.095 0.105 0.105 0.115 B 0.026 0.032 0.026 0.032 b 0.016 0.020 0.015 0.020 c 0.007 0.010 0.007 0.013 D 0.820 0.830 0.820 0.830 E 0.255 0.275 0.354 0.378 E1 0.295 0.305 0.395 0.405 E2 0.330 0.340 0.435 0.445 e 0.050 BSC 0.050 BSC E Note: This part is compatible with both pin numbering conventions used by various manufacturers. 12/5/06, v. 1.0 Alliance Memory P. 7 of 9 AS7C1024C ® Ordering Codes Package Volt/Temp 12 ns Plastic SOJ, 300 mil 5V industrial AS7C1024C-12TJIN Plastic SOJ, 400 mil 5V industrial AS7C1024C-12JIN Part numbering system AS7C 1024C SRAM prefix Device number 12/5/06, v. 1.0 –XX X X X Package: Temperature range N = LEAD FREE Access time J = SOJ 400 mil I = industrial, -40° PART C to 85° C TJ = SOJ 300 mil Alliance Memory P. 8 of 9 AS7C1024C ® ® Alliance Memory, Inc. 1116 South Amphlett San Mateo, CA 94402 Tel: 650-525-3737 Fax: 650-525-0449 www.alliancememory.com Copyright © Alliance Memory All Rights Reserved Part Number: AS7C1024C Document Version: v. 1.0 © Copyright 2003 Alliance Memory, Inc. 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