September 2006 Advance Information AS7C513C ® 5 V 32K X 16 CMOS SRAM Features • JEDEC standard packaging - 44-pin 400 mil SOJ - 44-pin TSOP 2 • ESD protection ≥ 2000 volts Pin arrangement A6 A7 I/O0–I/O7 I/O8–I/O15 Control circuit Address decoder A8 WE I/O buffer UB OE LB CE 12/5/06, v 1.0 GND NC A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC GND I/O4 I/O5 I/O6 I/O7 WE A14 A13 A12 A11 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A4 A5 A6 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VCC I/O11 I/O10 I/O9 I/O8 NC A7 A8 A9 A10 NC A14 A5 A13 A4 A11 A3 VCC 32,768 x 16 Array A12 A2 A9 A1 A10 A0 Address decoder Logic block diagram 44-Pin SOJ (400 mil), TSOP 2 AS7C513C • Industrial (-40o to 85oC) temperature • Organization: 32,768 words × 16 bits • Center power and ground pins for low noise • High speed - 12 ns address access time - 6 ns output enable access time • Low power consumption via chip deselect • Easy memory expansion with CE, OE inputs • TTL-compatible, three-state I/O • Upper and Lower byte pin Alliance Memory P. 1 of 9 Copyright © Alliance Memory. All rights reserved. AS7C513C ® Functional description The AS7C513C is a 5V high-performance CMOS 524,288-bit Static Random Access Memory (SRAM) device organized as 32,768 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 12 ns with output enable access times (tOE) of 6 ns are ideal for highperformance applications. When CE is high, the device enters standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is static, then full standby power is reached (ISB1). A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE) with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output drivers stay in high-impedance mode. The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O0 through I/O7, and UB controls the higher bits, I/O8 through I/O15. All chip inputs and outputs are TTL-compatible, and operation is from a single 5 V supply. The AS7C513C is packaged in common industry standard packages. Absolute maximum ratings Symbol Min Max Unit Voltage on VCC relative to GND Parameter Vt1 –0.50 +7.0 V Voltage on any pin relative to GND Vt2 –0.50 VCC +0.50 V Power dissipation PD – 1.25 W Storage temperature (plastic) Tstg –55 +125 °C Ambient temperature with VCC applied Tbias –55 +125 °C DC current into outputs (low) IOUT – 50 mA Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE WE OE LB UB I/O0–I/O7 I/O8–I/O15 Mode H X X X X High Z High Z Standby (ISB), ISBI) L H L L H DOUT High Z Read I/O0–I/O7 (ICC) L H L H L High Z DOUT Read I/O8–I/O15 (ICC) L H L L L DOUT DOUT Read I/O0–I/O15 (ICC) L L X L L DIN DIN Write I/O0–I/O15 (ICC) L L X L H DIN High Z Write I/O0–I/O7 (ICC) L L X H L High Z DIN Write I/O8–I/O15 (ICC) L L H X H X X H X H High Z High Z Output disable (ICC) Key: H = high, L = low, X = don’t care. 12/5/06, v 1.0 Alliance Memory P. 2 of 9 AS7C513C ® Recommended operating conditions Parameter Symbol Min Nominal Max Unit VCC 4.5 5.0 5.5 V VIH 2.2 – VCC + 0.5 V VIL –0.5 – 0.8 TA –40 – 85 Supply voltage Input voltage Ambient operating temperature (Industrial) V o C Notes: VIL min = -1.5V for pulse width less than 5ns, once per cycle. VIH max = VCC+2.0V for pulse width less than 5ns, once per cycle. DC operating characteristics (over the operating range)1 AS7C513C-12 Parameter Sym Test conditions Min Max Unit Input leakage current | ILI | VCC = Max, VIN = GND to VCC – 5 µA Output leakage current | ILO | VCC = Max, CE = VIH, VOUT = GND to VCC – 5 µA ICC VCC = Max, CE ≤ VIL, IOUT = 0mA, f = fMax – 210 mA – 60 mA Operating power supply current VCC = Max, ISB Standby power supply current Output voltage CE ≥ VIH , f = fMax ISB1 VCC = Max, CE ≥ VCC–0.2 V, VIN ≤ 0.2 V or VIN ≥ VCC–0.2 V, f = 0 – 10 mA VOL IOL = 8 mA, VCC = Min – 0.4 V VOH IOH = –4 mA, VCC = Min 2.4 – V Capacitance (f = 1MHz, Ta = 25 °C, VCC = NOMINAL)2 Parameter Symbol Signals Test conditions Max Unit Input capacitance CIN A, CE, WE, OE, LB, UB VIN = 3dV 6 pF I/O capacitance CI/O I/O VOUT = 3dV 7 pF Note: This parameter is guaranteed by device characterization, but is not production tested. 12/5/06, v 1.0 Alliance Memory P. 3 of 9 AS7C513C ® Read cycle (over the operating range)3,9 AS7C513C-12 Parameter Symbol Min Max Unit tRC 12 – ns Address access time tAA – 12 ns 3 Chip enable (CE) access time tACE – 12 ns 3 Output enable (OE) access time tOE – 7 ns Output hold from address change tOH 4 – ns 5 CE low to output in low Z tCLZ 4 – ns 4, 5 CE high to output in high Z tCHZ – 6 ns 4, 5 OE low to output in low Z tOLZ 0 – ns 4, 5 Byte select access time tBA – 7 ns Byte select Low to low Z tBLZ 0 – ns 4, 5 Byte select High to high Z tBHZ – 6 ns 4, 5 OE high to output in high Z Read cycle time Notes tOHZ – 6 ns 4, 5 Power up time tPU 0 – ns 4, 5 Power down time tPD – 12 ns 4, 5 Key to switching waveforms Rising input Falling input Undefined output/don’t care Read waveform 1 (address controlled)3,6,7,9 tRC Address DataOUT tAA tOH Previous data valid tOH Data valid Read waveform 2 (OE, CE, UB, LB controlled)3,6,8,9 tRC Address tAA OE tOE tOLZ tOH CE tLZ tOHZ tHZ tACE LB, UB tBLZ tBA DataIN 12/5/06, v 1.0 tBHZ Data valid Alliance Memory P. 4 of 9 AS7C513C ® Write cycle (over the operating range) 11 AS7C513C-12 Symbol Min Max Unit Write cycle time Parameter tWC 12 – ns Notes Chip enable (CE) to write end tCW 9 – ns Address setup to write end tAW 9 – ns Address setup time tAS 0 – ns Write pulse width tWP 9 – ns Write recovery time tWR 0 – ns Address hold from end of write tAH 0 – ns Data valid to write end tDW 7 – ns Data hold time tDH 0 – ns 5 Write enable to output in high Z tWZ – 6 ns 4, 5 Output active from write end tOW 1 – ns 4, 5 Byte select low to end of write tBW 9 – ns Write waveform 1 (WE controlled)11 tWC tAH Address tWR tCW CE tBW LB, UB tAW tAS tWP WE tDW DataIN Data valid tWZ DataOUT 12/5/06, v 1.0 tDH Data undefined Alliance Memory tOW high Z P. 5 of 9 AS7C513C ® Write waveform 2 (CE controlled)11 tWC tAH Address tAS tWR tCW CE tAW tBW LB, UB tWP WE tDH tDW Data valid DataIN tWZ tCLZ DataOUT high Z tOW Data undefined high Z AC test conditions – – – – Output load: see Figure B. Input pulse level: GND to 3.0 V. See Figure A. Input rise and fall times: 3 ns. See Figure A. Input and output timing reference levels: 1.5 +5 V 480 Ω DOUT +3.0V GND 90% 10% 90% 3 ns 10% Figure A: Input pulse 255 Ω C13 Thevenin Equivalent: 168 Ω DOUT +1.728 V GND Figure B: 5 V Output load Notes: 1 2 3 4 5 6 7 8 9 10 11 12 13 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions, Figures A and B. These parameters are specified with CL = 5 pF, as in Figures B. Transition is measured ± 200 mV from steady-state voltage. This parameter is guaranteed, but not tested. WE is high for read cycle. CE and OE are low for read cycle. Address is valid prior to or coincident with CE transition low. All read cycle timings are referenced from the last valid address to the first transitioning address. N/A. All write cycle timings are referenced from the last valid address to the first transitioning address. Not applicable. C = 30 pF, except all high Z and low Z parameters where C = 5 pF. 12/5/06, v 1.0 Alliance Memory P. 6 of 9 AS7C513C ® Package dimensions c 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 E He 44-pin TSOP 2 D A l 0–5° A1 e b Min (mm) Max (mm) A1 0.05 0.15 A2 0.95 1.05 b 0.30 0.45 c 0.120 0.21 D 18.31 18.52 E 10.06 10.26 He 11.68 11.94 A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1718 19 20 21 22 A2 44-pin TSOP 2 e l 1.2 0.80 (typical) 0.40 0.60 44-pin SOJ 400 mil D e Min (in) Max (in) 44-pin SOJ E1 E2 Pin 1 c B A2 A A1 b Seating plane E A 0.128 A1 0.025 – A2 0.105 0.115 B 0.026 0.032 b 0.015 0.020 c 0.007 0.013 D 1.120 1.130 E Alliance Memory 0.370 NOM E1 0.395 0.405 E2 0.435 0.445 e 12/5/06, v 1.0 0.148 0.050 NOM P. 7 of 9 AS7C513C ® Ordering codes Volt/Temp 12 ns Plastic SOJ, 400 mil Package 5V Industrial AS7C513C-12JIN TSOP 2, 10.2 x 18.4 mm 5V Industrial AS7C513C-12TIN Part numbering system AS7C 513C –XX X Device Access number time J = SOJ 400 mil T = TSOP 2, 10.2 x 18.4 mm Package: SRAM prefix 12/5/06, v 1.0 X X Temperature range: I = industrial: -40° C to 85° C N = LEAD FREE PART Alliance Memory P. 8 of 9 AS7C1026C ® ® Alliance Memory, Inc. 1116 South Amphlett San Mateo, CA 94402 Tel: 650-525-3737 Fax: 650-525-0449 www.alliancememory.com Copyright © Alliance Memory All Rights Reserved Part Number: AS7C1026C Document Version: v 1.0 © Copyright 2003 Alliance Memory, Inc. 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