AMIS-734256, AMIS-734512, AMIS-734024 Data Sheet 25µm-pitch Wide Aperture Spectroscopic Photodiode Arrays 1.0 Description AMI Semiconductor’s HSN series is family of self-scanning photodiode solid-state linear imaging arrays. These photodiode sensors employ AMI Semiconductor’s proprietary CMOS image sensing technology to integrate the sensors into a single monolithic chip. These sensors are optimally designed for applications in spectroscopy. Accordingly, these sensors contain a linear array of photodiodes with an optimized geometrical aspect ratio (25µm aperture pitch x 2500µm aperture width) for helping to maintain mechanical stability in spectroscopic instruments and for providing a large light-capturing ability. The family of sensors consists of photodiode arrays of various lengths, 256, 512, and 1024 pixels. The HSN photodiode arrays are mounted in 22-pin ceramic side-brazed dual-in-line packages, which fit in standard DIP sockets. A diagram of its pin-out configuration is seen in Figure 1. Figure 1: Pin Out Configuration AMI Semiconductor – Aug. 06, M-20603-001 www.amis.com 1 AMIS-734256, AMIS-734512, AMIS-734024 25µm-pitch Wide Aperture Spectroscopic Photodiode Arrays 2.0 Key Features • • • • • • • • • • • Selectable saturation charge capacities: 65pC capacity for wider dynamic range and 25pC for lower noise readout Wide spectral response (180 – 1000nm) for UV and IR response NP junction photodiodes with superior resistance to UV damage Low dark current Integration time up to 11 seconds at room temperature Integration time extended to hours by cooling Anti-blooming circuitry High linearity Low power dissipation (less than 1mW) Geometrical structure for enhanced stability and registration Standard 22-lead dual-in-line IC package 3.0 Sensor Characteristics Figure 2: Geometry and Layout of Photodiode Pixels AMI Semiconductor – Aug. 06, M-20603-001 www.amis.com 2 Data Sheet AMIS-734256, AMIS-734512, AMIS-734024 Data Sheet 25µm-pitch Wide Aperture Spectroscopic Photodiode Arrays During normal operation, the photons incident in or near the NP photodiode junction generate free charges, which are collected and stored on the junction's depletion capacitance. The number of collected charges is proportional to the light exposure. Figure 3 shows the stored signal charge as function of light exposure at a wavelength of 575nm. The exposure is the product of the light intensity in nW/cm2 and integration time in seconds. The charge accumulates linearly until reaching the saturation charge and the corresponding exposure is the saturation exposure. There are two saturation limits which are described in Section 4.0. The responsivity may be calculated as the saturation charge divided by the saturation exposure. The predicted typical responsivity of a photodiode is 1.5×10-4 C/J/cm2 at 575nm. Figure 4 shows the predicted responsivity of the photodiodes as a function of wavelength. Figure 3: Stored Signal Charge as a Function of Exposure at a Wavelength of 575nm Figure 4: Predicted Spectral Response AMI Semiconductor – Aug. 06, M-20603-001 www.amis.com 3 AMIS-734256, AMIS-734512, AMIS-734024 Data Sheet 25µm-pitch Wide Aperture Spectroscopic Photodiode Arrays The quantum efficiency (QE) can be calculated by dividing the responsivity by the area of the sensor's element and multiplying the resulting ratio by the energy per photon in electron volts (eV). The dark current is typically 0.2pA at 25°C and varies as function of temperature. The dark current will contribute dark-signal charges and these charges will increase linearly with integration time. The dark signal and the photo-generated signal combined result in the total signal charge. 4.0 Selectable Charge Capacity The HSN devices have the unique feature of having a selectable charge capacity. There is a bank of capacitors with one capacitor for each photodiode pixel. When the capacitors are connected to the photodiodes, they give the photodiodes a charge capacity of typically 65pC. This large charge capacity is useful in applications that demand high dynamic range and high signal-to-noise ratios. With the capacitors disconnected, the photodiodes typically have an intrinsic charge capacity of 25pC. With a reduced capacitance, the photodiode array can operate with a lower reset (kTC) noise. The ADDCAP pin is provided to control the connection of the capacitors. When ADDCAP is high, all the capacitors are connected. When ADDCAP is low, all the capacitors are disconnected. It is advised that all the photodiodes are reset after each toggle of ADDCAP. This is simply done by clocking one line scan of the photodiode array. 5.0 Anti-Blooming Circuit Each photodiode pixel has a built-in anti-blooming circuit structure. Without an anti-blooming circuit, it is possible that a fraction of the excess charge from one pixel will flow into neighboring pixels. The anti-blooming circuit prevents this by redirecting the excess current into the anti-blooming drain before the photodiode is too full. A self-biased anti-blooming gate sets the level at which the charge begins to flow into the drain. Think of it this way. If the photodiode were your bathroom sink, then the anti-blooming circuit would be your sink’s overflow drain. The anti-blooming circuit may be disabled by grounding the anti-blooming gate. This would, in effect, raise the drain level. 6.0 Self-Scanning Circuit Figure 5 shows a simplified electrically equivalent circuit diagram of the photodiode array. A MOS read switch connects every photodiode in the array to a common output video line. Incident photons generate an electron charge, which is collected on each imaging photodiode while the switch is open. The shift register is activated by the start pulse. A pulse propagates through each shift register stage and activates the MOS read switches sequentially. As the shift register sequentially closes each read switch, the negative stored charge, which is proportional in amount to the light exposure from the corresponding photodiode, is readout onto the video line, QOUT. Typically, an external charge-integrating amplifier senses the negative output charge on the video line from each photodiode pixel. The shift register continues scanning the photodiodes in sequence, until the last shift register stage is reached, at which time the fourth and last dummy pixel is read out and end-of-scan (EOS) output is held high for one clock cycle. The next start pulse can then restart the shift register. AMI Semiconductor – Aug. 06, M-20603-001 www.amis.com 4 AMIS-734256, AMIS-734512, AMIS-734024 Data Sheet 25µm-pitch Wide Aperture Spectroscopic Photodiode Arrays Figure 5: Simplified Circuit Diagram of an HSN Photodiode Array The diagram in Figure 5 does not include the capacitor bank and the anti-blooming circuitry. 7.0 I/O Pins Besides the VSS and VDD supply pins, there are nine functionally active I/O pins. Only two clocks, CLK and START, are required for controlling the timing of the sensor's video readout. One additional digital input, ADDCAP controls the bank of capacitors as described in the Section 6.0. The digital output, EOS, marks the end of the line-scan. The charge output pin, QOUT, is typically connected to a charge-integrating amplifier, which is biased to Vbias (see Section 8.0). For normal anti-blooming operation, the ABG requires a 0.1µF capacitor connected to VSS and the ABD is also biased to Vbias. Each temperature diode is operated with a small constant current, which forward biases its PN junction. By measuring the forward-bias voltage, one can track the silicon die temperature. The temperature diodes may be disabled by connecting their anodes to VSS. These I/Os are listed with their acronym designators and functional descriptions in Table 1. Table 1: Symbols and Functions and I/O Pins Symbol Function and Description VSS Ground VDD +5.0V START Start pulse: input to start the line scan CLK Clock pulse: input to clock the shift register ADDCAP Add capacitors: input that selects the bank of capacitors to increase charge capacity EOS End of scan: output from the shift register to indicate the completion of one line scan QOUT Video charge output: output from the photodiodes pixels ABG Anti-blooming gate: self-biased gate for setting anti-blooming level. Requires 0.1-µF connected to VSS ABD Anti-blooming drain: bias for anti-blooming drain, set to Vbias TD1 Temperature Diode 1: anode of temperature Diode 1 TD2 Temperature Diode 2: anode of temperature Diode 2 NC No connection AMI Semiconductor – Aug. 06, M-20603-001 www.amis.com 5 AMIS-734256, AMIS-734512, AMIS-734024 Data Sheet 25µm-pitch Wide Aperture Spectroscopic Photodiode Arrays 8.0 Clock and Voltage Requirements The clocking requirements are relatively simple. As it was indicated in Figure 5 and Table 1, there are only two input signals that require clocked inputs. They are CLK, the clock for the shift register, and START, the shift register start pulse. The timing specifications and the symbol definition for Figure 6 are listed in Table 2. The control clock amplitudes for I/Os are compatible with the 5V CMOS devices. Figure 6: Timing Diagram Table 2: Symbol Definitions and Timing Specifications for Timing Diagram Item Symbol Min. Typ. Clock cycle time to 1000 10000 Clock high pulse width twh 900 Clock low pulse width twl 100 Clock duty cycle 1 50 Data setup time tds 100 Data hold time tdh 100 EOS low-to-high delay telh EOS high-to-low delay tehl Signal delay time tsd 50 Signal settling time tsh Signal settle to clock edge tsch 0 AMI Semiconductor – Aug. 06, M-20603-001 www.amis.com 6 Max. 99 400 400 900 Units ns ns ns % ns ns ns ns ns ns ns AMIS-734256, AMIS-734512, AMIS-734024 Data Sheet 25µm-pitch Wide Aperture Spectroscopic Photodiode Arrays 9.0 Recommended Operating Conditions Table 3 lists the recommended operating conditions. ° Table 3: Recommended Operating Conditions at 25 C Parameters Symbol Power supply VDD (1) Input clock pulses high level Vih (1) Input clock pulse low level Vil Video charge output external bias Vbias Clock frequency Fclk Integration time Notes: (1) (2) Min. 4.5 VDD – 0.8 0.0 VDD – 0.5 0.26 (734256) 0.52 (734512) 1.03 (734024) Tint (2) Typ. 5.0 VDD 0.0 VDD – 0.5 0.1 Max. 5.5 VDD 0.8 VDD 1.0 Units Volts Volts Volts Volts MHz ms 11000 (w/ cap) Applies to all control-clock inputs. Integration time is specified at room temperature such that the maximum dark current charge build up in each pixel is less than 10 percent of the minimum saturation charge. Accordingly, it may be as long as 11 seconds at room temperature with the added capacitors. Longer integration times may be achieved by cooling the device. An appropriate clock frequency must be chosen so that the shift register completes its operation within the desired integration time. 10.0 Electro-Optical Characteristics Table 4 lists the electro-optical characteristics. ° Table 4: Electro-Optical Characteristics at 25 C Parameters Symbol Center-to-center spacing Aperture width Pixel area A (1) Fill factor FF (1)(2) Quantum efficiency QE (1)(2) Responsivity R (3) Non-uniformity of response Saturation exposure Saturation charge (2) (4) Esat Qsat Min. 370 (w/cap) 130 (w/o cap) 55 (w/cap) 20 (w/o cap) (5) Average dark current Spectral response peak (6) Spectral response range Notes: (1) (2) (3) (4) (5) (6) λ Typ. 25 2500 -4 6.25 x 10 72 70 -4 1.5 x 10 2 430 (w/ cap) 170 (w/o cap) 65 (w/cap) 25 (w/o cap) 0.2 600 180 - 1000 Max. Units µm µm 2 cm % % C/J/cm2 +/-% nJ/cm2 pC pA nm nm Fill factor, quantum efficiency and responsivity are related by the equation R = (qel/hc).QE.FF.A, where qe is the charge of an electron and hc/l is the energy of a photon at a given wavelength. Responsivity is therefore given per pixel. At wavelength of 575nm (Yellow-Green) and with no window. Measured at 50 percent Vsat with an incandescent tungsten lamp filtered with an Schott KG-1 heat-absorbing filter. Saturation charge specified for a video output bias of 4.5V. Max dark leakage £ 1.5 x average dark leakage measured with an integration period of 500ms at 25°C. From 250-1000nm, responsivity ³ 20 percent of its peak value. AMI Semiconductor – Aug. 06, M-20603-001 www.amis.com 7 AMIS-734256, AMIS-734512, AMIS-734024 25µm-pitch Wide Aperture Spectroscopic Photodiode Arrays 11.0 Package Dimensions Figure 7 provides the package dimensions. Figure 7: Package Dimensions AMI Semiconductor – Aug. 06, M-20603-001 www.amis.com 8 Data Sheet AMIS-734256, AMIS-734512, AMIS-734024 Data Sheet 25µm-pitch Wide Aperture Spectroscopic Photodiode Arrays 12.0 Company or Product Inquiries For more information about AMI Semiconductor, our technology and our product, visit our Web site at: http://www.amis.com North America Tel: +1.208.233.4690 Fax: +1.208.234.6795 Europe Tel: +32 (0) 55.33.22.11 Fax: +32 (0) 55.31.81.12 Production Technical Data - The information contained in this document applies to a product in production. AMI Semiconductor and its subsidiaries (“AMIS”) have made every effort to ensure that the information is accurate and reliable. However, the characteristics and specifications of the product are subject to change without notice and the information is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify that data being relied on is the most current and complete. AMIS reserves the right to discontinue production and change specifications and prices at any time and without notice. Products sold by AMIS are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMIS makes no other warranty, express or implied, and disclaims the warranties of noninfringement, merchantability, or fitness for a particular purpose. AMI Semiconductor's products are intended for use in ordinary commercial applications. These products are not designed, authorized, or warranted to be suitable for use in life-support systems or other critical applications where malfunction may cause personal injury. Inclusion of AMIS products in such applications is understood to be fully at the customer’s risk. Applications requiring extended temperature range, operation in unusual environmental conditions, or high reliability, such as military or medical life-support, are specifically not recommended without additional processing by AMIS for such applications. Copyright © 2006 AMI Semiconductor, Inc. AMI Semiconductor – Aug. 06, M-20603-001 www.amis.com 9