AOSMD AOZ1212

AOZ1212
EZBuck™ 3A Simple Buck Regulator
General Description
Features
The AOZ1212 is a high ef ciency , simple to use, 3A buck
regulator e xible enough to be optimized for a variety of
applications. The AOZ1212 works from a 4.5V to 27V
input voltage range, and provides up to 3A of continuous
output current on each buck regulator output. The output
voltage is adjustable down to 0.8V.
The AOZ1212 comes in an SO-8 or DFN-8 package and
is rated over a -40°C to +85°C ambient temperature
range.
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4.5V to 27V operating input voltage range
70mΩ internal NFET, ef ciency: up to 95%
Internal soft start
Output voltage adjustable down to 0.8V
3A continuous output current
Fixed 370kHz PWM operation
Cycle-by-cycle current limit
Short-circuit protection
Thermal shutdown
Small size SO-8 or DFN-8 package
Applications
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Point of load DC/DC conversion
Set top boxes
DVD drives and HDD
LCD monitors & TVs
Cable modems
Telecom/networking/datacom equipment
Typical Application
C7
VIN
C1
22µF
VIN
BS
EN
L1
6.8µH
AOZ1212
R1
C2, C3
22µF
FB
VBIAS
C4
VOUT
LX
COMP
GND
R2
RC
CC
Figure 1. 3.3V/3A Buck Regulator
Rev. 1.1 October 2007
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Page 1 of 19
AOZ1212
Ordering Information
Part Number
Ambient Temperature Range
Package
Environmental
AOZ1212AI
-40°C to +85°C
SO-8
RoHS
AOZ1212AI
-40°C to +85°C
SO-8
RoHS
S nt
RoH plia
Com
All AOS Products are offering in packaging with Pb-free plating and compliant to RoHS standards.
Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.
Pin Configuration
LX
1
8
VBIAS
LX
1
BST
2
7
VIN
BST
2
GND
3
6
EN
GND
3
FB
4
5
COMP
FB
4
VIN
GND
SO-8
DFN-8
(Top View)
(Top Thru View)
8
VBIAS
7
VIN
6
EN
5
COMP
Pin Description
Pin Number
Pin Name
Pin Function
1
LX
PWM output connection to inductor. LX pin needs to be connected externally. Thermal connection
for output stage.
2
BST
Bootstrap voltage input. High side driver supply. Connected to 0.1µF capacitor between BST and
LX.
3
GND
4
FB
Feedback input. It is regulated to 0.8V. The FB pin is used to determine the PWM output voltage
via a resistor divider between the output and GND.
5
COMP
External loop compensation. Output of internal error ampli er . Connect a series RC network to
GND for control loop compensation.
6
EN
Enable pin. The enable pin is active HIGH. Connect EN pin to VIN if not used. Do not leave the EN
pin oating.
7
VIN
Supply voltage input. Range from 4.5V to 27V. When VIN rises above the UVLO threshold the
device starts up. All VIN pins need to be connected externally.
8
VBIAS
Compensation pin of internal linear regulator. Place put a 1µF capacitor between this pin and
ground.
Rev. 1.1 October 2007
Ground.
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Page 2 of 19
AOZ1212
Block Diagram
VIN
+5V
VBIAS
UVLO
& POR
EN
5V LDO
Regulator
OTP
+
ISen
–
Reference
& Bias
Softstart
+
0.8V
FB
BST
ILimit
–
Q1
+
GM = 200µA/V
EAmp
–
PWM
Comp
PWM
Control
Logic
LX
+
COMP
+
0.2V
Frequency
Foldback
Comparator
Q2
370kHz/24kHz
Oscillator
–
GND
Absolute Maximum Ratings
Recommend Operating Ratings
Exceeding the Absolute Maximum Ratings may damage the device.
The device is not guaranteed to operate beyond the Maximum
Operating Ratings.
Parameter
Rating
Supply Voltage (VIN)
LX to GND
-0.7V to VIN+0.3V
EN to GND
-0.3V to VIN+0.3V
FB to GND
-0.3V to 6V
COMP to GND
-0.3V to 6V
BST to GND
VBIAS to GND
VLX+6V
-0.3V to 6V
Junction Temperature (TJ)
+150°C
Storage Temperature (TS)
-65°C to +150°C
ESD Rating: Human Body Model(1)
2kV
Note:
1. Devices are inherently ESD sensitive, handling precautions are
required. Human body model rating: 1.5kΩ in series with 100pF.
Rev. 1.1 October 2007
Parameter
30V
Supply Voltage (VIN)
Output Voltage Range
Ambient Temperature (TA)
Package Thermal Resistance (ΘJA)(2)
SO-8
DFN-8
Rating
4.5V to 27V
0.8V to VIN
-40°C to +85°C
105°C/W
53°C/W
Note:
2. The value of ΘJA is measured with the device mounted on 1-in2
FR-4 board with 2oz. Copper, in a still air environment with TA = 25°C.
The value in any given application depends on the user's speci c
board design.
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Page 3 of 19
AOZ1212
Electrical Characteristics
TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified(3)
Symbol
VIN
Parameter
Conditions
Supply Voltage
Min.
Typ.
4.5
Max.
Units
27
V
Input Under-Voltage Lockout Threshold
VIN Rising
VIN Falling
Supply Current (Quiescent)
IOUT = 0, VFB = 1.2V, VEN > 2V
2
3
mA
IOFF
Shutdown Supply Current
VEN = 0V
3
20
µA
VFB
Feedback Voltage
0.8
0.818
V
VUVLO
IIN
IFB
4.3
4.1
0.782
V
Load Regulation
0.5
%
Line Regulation
0.08
%/V
Feedback Voltage Input Current
200
nA
0.6
V
ENABLE
VEN
EN Input Threshold
VHYS
EN Input Hysteresis
Off Threshold
On Threshold
2.5
mV
200
MODULATOR
fO
Frequency
315
DMAX
Maximum Duty Cycle
85
DMIN
Minimum Duty Cycle
370
425
kHz
%
6
%
GVEA
Error Ampli er Voltage Gain
500
V/V
GEA
Error Ampli er Transconductance
200
µA / V
PROTECTION
ILIM
Current Limit
3.5
5.0
A
Over-Temperature Shutdown Limit
TJ Rising
TJ Falling
145
100
°C
fSC
Short Circuit Hiccup Frequency
VFB = 0V
24
kHz
tSS
Soft Start Interval
46
ms
PWM OUTPUT STAGE
RDS(ON)
High-Side Switch On-Resistance
High-Side Switch Leakage
70
VEN = 0V, VLX = 0V
100
mΩ
10
µA
Note:
3. Speci cation in BOLD indicate an ambient temperature range of -40°C to +85°C. These speci cations are guar anteed by design.
Rev. 1.1 October 2007
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Page 4 of 19
AOZ1212
Typical Performance Characteristics
Circuit of Figure 1. TA = 25°C, VIN = VEN = 24V, VOUT = 3.3V unless otherwise speci ed.
Light Load (DCM) Operation
Full Load (CCM) Operation
Vin ripple
0.1V/div
Vin ripple
0.1V/div
Vo ripple
20mV/div
Vo ripple
20mV/div
IL
1A/div
IL
1A/div
VLX
20V/div
VLX
20V/div
1µs/div
1µs/div
Startup to Full Load
Short Circuit Protection
Vo
2V/div
Vo
2V/div
lL
2A/div
lin
0.5A/div
2ms/div
200µs/div
50% to 100% Load Transient
Short Circuit Recovery
Vo
2V/div
Vo Ripple
200mV/div
lo
1A/div
200µs/div
Rev. 1.1 October 2007
IL
2A/div
2ms/div
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AOZ1212
Efficiency Curves
Efficiency
Efficiency
VIN = 5V
100
VIN = 12V
100
8.0V OUTPUT
95
3.3V OUTPUT
Efficieny (%)
Efficieny (%)
95
90
1.8V OUTPUT
85
80
75
0.2
5.0V OUTPUT
90
3.3V OUTPUT
85
80
0.5 0.8
1.1
1.4 1.7
2.0 2.3
2.6
2.9
3.2
75
0.2
0.5 0.8
1.1
1.4 1.7
2.0 2.3
2.6
2.9
3.2
Current (A)
Current (A)
Efficiency
VIN = 24V
100
95
Efficieny (%)
8.0V OUTPUT
90
5.0V OUTPUT
85
3.3V OUTPUT
80
75
Rev. 1.1 October 2007
0.2
0.5 0.8
1.1
1.4 1.7 2.0 2.3
Current (A)
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2.6
2.9
3.2
Page 6 of 19
AOZ1212
Detailed Description
The AOZ1212 is a current-mode step down regulator with
integrated high side NMOS switch. It operates from a
4.5V to 27V input voltage range and supplies up to 3A of
load current. The duty cycle can be adjusted from 6% to
85% allowing a wide range of output voltages. Features
include; enable control, Power-On Reset, input under
voltage lockout, x ed internal soft-start and thermal shut
down.
high-side switch is off. The inductor current is freewheeling through the Schottky diode to the output.
The AOZ1212 is available in an SO-8 or DFN-8 package.
Output Voltage Programming
Enable and Soft Start
The AOZ1212 has an internal soft start feature to limit
in-rush current and ensure the output voltage ramps up
smoothly to the regulation voltage. A soft start process
begins when the input voltage rises to 4.1V and voltage
on EN pin is HIGH. In the soft start process, the output
voltage is typically ramped to regulation voltage in 6.8ms.
The 6.8ms soft start time is set internally.
If the enable function is not used, connect the EN pin to
VIN. Pulling EN to ground will disable the AOZ1212. Do
not leave EN open. The voltage on the EN pin must be
above 2.5 V to enable the AOZ1212. When voltage on
EN pin falls below 0.6V, the AOZ1212 is disabled. If an
application circuit requires the AOZ1212 to be disabled,
an open drain or open collector circuit should be used to
interface with the EN pin.
Switching Frequency
The AOZ1212 switching frequency is x ed and set by
an internal oscillator. The switching frequency is set to
370kHz.
Output voltage can be set by feeding back the output to
the FB pin with a resistor divider network. In the application circuit shown in Figure 1. The resistor divider
network includes R1 and R2. Typically, a design is started
by picking a x ed R2 value and calculating the required
R1 value with equation below.
R 

V O = 0.8 ×  1 + ------1-
R 2

Some standard values for R1 and R2 for the most
commonly used output voltages are listed in Table 1.
Table 1.
VO (V)
R1 (kΩ)
R2 (kΩ)
0.8
1.0
Open
1.2
4.99
10
Steady-State Operation
1.5
10
11.5
Under steady-state conditions, the converter operates in
x ed frequency and Continuous-Conduction Mode
(CCM).
1.8
12.7
10.2
2.5
21.5
10
3.3
31.6
10
The AOZ1212 integrates an internal N-MOSFET as the
high-side switch. Inductor current is sensed by amplifying
the voltage drop across the drain to source of the high
side power MOSFET. Since the N-MOSFET requires a
gate voltage higher than the input voltage, a boost
capacitor connected between the LX and BST pins drives
the gate. The boost capacitor is charged while LX is low.
An internal 10Ω switch from LX to GND is used to ensure
that LX is pulled to GND even in the light load. Output
voltage is divided down by the external voltage divider at
the FB pin. The difference of the FB pin voltage and
reference is ampli ed b y the internal transconductance
error ampli er . The error voltage, which shows on the
COMP pin, is compared against the current signal. The
current signal is the sum of inductor current signal and
ramp compensation signal, at the PWM comparator
input. If the current signal is less than the error voltage,
the internal high-side switch is on. The inductor current
o ws from the input through the inductor to the output.
When the current signal exceeds the error voltage, the
5.0
52.3
10
Rev. 1.1 October 2007
The combination of R1 and R2 should be large enough to
avoid drawing excessive current from the output, which
will cause power loss.
Protection Features
The AOZ1212 has multiple protection features to prevent
system circuit damage under abnormal conditions.
Over Current Protection (OCP)
The sensed inductor current signal is also used for over
current protection. Since the AOZ1212 employs peak
current mode control, the COMP pin voltage is proportional to the peak inductor current. The COMP pin voltage
is limited to be between 0.4V and 2.5V internally. The
peak inductor current is automatically limited cycle by
cycle.
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AOZ1212
The cycle-by-cycle current limit threshold is internally set.
When the load current reaches the current limit threshold, the cycle-by-cycle current limit circuit turns off the
high side switch immediately to terminate the current
duty cycle. The inductor current stops rising. The cycleby-cycle current limit protection directly limits inductor
peak current. The average inductor current is also limited
due to the limitation on the peak inductor current. When
cycle-by-cycle current limit circuit is triggered, the output
voltage drops as the duty cycle decreases.
The AOZ1212 has internal short circuit protection to
protect itself from catastrophic failure under output short
circuit conditions. The FB pin voltage is proportional to
the output voltage. Whenever the FB pin voltage is below
0.2V, the short circuit protection circuit is triggered. To
prevent current limit running away when the comp pin
voltage is higher than 2.1V, the short circuit protection is
also triggered. As a result, the converter is shut down
and hiccups at a frequency equals to 1/16 of normal
switching frequency. The converter will start up via a soft
start once the short circuit condition is resolved. In short
circuit protection mode, the inductor average current is
greatly reduced because of the low hiccup frequency.
Power-On Reset (POR)
A power-on reset circuit monitors the input voltage.
When the input voltage exceeds 4.3V, the converter
starts operation. When input voltage falls below 4.1V,
the converter will stop switching.
Thermal Protection
An internal temperature sensor monitors the junction
temperature. It shuts down the internal control circuit and
high side NMOS if the junction temperature exceeds
145°C. The regulator will restart automatically under the
control of soft-start circuit when the junction temperature
decreases to 100°C.
Application Information
The basic AOZ1212 application circuit is shown in
Figure 1. Component selection is explained below.
Input Capacitor
The input capacitor (C1 in Figure 1) must be connected to
the VIN pin and GND pin of the AOZ1212 to maintain
steady input voltage and lter out the pulsing input
current. The voltage rating of the input capacitor must be
greater than maximum input voltage + ripple voltage.
The input ripple voltage can be approximated by equation
below:
IO
VO VO

∆V IN = ------------------ ×  1 – ---------- × ---------V IN  V IN
f × C IN 
Rev. 1.1 October 2007
Since the input current is discontinuous in a buck
converter, the current stress on the input capacitor is
another concern when selecting the capacitor. For a buck
circuit, the RMS value of input capacitor current can be
calculated by:
VO 
VO
I CIN _RMS = I O × ---------  1 – ----------
V IN 
V IN 
if let m equal the conversion ratio:
VO
---------- = m
V IN
The relationship between the input capacitor RMS
current and voltage conversion ratio is calculated and
shown in Figure 2. It can be seen that when VO is half of
VIN, CIN is under the worst current stress. The worst
current stress on CIN is 0.5 x IO.
0.5
0.4
ICIN_RMS(m) 0.3
IO
0.2
0.1
0
0
0.5
m
1
Figure 2. ICIN vs. Voltage Conversion Ratio
For reliable operation and best performance, the input
capacitors must have a current rating higher than
ICIN_RMS at the worst operating conditions. Ceramic
capacitors are preferred for input capacitors because of
their low ESR and high ripple current rating. Depending
on the application circuits, other low ESR tantalum
capacitor or aluminum electrolytic capacitor may also be
used. When selecting ceramic capacitors, X5R or X7R
type dielectric ceramic capacitors are preferred for their
better temperature and voltage characteristics. Note that
the ripple current rating from capacitor manufactures is
based on certain amount of life time. Further de-rating
may be necessary for practical design requirement.
Inductor
The inductor is used to supply constant current to output
when it is driven by a switching voltage. For given input
and output voltage, inductance and switching frequency
together decide the inductor ripple current, which is,
VO 
VO
∆I L = ----------- ×  1 – ----------
V IN 
f ×L 
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AOZ1212
The peak inductor current is:
∆I
I Lpeak = I O + --------L2
High inductance gives low inductor ripple current but
requires larger size inductor to avoid saturation. Low
ripple current reduces inductor core losses. It also
reduces RMS current through inductor and switches,
which results in less conduction loss.
When selecting the inductor, make sure it is able to
handle the peak current without saturation even at the
highest operating temperature.
The inductor takes the highest current in a buck circuit.
The conduction loss on inductor needs to be checked for
thermal and ef ciency requirements .
Surface mount inductors in different shape and styles are
available from Coilcraft, Elytone and Murata. Shielded
inductors are small and radiate less EMI noise. But they
cost more than unshielded inductors. The choice
depends on EMI requirement, price and size.
Output Capacitor
The output capacitor is selected based on the DC output
voltage rating, output ripple voltage speci cation and
ripple current rating.
The selected output capacitor must have a higher rated
voltage speci cation than the maxim um desired output
voltage including ripple. De-rating needs to be considered for long term reliability.
Output ripple voltage speci cation is another impor tant
factor for selecting the output capacitor. In a buck converter circuit, output ripple voltage is determined by
inductor value, switching frequency, output capacitor
value and ESR. It can be calculated by the equation
below:
1
∆V O = ∆I L ×  ES R CO + ---------------------------

8 × f × C O
∆V O = ∆I L × ES R CO
For lower output ripple voltage across the entire operating temperature range, X5R or X7R dielectric type of
ceramic, or other low ESR tantalum capacitor or
aluminum electrolytic capacitor may also be used as output capacitors.
In a buck converter, output capacitor current is continuous. The RMS current of output capacitor is decided by
the peak to peak inductor ripple current. It can be calculated by:
∆I L
I CO _RMS = ---------12
Usually, the ripple current rating of the output capacitor is
a smaller issue because of the low current stress. When
the buck inductor is selected to be very small and inductor ripple current is high, output capacitor could be overstressed.
Schottky Diode Selection
The external freewheeling diode supplies the current to
the inductor when the high side NMOS switch is off. To
reduce the losses due to the forward voltage drop and
recovery of diode, a Schottky diode is recommended.
The maximum reverse voltage rating of the chosen
Schottky diode should be greater than the maximum
input voltage, and the current rating should be greater
than the maximum load current.
Loop Compensation
The AOZ1212 employs peak current mode control for
easy use and fast transient response. Peak current mode
control eliminates the double pole effect of the output
L&C lter . It greatly simpli es the compensation loop
design.
where;
CO is output capacitor value and
ESRCO is the Equivalent Series Resistor of output capacitor.
When low ESR ceramic capacitor is used as output
capacitor, the impedance of the capacitor at the switching
frequency dominates. Output ripple is mainly caused by
capacitor value and inductor ripple current. The output
ripple voltage calculation can be simpli ed to:
1
∆V O = ∆I L ×  ---------------------------
8 × f × C 
If the impedance of ESR at switching frequency
dominates, the output ripple voltage is mainly decided by
capacitor ESR and inductor ripple current. The output
ripple voltage calculation can be further simpli ed to:
With peak current mode control, the buck power stage
can be simpli ed to be a one-pole and one-z ero system
in frequency domain. The pole is the dominant pole and
can be calculated by:
1
f p1 = -----------------------------------2π × C O × R L
O
Rev. 1.1 October 2007
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Page 9 of 19
AOZ1212
The zero is a ESR zero due to output capacitor and its
ESR. It is can be calculated by:
1
f Z 1 = -------------------------------------------------2π × C O × ESR CO
2π × C O
VO
R C = f C × ----------× ----------------------------V
G ×G
where;
CO is the output lter capacitor ,
FB
ESRCO is the equivalent series resistance of output capacitor.
The compensation design is actually to shape the
converter close loop transfer function to get desired gain
and phase. Several different types of compensation
network can be used for AOZ1212. For most cases, a
series capacitor and resistor network connected to the
COMP pin sets the pole-zero and is adequate for a stable
high-bandwidth control loop.
In the AOZ1212, FB pin and COMP pin are the inverting
input and the output of internal transconductance error
ampli er . A series R and C compensation network
connected to COMP provides one pole and one zero.
The pole is:
G EA
f p2 = -----------------------------------------2π × C C × G VEA
CS
fC is desired crossover frequency,
VFB is 0.8V,
GEA is the error ampli er tr ansconductance, which is 200x10-6
A/V, and
GCS is the current sense circuit transconductance, which is
5.64 A/V
The compensation capacitor CC and resistor RC together
make a zero. This zero is put somewhere close to the
dominate pole fp1 but lower than 1/5 of the selected
crossover frequency. CC can is selected by:
1.5
C C = -----------------------------------2π × R C × f p1
The equation above can also be simpli ed to:
where;
GEA is the error ampli er tr ansconductance, which is 200 x 10-6
A/V,
GVEA is the error ampli er v oltage
The zero given by the external compensation network,
capacitor CC (C5 in Figure 1) and resistor RC (R1 in
Figure 1), is located at:
1
f Z 2 = ------------------------------------2π × C C × R C
To design the compensation circuit, a target crossover
frequency fC for close loop must be selected. The system
crossover frequency is where the control loop has unity
gain. The crossover frequency is also called the
converter bandwidth. Generally a higher bandwidth
means faster response to load transient. However, the
bandwidth should not be too high due to system stability
concern. When designing the compensation loop,
converter stability under all line and load condition must
be considered.
Usually, it is recommended to set the bandwidth to be
less than 1/10 of switching frequency. It is recommended
to choose a crossover frequency less than 30kHz.
Rev. 1.1 October 2007
EA
where;
RL is load resistor value, and
f C = 30kHz
The strategy for choosing RC and CC is to set the cross
over frequency with RC and set the compensator zero
with CC. Using selected crossover frequency, fC, to
calculate RC:
CO × RL
C C = ---------------------RC
An easy-to-use application software which helps to
design and simulate the compensation loop can be found
at www.aosmd.com.
Thermal Management and Layout
Consideration
In the AOZ1212 buck regulator circuit, high pulsing
current o ws through two circuit loops. The rst loop
starts from the input capacitors, to the VIN pin, to the LX
pins, to the lter inductor , to the output capacitor and
load, and then returns to the input capacitor through
ground. Current o ws in the rst loop when the high side
switch is on. The second loop starts from inductor, to the
output capacitors and load, to the GND pin of the
AOZ1212, to the LX pins of the AZO1212. Current o ws
in the second loop when the low side diode is on.
In PCB layout, minimizing the two loops area reduces the
noise of this circuit and improves ef ciency . A ground
plane is recommended to connect input capacitor, output
capacitor, and GND pin of the AOZ1212.
In the AOZ1212 buck regulator circuit, the three major
power dissipating components are the AOZ1212,
external diode and output inductor. The total power
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Page 10 of 19
AOZ1212
dissipation of converter circuit can be measured by input
power minus output power.
P total _loss = V IN × I IN – V O × I O
The power dissipation of inductor can be approximately
calculated by output current and DCR of the inductor.
P inductor _loss = IO2 × R inductor × 1.1
Several layout tips are listed below for the best electric
and thermal performance. Figure 3a and Figure 3b show
layout examples for the AOZ1212A and AOZ1212D
respectively.
1. Do not use thermal relief connection to the VIN and
the GND pin. Pour a maximized copper area to the
GND pin and the VIN pin to help thermal dissipation.
2. Input capacitor should be connected as close as
possible to the VIN and GND pins.
The power dissipation of the diode is:
3. Make the current trace from LX pins to L to CO to
GND as short as possible.
VO

P diode_loss = I O × V F ×  1 – ---------
V IN 

The actual AOZ1212 junction temperature can be
calculated with power dissipation in the AOZ1212 and
thermal impedance from junction to ambient.
4. Pour copper plane on all unused board area and
connect it to stable DC nodes, like VIN, GND or VOUT.
5. Keep sensitive signal traces such as the trace
connecting FB and COMP pins away from the
LX pins.
T junction = ( P total _loss – P inductor _loss ) × Θ JA
+ + T ambient
The maximum junction temperature of AOZ1212 is
145°C, which limits the maximum load current capability.
The thermal performance of the AOZ1212 is strongly
affected by the PCB layout. Care should be taken by
users during design process to ensure that the IC will
operate under the recommended environmental
conditions.
Rev. 1.1 October 2007
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Page 11 of 19
Cc
R2
C1
AOZ1212
Rc
5 COMP
4 FB
6 EN
3 GND
7 Vin
2 BST
8 VBIAS
1 LX
R1
C4
Cb
VIN
AOZ1212
L1
Vo
C
2
C2
Cc
R2
Figure 3a. Layout Example for AOZ1212AI
Rc
COMP
AOZ1212
5
R1
4
FB
3
GND
2
BST
1
LX
VBIAS 8
Vin
C4
C1
Vin 7
Cb
GND
EN 6
Vo
L1
C2
C
2
Figure 3a. Layout Example for AOZ1212DI
Rev. 1.1 October 2007
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Page 12 of 19
AOZ1212
Package Dimensions, SO-8
D
Gauge Plane
Seating Plane
e
0.25
8
L
E
E1
h x 45°
1
C
θ
7° (4x)
A2 A
0.1
b
A1
Dimensions in millimeters
2.20
5.74
1.27
Unit: mm
0.80
Symbols
A
A1
A2
b
c
D
E1
e
E
h
L
θ
Min.
1.35
0.10
1.25
0.31
0.17
4.80
3.80
Nom.
1.65
—
1.50
—
—
4.90
3.90
1.27 BSC
5.80
6.00
0.25
—
0.40
—
0°
—
Max.
1.75
0.25
1.65
0.51
0.25
5.00
4.00
6.20
0.50
1.27
8°
Dimensions in inches
Symbols
A
A1
A2
b
c
D
E1
e
E
h
L
θ
Min.
0.053
0.004
0.049
0.012
0.007
0.189
0.150
Nom. Max.
0.065 0.069
—
0.010
0.059 0.065
—
0.020
—
0.010
0.193 0.197
0.154 0.157
0.050 BSC
0.228 0.236 0.244
0.010
—
0.020
0.016
—
0.050
0°
—
8°
Notes:
1. All dimensions are in millimeters.
2. Dimensions are inclusive of plating
3. Package body sizes exclude mold flash and gate burrs. Mold flash at the non-lead sides should be less than 6 mils.
4. Dimension L is measured in gauge plane.
5. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.
Rev. 1.1 October 2007
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Page 13 of 19
AOZ1212
Tape and Reel Dimensions, SO-8
SO-8 Carrier Tape
P1
D1
See Note 3
P2
T
See Note 5
E1
E2
E
See Note 3
B0
K0
A0
D0
P0
Feeding Direction
Unit: mm
Package
SO-8
(12mm)
B0
5.20
±0.10
A0
6.40
±0.10
K0
2.10
±0.10
D0
1.60
±0.10
D1
1.50
±0.10
E
12.00
±0.10
SO-8 Reel
E1
1.75
±0.10
E2
5.50
±0.10
P0
8.00
±0.10
P2
2.00
±0.10
P1
4.00
±0.10
T
0.25
±0.10
W1
S
G
V
N
M
K
R
H
W
W
N
Tape Size Reel Size
M
12mm
ø330
ø330.00 ø97.00 13.00
±0.10 ±0.30
±0.50
W1
17.40
±1.00
K
H
10.60
ø13.00
+0.50/-0.20
S
2.00
±0.50
G
—
R
—
V
—
SO-8 Tape
Leader/Trailer
& Orientation
Trailer Tape
300mm min. or
75 empty pockets
Rev. 1.1 October 2007
Components Tape
Orientation in Pocket
www.aosmd.com
Leader Tape
500mm min. or
125 empty pockets
Page 14 of 19
AOZ1212
Package Dimensions, DFN 5x4
TOP VIEW
BOTTOM VIEW
FRONT VIEW
Dimensions in millimeters
RECOMMENDED LAND PATTERN
Notes:
1. Dimensions and tolerancing conform to ASME Y14.5M-1994.
Symbols
A
Min.
0.70
A3
b
D
0.40
4.90
D2
D3
2.05
1.66
E
E2
e
3.90
2.23
L
L1
0.50
—
Nom.
0.75
Max.
0.80
Dimensions in inches
Symbols
A
Min.
0.028
A3
b
D
0.016
0.190
2.25
1.88
D2
D3
0.080
0.064
4.00
4.10
2.33
2.43
0.95 BSC
E
E2
e
0.154
0.088
L
L1
0.020
—
0.20 Ref.
0.45
0.50
5.00
5.10
2.15
1.76
0.55
0.40
0.60
—
Nom.
0.30
Max.
0.032
0.008 Ref.
0.018 0.020
0.200 0.210
0.085
0.070
0.089
0.074
0.157 0.161
0.092 0.095
0.037 BSC
0.022
0.016
L2
L3
aaa
0.285 Ref.
0.835 Ref.
0.15
L2
L3
aaa
0.011
0.033
0.006
bbb
ccc
0.10
0.10
bbb
ccc
0.004
0.004
ddd
eee
0.08
0.05
ddd
eee
0.003
0.002
0.024
—
2. All dimensions are in millimeters.
3. The location of the terminal #1 identifier and terminal numbering convention conforms to JEDEC publication 95 SP-002.
4. Dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. If the terminal has the
optional radius on the other end of the terminal, the dimension b should not be measured in that radius area.
5. Coplanarity applies to the terminals and all other bottom surface metallization.
6. Drawing shown are for illustration only.
7. The dimensions with * are just for reference
8. Pin #3 and Pin #7 are fused to DAP.
Rev. 1.1 October 2007
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Page 15 of 19
AOZ1212
Tape and Reel Dimensions, 5x4 DFN-8
Tape
R0
20
0.
.40
T
D1
E1
E2
D0
E
B0
Feeding
Direction
K0
P0
A0
UNIT: mm
Package
A0
B0
K0
D0
D1
E
E1
E2
P0
P1
P2
T
DFN 5x4
(12 mm)
5.30
±0.10
4.30
±0.10
1.20
±0.10
1.50
Min.
Typ.
1.50
+0.10 / –0
12.00
±0.30
1.75
±0.10
5.50
±0.10
8.00
±0.10
4.00
±0.20
2.00
±0.10
0.30
±0.05
Leader/Trailer and Orientation
Trailer Tape
300mm Min.
Rev. 1.1 October 2007
Components Tape
Orientation in Pocket
www.aosmd.com
Leader Tape
500mm Min.
Page 16 of 19
AOZ1212
II
R1
59
Reel
I
R1
6.0±1
21
M
R1
27
I
Zoom In
R6
R1
P
5
R5
B
W1
III
Zoom In
Tape Size
Reel Size
12mm
ø330
M
W1
B
P
ø330
12.40
2.40
±0.3
0.5
+0.3
-4.0
+2.0
-0.0
3-1.8
0.05
II
/4
ø9
6±
0.2
05
A A
N=ø100±2
ø1
0.
"
A
.9
±
3-
ø2
3-ø1
3-
/8"
Zoom In
1.8
6.0
1.8
6.45±0.05
8.00
6.2
ø2
2.20
1.
8.9±0.1
14 REF
0
ø90.0
20
ø13.0
ø17.0
0
R1.10
R3.10
C
1.8
12 REF
44.5±0.1
.95
R3
4.0
6.10
VIEW: C
3-
ø3
"
3/
16
3ø
38°
40°
10.0
EF
8R
R4
46.0±0.1
R0.5
.1
3.3
6.50
A
2.00
ø86
.0±0
10°
R1
5.0
11.90
41.5 REF
43.00
44.5±0.1
0.00
-0.05
2.00
6.50
8.0±0.1
/1
0.80
3.00
2.5
1.80
+0.05
6"
8.000.00
10.71
6°
Rev. 1.1 October 2007
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Page 17 of 19
AOZ1212
AOZ1212 Package Marking
AOZ1212AI
Z1212AI
FAYWLT
Part Number
Assembly Lot Code
Fab & Assembly Location
Year & Week Code
AOZ1212DI
Z1212DI
FAYWLT
Fab & Assembly Location
Part Number
Assembly Lot Code
Year & Week Code
Rev. 1.1 October 2007
www.aosmd.com
Page 18 of 19
AOZ1212
This datasheet contains preliminary data; supplementary data may be published at a later date.
Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.
LIFE SUPPORT POLICY
ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a signi cant injur y of
the user.
Rev. 1.1 October 2007
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Page 19 of 19