PRELIMINARY CM9107 Triple-Output LDO for WLAN Features Product Description • • The CM9107 is a triple-output, low noise, low dropout (LDO) linear regulator with an integrated microproces sor reset circuit. It is designed for use with wireless local-area network chipsets. It has an input voltage range of 3.0V to 3.6V, and supplies a 500mA, 1.80V preset output (LDO1); a 300mA, 2.84V output (LDO2), and a 200mA, low noise output of 2.84V (LDO3). The CM9107 has excellent line and load regulation over the operating temperature range. • • • • • • • • • • • • 3.0V to 3.6V input voltage range Preset output voltage with excellent line and load regulation LDO1 = 1.80V/500mA, ±1.5% max load regulation LDO2 = 2.84V/300mA, ±1% max load regulation LDO3 = 2.84V/200mA, ±1% max load regulation Low output noise (<30µVrms for LDO3) Low dropout voltage; 135mV (typ.) for LDO2 at 300mA, and 110mV (typ.) for LDO3 at 200mA. Low quiescent current, < 600µA typical Integrated microprocessor RESET circuit with adjustable RESET delay (2.5ms per-nF of CT) Logic controlled shutdown Power good signal Built-in power up and power down sequence con trol between LDO1 and LDO2 Over-temperature and over-current protection TQFN-16, RoHS compliant lead-free package The CM9107 LDOs features low dropout voltage by using efficient P-channel MOSFETs for each output. It also features a power good signal (active high) when all three LDOs are in regulation. It provides two shut down control pins, LDO1 and LDO2 power sequencing, plus short-circuit and over-temperature shutdown pro tection. The CM9107 also provides a microprocessor RESET circuit with RST and RST outputs. The RESET signal is asserted when the VIN supply voltage drops below 2.63V, remaining asserted for the adjustable RESET delay period, controlled by an external capacitor on the CT pin. Applications • • • Wireless LAN 802.11 chipset power supply Wireless LAN cards Wireless instrumentation The CM9107 is packaged in a 16-pin TQFN (4mm x 4mm) package. It can operate over the industrial tem perature range of –40°C to 85°C. Typical Application 1 RST 2 1.8V, 500mA Baseband 12 VO1 Co1 CM9107 2.84V, 300mA 10 VO2 4 SHDN3 CC2 5 3.3uF Processor/ MAC CB1 3 SHDN GND Co2 GND3 CT 13 11 CT VO3 0.01uF 14 VIN 15 VIN3 16 PGOOD CIN CC3 10uF RST 3.0V to 3.6V Analog Circuitry 3.3uF 9 Cb 0.033uF 6 7 8 2.84V, 200mA VCO Co3 3.3uF © 2006 California Micro Devices Corp. All rights reserved. 07/11/06 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 l Tel: 408.263.3214 l Fax: 408.263.7846 l www.cmd.com 1 PRELIMINARY CM9107 Package Pinout PACKAGE / PINOUT DIAGRAM TOP VIEW BOTTOM VIEW 10 VO2 10 9 CC2 9 16 VIN 13 15 VIN3 14 14 1 GND PAD 2 3 4 5 11 6 12 11 CB1 7 PGOOD 15 13 12 VO1 8 4 (Pins Up View) GND 8 3 CC3 6 SHDN SHDN3 GND3 7 2 VO3 5 1 CT CM910 700QE RST RST Pin 1 Marking 16 (Pins Down View) CM9107-00QE 16-Lead TQFN Package (4mmx4mm) Note: This drawing is not to scale. PIN DESCRIPTIONS LEAD(s) NAME DESCRIPTION 1 RST 2 CT 3 SHDN Shutdown control input pin for LDO1 and LDO2. Active low, LDO1 and LDO2 will be off when the pin is pulled low. Connect to VIN when unused. 4 SHDN3 Shutdown control input pin for LDO3. Active low. Connect to VIN when unused. Reset bar pin. This is the inverse output of the RST signal pin (pin 16). CT pin for setting the delay time for RST assert (2.5ms per nF). 5 VO3 LDO3 output pin (2.84V). Connect a low-ESR bypass capacitor of 2.2µF, minimum. 6 CC3 This pin is used for testing. In the application it could be either floating or tied to ground 7 GND3 Ground pin for LDO3 8 GND Ground pin for LDO1, LDO2 and control circuit 9 CC2 This pin is used for testing. In the application it could be either floating or tied to ground 10 VO2 LDO2 output pin (2.84V). Connect a low-ESR bypass capacitor of 2.2µF, minimum. 11 CB1 Bypass capacitor pin for internal bandgap reference (typically 0.033µF low-ESR type). 12 VO1 LDO1 output pin (1.80V). Connect a low-ESR bypass capacitor of 2.2µF, minimum. 13 VIN Power input pin for LDO2 and LDO3. Connect to a low-ESR bypass capacitor of 2.2µF, minimum. 14 VIN3 Power input pin for LDO3. Connect to Pin 13, on the PC board, very near the device. 15 PGOOD Power good output pin with internal pull-up resistor to VIN, goes high when all 3 LDOs are in regulation. © 2006 California Micro Devices Corp. All rights reserved. 2 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 l Tel: 408.263.3214 l Fax: 408.263.7846 l www.cmd.com 07/11/06 PRELIMINARY CM9107 Pin Descriptions (cont’d) PIN DESCRIPTIONS 16 RST Reset output pin. When VIN falls below the RESET threshold, this RST pin is asserted (active high). When VIN rises above the RESET threshold, RST goes low after a delay of 2.5ms per nF of CT capacitance. Refer to RESET section in the Application Information. Ordering Information PART NUMBERING INFORMATION Lead Free Finish Pins Package Ordering Part Number1 Part Marking 16 TQFN CM9107-00QE CM9107 00QE Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNITS ±2 kV [GND - 0.3] to +6.0 V [GND - 0.3] to +6.0 [GND - 0.3] to +6.0 [GND - 0.3] to +5.0 [GND - 0.3] to +5.0 V V V V Storage Temperature Range -65 to +150 °C Operating Temperature Range (Ambient) -40 to +85 °C 300 °C ESD Protection (HBM) VIN, VIN3, GND3 to GND Pin Voltages VO1, VO2, VO3 to GND CB1 to GND to GND SHDN, SHDN3 to GND CT, RST, RST, PGOOD to GND Lead Temperature (Soldering, 10sec) ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) SYMBOL VIN IQ VSHDN VIL VIH TSTART PARAMETER CONDITIONS Input Supply Voltage MIN TYP MAX UNITS 3.0 3.3 3.6 V Quiescent Current All outputs are no load 600 750 µA Shutdown Supply Current Shutdown (active low) Input Low Threshold Shutdown Input High Threshold SHDN = SHDN3 = 0 5.0 10 µA 0.4 V Start-up Time (from SHDN going high to VOUT in regulation) (Note 3) 2.0 V VOUT = 95% of final value 120 µs © 2006 California Micro Devices Corp. All rights reserved. 07/11/06 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 l Tel: 408.263.3214 l Fax: 408.263.7846 l www.cmd.com 3 PRELIMINARY CM9107 Specifications (cont’d) ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) SYMBOL TPGOOD PARAMETER CONDITIONS PGOOD Threshold All output currents = 50% rating MIN OPGOOD PGOOD Output Level ISINK = 2mA TYP MAX UNITS +5 % 0.25 V -5 TOVER OTP Threshold 150 ºC THYS OTP Hysteresis 20 ºC UVLO Undervoltage Lockout (Note 2) LDO1 VOUT VOUT acc ILIM VR LIN All outputs are no load. 2.20 IOUT = 10mA -1.5 Output Voltage 2.45 2.65 V +1.5 % 1.80 Output Voltage Accuracy Over-current Limit (Note 2) 550 V 750 mA Line Regulation VIN = 3.0V to 3.6V, IOUT = 10mA -0.15 0.15 %/V VR LOAD Load Regulation (Note 5) IOUT =10mA to 500mA -1.5 1.5 % VOUT N Output Noise 10Hz < f < 100kHz, Co1 = 3.3µF, IOUT = 50mA 100 µVrms LDO2 VOUT VOUT acc ILIM VR LIN Output Voltage 2.84 IOUT = 10mA Output Voltage Accuracy -1.5 Over-current Limit (Note 2) 330 V +1.5 550 % mA Line Regulation VIN = 3.0V to 3.6V, IOUT = 10mA 0.15 %/V VR LOAD Load Regulation (Note 5) IOUT = 10mA to 300mA 0.2 1.0 % VDROP Dropout Voltage (Note 4) IOUT = 30 mA 135 220 mV Output Noise 10Hz < f < 100kHz, IOUT = 10mA Co2 = 2.2µF Co2 = 10µF VOUT N -0.15 70 60 µVrms µVrms 2.84 V LDO3 VOUT VOUT acc ILIM VR LIN Output Voltage IOUT = 10mA Output Voltage Accuracy -1.5 Over-current Limit (Note 2) 250 +1.5 450 % mA Line Regulation VIN3 = 3.0V to 3.6V, IOUT = 10mA VR LOAD Load Regulation (Note 5) IOUT = 10mA to 200mA 0.2 1.0 % VDROP Dropout Voltage (Note 4) IOUT = 200mA 110 200 mV VOUT N Output Noise 10Hz < f < 100kHz, IOUT = 10mA Co3 = 2.2µF Co3 = 10µF RESET TRESET THYS RESET VDROP RESETD TRST RESET Threshold (Vth) (Note 2) -0.15 30 20 2.56 RESET Threshold Hysteresis VIN Dropout Reset Delay VCC = Vth to Vth –100mV RST / RST Timeout Period (Note 2) CT = 10nF 0.15 2.63 %/V µVrms µVrms 2.69 V 10 mV 20 µs 25 ms © 2006 California Micro Devices Corp. All rights reserved. 4 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 l Tel: 408.263.3214 l Fax: 408.263.7846 l www.cmd.com 07/11/06 PRELIMINARY CM9107 Specifications (cont’d) ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) SYMBOL VRST_L PARAMETER CONDITIONS MIN TYP RST / RST Output Low Signal VRST_H UNITS 0.4 V .8 x VIN RST / RST Output High Signal IQ RST MAX V RESET Block Quiescent Current 4 µA Note 1: VIN = VIN3 = 3.3V. CIN = 10µF, CO1 = CO2 = CO3 = 3.3µF, CB = 33nF. TA = 25°C unless otherwise specified. Note 2: Parameter is guaranteed by design, not production tested. Note 3: The start-up time is defined as from SHDN pin goes high until Vo1 reaches regulation; or from SHDN3 goes high until VO3 reaches regulation. Note 4: The dropout voltage is defined as Vind– Vod, where Vod is 50mV below VOUT value measured at VIN = 3.3V. Note 5: Regulation is measured at constant junction temperature using low duty cycle pulse testing. Functional Block Diagram CC2 CC3 3.3V VIN CB1 CIN Cb UVLO & Bandgap 10uF 0.033uF LDO1 PGOOD VO1 Window Comparator Pgood Logic 1.8V 500mA CO1 3.3uF GND LDO2 SHDN Control Logic SHDN3 Enables 2.84V VO2 300mA Window Comparator CO2 3.3uF OTP 150oC VIN RST RST LDO3 Reset Circuit VIN3 VO3 Window Comparator CT CO3 CT .01uF 2.84V 200mA CM9107 GND3 3.3uF © 2006 California Micro Devices Corp. All rights reserved. 07/11/06 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 l Tel: 408.263.3214 l Fax: 408.263.7846 l www.cmd.com 5 PRELIMINARY CM9107 20 0 Vout = 2.84V Load = 50 mA Output Voltage Deviation (mV) Vout = 1.8V Load = 50 mA 20 0 Input Voltage (V) Input Voltage (V) Output Voltage Deviation (mV) Typical Performance Curves 4 3 4 3 Time (10 ms/div) Time (1 ms/div) Line Reguation Response, LDO2 0 Output Voltage Deviation (mV) Vout = 2.84V Load = 50 mA 20 10 0 100 4 3 0 Time (1 ms/div) Time (5 ms/div) Vout = 2.84V Vin = 3.3V 20 10 0 100 Load Reguation Response, LDO1 Output Voltage Deviation (mV) Output Voltage Deviation (mV) Line Reguation Response, LDO3 Vout = 2.84V Vin = 3.3V 20 10 0 100 Load Current (mA) Load Current (mA) Vout = 1.8V Vin = 3.3V 20 Load Current (mA) Input Voltage (V) Output Voltage Deviation (mV) Line Reguation Response, LDO1 0 0 Time (20 ms/div) Time (10 ms/div) Load Reguation Response, LDO2 Load Reguation Response, LDO3 © 2006 California Micro Devices Corp. All rights reserved. 6 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 l Tel: 408.263.3214 l Fax: 408.263.7846 l www.cmd.com 07/11/06 PRELIMINARY CM9107 Application Information The CM9107 is a triple-output, low noise, low dropout (LDO) linear voltage regulator with an integrated micro processor reset circuit. It provides a single-chip power management solution for WLAN systems, providing the fixed output voltages needed for popular wireless chipsets. It has an input voltage range of 3.0V to 3.6V. The device can supply 500mA output from LDO1 (1.8V), 300mA from LDO2 (2.84V) and 200mA from the low-noise LDO3 (2.84V). +/-5% of their nominal regulation value. The PGOOD pin will go low when any output is out of regulation due to over-current dropout, or when thermal shutdown is triggered. The CM9107 achieves its low dropout voltage by using efficient, internal P-channel MOSFETs for each output. The dropout voltage for LDO2 is less than 220mV at 300mA load. The dropout voltage for LDO3 is less than 200mV at 200mA load. The lower voltage output from LDO1 assures sufficient headroom to deliver 500mA once VIN is above the undervoltage lockout point, typi cally 2.45V. The CM9107 has excellent line and load regulation over the operating temperature range. The LDO outputs allow the use of low cost, space-efficient ceramic capacitors. Shutdown Control and Power Up/Down Sequence The LDO3 has exceptionally low output noise, and is ideal for VCO power supplies. The WLAN’s VCO circuit is very phase noise sensitive, and needs clean power for reliable operation. At 10mA output, the noise den sity from 10Hz to 100kHz is typically less than 30µVRMS when using a 2.2µF output capacitor. With a 10µF output capacitor, the noise density is typically 20µVRMS. The PGOOD pin has an internal pull-up resistor. In the shutdown mode (SHDN and SHDN3 both low), PGOOD goes high. The CM9107 provides two active low, shutdown control pins, SHDN and SHDN3. SHDN controls both LDO1 and LDO2. LDO3 is independently controlled with SHDN3. Each shutdown pin has internal pull-up resis tor to VIN. Pulling the pins low shuts-down the appropri ate output. When SHDN goes high, LDO1’s output will rise first. Once LDO1’s output is above about 1.7V, LDO2’s out put will start to rise. When SHDN goes low, LDO2’s output will drop first. When LDO2’s output drops below about 2.7V, LDO1’s output will start to drop. Refer to Figure 1. SHDN Power down sequence Protection The CM9107 has independent over-current protection for each LDO output, with current foldback. The mini mum over-current limit is 550mA for LDO1, 330mA for LDO2, and 250mA for LDO3. The CM9107 includes a thermal shutdown. If there is excessive internal power dissipation due to an over current condition, or a high VIN-VOUT differential, and device’s junction temperature exceeds 150°C (typical), the outputs are turned off. The LDOs are turned on again after the junction temperature drops below 130°C. VO1 1.71V 1.80V Power up sequence 2.84V VO2 2.70V Figure 1. Power Sequencing Power Good Reset The CM9107 provides a high power good signal (PGOOD) if all three LDOs output voltages are within The CM9107’s RESET circuit monitors the VIN voltage only, upstream of the LDOs. This circuit is completely © 2006 California Micro Devices Corp. All rights reserved. 07/11/06 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 l Tel: 408.263.3214 l Fax: 408.263.7846 l www.cmd.com 7 PRELIMINARY CM9107 Application Information (cont’d) independent of the three LDOs and their control cir cuits, functioning as a supervisory circuit for the MAC/ Baseband microprocessor. The RESET circuit has complimentary RST and RST push-pull outputs. When the system is powered-up and VIN reaches a pre-set threshold, RESET waits for the programmed time-period and then signals the microprocessor that VIN is stable. During system operation, VIN is continu ously monitored, and if it drops below the preset threshold, it tells the microprocessor to reset, thus pre venting loss of data. The RESET signals are asserted when the VIN supply voltage drops below 2.63V and will remain asserted for the adjustable RESET delay period, controlled by con necting an external capacitor on the CT pin. The RESET delay period is 2.5ms/nF of CT pin capaci tance. At the end of the delay period, the RESET sig nals are released; RST goes low and RST goes high. Refer to Figure 2. If VIN drops below the RESET threshold again, the RESET signal is re-asserted. The reset delay and threshold hysteresis help assure valid RESET signals in the presence of erratic VIN behavior. The maximum low output voltage is 0.3V at 1.6mA sink current. Minimum high output voltage is 80% of VIN. The RESET circuit consumes less than 5µA quiescent current. Capacitor Selection The CM9107’s LDOs have a wide stability region for a range of output capacitance and ESR values. While 2.2µF will be sufficient for each LDO output, higher out put capacitance, such as 3.3µF, 4.7µF or 10µF, will reduce output noise and over-shoot during load tran sients. Low ESR ceramic capacitors are ideally suited for the outputs of the CM9107, with X5R and X7R dielectrics being the most stable over voltage and tem perature, providing the best performance. To reduce the noise generated by the bandgap circuit, a 33nF, low ESR ceramic capacitor is recommended from the CB1 pin to ground. Load Transient The input and output capacitors will effect the transient load response. The input capacitor will reduce input drop during load transients, improving response on all outputs, while increased output capacitance improves the individual LDO output’s load transient response. Layout Issues Input and output capacitors should be located close to the device. For good thermal conduction, connections to large areas of CU should be provided on the PCB. 20 μs delay VIN 2.63V RST 25 ms delay (CT = 0.01 μF) RST Figure 2. Reset Delay © 2006 California Micro Devices Corp. All rights reserved. 8 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 l Tel: 408.263.3214 l Fax: 408.263.7846 l www.cmd.com 07/11/06 PRELIMINARY CM9107 Application Circuit Power Good + 3.3V CIN 10uF Reset 0.01uF VIN3 PGOOD 12 Co1 11 VO2 SHDN3 CC2 9 Co2 LDO 1 & 2 VOUT1 +1.8V 3.3uF 10 SHDN VO3 Shutdown CB1 CM9107 3 4 VO1 GND CT CT 13 GND3 2 RST CC3 1 Reset 14 VIN 15 RST 16 VOUT2 +2.84V 3.3uF Cb 0.033uF 5 Shutdown 6 7 8 LDO 3 Co3 VOUT3 +2.84V 3.3uF Bill of Materials BILL OF MATERIALS ITEM 1 QUANTITY 1 REFERENCE CIN PART 10µF/10V/1210/X7R MFR any 2 3 Co1, Co2, Co3 3.3µF/10V/1206/X7R any 3 1 CT .01µF/10V/X7R any 4 1 CB .033µF/10V/X7R any © 2006 California Micro Devices Corp. All rights reserved. 07/11/06 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 l Tel: 408.263.3214 l Fax: 408.263.7846 l www.cmd.com 9 PRELIMINARY CM9107 Mechanical Details TQFN-16 Mechanical Specifications Mechanical Package Diagrams The CM9107-00QE is supplied in a 16-lead, 4.0mm x 4.0mm TQFN package. Dimensions are presented below. D E For complete information on the TQFN16, see the Cal ifornia Micro Devices TQFN Package Information doc ument. PACKAGE DIMENSIONS Package TQFN-16 (4x4) Leads 16 Dim. Millimeters Pin 1 Marking 0.15 C Inches Min Nom Max Min Nom Max A 0.70 0.75 0.8 0.027 0.029 0.031 A1 0.00 0.02 0.05 0.000 0.001 0.002 A3 0.203 REF 0.15 C TOP VIEW 0.10 C .008 b 0.25 0.30 0.35 0.010 0.012 0.014 D 3.85 4.00 4.15 0.152 0.157 0.163 D1 2.40 2.50 2.80 0.094 0.098 0.110 E 3.85 4.00 4.15 0.152 0.157 0.163 E1 2.40 2.50 2.80 0.094 0.098 0.110 0.08 C e 0.65 BSC. 0.026 L 0.40 BSC 0.016 A 3000 pieces E1 # per tape and reel A3 A1 SIDE VIEW D1 Controlling dimension: millimeters L b e 16X 0.10 M CAB BOTTOM VIEW Package Dimensions for 16-Lead QFN © 2006 California Micro Devices Corp. All rights reserved. 10 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 l Tel: 408.263.3214 l Fax: 408.263.7846 l www.cmd.com 07/11/06