24LLC16 16K-Bit-Serial EEPROM OVERVIEW The 24LLC16 serial EEPROM has a 16 Kbits (2,048 bytes) capacity, supporting the standard I2C™-bus serial interface. It is fabricated using CERAMATE’s most advanced CMOS technology. One of its major features is a hardware-based write protection circuit for the entire memory area. Hardware-based write protection is controlled by the state of the write-protect (WP) pin. Using one-page write mode, you can load up to 16 bytes of data into the EEPROM in a single write operation. Another significant feature of the 24LLC1616 is its support for fast mode and standard mode. FEATURES I2C-Bus Interface Operating Characteristics • Two-wire serial interface • Operating voltage: 2.0 V to 5.5 V • Automatic word address increment • Operating current — Maximum write current: < 3 mA at 5.5 V EEPROM — Maximum read current: < 200 µA at 5.5 V • 16 Kbits (2,048 bytes) storage area • 16-byte page buffer • Typical 3 ms write cycle time with auto-erase function • Hardware-based write protection for the entire EEPROM (using the WP pin) • EEPROM programming voltage generated on chip • 1,000,000 erase/write cycles • 100 years data retention — Maximum stand-by current: < 2 µA at 2.0 V • Operating temperature range — – 25°C to + 70°C (commercial) — – 40°C to + 85°C (industrial) • Operating clock frequencies — 100 kHz at standard mode — 400 kHz at fast mode • Electrostatic discharge (ESD) — 5,000 V (HBM) — 400 V (MM) Packages • ORDERING INFORMATION 24 LLC Operating Voltage Type LLC:2.0~5.5V,CMOS 16=16K 8-pin DIP, SOP, and TSSOP 16 X X Temp. grade Packing Blank:-25℃~+70℃ Blank :Tube A :Taping(SOP8) T :Taping(TSSOP8) * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: [email protected] Tel:886-3-3214525 Http: www.ceramate.com.tw Page 1 of 22 Rev 1.0 Aug.5, 2002 Fax:886-3-3521052 24LLC16 16K-Bit-Serial EEPROM SDA Start/Stop Logic Control Logic WP SCL HV Generation Timing Control Slave Address Comparator Word Address Pointer Row decoder EEPROM Cell Array 2,048 x 8 bits A0 A1 A2 Column Decoder Data Register DOUT and ACK Figure 5-1. 24LLC16 Block Diagram * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: [email protected] Tel:886-3-3214525 Http: www.ceramate.com.tw Page 2 of 22 Rev 1.0 Aug.5, 2002 Fax:886-3-3521052 24LLC16 16K-Bit-Serial EEPROM VCC WP SCL SDA 24LLC16 A0 NOTE: A1 A2 VSS The 24LLC16 is available in 8-pin DIP, SOP, and TSSOP package. Figure 5-2. Pin Assignment Diagram Table 5-1. 24LLC16 Pin Descriptions Name Type A0, A1, A2 – No internal connection VSS – Ground pin. SDA I/O SCL Description Circuit Type – – 2 Bi-directional data pin for the I C-bus serial data interface. Schmitt trigger input and open-drain output. An external pull-up resistor must be connected to VDD. 3 Input Schmitt trigger input pin for serial clock input. 2 WP Input Input pin for hardware write protection control. If you tie this pin to VCC, the write function is disabled to protect previously written data in the entire memory; if you tie it to VSS, the write function is enabled. This pin is internally pulled down to VSS. 1 VCC – Single power supply. – NOTE: See the following page for diagrams of pin circuit types 1, 2, and 3. * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: [email protected] Tel:886-3-3214525 Http: www.ceramate.com.tw Page 3 of 22 Rev 1.0 Aug.5, 2002 Fax:886-3-3521052 24LLC16 16K-Bit-Serial EEPROM WP Noise Filter SCL Figure 5-3. Pin Circuit Type 1 Figure 5-4. Pin Circuit Type 2 SDA Data Out VSS Noise Filter Data In Figure 5-5. Pin Circuit Type 3 * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: [email protected] Tel:886-3-3214525 Http: www.ceramate.com.tw Page 4 of 22 Rev 1.0 Aug.5, 2002 Fax:886-3-3521052 24LLC16 16K-Bit-Serial EEPROM FUNCTION DESCRIPTION 2 I C-BUS INTERFACE 2 The 24LLC16 supports the I C-bus serial interface data transmission protocol. The two-wire bus consists of a serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected to VCC by a pull-up resistor that is located somewhere on the bus. Any device that puts data onto the bus is defined as a “transmitter” and any device that gets data from the bus is a “receiver.” The bus is controlled by a master device which generates the serial clock and start/stop conditions, 2 controlling bus access. Only one 24LLC16 devices can be connected to the I C-bus as slaves (see Figure 56). Both the master and slaves can operate as a transmitter or a receiver, but the master device determines which bus operating mode would be active. VCC VCC R R SDA SCL Slave Master Bus Master (Transmitter/ Receiver) 24LLC16 Figure 5-6. Typical Configuration * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: [email protected] Tel:886-3-3214525 Http: www.ceramate.com.tw Page 5 of 22 Rev 1.0 Aug.5, 2002 Fax:886-3-3521052 24LLC16 16K-Bit-Serial EEPROM I2C-BUS PROTOCOLS 2 Here are several rules for I C-bus transfers: — A new data transfer can be initiated only when the bus is currently not busy. — MSB is always transferred first in transmitting data. — During a data transfer, the data line (SDA) must remains stable whenever the clock line (SCL) is High. 2 The I C-bus interface supports the following communication protocols: • Bus not busy: The SDA and the SCL lines remain in High level when the bus is not active. • Start condition: A start condition is initiated by a High-to-Low transition of the SDA line while SCL remains in High level. All bus commands must be preceded by a start condition. • Stop condition: A stop condition is initiated by a Low-to-High transition of the SDA line while SCL remains in High level. All bus operations must be completed by a stop condition (see Figure 5-7). ~ ~ SCL ~ ~ SDA Start Condition Data or Data ACK Valid Change Stop Condition Figure 5-7. Data Transmission Sequence • Data valid: Following a start condition, the data becomes valid if the data line remains stable for the duration of the High period of SCL. New data must be put onto the bus while SCL is Low. Bus timing is one clock pulse per data bit. The number of data bytes to be transferred is determined by the master device. The total number of bytes that can be transferred in one operation is theoretically unlimited. • ACK (Acknowledge): An ACK signal indicates that a data transfer is completed successfully. The transmitter (the master or the slave) releases the bus after transmitting eight bits. During the 9th clock, which the master generates, the receiver pulls the SDA line low to acknowledge that it has successfully received the eight bits of data (see Figure 5-8). But the slave does not send an ACK if an internal write cycle is still in progress. In data read operations, the slave releases the SDA line after transmitting 8 bits of data and then monitors the line for an ACK signal during the 9th clock period. If an ACK is detected, the slave will continue to transmit data. If an ACK is not detected, the slave terminates data transmission and waits for a stop condition to be issued by the master before returning to its stand-by mode. * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: [email protected] Tel:886-3-3214525 Http: www.ceramate.com.tw Page 6 of 22 Rev 1.0 Aug.5, 2002 Fax:886-3-3521052 24LLC16 16K-Bit-Serial EEPROM Master SCL Line Bit 1 Bit 9 Data from Transmitter ACK from Receiver ACK Figure 5-8. Acknowledge Response From Receiver • Slave Address: After the master initiates a start condition, it must output the address of the device to be accessed. The most significant four bits of the slave address are called the “device identifier.” The identifier for the 24LLC16 is “1010B”. The next three bits (B2, B1, B0) are for block selection. They are used by the master to select which of the blocks of internal memory (1 block=256 words) are to be accessed. (see Table 5-2 below.) These bits are in effect the three most significant bits of the word address • Read/Write: The final (eighth) bit of the slave address defines the type of operation to be performed. If the R/W bit is “1”, a read operation is executed. If it is “0”, a write operation is executed. Table 5-2. Slave Address Byte Function Device Identifier R/W Bit Block Select b7 b6 b5 b4 b3 b2 b1 b0 Read 1 0 1 0 B2 B1 B0 1 Write 1 0 1 0 B2 B1 B0 0 * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: [email protected] Tel:886-3-3214525 Http: www.ceramate.com.tw Page 7 of 22 Rev 1.0 Aug.5, 2002 Fax:886-3-3521052 24LLC16 16K-Bit-Serial EEPROM BYTE WRITE OPERATION In a complete byte write operation, the master transmits the slave address, word address, and one data byte to the 24LLC16 slave device (see Figure 5-9). Start Slave Address Word Address A C K Data A C K Stop A C K Figure 5-9. Byte Write Operation Following a start condition, the master sends the device identifier (4 bits), three “don’t care” bits, and an R/W bit set to “0” onto the bus. Then the addressed 24LLC16 generates an ACK, and waits for the next byte. The next byte to be transmitted by the master is the word address. This 8-bit address is written into the word address pointer of the 24LLC16 When the 24LLC16 receives the word address, it responds by issuing an ACK and then waits for the next 8bit data. When it receives the data byte, the 24LLC16 again responds with an ACK. The master terminates the transfer by generating a Stop condition, at which time the 24LLC16 begins the internal write cycle. While the internal write cycle is in progress, all 24LLC16 inputs are disabled and the 24LLC16 does not respond to any additional request from the master. * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: [email protected] Tel:886-3-3214525 Http: www.ceramate.com.tw Page 8 of 22 Rev 1.0 Aug.5, 2002 Fax:886-3-3521052 24LLC16 16K-Bit-Serial EEPROM PAGE WRITE OPERATION The 24LLC16 can also perform 16-byte page write operation. A page write operation is initiated in the same way as a byte write operation. However, instead of finishing the write operation after the first data byte is transferred, the master can transmit up to 15 additional bytes. The 24LLC166 responds with an ACK each time it receives a complete byte of data (see Figure 5-10). Start Slave Address Word Address n Data n Data (<= n + 15) Stop ... A C K A C K A C K A C K A C K Figure 5-10. Page Write Operation The 24LLC16 automatically increments the word address pointer each time it receives a complete data byte. When one byte is received, the internal word address pointer increments to the next address so that the next data byte can be received. If the master transmits more than 16 bytes before it generates a stop condition to end the page write operation, the 24LLC16 word address pointer value “rolls over” and the previously received data is overwritten. If the master transmits less than 16 bytes and generates a stop condition, the 24LLC16 writes the received data to the corresponding EEPROM address. During a page write operation, all inputs are disabled and there would be no response to additional requests from the master until the internal write cycle is completed. * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: [email protected] Tel:886-3-3214525 Http: www.ceramate.com.tw Page 9 of 22 Rev 1.0 Aug.5, 2002 Fax:886-3-3521052 24LLC16 16K-Bit-Serial EEPROM POLLING FOR AN ACK SIGNAL When the master issues a stop condition to initiate a write cycle, the 24LLC16 starts an internal write cycle. The master can then immediately begin polling for an ACK from the slave device to determine whether the write cycle is completed. To poll for an ACK signal in a write operation, the master issues a start condition followed by the slave address. As long as the 24LLC16 remains busy with the write operation, no ACK is returned. When the 24LLC16 completes the write operation, it returns an ACK and the master can then proceed with the next read or write operation (see Figure 5-11). Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Condition Send Slave Address with R/W bit = "0" ACK = "0" ? No Yes Start Next Operation Figure 5-11. Master Polling for an ACK Signal from a Slave Device * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: [email protected] Tel:886-3-3214525 Http: www.ceramate.com.tw Page 10 of 22 Rev 1.0 Aug.5, 2002 Fax:886-3-3521052 24LLC16 16K-Bit-Serial EEPROM HARDWARE-BASED WRITE PROTECTION You can also write-protect the entire memory area of the 24LLC16 This method of write protection is controlled by the state of the Write Protect (WP) pin. When the WP pin is connected to VCC, any attempt to write a value to the memory is ignored. The 24LLC16 will acknowledge slave and word address, but it will not generate an acknowledge after receiving first byte of data. In this situation the write cycle will not be started when a stop condition is generated. By connecting the WP pin to VSS, the write function is allowed for the entire memory. These write protection features effectively change the EEPROM to a ROM in order to protect data from being overwritten. Whenever the write function is disabled, a slave address and a word address are acknowledged on the bus, but data bytes are not acknowledged. The WP pin is internally pulled down to VSS. CURRENT ADDRESS BYTE READ OPERATION The internal word address pointer maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either read or write) was to the address “n”, the next read operation would access data at address “n+1”. When the 24LLC16 receives a slave address with the R/W bit set to “1”, it issues an ACK and sends eight bits of data. In a current address byte read operation the master does not acknowledge the data, and it generates a Stop condition, forcing the 24LLC16 to stop the transmission (see Figure 5-12). Start Slave Address Data A C K Stop N O A C K Figure 5-12. Current Address Byte Read Operation * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: [email protected] Tel:886-3-3214525 Http: www.ceramate.com.tw Page 11 of 22 Rev 1.0 Aug.5, 2002 Fax:886-3-3521052 24LLC16 16K-Bit-Serial EEPROM RANDOM ADDRESS BYTE READ OPERATION Using random read operations, the master can access any memory location at any time. Before it issues the slave address with the R/W bit set to “1”, the master must first perform a “dummy” write operation. This operation is performed in the following steps: 1. The master first issues a start condition, the slave address, and the word address to be read. (This step sets the internal word address pointer of the 24LLC16 to the desired address.) 2. When the master receives an ACK for the word address, it immediately re-issues a start condition followed by another slave address, with the R/W bit set to “1”. 3. The 24LLC16 then sends an ACK and the 8-bit data stored at the pointed address. 4. At this point, the master does not acknowledge the transmission, generating a stop condition. 5. The 24LLC16 stops transmitting data and reverts to stand-by mode (see Figure 5-13). Start Slave Address Word Address A C K Start A C K Slave Address Data (n) A C K Stop N O A C K Figure 5-13. Random Address Byte Read Operation * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: [email protected] Tel:886-3-3214525 Http: www.ceramate.com.tw Page 12 of 22 Rev 1.0 Aug.5, 2002 Fax:886-3-3521052 24LLC16 16K-Bit-Serial EEPROM SEQUENTIAL READ OPERATION Sequential read operations can be performed in two ways: current address sequential read operation, and random address sequential read operation. The first data is sent in either of the two ways, current address byte read operation or random address byte read operation described earlier. If the master responds with an ACK, the 24LLC16 continues transmitting data. If the master does not issue an ACK, generating a stop condition, the slave stops transmission, ending the sequential read operation. Using this method, data is output sequentially from address “n” followed by address “n+1”. The word address pointer for read operations increments to all word addresses, allowing the entire EEPROM to be read sequentially in a single operation. After the entire EEPROM is read, the word address pointer “rolls over” and the 24LLC16 continues to transmit data for each ACK it receives from the master (see Figure 5-14). Start Slave Address Data (n) Data (n+x) Stop ~ ~ A C K A C K A C K N O A C K Figure 5-14. Sequential Read Operation * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: [email protected] Tel:886-3-3214525 Http: www.ceramate.com.tw Page 13 of 22 Rev 1.0 Aug.5, 2002 Fax:886-3-3521052 24LLC16 16K-Bit-Serial EEPROM ELECTRICAL DATA Table 5-3. Absolute Maximum Ratings (TA = 25 °C) Symbol Conditions Rating Unit Supply voltage VCC – – 0.3 to + 7.0 V Input voltage VIN – – 0.3 to + 7.0 V Output voltage VO – – 0.3 to + 7.0 V Operating temperature TA – – 40 to + 85 °C Storage temperature TSTG – – 65 to + 150 °C Electrostatic discharge VESD HBM 5000 V MM 400 Parameter Table 5-4. D.C. Electrical Characteristics (TA = – 25 °C to + 70 °C (Commercial), – 40 °C to + 85 °C (Industrial), VCC = 2.0 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit – – 0.3 VCC V 0.7 VCC – – V Input low voltage VIL Input high voltage VIH Input leakage current ILI VIN = 0 to VCC – – 10 µA Output leakage current ILO VO = 0 to VCC – – 10 µA Output Low voltage VOL IOL = 3 mA, VCC = 2.0 V – – 0.4 V ICC1 VCC = 5.5 V, 400 kHz – – 3 mA ICC2 VCC = 2.0 V, 100 kHz – – 1 ICC3 VCC = 5.5 V, 400 kHz – – 0.2 ICC4 VCC = 2.0 V, 100 kHz – – 60 µA ICC5 VCC = SDA = SCL = 5.5 V, all other inputs = 0 V – – 5 µA ICC6 VCC = SDA = SCL = 2.0 V, all other inputs = 0 V – – 2 Supply current Write Read Stand-by current SCL, SDA * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: [email protected] Tel:886-3-3214525 Http: www.ceramate.com.tw Page 14 of 22 Rev 1.0 Aug.5, 2002 Fax:886-3-3521052 24LLC16 16K-Bit-Serial EEPROM Table 5-4. D.C. Electrical Characteristics (Continued) (TA = – 25 °C to + 70 °C (Commercial), – 40 °C to + 85 °C (Industrial), VCC = 2.0 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Input capacitance CIN 25 °C, 1MHz, VCC = 5 V, VIN = 0 V, A0, A1, A2, SCL and WP pin – – 10 pF Input/Output capacitance CI/O 25 °C, 1MHz, VCC = 5 V, VI/O = 0 V, SDA pin – – 10 Table 5-5. A.C. Electrical Characteristics (TA = – 25 °C to + 70 °C (Commercial), – 40 °C to + 85 °C (Industrial), VCC = 2.0 V to 5.5 V) Parameter Symbol Conditions VCC = 2.0 to 5.5 V (Standard Mode) VCC = 4.5 to 5.5 V (Fast Mode) Min Max Min Max Unit Fclk – 0 100 (1) 0 400 (1) kHz Clock High time tHIGH – 4 – 0.6 – µs Clock Low time tLOW – 4.7 – 1.3 – µs External clock frequency Rising time tR SDA, SCL – 1 – 0.3 µs Falling time tF SDA, SCL – 0.3 – 0.3 µs Start condition hold time tHD:STA – 4 – 0.6 – µs Start condition setup time tSU:STA – 4.7 – 0.6 – µs Data input hold time tHD:DAT – 0 – 0 – µs Data input setup time tSU:DAT – 0.25 – 0.1 – µs Stop condition setup time tSU:STO – 4 – 0.6 – µs Bus free time tBUF Before new transmission 4.7 – 1.3 – µs Data output valid from clock low (2) tAA – 0.3 3.5 – 0.9 µs Noise spike width tSP – – 100 – 50 ns Write cycle time tWR – – 5 – 5 ms NOTES: 1. 2. Upon customers request, up to 400 kHz (Max.) in standard mode and 1 MHz in fast mode are available. When acting as a transmitter, the 24LLC16 must provide an internal minimum delay time to bridge the undefined period (minimum 300 ns) of the falling edge of SCL. This is required to avoid unintended generation of a start or stop condition. * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: [email protected] Tel:886-3-3214525 Http: www.ceramate.com.tw Page 15 of 22 Rev 1.0 Aug.5, 2002 Fax:886-3-3521052 24LLC16 16K-Bit-Serial EEPROM tF tHIGH tR tLOW SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO SDA In tAA tBUF SDA Out Figure 5-15. Timing Diagram for Bus Operations ~ ~ SCL ~ ~ SDA 8th Bit ACK ~ ~ WORDn tWR Stop Condition Start Condition Figure 5-16. Write Cycle Timing Diagram * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: [email protected] Tel:886-3-3214525 Http: www.ceramate.com.tw Page 16 of 22 Rev 1.0 Aug.5, 2002 Fax:886-3-3521052 24LLC16 16K-Bit-Serial EEPROM CHARACTERISTIC CURVES NOTE The characteristic values shown in the following graphs are based on actual test measurements. They do not, however, represent guaranteed operating values. (Frequency = 100 kHz) 2.0 1.6 Temp = -40 C Temp = -25 C 1.2 Temp = 25 C I CC (mA) 0.8 Temp = 70 C Temp = 85 C 0.4 0 1.5 2.5 3.5 4.5 5.5 VCC (V) Figure 5-17. Write Current * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: [email protected] Tel:886-3-3214525 Http: www.ceramate.com.tw Page 17 of 22 Rev 1.0 Aug.5, 2002 Fax:886-3-3521052 24LLC16 16K-Bit-Serial EEPROM (Frequency = 100 kHz) 140 120 100 I CC (uA) Temp = -40 C Temp = -25 C 80 Temp = 25 C 60 Temp = 70 C Temp = 85 C 40 20 0 1.5 2.5 3.5 4.5 5.5 VCC (V) Figure 5-18. Read Current 1.5 (Frequency = 100 kHz) 1.2 0.9 I CC (uA) Temp = -40 C 0.6 Temp = -25 C Temp = 25 C 0.3 0 Temp = 70 C Temp = 85 C 1.5 2.5 3.5 4.5 5.5 VCC (V) Figure 5-19. Stand-by Current * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: [email protected] Tel:886-3-3214525 Http: www.ceramate.com.tw Page 18 of 22 Rev 1.0 Aug.5, 2002 Fax:886-3-3521052 24LLC16 16K-Bit-Serial EEPROM (TA = 25 C) 70 VDD = 6 V 60 VDD = 5 V 50 VDD = 4 V 40 I OL (mA) VDD = 3 V 30 20 VDD = 2 V 10 0 0 1 2 3 4 5 6 VOL (V) Figure 5-20. Output Low Voltage * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: [email protected] Tel:886-3-3214525 Http: www.ceramate.com.tw Page 19 of 22 Rev 1.0 Aug.5, 2002 Fax:886-3-3521052 24LLC16 16K-Bit-Serial EEPROM Package Information (1) PDIP-8L D E1 E-PIN O0.118 NOTE 9 PIN #1 INDENT O0.025 DEEP 0.006-0.008 E 7 (4X) A1 L A A2 15 (4X) B e S SYMBOL B1 C B2 eB DIMENSIONS IN MILLIMETERS DIMENSIONS IN INCHS MIN NOM MAX MIN NOM MAX A - - 5.33 - - 0.210 A1 0.38 - - 0.015 - - A2 3.25 3.30 3.45 0.128 0.130 0.136 B 0.36 0.46 0.56 0.014 0.018 0.022 B1 1.14 1.27 1.52 0.045 0.050 0.060 B2 0.81 0.99 1.17 0.032 0.039 0.046 C 0.20 0.25 0.33 0.008 0.010 0.013 D 9.12 9.30 9.53 0.359 0.366 0.375 E 7.62 - 8.26 0.300 - 0.325 E1 6.20 6.35 6.60 0.244 0.250 0.260 e - 2.54 - - 0.100 - L 3.18 - - 0.125 - - Eb 8.38 - 9.40 0.330 - 0.370 s 0.71 0.84 0.97 0.028 0.033 0.038 * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: [email protected] Tel:886-3-3214525 Http: www.ceramate.com.tw Page 20 of 22 Rev 1.0 Aug.5, 2002 Fax:886-3-3521052 24LLC16 16K-Bit-Serial EEPROM E H (2) SOP-8L(JEDEC) L VIEW "A" D 0.015x45 7 (4X) C A A2 7 (4X) VIEW "A" B A1 e y SYMBOL DIMENSIONS IN MILLIMETERS DIMENSIONS IN INCHS MIN NOM MAX MIN NOM MAX A 1.47 1.60 1.73 0.058 0.063 0.068 A1 0.10 - 0.25 0.004 - 0.010 A2 - 1.45 - - 0.057 - B 0.33 0.41 0.51 0.013 0.016 0.020 C 0.19 0.20 0.25 0.0075 0.008 0.0098 D 4.80 4.85 4.95 0.189 0.191 0.195 E 3.81 3.91 3.99 0.150 0.154 0.157 e - 1.27 - - 0.050 - H 5.79 5.99 6.20 0.228 0.236 0.244 L 0.38 0.71 1.27 0.015 0.028 0.050 Y - - 0.10 - - 0.004 - 8 θ o 0 - o 8 o 0 o * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: [email protected] Tel:886-3-3214525 Http: www.ceramate.com.tw Page 21 of 22 Rev 1.0 Aug.5, 2002 Fax:886-3-3521052 24LLC16 16K-Bit-Serial EEPROM E E1 (3) TSSOP-8L PIN 1 INDICATOR O0.70 SURFACE POLISHED L L1 DETAIL A D e DETAIL A C A1 b y SYMBOLS L1 A A2 E1 DIMENSIONS IN MILLIMETERS A MIN 1.05 NOM 1.10 MAX 1.20 A1 0.05 0.10 0.15 A2 B 0.20 1.00 0.25 1.05 0.28 C - 0.127 - D E 2.90 6.20 3.05 6.40 3.10 6.60 E1 4.30 4.40 4.50 E L 0.50 0.65 0.60 0.70 L1 0.90 1.00 1.10 Y 0o 4o 0.10 8o θ * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: [email protected] Tel:886-3-3214525 Http: www.ceramate.com.tw Page 22 of 22 Rev 1.0 Aug.5, 2002 Fax:886-3-3521052