DALLAS DS2250

DS2250(T)
DS2250(T)
Soft Microcontroller Module
FEATURES
PIN ASSIGNMENT
• 8–bit 8051 compatible microcontroller adapts to task–
at–hand:
– 8K, 32K, or 64K bytes of nonvolatile RAM for
program and/or data memory storage
– Initial downloading of software in end system
via on–chip serial port
– Capable of modifying its own program and/or
data memory in end use
1
20
21
40
40-PIN SIMM
• High–reliability operation:
– Maintains all nonvolatile resources for 10 years
in the absence of VCC
– Power–fail reset
– Early warning power–fail interrupt
– Watchdog timer
• Software Security Feature:
– Executes encrypted software to prevent unauthorized disclosure
• On–chip, full–duplex serial I/O ports
• Two on–chip timer/event counters
• 32 parallel I/O lines
• Compatible with
industry standard 8051 instruction
set
• Permanently Powered real time clock
DESCRIPTION
The DS2250(T) Soft Microcontroller Module is a fully
8051 compatible 8–bit CMOS microcontroller that offers
“softness” in all aspects of its application. This is accomplished through the comprehensive use of nonvolatile technology to preserve all information in the absence of system VCC. The internal program/data
memory space is implemented using 8K, 32K, or 64K
bytes of nonvolatile CMOS SRAM. Furthermore, inter-
Copyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
nal data registers and key configuration registers are
also nonvolatile. An optional real time clock gives permanently powered timekeeping. The clock keeps time
to a hundredth of a second using an on–board crystal.
All nonvolatile memory and resources are maintained
for over 10 years at room temperature in the absence of
power.
121395 1/19
DS2250(T)
ORDERING INFORMATION
PART NUMBER
RAM SIZE
MAX CRYSTAL SPEED
TIMEKEEPING?
DS2250–8–16
8K bytes
16 MHz
No
DS2250–32–16
32K bytes
16 MHz
No
DS2250–64–16
64K bytes
16 MHz
No
DS2250T–8–16
8K bytes
16 MHz
Yes
DS2250T–32–16
32K bytes
16 MHz
Yes
DS2250T–64–16
64K bytes
16 MHz
Yes
Operating information is contained in the User’s Guide section of the Secure Microcontroller Data Book. This data
sheet provides ordering information, pinout, and electrical specifications.
121395 2/19
DS2250(T)
DS2250(T) BLOCK DIAGRAM Figure 1
DS2250(T)
VCC
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
VCCO
P0.0–0.7
P2.0–2.7
P3.0–3.7
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
BYTE–WIDE
ADDRESS BUS
P1.0–1.7
8K OR 32K
SRAM
BYTE–WIDE
DATA BUS
DS5000FP
CE1
RST
R/W
ALE
PSEN
EA
XTAL1
XTAL2
GND
32K
SRAM
(–64 only)
CE2
+3V
REAL TIME
CLOCK
(DS2250T)
121395 3/19
DS2250(T)
PIN DESCRIPTION
PIN
1,, 3,, 5,, 7,, 9,,
11, 13, 15
DESCRIPTION
P1.0 – P1.7. General p
purpose
p
I/O Port 1
17
RST – Active high reset input. A logic 1 applied to this pin will activate a reset state. This pin
is pulled down internally so this pin can be left unconnected if not used. An RC power–on
reset circuit is not needed and is not recommended.
19
P3.0 RXD. General purpose I/O port pin 3.0. Also serves as the receive signal for the on
board UART. This pin should not be connected directly to a PC COM port.
21
P3.1 TXD. General purpose I/O port pin 3.1. Also serves as the transmit signal for the on
board UART. This pin should not be connected directly to a PC COM port.
23
P3.2 INT0. General purpose I/O port pin 3.2. Also serves as the active low External
Interrupt 0.
25
P3.3 INT1. General purpose I/O port pin 3.3. Also serves as the active low External
Interrupt 1.
27
P3.4 T0. General purpose I/O port pin 3.4. Also serves as the Timer 0 input.
29
P3.5 T1. General purpose I/O port pin 3.5. Also serves as the Timer 1 input.
31
P3.6 WR. General purpose I/O port pin. Also serves as the write strobe for Expanded bus
operation.
33
P3.7 RD. General purpose I/O port pin. Also serves as the read strobe for Expanded bus
operation.
35, 37
XTAL2, XTAL1. Used to connect an external crystal to the internal oscillator. XTAL1 is the
input to an inverting amplifier and XTAL2 is the output.
39
26, 28, 30,
32, 34, 36,
38, 40
GND – Logic ground.
P2.7–P2.0. General purpose I/O Port 2. Also serves as the MSB of the Expanded Address
bus.
24
PSEN – Program Store Enable. This active low signal is used to enable an external program
memory when using the Expanded bus. It is normally an output and should be unconnected if
not used. PSEN also is used to invoke the Bootstrap Loader. At this time, PSEN will be pulled
down externally. This should only be done once the DS2250(T) is already in a reset state.
The device that pulls down should be open drain since it must not interfere with PSEN under
normal operation.
22
ALE – Address Latch Enable. Used to de–multiplex the multiplexed Expanded Address/Data
bus on Port 0. This pin is normally connected to the clock input on a ’373 type transparent
latch. When using a parallel programmer, this pin also assumes the PROG function for programming pulses.
20
EA – External Access. This pin forces the DS2250(T) to behave like an 8031. No internal
memory (or clock) will be available when this pin is at a logic low. Since this pin is pulled
down internally, it should be connected to +5V to use NVRAM. In an parallel programmer, this
pin also serves as VPP for super voltage pulses.
121395 4/19
DS2250(T)
PIN
4, 6, 8, 10,
12, 14, 16, 18
2
DESCRIPTION
P0.0–P0.7. General purpose I/O Port 0. This port is open–drain and can not drive a logic 1.
It requires external pull–ups. Port 0 is also the multiplexed Expanded Address/Data bus.
When used in this mode, it does not require pull–ups.
VCC + – 5 volts.
INSTRUCTION SET
The DS2250(T) executes an instruction set which is object code compatible with the industry standard 8051
microcontroller. As a result, software development
packages which have been written for the 8051 are
compatible with the DS2250(T), including cross–assemblers, high–level language compilers, and debugging tools. Note that the DS2250(T) is functionally identical to the DS5000(T) except for package and the 64K
memory option.
A complete description for the DS2250(T) instruction
set is available in the User’s Guide section of the Secure
Microcontroller Data Book.
MEMORY ORGANIZATION
Figure 2 illustrates the address spaces which are accessed by the DS2250(T). As illustrated in the figure,
separate address spaces exist for program and data
memory. Since the basic addressing capability of the
machine is 16 bits, a maximum of 64 Kbytes of program
memory and 64 Kbytes of data memory can be accessed by the DS2250(T) CPU. The 8K or 32K byte
RAM area inside of the DS2250(T) can be used to contain both program and data memory. A second 32K
RAM is available for data only.
The Real–time Clock (RTC) in the DS2250(T) is
reached in the memory map by setting a SFR bit. The
MCON.2 bit (ECE2) is used to select an alternate data
memory map. While ECE2=1, all MOVXs will be routed
to this alternate memory map. The real–time clock is a
serial device that resides in this area. A full description
of the RTC access and example software is given in the
User’s Guide section of the Secure Microcontroller Data
Book.
121395 5/19
DS2250(T)
DS2250(T) MEMORY MAP Figure 2
DATA MEMORY (MOVX)
PROGRAM MEMORY
ECE2=0
FFFFh
8000h
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉ ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
NVRAM
DATA
PARTITION
NVRAM
PROGRAM
0000h
ÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÉÉÉÉÉÉ
ÌÌÌÌÌÌ
ÉÉÉÉÉÉ
ÌÌÌÌÌÌ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ECE2=1
64K
32K
NVRAM
DATA
ÉÉ
ÉÉ
ÌÌ
ÌÌ
LEGEND:
= NVRAM MEMORY
= EXPANDED BUS (PORTS 0 AND 2)
= NOT AVAILABLE
PROGRAM LOADING
The Program Load Modes allow initialization of the
NVRAM Program/Data Memory. This initialization may
be performed in one of two ways:
1. Serial Program Loading which is capable of performing Bootstrap Loading of the DS2250(T). This
feature allows the loading of the application program
to be delayed until the DS2250(T) is installed in the
end system.
2. Parallel Program Load cycles which perform the initial loading from parallel address/data information
presented on the I/O port pins. this mode is timing–
set compatible with the 87C51H microcontroller programming mode.
121395 6/19
The DS2250(T) is placed in its Program Load configuration by simultaneously applying a logic 1 to the RST pin
and forcing the PSEN line to a logic 0 level. Immediately
following this action, the DS2250(T) will look for a parallel Program Load pulse, or a serial ASCII carriage return
(0DH) character received at 9600, 2400, 1200, or 300
bps over the serial port.
The hardware configurations used to select these
modes of operation are illustrated in Figure 3.
DS2250(T)
PROGRAM LOADING CONFIGURATIONS Figure 3
VCC
GND
VCC
P1.7–
P1.0
P0.7–
P0.0
P2.5–
P2.0
P3.7–
P3.2
P2.6
TXD
P2.7
GND
DS2250
DS2250
RXD
PROGRAM
ADDRESS
A7–A0
P1.7–
P1.0
P0.7–
P0.0
A11–A8
P2.3–
P2.0
P3.7–
P3.4
D7–D0
PROGRAM
DATA IN/VERIFY
DATA OUT
A15–A12 PROGRAM
ADDRESS
EA/VPP
DRIVE/
RCV
RS232C
ALE/PROG
PROGRAM
CONTROL
P2.7
P2.6
XTAL1
R<2K
P2.5
R<2K
11.059 MHz
RST
XTAL1
PSEN
PSEN
XTAL2
XTAL2
SERIAL
LOADING
Table 1 summarizes the selection of the available Parallel Program Load cycles. The timing associated with
these cycles is illustrated in the electrical specs.
SERIAL BOOTSTRAP LOADER
The Serial Program Load Mode is the easiest, fastest,
most reliable, and most complete method of initially
loading application software into the DS2250(T) nonvolatile RAM. Communication can be performed over a
standard asynchronous serial communications port. A
typical application would use a simple RS232C serial interface to program the DS2250(T) as a final production
procedure. The hardware configuration which is required for the Serial Program Load mode is illustrated in
Figure 3. Port pins 2.7 and 2.6 must be either open or
pulled high to avoid placing the device in a parallel load
cycle. Although an 11.0592 MHz crystal is shown in Figure 3, a variety of crystal frequencies and loader baud
rates are supported, shown in Table 2. The serial loader
is designed to operate across a three–wire interface
from a standard UART. The receive, transmit, and
ground wires are all that are necessary to establish
communication with the DS2250(T).
RST
PARALLEL
LOADING
program in an Intel hex representation to be loaded into
and read back from the device. Intel hex is the typical
format which existing 8051 cross–assemblers output.
The serial loader responds to single character commands which are summarized below:
COMMAND
C
D
F
K
L
R
T
U
V
W
Z
P
G
FUNCTION
Return CRC–16 checksum of embedded RAM
Dump Intel Hex File
Fill embedded RAM block with
constant
Load 40–bit Encryption Key
Load Intel Hex File
Read MCON register
Trace (Echo) incoming Intel Hex
data
Clear Security Lock
Verify Embedded RAM with incoming Intel Hex
Write MCON register
Set Security Lock
Put a value to a port.
Get a value from a port.
The Serial Bootstrap Loader implements an easy–to–
use command line interface which allows an application
121395 7/19
DS2250(T)
PARALLEL PROGRAM LOAD CYCLES Table 1
MODE
Program
RST
PSEN
PROG
EA
P2.7
P2.6
P2.5
1
0
0
VPP
1
0
X
Security Set
1
0
0
VPP
1
1
X
Verify
1
X
X
1
0
0
X
Prog Expanded
1
0
0
VPP
0
1
0
Verify Expanded
1
0
1
1
0
1
0
Prog MCON or Key registers
1
0
0
VPP
0
1
1
Verify MCON registers
1
0
1
1
0
1
1
The Parallel Program Cycle is used to load a byte of
data into a register or memory location within the
DS2250(T). The Verify Cycle is used to read this byte
back for comparison with the originally loaded value to
verify proper load ing. The Security Set Cycle may be
used to enable and the Software Security feature. One
may also enter bytes for the MCON register or for the
five encryption registers using the Program MCON
cycle. When using this cycle, the absolute register address must be presented at Ports 1 and 2 as in the normal program cycle (Port 2 should be 00H). The MCON
contents can likewise be verified using the Verify MCON
cycle.
When the DS2250(T) first detects a Parallel Program
Strobe pulse or a Security Set Strobe pulse while in the
Program Load Mode following a Power On Reset, the
internal hardware of the device is initialized so that an
existing 4 Kbyte program can be programmed into a
DS2250(T) with little or no modification. This initialization automatically sets the Range Address for 8 Kbytes
and maps the lowest 4 Kbyte bank of Embedded RAM
121395 8/19
as program memory. The next 4 Kbytes of Embedded
RAM are mapped as Data Memory.
In order to program more than 4 Kbytes of program
code, the Program/Verify Expanded cycles can be
used. Up to 32 Kbytes of program code can be entered
and verified. Note that the expanded 32 Kbyte Program/
Verify cycles take much longer than the normal 4 Kbyte
Program/Verify cycles.
A typical parallel loading session would follow this procedure. First, set the contents of the MCON register
with the correct range and partition only if using expanded programming cycles. Next, the encryption registers
can be loaded to enable encryption of the program/data
memory (not required). Then, program the DS2250(T)
using either normal or expanded program cycles and
check the memory contents using Verify cycles. The
last operation would be to turn on the security lock feature by either a Security Set cycle or by explicitly writing
to the MCON register and setting MCON.0 to a 1.
DS2250(T)
SERIAL LOADER BAUD RATES FOR DIFFERENT CRYSTAL FREQUENCIES Table 2
BAUD RATE
CRYSTAL FREQ (MHz)
300
14.7456
1200
2400
9600
19200
Y
Y
Y
Y
Y
11.0592
Y
Y
Y
Y
9.21600
Y
Y
Y
Y
7.37280
Y
Y
Y
Y
5.52960
Y
Y
Y
Y
1.84320
Y
Y
Y
Y
ADDITIONAL INFORMATION
A complete description for all operational aspects of the
DS2250(T) is provided in the User’s Guide section of the
Secure Microcontroller Data Book.
DEVELOPMENT SUPPORT
Dallas Semiconductor offers a kit package for developing and testing user code. The DS5000TK Evaluation
57600
Y
Kit allows the user to download Intel hex formatted code
directly to the DS2250(T) from a PC–XT/AT or compatible computer. The kit consists of a DS5000T–32–12,
an interface pod, demo software, and an RS232 connector that attaches to the COM1 or COM2 serial port of
a PC. The kit can be used with a DS2250(T). A mechanical adaptor, the DS9075–40V, allows a DS2250(T) to
be used in the DS5000TK. See the Secure Microcontroller User’s Guide for further details.
121395 9/19
DS2250(T)
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
–0.3V to +7.0V
0°C to 70°C
–40°C to +70°C
260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
DC CHARACTERISTICS
PARAMETER
(tA = 0°C to70°C; VCC = 5V + 5%)
SYMBOL
MIN
Input Low Voltage
VIL
Input High Voltage
VIH1
Input High Voltage RST, XTAL1
VIH2
Output Low Voltage
@ IOL=1.6 mA (Ports 1, 2, 3)
VOL1
Output Low Voltage
@ IOL=3.2 mA (Ports 0, ALE,
PSEN)
VOL2
Output High Voltage
@ IOH=–80 µA(Ports 1, 2, 3)
VOH1
2.4
Output High Voltage
@IOH=–400 µA(Ports 0, ALE,
PSEN)
VOH2
2.4
TYP
MAX
UNITS
NOTES
–0.3
+0.8
V
1
2.0
VCC +0.3
V
1
3.5
VCC +0.3
V
1
0.15
0.45
V
0.15
0.45
V
1
4.8
V
1
4.8
V
1
Input Low Current VIN = 0.45V
(Ports 1, 2, 3)
IIL
–50
µA
Transition Current; 1 to 0
VIN = 2.0V (Ports 1, 2, 3)
ITL
–500
µA
Input Leakage Current
0.45 < VIN < VCC (Port 0)
IL
+10
µA
125
KΩ
80
µA
4
RST, EA Pulldown Resistor
RRE
Stop Mode Current
ISM
40
Power Fail Warning Voltage
VPFW
4.15
4.6
4.75
V
1
Minimum Operating Voltage
VCCmin
4.05
4.5
4.65
V
1
Programming Supply Voltage
(Parallel Program Mode)
VPP
12.5
13
V
1
Program Supply Current
IPP
20
mA
Operating Current DS2250–8K
DS2250–32K @ 12 MHz
DS2250(T)–64–16 @ 16 MHz
ICC
43
48
54
mA
2
Idle Mode Current @ 8 MHz
ICC
6.2
mA
3
121395 10/19
15
DS2250(T)
AC CHARACTERISTICS
EXPANDED BUS MODE TIMING SPECIFICATIONS
SYMBOL
(tA = 0°C to70°C; VCC = 5V + 5%)
#
PARAMETER
MIN
MAX
UNITS
1
Oscillator Frequency
2
ALE Pulse Width
1/tCLK
1.0
16 (–16)
MHz
tALPW
2tCLK–40
ns
3
4
Address Valid to ALE Low
tAVALL
tCLK –40
ns
Address Hold After ALE Low
tAVAAV
tCLK –35
ns
5
ALE Low to Valid Instr. In
6
ALE Low to PSEN Low
tALLPSL
tCLK –25
ns
7
PSEN Pulse Width
tPSPW
3tCLK –35
ns
8
PSEN Low to Valid Instr. In
9
Input Instr. Hold after PSEN Going High
10
Input Instr. Float after PSEN Going High
tPSIX
11
Address Hold after PSEN Going High
tPSAV
12
Address Valid to Valid Instr. In @12 MHz
@16 MHz
tAVVI
13
PSEN Low to Address Float
tPSLAZ
0
ns
14
RD Pulse Width
tRDPW
6tCLK –100
ns
15
WR Pulse Width
tWRPW
6tCLK –100
16
RD Low to Valid Data In
17
Data Hold after RD High
18
Data Float after RD High
tRDHDZ
2tCLK –70
ns
19
ALE Low to Valid Data In
@12 MHz
@16 MHz
tALLVD
8CLK –150
8tCLK –90
ns
ns
20
Valid Addr. to Valid Data In
@12 MHz
@16 MHz
tAVDV
9tCLK –165
9tCLK –105
ns
ns
21
ALE Low to RD or WR Low
tALLRDL
3tCLK –50
3tCLK +50
ns
22
Address Valid to RD or WR Low
tAVRDL
4tCLK –130
ns
23
Data Valid to WR Going Low
24
Data Valid to WR High
25
Data Valid after WR High
26
RD Low to Address Float
27
RD or WR High to ALE High
@12 MHz
@16 MHz
@12 MHz
@16 MHz
@12 MHz
@16 MHz
tALLVI
tPSLVI
tPSIV
3tCLK –150
3tCLK –90
0
ns
ns
ns
ns
tCLK –20
tCLK –8
ns
ns
5tCLK –150
5tCLK –90
tRDLDV
tRDHDV
@12 MHz
@16 MHz
4tCLK –150
4tCLK–90
ns
ns
ns
5tCLK –165
5tCLK –105
0
ns
ns
ns
tDVWRL
tCLK –60
ns
tDVWRH
7tCLK –150
7tCLK –90
ns
ns
tWRHDV
tCLK –50
ns
tRDLAZ
tRDHALH
tCLK –40
0
ns
tCLK +50
ns
121395 11/19
DS2250(T)
EXPANDED PROGRAM MEMORY READ CYCLE
2
ALE
6
7
5
8
11
PSEN
13
9
3
PORT 0
10
4
A7–A0
INSTR IN
A7–A0
12
PORT 2
A15–A8
A15–A8
EXPANDED DATA MEMORY READ CYCLE
27
ALE
PSEN
19
21
14
RD
16
18
3
PORT 0
26
4
A7–A0
(Rn OR DPL)
17
DATA IN
A7–A0
(PCL)
INSTR
IN
22
20
PORT 2
121395 12/19
P2.7–P2.0 OR A15–A8 FROM DPH
A15–A8 FROM PCH
DS2250(T)
EXPANDED DATA MEMORY WRITE CYCLE
27
ALE
PSEN
21
15
WR
23
4
3
PORT 0
25
24
A7–A0
(Rn OR DPL)
A7–A0
(PCL)
DATA OUT
INSTR
IN
22
PORT 2
P2.7–P2.0 OR A15–A8 FROM DPH
A15–A8 FROM PCH
EXTERNAL CLOCK TIMING
28
29
30
31
1
121395 13/19
DS2250(T)
AC CHARACTERISTICS (cont’d)
EXTERNAL CLOCK DRIVE
#
PARAMETER
28
External Clock High Time
29
(tA = 0°C to70°C; VCC = 5V + 5%)
SYMBOL
MIN
@12 MHz
@16 MHz
tCLKHPW
20
15
ns
ns
External Clock Low Time
@12 MHz
@16 MHz
tCLKLPW
20
15
ns
ns
30
External Clock Rise Time
@12 MHz
@16 MHz
tCLKR
20
15
ns
ns
31
External Clock Fall Time
@12 MHz
@16 MHz
tCLKF
20
15
ns
ns
AC CHARACTERISTICS (cont’d)
POWER CYCLING TIMING
MAX
UNITS
(tA = 0°C to70°C; VCC = 5V + 5%)
#
PARAMETER
SYMBOL
MIN
tF
40
MAX
UNITS
32
Slew Rate from VCCmin to 3.3V
33
Crystal Start up Time
tCSU
(note 5)
34
Power On Reset Delay
tPOR
21504
µs
tCLK
SERIAL PORT TIMING – MODE 0
INSTRUCTION
0
1
2
3
4
5
6
7
8
ALE
35
CLOCK
36
37
DATA OUT
0
1
2
3
4
5
6
7
SET TI
WRITE TO
SBUF REGISTER
39
38
SET RI
INPUT DATA
VALID
CLEAR RI
121395 14/19
VALID
VALID
VALID
VALID
VALID
VALID
DS2250(T)
AC CHARACTERISTICS (cont’d)
SERIAL PORT TIMING – MODE 0
#
PARAMETER
35
(tA = 0°C to70°C; VCC = 5V + 5%)
SYMBOL
MIN
MAX
UNITS
Serial Port Cycle Time
tSPCLK
12tCLK
µs
36
Output Data Setup to Rising Clock Edge
tDOCH
10tCLK –133
ns
37
Output Data Hold after Rising Clock Edge
tCHDO
2tCLK –117
38
Clock Rising Edge to Input Data Valid
tCHDV
39
Input Data Hold after Rising Clock Edge
tCHDIV
ns
10tCLK –133
0
ns
ns
POWER CYCLE TIMING
VCC
VPFW
VCCMIN
VLI
32
INTERRUPT
SERVICE
ROUTINE
33
CLOCK
OSC
34
INTERNAL
RESET
LITHIUM
CURRENT
121395 15/19
DS2250(T)
AC CHARACTERISTICS (cont’d)
PARALLEL PROGRAM LOAD TIMING
#
PARAMETER
40
(tA = 0°C to70°C; VCC = 5V + 5%)
SYMBOL
MIN
MAX
UNITS
Oscillator Frequency
1/tCLK
1.0
12.0
MHz
41
Address Setup to PROG Low
tAVPRL
0
42
Address Hold after PROG High
tPRHAV
0
43
Data Setup to PROG Low
tDVPRL
0
44
Data Hold after PROG High
tPRHDV
0
45
P2.7, 2.6, 2.5 Setup to VPP
tP27HVP
0
46
VPP Setup to PROG Low
tVPHPRL
0
47
VPP Hold after PROG Low
tPRHVPL
0
48
PROG Width Low
tPRW
2400
49
Data Output from Address Valid
tAVDV
48
1800*
tCLK
50
Data Output from P2.7 Low
tDVP27L
48
1800*
tCLK
51
Data Float after P2.7 High
tP27HDZ
0
48
1800*
tCLK
52
Delay to Reset/PSEN Active after
Power On
tPORPV
21504
tCLK
53
Reset/PSEN Active (or Verify Inactive) to
VPP High
tRAVPH
1200
tCLK
54
VPP Inactive (Between Program Cycles)
tVPPPC
1200
tCLK
55
Verify Active Time
tVFT
48
2400*
tCLK
* Second set of numbers refers to expanded memory programming up to 32K bytes.
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tCLK
DS2250(T)
PARALLEL PROGRAM LOAD TIMING
P2.3–P2.0
P1.7–P1.0
ADDRESS
41
ADDRESS
ADDRESS
42
49
DATA
PORT
DATA
DATA
44
43
ALE/PROG
51
47
46
48
54
VPP
EA/VPP
VIH
45
50
53
P2.7, P2.6, P2.5
ACTIVE
55
+5V
VCC
52
53
RST
PSEN
CAPACITANCE
PARAMETER
(test frequency = 1 MHz; tA = 25°C)
SYMBOL
MIN
TYP
MAX
UNITS
Output Capacitance
CO
10
pF
Input Capacitance
CI
10
pF
NOTES
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DS2250(T)
DS2250(T) TYPICAL ICC VS. FREQUENCY
30.0
NORMAL
OPERATION
Icc CURRENT (mA)
25.0
20.0
15.0
10.0
IDLE MODE
OPERATION
5.0
0
0.0
5.0
10.0
15.0
FREQUENCY OF OPERATION (MHz)
(VCC=+5V, tA=25°C)
Normal operation is measured using:
1)
External crystals on XTAL1 and 2
2)
All port pins disconnected
3)
RST=0 volts and EA=VCC
4)
Part performing endless loop writing to internal memory.
Idle mode operation is measured using:
1)
External clock source at XTAL1; XTAL2 floating
2)
All port pins disconnected
3)
RST=0 volts and EA=VCC
4)
Part set in IDLE mode by software.
NOTES:
1. All voltages are referenced to ground.
2. Maximum operating ICC is measured with all output pins disconnected; XTAL1 driven with tCLKR,
tCLKF=10 ns, VIL = 0.5V; XTAL2 disconnected; EA = RST = PORT0 = VCC.
3. Idle mode ICC is measured with all output pins disconnected; XTAL1 driven at 8 MHz with tCLKR, tCLKF = 10 ns,
VIL = 0.5V; XTAL2 disconnected; EA = PORT0 = VCC, RST = VSS.
4. Stop mode ICC is measured with all output pins disconnected; EA = PORT0 = VCC; XTAL2 not connected;
RST = VSS.
5. Crystal start up time is the time required to get the mass of the crystal into vibrational motion from the time that
power is first applied to the circuit until the first clock pulse is produced by the on-chip oscillator. The user
should check with the crystal vendor for the worst case spec on this time.
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DS2250(T)
PACKAGE DRAWING
P
O
(SIDE B)
N
(SIDE A)
A
B
J
(SIDE B) C
M
CL
E
D
G
I
I
H
K
L
F
PKG
40–PIN
DIM
MIN
MAX
A
2.645
2.655
B
2.379
2.389
C
0.845
0.855
D
0.395
0.405
E
0.245
0.255
F
0.050 BSC
G
0.075
0.085
H
0.245
0.255
I
0.950 BSC
J
0.120
0.130
K
1.320
1.330
L
1.445
1.455
M
0.057
0.067
N
–
0.160
O
–
0.195
P
–
0.054
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