EPSON S1L51254

DATA SHEET
ASIC
S1L50000
S1L50000 SERIES HIGH DENSITY GATE ARRAY
ΠDESCRIPTION
EPSON Electronics America, Inc.’s S1L50000 Series is a family of ultra high-speed VLSI CMOS
gate array utilizing a 0.35µm “sea-of-gates” architecture. The S1L50000H products feature 5V
tolerant I/O buffers.
•
•
•
Ultra-high-speed, high density and low power consumption
Low voltage operation: 3.3V and 2.0V
Number of raw gates: 28,710 ~ 815,468 gates
ΠFEATURES
•
Process
0.35µm 2/3/4 layer metalization CMOS process
•
Integration
A maximum of 815,468 gates (2 input NAND gate equivalent)
•
Operating Speed
Internal gates: 140 ps (3.3V Typ), 210 ps (2.0V Typ)
(2-input pair NAND, F/O = 2, Typical wire load)
Input buffer: 380 ps (5.0V Typ) Built-in level shifter is used.
400 ps (3.3V Typ), 1.30 ns (2.0V Typ)
(F/O = 2, Typical wire load)
Output buffer: 2.12 ns (5.0V Typ) Built-in level shifter is used.
2.02 ns (3.3 V Typ), 3.90 ns (2.0V Typ)
(CL = 15 pF)
•
I/F Levels
Input/Output TTL/CMOS/LVTTL compatible
•
Input Modes
TTL, CMOS, LVTTL, TTL Schmitt, CMOS Schmitt, LVTTL Schmitt, PCI
Built-in pull-up and pull-down resistors can be usable.
(2 types for each resistor value)
•
Output Modes
Normal, 3-state, bi-directional, PCI
•
Output Drive
IOL = 0.1, 1, 3, 8, 12, 24 mA selectable
(Built-in level shifter is used at 5.0V)
IOL = 0.1, 1, 2, 6, 12 mA selectable (at 3.3V)
IOL = 0.05, 0.3, 0.6, 2, 4 mA selectable (at 2.0V)
•
RAM
Asynchronous 1-port, asynchronous 2-port
•
Dual Power
Operation supported by using level-shifter circuit
Internal logic: Operation supported by low voltage
I/O Buffer:
Built-in interfaces of both high and low voltages possible
•
Operation possible at VDD = 2.0 ± 0.2V
EPSON ELECTRONICS AMERICA, INC.
i150 River Oaks Pkwy iSan Jose, CA 95134 iTel: (408) 922-0200 iFax: (408) 922-0238
1
DATA SHEET
ASIC
S1L50000
ΠLINE UP
The S1L50000 Series comprises 11 types of masters, from which the customer is able to select
the master most suitable.
Master
S1L50282/283/284
S1L50752/753/754
S1L50992/993/994
S1L51252/253/254
S1L51772/773/774
S1L52502/503/504
S1L53352/353/354
S1L54422/423/424
S1L55062/063/064
S1L56682/683/684
S1L58152/153/154
Total
BC
(Raw Gates)
Number
of
Pads
Number
of
Columns (X)
Number
of
Rows (Y)
28710
75774
99198
125772
177062
250160
335858
442112
506688
668552
815468
88
144
168
188
224
264
308
352
376
432
480
319
519
594
669
794
944
1094
1256
1344
1544
1706
90
146
167
188
223
265
307
352
377
433
478
Cell Utilization Ratio (U)*1
2-layer 3-layer 4-layer
metal
metal
metal
50%
47%
47%
45%
45%
45%
43%
40%
40%
40%
40%
88%
85%
85%
80%
75%
75%
75%
70%
70%
70%
70%
95%
95%
95%
95%
95%
95%
95%
90%
90%
90%
90%
NOTE: *1: This is the value when there are no cells, such as RAM cells. The cell use efficiency is dependent not only on the scope of
the circuits, but also on the number of signals, the number of branches per signal, etc.; thus, use the values in this table only
as an estimate
2
EPSON ELECTRONICS AMERICA, INC.
i 150 River Oaks Pkwy i San Jose, CA 95134 i Tel: (408) 922-0200 i Fax: (408) 922-0238
DATA SHEET
ASIC
S1L50000
ΠELECTRICAL CHARACTERISTICS AND SPECIFICATIONS
Absolute Maximum Ratings (For Single Power Supply):
(Vss = 0V)
Item
Power Supply Voltage
Input Voltage
Output Voltage
Output Current/Pin
Storage Temperature
Symbol
VDD
VI
VO
IOUT
TSTG
Limits
Unit
-0.3 to 4.0
*1
-0.3 to VDD + 0.5
*1
-0.3 to VDD + 0.5
± 30
-65 to 150
V
V
V
mA
°C
*
1: Possible to use from -0.3V to 7.5V of I/O buffer voltage in the open-drain systems and input buffer in the IDC and IDH
systems.
Absolute Maximum Ratings (For Dual Power Supplies):
(Vss = 0V)
Item
Power Supply Voltage
Input Voltage
Symbol
HVDD
-0.3 to 7.0
LVDD
-0.3 to 4.0
HVI
LVI
Output Voltage
Output Current/Pin
Storage Temperature
**
Limits
HVO
Unit
V
V
*1
V
*1
V
*1
V
*1
V
-0.3 to HVDD + 0.5
-0.3 to LVDD + 0.5
-0.3 to HVDD + 0.5
LVO
-0.3 to LVDD + 0.5
IOUT
TSTG
± 30 (± 50 )
-65 to 150
*2
mA
°C
1: Possible to use from -0.3V to 7.5V of I/O buffer voltage in the open-drain systems and input buffer in the IDC and IDH
systems.
*2: Possible to use for 24mA of output buffer.
EPSON ELECTRONICS AMERICA, INC.
i150 River Oaks Pkwy iSan Jose, CA 95134 iTel: (408) 922-0200 iFax: (408) 922-0238
3
DATA SHEET
ASIC
S1L50000
Recommended Operating Conditions (For Single Power Supplies):
Item
Symbol
Power Supply Voltage
Input Voltage
Ambient Temperature
VDD
VI
Ta
Normal Input for Rising Edge Input
Normal Input for Falling Edge Input
Schmitt Input for Rising Edge Input
Schmitt Input for Falling Edge Input
tri
tfi
tri
tfi
Min
3.00
VSS
0
-40
-----
Typ
3.30
-25
25
-----
Max
3.60
*1
VDD
*2
70
*3
85
50
50
5
5
Unit
V
V
°C
ns
ns
ms
ms
*1: Possible to use 5.25 or 5.50V of I/O buffer in the open-drain systems and input buffer in the IDC and IDH systems.
*2: The ambient temperature range is recommended for Tj = 0 to 80°C
*3: The ambient temperature range is recommended for Tj = -40 to 125°C
Recommended Operating Conditions (For Single Power Supplies):
Item
Symbol
Power Supply Voltage
Input Voltage
Ambient Temperature
VDD
VI
Ta
Normal Input for Rising Edge Input
Normal Input for Falling Edge Input
Schmitt Input for Rising Edge Input
Schmitt Input for Falling Edge Input
tri
tfi
tri
tfi
Min
1.80
VSS
0
-40
-----
Typ
2.00
-25
25
-----
Max
2.20
*1
VDD
*2
70
*3
85
100
100
10
10
Unit
V
V
°C
ns
ns
ms
ms
*1: Possible to use 5.25 or 5.50V of I/O buffer in the open-drain systems and input buffer in the IDC and IDH systems.
*2: The ambient temperature range is recommended for Tj = 0 to 80°C
*3: The ambient temperature range is recommended for Tj = -40 to 125°C
4
EPSON ELECTRONICS AMERICA, INC.
i 150 River Oaks Pkwy i San Jose, CA 95134 i Tel: (408) 922-0200 i Fax: (408) 922-0238
DATA SHEET
ASIC
S1L50000
Recommended Operating Conditions (For Dual Power Supplies):
Item
Symbol
Power Supply Voltage (High Voltage)
HVDD
Power Supply Voltage (Low Voltage)
Input Voltage
Ambient Temperature
LVDD
HVI
LVI
Ta
Normal Input for Rising Edge Input
Normal Input for Falling Edge Input
Schmitt Input for Rising Edge Input
Schmitt Input for Falling Edge Input
tri
tri
tri
tri
Min
4.75
4.50
3.00
VSS
VSS
0
-40
-----
Typ
5.00
5.00
3.30
--25
25
-----
Max
5.25
5.50
3.60
HVDD
*1
LVDD
*2
70
*3
85
50
50
5
5
Unit
V
V
V
°C
ns
ns
ms
ms
*1: Possible to use 5.25 or 5.50V of I/O buffer in the open-drain systems and input buffer in the LIDC and LIDH systems.
*2: The ambient temperature range is recommended for Tj = 0 to 80°C
*3: The ambient temperature range is recommended for Tj = -40 to 125°C
Recommended Operating Conditions (For Dual Power Supplies):
Item
Symbol
Power Supply Voltage (High Voltage)
Power Supply Voltage (Low Voltage)
Input Voltage
Ambient Temperature
Normal Input for Rising Edge Input
Normal Input for Falling Edge Input
Schmitt Input for Rising Edge Input
Schmitt Input for Falling Edge Input
HVDD
LVDD
HVI
LVI
Ta
Htri
Ltri
Htfi
Ltfi
Htri
Ltri
Htfi
Ltfi
Min
3.00
1.80
VSS
VSS
0
-40
---------
Typ
3.30
2.00
--25
25
---------
Max
3.60
2.20
HVDD
LVDD
*1
70
*2
85
50
100
50
100
5
10
5
10
Unit
V
V
V
°C
ns
ns
ms
ms
*1: Possible to use 5.25 or 5.50V of I/O buffer in the open-drain systems and input buffer in the LIDC and LIDH systems or HIDC and
HIDH systems.
*2: The ambient temperature range is recommended for Tj = 0 to 80°C
*3: The ambient temperature range is recommended for Tj = -40 to 125°C
EPSON ELECTRONICS AMERICA, INC.
i150 River Oaks Pkwy iSan Jose, CA 95134 iTel: (408) 922-0200 iFax: (408) 922-0238
5
DATA SHEET
ASIC
S1L50000
Electrical Characteristics of the S1L50000 Series:
(VDD = 5.0V, VSS = 0V, Ta = -40 to 85°C)
Item
ILI
IOZ
VOH
Low Level Output Voltage
VOL
High Level Input Voltage
Low Level Input Voltage
High Level Input Voltage
Low Level Input Voltage
Hysteresis Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Input Voltage
Low Level Input Voltage
Hysteresis Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
VIH1
VIL1
VT1+
VT1VH1
VIH2
VIL2
VT2+
VT2VH2
VIH3
VIL3
IOH3
Low Level Output Current
Pull-up Resistance*
Pull-down Resistance*
*
6
Symbol
Input Leakage Current
Off State Leakage Current
High Level Output Voltage
IOL3
RPU
RPD
High Level Maintenance Current
IBHH
Low Level Maintenance Current
IBHL
High Level Reversal Current
IBHHO
Low Level Reversal Current
IBHLO
Input Terminal Capacitance
Output Terminal Capacitance
Input/Output Terminal
Capacitance
CI
CO
CIO
Conditions
Typ
Max
-1
-1
HVDD
-0.4
----
1
1
--
µA
µA
V
--
--
0.4
V
3.5
-2.0
0.8
0.3
2.0
-1.2
0.6
0.1
2.0
--
-------------
-1.0
4.0
3.1
--0.8
2.4
1.8
--0.8
V
V
V
V
V
V
V
V
V
V
V
V
-44
--
---
--142
mA
mA
95
-30
--60
mA
mA
Type 2
60
120
Type 1
30
60
Type 2
60
120
--
--
-206
(120)
144
(240)
288
(120)
144
(240)
288
-80
--
--
33
µA
-550
--
--
µA
330
--
--
µA
----
----
10
10
10
pF
pF
pF
--IOH = -0.1mA (Type S), -1mA (Type M),
-3mA (Type 1), -8mA (Type 2), -12mA
(Type 3, Type 4)
VDD = Min
IOL = 0.1mA (Type S), 1mA (Type M),
3mA (Type 1), 8mA (Type 2), 12mA
(Type 3), 24mA (Type 4)
VDD = Min
CMOS Level, HVDD = Max
CMOS Level, HVDD = Min
CMOS Schmitt
CMOS Schmitt
CMOS Schmitt
TTL Level, HVDD = Max
TTL Level, HVDD = Min
TTL Schmitt
TTL Schmitt
TTL Schmitt
PCI Level, HVDD = Max
PCI Level, HVDD = Min
PCI Response,
VOH = 1.4V, HVDD = Min
VOH = 3.1V, HVDD = Max
PCI Response
VOH = 2.20V, HVDD = Min
VOL = 0.71V, HVDD = Max
VI = 0V
Type 1
VI = VDD
Bus Hold Response, VIN = 2.0V
(TTL)
HVDD = Min
Bus Hold Response, VIN = 0.8V
(TTL)
HVDD = Min
Bus Hold Response, VIN = 0.8V
(TTL)
HVDD = Max
Bus Hold Response, VIN = 2.0V
(TTL)
HVDD = Max
f = 1Mhz, VDD = 0V
f = 1Mhz, VDD = 0V
f = 1Mhz, VDD = 0V
Min
Unit
KΩ
KΩ
µA
The values in parentheses are for the case of Ta = 0 to 70°C.
EPSON ELECTRONICS AMERICA, INC.
i 150 River Oaks Pkwy i San Jose, CA 95134 i Tel: (408) 922-0200 i Fax: (408) 922-0238
DATA SHEET
ASIC
S1L50000
Electrical Characteristics of the S1L50000 Series:
(VDD = 3.3V ± 0.3V, VSS = 0V, Ta = -40 to 85°C)
Item
Symbol
*
Quiescent Current
Input Leakage Current
Off State Leakage Current
High Level Output Voltage
IDDS
ILI
IOZ
VOH
Low Level Output Voltage
VOL
High Level Input Voltage
Low Level Input Voltage
High Level Input Voltage
Low Level Input Voltage
Hysteresis Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
VIH1
VIL1
VT1+
VT1VH1
VIH3
VIL3
IOH3
Low Level Output Current
Pull-up Resistance**
Pull-down Resistance**
IOL3
RPU
RPD
High Level Maintenance
Current
Low Level Maintenance
Current
High Level Reversal Current
IBHH
IBHHO
Low Level Reversal Current
IBHLO
Input Terminal Capacitance
Output Terminal Capacitance
Input/Output Terminal
Capacitance
CI
CO
CIO
IBHL
Conditions
Min
Max
Unit
Quiescent Conditions
--IOH = -0.1mA (Type S), -1mA (Type
M), -2mA (Type 1), -6mA (Type 2),
-12mA (Type 3, Type 4)
VDD = Min
IOL = 0.1mA (Type S), 1mA (Type
M), 2mA (Type 1), 6mA (Type 2),
12mA (Type 3), 24mA (Type 4)
VDD = Min
LVTTL Level, VDD = Max
LVTTL Level, VDD = Min
LVTTL Schmitt
LVTTL Schmitt
LVTTL Schmitt
PCI Level, VDD = Max
PCI Level, VDD = Min
PCI Response,
VOH = 0.90V, VDD = Min
VOH = 2.52V, VDD = Max
PCI Response
VOH = 1.80V, VDD = Min
VOL = 2.52V, VDD = Max
VI = 0V
Type 1
--1
-1
VDD
-0.4
-----
170
1
1
--
µA
µA
µA
V
--
--
0.4
V
2.0
-1.1
0.6
0.1
1.71
--
--------
-0.8
2.4
1.8
--0.98
V
V
V
V
V
V
V
-36
--
---
--115
mA
mA
48
-20
--50
mA
mA
Type 2
40
100
Type 1
20
50
Type 2
40
100
--
--
-137
(100)
120
(200)
240
(100)
120
(200)
240
-20
µA
--
--
17
µA
-350
--
--
µA
210
--
--
µA
----
----
10
10
10
pF
pF
pF
VI = VDD
Bus Hold Response,
VIN = 2.0V, VDD = Min
Bus Hold Response,
VIN = 0.8V, VDD = Min
Bus Hold Response,
VIN = 0.8V, VDD = Max
Bus Hold Response,
VIN = 2.0V, VDD = Max
f = 1Mhz, VDD = 0V
f = 1Mhz, VDD = 0V
f = 1Mhz, VDD = 0V
Typ
KΩ
KΩ
* The quiescent current is a typical value (Tj=85°C) for each master.
** The values in parentheses are for the case of Ta = 0 to 70°C.
EPSON ELECTRONICS AMERICA, INC.
i150 River Oaks Pkwy iSan Jose, CA 95134 iTel: (408) 922-0200 iFax: (408) 922-0238
7
DATA SHEET
ASIC
S1L50000
Electrical Characteristics of the S1L50000 Series:
(VDD = 2.0V ± 0.2V, VSS = 0V, Ta = -40 to 85°C)
Item
Symbol
*
*
8
Quiescent Current
Input Leakage Current
Off State Leakage Current
High Level Output Voltage
IDDS
ILI
IOZ
VOH
Low Level Output Voltage
VOL
High Level Input Voltage
Low Level Input Voltage
High Level Input Voltage
Low Level Input Voltage
Hysteresis Voltage
Pull-up Resistance
VIH1
VIL1
VT1+
VT1VH1
RPU
Pull-down Resistance
RPD
High Level Maintenance
Current
Low Level Maintenance
Current
High Level Reversal Current
IBHH
IBHHO
Low Level Reversal Current
IBHLO
Input Terminal Capacitance
Output Terminal Capacitance
Input/Output Terminal
Capacitance
CI
CO
CIO
IBHL
Conditions
Quiescent Conditions
--IOH = -0.05mA (Type S), -0.3mA
(Type M), -0.6mA (Type 1), -2mA
(Type 2), -4mA (Type 3, Type 4)
VDD = Min
IOL = 0.05mA (Type S), 0.3mA
(Type M), 0.6mA (Type 1), 2mA
(Type 2), 4mA (Type 3), 8mA
(Type 4)
VDD = Min
CMOS Level, VDD = Max
CMOS Level, VDD = Min
CMOS Schmitt
CMOS Schmitt
CMOS Schmitt
VI = 0V
Type 1
Type 2
VI = VDD
Type 1
Type 2
Bus Hold Response,
VIN = 1.6V, VDD = Min
Bus Hold Response,
VIN = 0.3V, VDD = Min
Bus Hold Response,
VIN = 0.3V, VDD = Max
Bus Hold Response,
VIN = 1.6V, VDD = Max
f = 1Mhz, VDD = 0V
f = 1Mhz, VDD = 0V
f = 1Mhz, VDD = 0V
Max
Unit
--1
-1
VDD
-0.2
Min
-----
Typ
150
1
1
--
µA
µA
µA
V
--
--
0.2
V
1.6
-0.4
0.3
0
30
60
30
60
--
-----120
240
120
240
--
-0.3
1.6
1.4
-300
600
300
600
-2
V
V
V
V
V
--
--
2
µA
-100
--
--
µA
100
--
--
µA
----
----
10
10
10
pF
pF
pF
KΩ
KΩ
µA
The quiescent current is a typical value (Tj=85°C) for each master.
EPSON ELECTRONICS AMERICA, INC.
i 150 River Oaks Pkwy i San Jose, CA 95134 i Tel: (408) 922-0200 i Fax: (408) 922-0238
DATA SHEET
ASIC
S1L50000
GATE ARRAY DEVELOPMENT FLOW
CUSTOMER
EEA
Product Plan
Functional Spec.
G/A Development
Request
Schematic Pin
Assignment
• Test pattern (timing chart)
• Timing wave form
• Marking diagram
• P/O
Circuit Design
Test Pattern Design
1
Logical Check
(Simulation)
Logical Check
(Simulation)
NG
Verification *
OK
Timing Check
(Simulation)
2
Delay Analyzing
Refer to Note
NG
EWS
OK
Verification
G/A Development
Request
Simulation
File
• Schematic
• Pin assignment
• Timing wave form
• Marking diagram
• P/O
NG
Verification *
OK
Place & Route
Delay Analyzing
Simulation List
NG
Verification
Customer Spec.
(Sign Off)
OK
Post Simulation
Make Masks
TS (Test Sample)
Fabrication
NG
Check
ES (Engr. Sample)
Fabrication
OK
NG
Check
OK
ET(TS) Approve
the Prototype
Approve Delivery
Spec.
ES(TS) Proto.
Approval
MP Setup
Delivery Spec.
Delivery Spec.
Publication
Delivery Spec.
Approval
MP
* Jobs are done by customer and EEA engineer. Steps in shadowed boxes are based on customer’s requirement.
NOTE:
When the customer performs all tasks to the point of logical simulations and delay simulations on engineering workstations, etc.,
the route taken is (2, Joint Design). When EEA performs the logical simulations, the route taken is (1, Turnkey Design).
EPSON ELECTRONICS AMERICA, INC.
i150 River Oaks Pkwy iSan Jose, CA 95134 iTel: (408) 922-0200 iFax: (408) 922-0238
9
DATA SHEET
ASIC
S1L50000
ΠEEA CUSTOMER ENGINEERING
To help customers implement their design of EEA ASIC’s, we offer training at our design centers
and at customer sites when required.
When a design is started, an EEA engineer is assigned to the project and will remain with the
project through its completion. EEA engineers will work with the customer on design, software and
other technical issues. When the design files are transferred to EEA, the assigned engineer will
verify the design’s integrity and prepare it for place and route. The EEA Customer Engineering
Group provides all technical customer-support services including:
•
•
•
•
•
•
•
Pre-Sale Technical Support
Customer Training
Design Assistance
Custom Cell Development
Place and Route
Scan Insertion and ATPG
Netlist Conversion and Synthesis
•
•
•
•
•
•
•
Software Documentation
Simulation Support
Turnkey Design
Design Verification
Static Timing Analysis
JTAG Insertion
Test Vector Conversion
ΠEDA/CAE SUPPORT
•
Schematic Capture
ΠViewlogic (Synopsys): Viewdraw
ΠEEA: Auklet (ECS)
•
Synthesis
•
•
10
Œ
Œ
Synopsys: DesignCompiler
Exemplar Logic: Leonardo
Simulation
DFT
Œ
Œ
Œ
Œ
Œ
Cadence: Verilog-XL
Synopsys: VSS (VHDL)
Avant!: Polaris (Purespeed)
Viewlogic (Synopsys): Viewsim
Modeltech: V-System (VHDL)
Œ
Œ
Synopsys: TestCompiler+
Viewlogic (Synopsys): TestGen (Sunrise)
•
Place & Route
ΠCadence: GateEnsemble
ΠAvant!: Aquarius-GA (Apollo)
•
Delay Calculation (Post-Route)
ΠEEA: Peacock (EXDT)
EPSON ELECTRONICS AMERICA, INC.
i 150 River Oaks Pkwy i San Jose, CA 95134 i Tel: (408) 922-0200 i Fax: (408) 922-0238
DATA SHEET
ASIC
S1L50000
ΠEDA/CAE SUPPORT (continued)
•
Static Timing
ΠSynopsys: PrimeTime (DesignTime)
ΠViewlogic (Synopsys): Motive
•
Layout Verification
ΠCadence: Dracula/LVS
EPSON ELECTRONICS AMERICA, INC.
i150 River Oaks Pkwy iSan Jose, CA 95134 iTel: (408) 922-0200 iFax: (408) 922-0238
11
DATA SHEET
ASIC
S1L50000
NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of EPSON
ELECTRONICS AMERICA, INC.. EEA reserves the right to make changes to this material without notice. EEA does not assume any liability
of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there
is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license
to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in
accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions there of may
contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Control Law of
Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government
agency.
EPSON implies SEIKO EPSON CORPORATION and EPSON affiliated company.
 EPSON ELECTRONICS AMERICA, INC. 1999 All Rights Reserved, Rev. 2.3
Trademark & Company Name
XNF is registered trademark of Synopsys Inc. All other product names mentioned herein are trademarks and/or registered trademarks of their
respective owners.
For additional information about EEA ASIC products and services, or to discuss a solution tailored to your specific requirement s, call your local
EEA sales office or contact the factory.
Northwest Regional
Sales Office & Design Center
Northeast Regional
Southeast Regional
Sales Office & Design Center Sales Office
Central Regional
Sales Office
5LYHU2DNV3DUNZD\
(GJHZDWHU3ODFH6XLWH
6L[)RUNV5RDG6XLWH
($PHULFDQ/DQH6XLWH
6DQ-RVH&$
:DNHILHOG0$
5DOHLJK1&
6FKDXPEXUJ,/
3KRQH
3KRQH
3KRQH
3KRQH
)D[
)D[
)D[
)D[
http://www.eea.epson.com
12
EPSON ELECTRONICS AMERICA, INC.
i 150 River Oaks Pkwy i San Jose, CA 95134 i Tel: (408) 922-0200 i Fax: (408) 922-0238