ESMT M12S16161A SDRAM 512K x 16Bit x 2Banks Synchronous DRAM FEATURES z z z z z z z z z GENERAL DESCRIPTION JEDEC standard 2.5V power supply LVTTL compatible with multiplexed address Dual banks operation MRS cycle with address key programs CAS Latency (2 & 3 ) Burst Length (1, 2, 4, 8 & full page) Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst Read Single-bit Write operation DQM for masking Auto & self refresh 32ms refresh period (2K cycle) The M12S16161A is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated with high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. ORDERING INFORMATION Part NO. MAX Freq. PACKAGE COMMENTS M12S16161A-7TG 143MHz 50 TSOP(II) Pb-free M12S16161A-7BG 143MHz VFBGA Pb-free PIN CONFIGURATION (TOP VIEW) VDD 1 50 VSS DQ0 2 49 DQ15 DQ1 3 48 DQ14 VSSQ 4 47 VSSQ DQ2 5 46 DQ13 DQ3 6 45 DQ12 VDDQ 7 44 VDDQ DQ4 8 43 DQ11 DQ5 9 42 DQ10 VSSQ 10 41 VSSQ DQ6 11 40 DQ9 DQ7 12 39 DQ8 VDDQ 13 38 VDDQ LDQM 14 37 N.C/RFU WE 15 36 UDQM CAS 16 35 CLK RAS 17 34 CKE CS 18 33 N.C BA 19 32 A9 A10/AP 20 31 A8 A0 21 30 A7 A1 22 29 A6 A2 23 28 A5 A3 24 27 A4 VDD 25 26 VSS Elite Semiconductor Memory Technology Inc. 50PIN TSOP(II) (400mil x 825mil) (0.8 mm PIN PITCH) 1 2 6 7 A VSS DQ15 3 4 5 DQ0 VDD B DQ14 VSSQ VDDQ DQ1 C DQ13 VDDQ VSSQ DQ2 D DQ12 DQ11 DQ4 DQ3 E DQ10 VSSQ VDDQ DQ5 F DQ9 VDDQ VSSQ DQ6 G DQ8 NC NC DQ7 H NC NC NC NC J NC UDQM LDQM WE K NC CLK RAS CAS L CKE NC NC CS M A11 A9 NC NC N A8 A7 A0 A10 P A6 A5 A2 A1 R VSS A4 A3 VDD 60 Ball VFBGA (6.4x10.1mm) (0.65mm ball pitch) Publication Date : May. 2007 Revision : 1.1 1/29 ESMT M12S16161A FUNCTIONAL BLOCK DIAGRAM 512K x 16 LWE LDQM Output Buffer Col. Buffer LCKE 512K x 16 Sense AMP Row Decoder LRAS LCBR ADD Row Buffer Refresh Counter Address Register CLK Data Input Register I/O Control Bank Select DQi Column Decoder Latency & Burst Length Programming Register LRAS LCBR LWE LCAS LWCBR LDQM Timing Register CLK CKE CS RAS CAS WE L(U)DQM PIN FUNCTION DESCRIPTION CLK Pin Name System Clock CS Chip Select CKE Clock Enable A0 ~ A10/AP Address BA Bank Select Address RAS Row Address Strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS Column Address Strobe WE Write Enable CAS low. Enables column access. Enables write operation and row precharge. L(U)DQM Data Input / Output Mask Elite Semiconductor Memory Technology Inc. Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and L(U)DQM. Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row / column addresses are multiplexed on the same pins. Row address : RA0 ~ RA10, column address : CA0 ~ CA7 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches data in starting from CAS , WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when L(U)DQM active. Publication Date : May. 2007 Revision : 1.1 2/29 ESMT M12S16161A DQ0 ~ 15 VDD/VSS Data Input / Output Power Supply/Ground VDDQ/VSSQ Data Output Power/Ground N.C/RFU No Connection/ Reserved for Future Use Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device. ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Voltage on VDD supply relative to VSS Storage temperature Power dissipation Short circuit current Symbol Value Unit VIN,VOUT VDD,VDDQ TSTG PD IOS -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ + 150 0.7 50 V V °C W MA Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA=0 to 70 °C ) Parameter Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Output leakage current Symbol Min Typ Max Unit Note VDD,VDDQ VIH VIL VOH VOL IIL IOL 2.375 0.8xVDD -0.3 VDD -0.2 -10 -10 2.5 0 - 2.625 VDD+0.3 0.3 0.2 10 10 V V V V V uA uA 1 2 IOH = -0.1mA IOL = -0.1mA 3 4 Note : 1.VIH (max) = 4.6V AC for pulse width ≤ 10ns acceptable. 2.VIL (min) = -1.5V AC for pulse width ≤ 10ns acceptable. 3.Any input 0V ≤ VIN ≤ VDD+ 0.3V, all other pins are not under test = 0V. 4.Dout is disabled, 0V ≤ VOUT ≤ VDD. CAPACITANCE (VDD = 2.5V, TA = 25 °C , f = 1MHz) Pin Symbol Min Max Unit CLOCK CCLK 2.5 4.0 pF CIN 2.5 5.0 pF CADD COUT 2.5 4.0 5.0 6.5 pF pF RAS , CAS , WE , CS , CKE, LDQM, UDQM ADDRESS DQ0 ~DQ15 Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 1.1 3/29 ESMT M12S16161A DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70 °C Parameter Operating Current (One Bank Active) Precharge Standby Current in power-down mode Precharge Standby Current in non power-down mode Symbol Test Condition CAS Latency ICC1 Burst Length = 1 tRC ≥ tRC (min), tCC ≥ tCC (min), IOL= 0mA ICC2P ICC2PS ICC2N Version -7 Unit Note 100 mA CKE ≤ VIL(max), tCC =15ns 2 mA CKE ≤ VIL(max), CLK ≤ VIL(max), tCC = ∞ 2 CKE ≥ VIH(min), CS ≥ VIH(min), tCC =15ns 25 mA 1 Input signals are changed one time during 30ns ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 10 mA ICC3P CKE ≤ VIL(max), tCC =15ns 10 mA ICC3PS CKE ≤ VIL(max), CLK ≤ VIL(max), tCC = ∞ 10 ICC3N CKE ≥ VIH(min), CS ≥ VIH(min), tCC=15ns Input signals are changed one time during 30ns 25 mA ICC3NS CKE ≥ VIH (min), CLK ≤ VIL(max), tCC= ∞ Input signals are stable 10 mA Operating Current (Burst Mode) IOL= 0Ma, Page Burst All Band Activated, tCCD = tCCD (min) 3 120 mA 1 ICC4 2 120 Refresh Current ICC5 tRC ≥ tRC(min) 120 mA 2 Self Refresh Current ICC6 CKE ≤ 0.2V 1 mA Active Standby Current in power-down mode Active Standby Current in non power-down mode (One Bank Active) Note: 1.Measured with outputs open. Addresses are changed only one time during tCC(min). 2.Refresh period is 32ms. Addresses are changed only one time during tCC(min). Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 1.1 4/29 ESMT M12S16161A AC OPERATING TEST CONDITIONS (VDD=2.375~2.625V,TA= 0 to 70 °C ) Parameter Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value 2.4 / 0.4 1.4 tr / tf = 1 / 1 1.4 See Fig.2 Unit V V ns V Ω Ω Ω Ω OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Symbol Version -7 Unit Note Row active to row active delay tRRD(min) 14 ns 1 RAS to CAS delay tRCD(min) 20 ns 1 Row precharge time tRP(min) 20 ns 1 tRAS(min) 42 ns 1 tRAS(max) 100 us Row cycle time tRC(min) 63 ns 1 Last data in to new col. Address delay tCDL(min) 1 CLK 2 Last data in to row precharge tRDL(min) 2 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Col. Address to col. Address delay tCCD(min) 1 CLK 3 ea 4 Row active time Number of valid output data CAS latency=3 2 CAS latency=2 1 Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks. Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 1.1 5/29 ESMT M12S16161A AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter CLK cycle time CLK to valid output delay CAS Latency =3 CAS Latency =2 CAS Latency =3 CAS Latency =2 Symbol tCC -7 Min 7 8.6 tSAC Max Unit Note 1000 ns 1 ns 1 - 6 - 6 Output data hold time tOH 2 ns 2 CLK high pulse width tCH 2.5 ns 3 CLK low pulse width tCL 2.5 ns 3 Input setup time tSS 2 ns 3 Input hold time tSH 1 ns 3 CLK to output in Low-Z tSLZ 1 ns 2 CLK to output in Hi-Z CAS Latency =3 tSHZ CAS latency =2 - 6 - 6 ns *All AC parameters are measured from half to half. Note: 1.Parameters depend on programmed CAS latency. 2.If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter. 3.Assumed input rise and fall time (tr & tf)=1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to the parameter. Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 1.1 6/29 ESMT M12S16161A FREQUENCY vs. AC PARAMENTER RELATIONSHIP TABLE M12S16161A-7T(G) Frequency 143MHz(7.0ns) 125MHz(8.0ns) 111MHz(9.0ns) 100MHz(10.0ns) 83MHz(12.0ns) (Unit: number of clock) CAS Latency 3 3 2 2 2 tRC 63ns 9 8 7 7 6 tRAS 42ns 6 6 5 5 4 tRP 20ns 3 3 3 2 2 tRRD 14ns 2 2 2 2 2 tRCD 20ns 3 3 3 2 2 tCCD 7ns 1 1 1 1 1 tCDL 7ns 1 1 1 1 1 tRDL 14ns 2 2 2 2 2 Note : 1. tRDL ≥ 16.7ns is recommended for M12S16161A. Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 1.1 7/29 ESMT M12S16161A Mode Register 11 0 11 x 10 0 10 x 9 0 9 1 8 0 8 0 7 1 7 0 11 10 9 11 x 11 0 10 x 10 0 9 x 9 0 8 1 8 1 8 0 7 0 7 1 7 0 6 5 4 3 2 1 0 6 5 LTMODE 4 3 WT 2 1 0 6 4 3 2 1 0 5 4 v v 5 4 LTMODE 3 v 3 WT 2 v 2 1 v 1 BL 0 v 0 JEDEC Standard Test Set (refresh counter test) 5 BL Burst Read and Single Write (for Write Through Cache) Use in future 6 v 6 Vender Specific v =Valid x =Don’t care Mode Register Set Burst length Wrap type Bit2-0 000 001 010 011 100 101 110 111 0 1 Bits6-4 Latency mode 000 001 010 011 100 101 110 111 Mode Register Write Timing WT=0 1 2 4 8 R R R Full page WT=1 1 2 4 8 R R R R Sequential Interleave CAS Latency R R 2 3 R R R R Remark R : Reserved CLOCK CKE CS RAS CAS WE A0-A11 Mode Register W rite Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 1.1 8/29 ESMT M12S16161A Burst Length and Sequence (Burst of Two) Starting Address (column address A0 binary) 0 1 Sequential Addressing Sequence (decimal) 0,1 1,0 Interleave Addressing Sequence (decimal) 0,1 1,0 Sequential Addressing Sequence (decimal) 0,1,2,3 1,2,3,0 2,3,0,1 3,0,1,2 Interleave Addressing Sequence (decimal) 0,1,2,3 1,0,3,2 2,3,0,1 3,2,1,0 (Burst of Four) Starting Address (column address A1-A0, binary) 00 01 10 11 (Burst of Eight) Starting Address (column address A2-A0, binary) 000 001 010 0 11 100 101 11 0 111 Sequential Addressing Sequence (decimal) 0,1,2,3,4,5,6,7 1,2,3,4,5,6,7,0 2,3,4,5,6,7,0,1 3,4,5,6,7,0,1,2 4,5,6,7,0,1,2,3 5,6,7,0,1,2,3,4 6,7,0,1,2,3,4,5 7,0,1,2,3,4,5,6 Interleave Addressing Sequence (decimal) 0,1,2,3,4,5,6,7 1,0,3,2,5,4,7,6 2,3,0,1,6,7,4,5 3,2,1,0,7,6,5,4 4,5,6,7,0,1,2,3 5,4,7,6,1,0,3,2 6,7,4,5,2,3,0,1 7,6,5,4,3,2,1,0 Full page burst is an extension of the above tables of Sequential Addressing, with the length being 256 for 1Mx16 divice. POWER UP SEQUENCE 1.Apply power and start clock, attempt to maintain CKE= “H”, L(U)DQM = “H” and the other pin are NOP condition at the inputs. 2.Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 3.Issue precharge commands for all banks of the devices. 4.Issue 2 or more auto-refresh commands. 5.Issue mode register set command to initialize the mode register. Cf.)Sequence of 4 & 5 is regardless of the order. Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 1.1 9/29 ESMT M12S16161A SIMPLIFIED TRUTH TABLE COMMAND Mode Register Set Auto Refresh Entry Self Refresh Exit Register Refresh Bank Active & Row Addr. Auto Precharge Disable Read & Column Address Write & Column Address Auto Precharge Enable Auto Precharge Disable CKEn-1 CKEn CS H X L H H L L L H H X L H L H X L DQM BA A10/AP A9~A0 Note X OP CODE 1,2 3 X X 3 RAS L CAS L WE L L L H H X L H X H H X H X V H L H X V X X L H L L X H X L H H L X V L H V X L H Auto Precharge Enable Burst Stop Bank Selection Both Banks Precharge Clock Suspend or Active Power Down Precharge Power Down Mode H X Entry H L Exit L H Entry H L Exit L H DQM No Operation Command Row Address Column L H H H X L L H L H L X H L H L X V X X H X V X X H X V X X H X V X V X X H X V X H X H H L X X 4 Address (A0~A7) 4,5 Column 4 Address 4,5 (A0~A7) H H 3 3 X X X 6 4 4 X X X X X V X X X 7 (V= Valid, X= Don’t Care, H= Logic High , L = Logic Low) Note: 1. OP Code: Operation Code A0~ A10/AP, BA: Program keys.(@MRS) 2. MRS can be issued only at both banks precharge state. A new command can be issued after 2 clock cycle of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by “Auto”. Auto / self refresh can be issued only at both banks idle state. 4. BA: Bank select address. If “Low”: at read, write, row active and precharge, bank A is selected. If “High”: at read, write, row active and precharge, bank B is selected. If A10/AP is “High” at row precharge, BA ignored and both banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read /write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 1.1 10/29 ESMT M12S16161A Single Bit Read-Write-Read Cycle (Same Page) @CAS Latency=3, Burst Length=1 tCH 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK tCL tCC HIGH CKE tRAS tRC tSH *Note1 CS tRP tRCD tSS tSH RAS tCCD tSS tSH CAS tSS tSS tSH ADDR Ra Ca Cb *Note2 Rb Cc tSH tSS *Note2,3 BA BS BS A10 /AP Ra *Note 3 *Note2,3 *Note2,3 BS BS *Note 3 *Note 3 *Note4 *Note2 BS BS *Note4 Rb tRAC tSAC tSH DQ tSLZ Qc Db Qa tSS tOH tSH WE tSS tSS tSH DQM Row Active Read W rite Read Row Active Precharge :D on' t Care Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 1.1 11/29 ESMT M12S16161A *Note: 1. All inputs expect CKE & DQM can be don’t care when CS is high at the CLK high going edge. 2. Bank active & read/write are controlled by BA. BA Active & Read/Write 0 Bank A 1 Bank B 3.Enable and disable auto precharge function are controlled by A10/AP in read/write command. A10/AP 0 1 BA Operation 0 Disable auto precharge, leave bank A active at end of burst. 1 Disable auto precharge, leave bank B active at end of burst. 0 Enable auto precharge, precharge bank A at end of burst. 1 Enable auto precharge, precharge bank B at end of burst. 4.A10/AP and BA control bank precharge when precharge command is asserted. A10/AP BA precharge 0 0 Bank A 0 1 Bank B 1 X Both Banks Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 1.1 12/29 ESMT M12S16161A Power Up Sequence 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK CKE High l evel is n ec es sar y CS tRC tRC tRP RAS CAS ADDR RAa Key BA Key A10 /AP Key RAa High-Z DQ WE DQM High level is necessary Precharge All Banks Auto Ref res h Auto Ref resh Mode R egis ter Set ( A- Ban k ) Row Active : Don't care Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 1.1 13/29 ESMT M12S16161A Read & Write Cycle at Same Bank @Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE t RC *Note1 CS tRCD RAS *Note2 CAS ADDR Ra Rb Ca0 Cb0 BA A10/AP Ra Rb tO H CL=2 Qa0 t R AC QC Qa2 Qa1 CL=3 Db1 Db2 Db3 *Note4 tRDL tOH Qa1 Qa0 t R AC *Note3 Db0 tS H Z t S AC *Note3 Qa3 Qa2 Qa3 t S AC Db0 tS H Z *Note4 Db1 Db2 Db3 tRDL WE DQ M Row Active (A- Bank) Read (A- Bank) Precharge Row Active (A- Bank) (A- Bank) W r ite (A-Bank) Precharge (A- Bank) : Don't care *Note: 1.Minimum row cycle times is required to complete internal DRAM operation. 2.Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clock. 3.Access time from Row active command. tcc*(tRCD +CAS latency-1)+tSAC 4.Ouput will be Hi-Z after the end of burst.(1,2,4,8 bit burst) Burst can’t end in Full Page Mode. Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 1.1 14/29 ESMT M12S16161A Page Read & Write Cycle at Same Bank @ Burst Length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CS tRCD RAS *Note2 CAS ADDR Ra Ca0 Cb0 Cc0 Cd0 BA A10/AP Ra tRDL CL=2 Qa0 Qa1 Qb0 Qb1 Qb2 Dc0 Qa0 Qa1 Qb0 Qb1 Dc0 Dc1 Dd0 Dd1 DQ CL=3 Dc1 Dd0 Dd2 tCDL WE *Note3 *Note1 DQM Row Active (A-Bank) Read (A-Bank) Read (A-Bank) Write (A-Bank) Write (A-Bank) Precharge (A-Bank) : Don't care *Note :1.To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus contention. 2.Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written. 3.DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 1.1 15/29 ESMT M12S16161A Page Read Cycle at Different Bank @ Burst Length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK CKE HIGH *Note1 CS RAS *Note2 CAS ADDR RAa CAa CAc CBb RBb CBd CAe BA A10/AP RAa RBb CL=2 QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 DQ CL=3 QAe1 WE DQM Row Active (A-Bank) Read (A-Bank) Read (B-Bank) Read (A-Bank) Read (B-Bank) Read (A-Bank) Precharge (A-Bank) Row Active (B-Bank) : Don't care *Note: 1. CS can be don’t cared when RAS , CAS and WE are high at the clock high going dege. 2.To interrupt a burst read by row precharge, both the read and the precharge banks must be the same. Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 1.1 16/29 ESMT M12S16161A Page Write Cycle at Different Bank @Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CS RAS CAS *Note2 ADDR RAa CAa CBb RBb CAc CBd BA A10/AP RAa DQ RBb DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 tCDL DBd1 tRDL WE *Note1 DQM Row Active (A-Bank) Row Active (B-Bank) Write (A-Bank) Write (B-Bank) Precharge (Both Banks) Write (A-Bank) Write (B-Bank) : Don't care *Note: 1.To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data. 2.To interrupt burst write by row precharge, both the write and the precharge banks must be the same. Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 1.1 17/29 ESMT M12S16161A Read & Write Cycle at Different Bank @ Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CS RAS CAS *Note2 ADDR RAa CAa CBb RBb CAc CBd BA A10/AP RAa DQ RBb DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 tCDL DBd1 tRDL WE *Note1 DQM Row Active (A-Bank) Row Active (B-Bank) Write (A-Bank) Write (B-Bank) Precharge (Both Banks) Write (A-Bank) Write (B-Bank) : Don't care *Note: 1.tCDL should be met to complete write. Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 1.1 18/29 ESMT M12S16161A Read & Write Cycle with auto Precharge @ Burst Length =4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CS RAS CAS ADDR Ra Rb Ra Rb Cb Ca BA A10 /A P CL= 2 Qa0 Q a1 Qa2 Q a3 Q a1 Qa2 Db0 Db1 Db2 Db3 Db0 Db1 Db2 Db3 DQ CL=3 Q a0 Qa3 WE DQM Row Active ( A - Bank ) Read with Auto Precharge ( A - Bank ) Auto Precharge Start Point ( A - Bank) W rite with Auto Pr echarge ( B- Bank ) Auto Pr echarge Star t Poin t ( B- Bank ) Row Active ( B - Bank ) :D on' t Ca re *Note: 1.tCDL Should be controlled to meet minimum tRAS before internal precharge start (In the case of Burst Length=1 & 2 and BRSW mode) Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 1.1 19/29 ESMT M12S16161A Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK CKE CS RAS CAS ADDR Ra Ca Cb Cc BA A10 /AP Ra Q a0 DQ Qa1 Q a2 Qb0 Q a3 tSHZ Q b1 Dc2 Dc 0 tSHZ WE *Note1 DQM Row Active Read Clock Suspension Read W rite DQM Read DQM W rite W rite DQM Cloc k Sus pension :Don't Car e *Note:1.DQM is needed to prevent bus contention. Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 1.1 20/29 ESMT M12S16161A Read Interrupted by Precharge Command & Read Burst Stop Cycle @Burst Length =Full page 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CS RAS CAS ADDR RAa CAa CAb BA RAa A10 /AP *Note2 1 1 QAa0 QAa1 QAa2 QAa 3 QAa4 CL=2 QAb0 QAb1 QAb 2 QAb3 QAb4 QAb5 DQ 2 2 CL=3 QAa0 QAa1 QAa 2 QAa3 QAa4 WE QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 *Note1 DQM Row Active ( A- B an k ) Read (A- Ban k) Burst Stop Read (A- Ban k) Precharge ( A- B an k ) :Don't Care *Note: 1.Burst can’t end in full page mode, so auto precharge can’t issue. 2.About the valid DQs after burst stop, it is same as the case of RAS interrupt. Both cases are illustrated above timing diagram. See the label 1,2 on them. But at burst write, burst stop and RAS interrupt should be compared carefully. Refer the timing diagram of “Full page write burst stop cycle”. 3.Burst stop is valid at every burst length. Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 1.1 21/29 ESMT M12S16161A Write Interrupted by Precharge Command & Write Burst stop Cycle @ Burst Length =Full page 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CS RAS CAS ADDR RAa CAa CAb BA A10 /AP RAa tBDL tRDL *Note2 DQ DAa0 DAa1 DAa2 DAa3 DAa4 DAb0 DAb1 DAb2 DAb3 DAb4 DAb5 WE DQM Row Active ( A- B an k ) W rite (A- Ban k ) Burst Stop W rite (A- Ban k ) Precharge ( A- B an k ) :Don't Care *Note: 1. Burst can’t end in full page mode, so auto precharge can’t issue. 2.Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of tRDL. DQM at write interrupted by precharge command is needed to prevent invalid write. Input data after Row precharge cycle will be masked internally. 3.Burst stop is valid at every burst length. Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 1.1 22/29 ESMT M12S16161A Burst Read Single bit Write Cycle @Burst Length=2 CLOCK *Note1 HIGH CKE CS RAS *Note2 CAS RAa ADDR CAa RBb CAb CBc RAc CAd BA A10 /AP RAa RAc RBb CL=2 DAa0 CL= 3 DAa0 QAb0 QAb1 QAd0 QAd1 DBc0 DQ QAb0 QAb1 QAd0 QAd1 DBc0 WE DQM Row Active ( A- B an k ) Row Active (B-Bank) W rite (A- Ban k) Read with Auto Precharge (A-Bank) Read ( A- B an k ) Row Act ive ( A- B an k ) Precharge ( A- B an k ) W rite with Auto Pr echarge ( B- Bank ) :Don't Care *Note:1.BRSW modes is enabled by setting A9 “High” at MRS(Mode Register Set). At the BRSW Mode, the burst length at write is fixed to “1” regardless of programmed burst length. 2.When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the next cycle of burst-end, so in the case of BRSW write command, the precharge command will be issued after two clock cycles. Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 1.1 23/29 ESMT M12S16161A Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Q a0 Qa1 16 17 18 19 CLOCK *Note2 tSS CKE tS S *Note1 tS S *Not e3 CS RAS CAS Ra ADDR Ca BA A10 /A P Ra tSHZ DQ Qa2 WE DQM Pr ech ar g e Pow er - Dow n Entry Row Active Precharge Power-Down Exit Active Power-down Entry Read Precharge Active Power-down Exit : Don't care *Note :1.Both banks should be in idle state prior to entering precharge power down mode. 2.CKE should be set high at least 1CLK+tss prior to Row active command. 3.Can not violate minimum refresh specification. (32ms) Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 1.1 24/29 ESMT M12S16161A Self Refresh Entry & Exit Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK *Note2 *Note4 tRCmin *Note6 *Note1 *Note3 CKE tSS *Note5 CS RAS *Note7 CAS ADDR BA A10 /AP Hi-Z DQ Hi-Z WE DQM Sel f R ef r esh En tr y S e l f R ef r e s h E xi t Auto Refresh : Don't care *Note: TO ENTER SELF REFRESH MODE 1. CS , RAS & CAS with CKE should be low at the same clock cycle. 2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE. 3. The device remains in self refresh mode as long as CKE stays “Low”. cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh. TO EXIT SELF REFRESH MODE 4. System clock restart and be stable before returning CKE high. 5. CS Starts from high. 6. Minimum tRC is required after CKE going high to complete self refresh exit. 7. 2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh. Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 1.1 25/29 ESMT M12S16161A Mode Register Set Cycle 0 1 2 3 4 5 Auto Refresh Cycle 6 0 1 2 3 4 5 6 7 8 9 10 CLOCK HIGH HIGH CKE CS *Note2 tRC RAS *Note1 CAS *Note3 ADDR Key DQ Ra Hi-Z Hi-Z WE DQM MRS New C om m an d Auto Ref res h New C om m an d :Don't Care *Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle. MODE REGISTER SET CYCLE *Note: 1. CS , RAS , CAS & WE activation at the same clock cycle with address key will set internal mode register. 2.Minimum 2 clock cycles should be met before new RAS activation. 3.Please refer to Mode Register Set table. Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 1.1 26/29 ESMT M12S16161A PACKAGE DIMENSIONS 50-LEAD TSOP(II) SDRAM(400mil) Symbol A A1 A2 B B1 C C1 D E E1 L L1 e θ Min 0.051 0.95 0.30 0.30 0.12 0.10 20.82 11.56 10.03 0.40 0 Dimension in mm Nom 0.127 1.00 0.35 0.127 20.95 11.76 10.16 0.50 0.80 REF 0.80 BSC - Elite Semiconductor Memory Technology Inc. Max 1.20 0.203 1.05 0.45 0.40 0.21 0.16 21.08 11.96 10.29 0.60 Min 0.002 0.037 0.012 0.012 0.005 0.004 0.820 0.455 0.394 0.016 8 0 Dimension in inch Nom 0.005 0.039 0.014 0.005 0.825 0.463 0.400 0.020 0.031 REF 0.031 BSC - Max 0.047 0.008 0.041 0.018 0.016 0.008 0.006 0.830 0.471 0.405 0.024 8 Publication Date : May. 2007 Revision : 1.1 27/29 ESMT PACKING 60-BALL M12S16161A DIMENSIONS SDRAM ( 6.4x10.1 mm ) Symbol A A1 A2 Φb D E D1 E1 e Dimension in mm Min Norm Max 1.00 0.20 0.25 0.30 0.61 0.66 0.71 0.30 0.35 0.40 6.30 6.40 6.50 10.00 10.10 10.20 3.90 9.10 0.65 Dimension in inch Min Norm Max 0.039 0.008 0.010 0.012 0.024 0.026 0.028 0.012 0.014 0.016 0.248 0.252 0.256 0.394 0.398 0.402 0.154 0.358 0.026 Controlling dimension : Millimeter. Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 1.1 28/29 ESMT M12S16161A Important Notice All rights reserved. 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To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 1.1 29/29