EXAR XRT83VSH314IB

XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
SEPTEMBER 2006
REV. 1.0.1
GENERAL DESCRIPTION
for external timing (8kHz, 1.544Mhz, 2.048Mhz,
nxT1/J1, nxE1).
The XRT83VSH314 is a fully integrated 14-channel
short-haul line interface unit (LIU) that operates from
a 1.8V Inner Core and 3.3V I/O power supplies.
Using internal termination, the LIU provides one bill of
materials to operate in T1, E1, or J1 mode
independently on a per channel basis with minimum
external components.
The LIU features are
programmed through a standard microprocessor
interface. EXAR’s LIU has patented high impedance
circuits that allow the transmitter outputs and receiver
inputs to be high impedance when experiencing a
power failure or when the LIU is powered off. Key
design features within the LIU optimize 1:1 or 1+1
redundancy and non-intrusive monitoring applications
to ensure reliability without using relays.
Additional features include RLOS, a 16-bit LCV
counter for each channel, AIS, QRSS/PRBS
generation/detection, TAOS, DMO, and diagnostic
loopback modes.
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
The on-chip clock synthesizer generates T1/E1/J1
clock rates from a selectable external clock frequency
and has five output clock references that can be used
T1 Digital Cross Connects (DSX-1)
ISDN Primary Rate Interface
CSU/DSU E1/T1/J1 Interface
T1/E1/J1 LAN/WAN Routers
Public Switching Systems and PBX Interfaces
T1/E1/J1 Multiplexer and Channel Banks
Integrated Multi-Service Access Platforms (IMAPs)
Integrated Access Devices (IADs)
Inverse Multiplexing for ATM (IMA)
Wireless Base Stations
FIGURE 1. BLOCK DIAGRAM OF THE XRT83VSH314
1 of 14 Channels
Driver
Monitor
TCLK_n
Tx/Rx Jitter
Attenuator
HDB3/B8ZS
Encoder
TPOS_n
Tx Pulse
Shaper &
Pattern Gen
Timing
Control
DMO
TTIP_n
Line
Driver
TRING_n
TNEG_n
Remote
Loopback
TxON
Digital
Loopback
Analog
Loopback
QRSS
Generation
& Detection
RPOS_n
HDB3/B8ZS
Decoder
RCLK_n
Tx/Rx Jitter
Attenuator
Peak
Detector
& Slicer
Clock & Data
Recovery
RNEG_n
RTIP_n
RRING_n
RLOS
RCLKOUT
AIS & LOS
Detector
RxON
RxTSEL
8kHzOUT
ICT
TEST
MCLKE1out
Programmable Master
Clock Synthesizer
Microprocessor
Interface
Test
ATP_TIP
MCLKT1out
MCLKE1Nout
ATP_RING
MCLKin
Reset
[7:0]
DATA
CS[5:1]
[10:0]
ADDR
uPTS0
uPTS1
uPTS2
uPCLK
RD_WE
WR_R/W
CS
ALE_TS
INT
RDY_TA
TDO
TCK
TDI
TMS
MCLKT1Nout
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
FEATURES
• Fully integrated 14-Channel short haul transceivers for T1/J1 (1.544MHz) and E1 (2.048MHz) applications
• T1/E1/J1 short haul and clock rate are per port selectable through software without changing components
• Internal Impedance matching on both receive and transmit for 75Ω (E1), 100Ω (T1), 110Ω (J1), and 120Ω
(E1) applications are per port selectable through software without changing components
• Power down on a per channel basis with independent receive and transmit selection
• Five pre-programmed transmit pulse settings for T1 short haul applications per channel
• User programable Arbitrary Pulse mode
• On-Chip transmit short-circuit protection and limiting protects line drivers from damage on a per channel
basis
• Selectable Crystal-Less digital jitter attenuators (JA) with 32-Bit or 64-Bit FIFO for the receive or transmit
path
• Driver failure monitor output (DMO) alerts of possible system or external component problems
• Transmit outputs and receive inputs may be "High" impedance for protection or redundancy applications on a
per channel basis
• Support for automatic protection switching
• 1:1 and 1+1 protection without relays
• Receive monitor mode handles 0 to 6dB resistive attenuation (flat loss) along with 0 to 6dB cable loss for
both T1 and E1
• Loss of signal (RLOS) according to ITU-T G.775/ETS300233 (E1) and ANSI T1.403 (T1/J1)
• Programmable data stream muting upon RLOS detection
• On-Chip HDB3/B8ZS encoder/decoder with an internal 16-bit LCV counter for each channel
• On-Chip digital clock recovery circuit for high input jitter tolerance
• QRSS/PRBS pattern generator and detection for testing and monitoring
• Error and bipolar violation insertion and detection
• Transmit all ones (TAOS) Generators and Detectors
• Supports local analog, remote, digital, and dual loopback modes
• 1.8V Digital Core
• 3.3V I/O and Analog Core
• 304-Pin BGA package
• -40°C to +85°C Temperature Range
• Supports gapped clocks for mapper/multiplexer applications
PRODUCT ORDERING INFORMATION
PRODUCT NUMBER
PACKAGE TYPE
OPERATING TEMPERATURE RANGE
XRT83VSH314IB
304 Lead PBGA
-40°C to +85°C
2
3
NC
NC
DVDD_8_9_10
DGND_8_9_10
RGND_12
RCLK_12
NC
UPTS1
A[0]
RTIP_12
RVDD_12
DGND_DRV
UPTS2
A[4]
A[3]
UPTS0
RNEG_12
TTIP_12
TxON
A[5]
A[2]
DVD_PRE
RPOS_12
TGND_12
RRING_12
TVDD_12
TRING_12
RGND_11
TRING_11
TGND_11
RPOS_11
RPOS_10
TGND_10
DGND_PRE
SENSE
TGND_9
RPOS_9
RPOS_8
TGND_8
A[9]
DVD_PRE
CS3
CS5
WR_RW
DVDD_DRV DVDD_11_12 DGND_11_12
TVDD_11
TTIP_11
RNEG_11
RNEG_10
TTIP_10
NC
ATP_RING
TTIP_9
RNEG_9
RNEG_8
TTIP_8
TVDD_8
ATP_TIP
DVDD_DRV
CS1
CS4
20
RRING_11
RVDD_11
TRING_9
RGND_9
RTIP_11
TVDD_9
RRING_9
RCLK_11
RCLK_9
RTIP_9
RVDD_10
RCLK_8
RVDD_9
RCLK_10
RVDD_8
RTIP_8
RTIP_10
TRING_8
RRING_8
TVDD_10
A[8]
RGND_8
RRING_10
RESET
NC
TRING_10
CS
A[10]
21
18
17
16
15
10
TCLK_12 TCLK_13
RCLK_6
RTIP_6
9
TNEG_12 TCLK_11 TNEG_13 VDDPLL_11 RVDD_13 RTIP_13 RRING_13 RGND_13 RGND_0 RRING_0
RTIP_0
RVDD_0
RCLK_0
RXTSEL RPOS_13 TGND_13 DGND_13_0 TGND_0 RPOS_0 GNDPLL_12
Bottom View
NC
7
6
5
4
MCLKT1xN
GNDPLL_11
DGND_PRE
DGND_DRV
TPOS_0
EIGHT_KHZ
TCLK_0
TNEG_0
TNEG_2
TNEG_1
TCLK_6
TNEG_6
TPOS_6
TCLK_2
TPOS_2
TPOS_1
D[3]
TPOS_3
TNEG_3
TCLK_3
TCLK_1
D[0]
D[4]
DVD_PRE
TNEG_5
TNEG_4
TCLK_4
TVDD_4
TTIP_4
RNEG_4
RNEG_5
TTIP_5
TDO
DVD_PRE
INT
TCLK_5
3
TVDD_2
TTIP_2
RNEG_2
RNEG_3
TTIP_3
D[1]
D[2]
D[7]
DMO
RPOS_1
TGND_1
D[5]
D[6]
RDY_TA
RNEG_1
TTIP_1
TRING_1
RRING_4
RTIP_4
RVDD_4
RTIP_5
RRING_5
RGND_5
TCK
TDI
1
CMPOUT
DVD_DRV
UPCLK
RCLK_1
RVDD_1
RGND_1
DVDD_1_2
TRING_2
RVDD_2
RCLK_2
RCLK_3
TVDD_3
TRING_3
NC
RLOS
NC
RTIP_1
RRING_1
RGND_2
RRING_2
RTIP_2
RVDD_3
RTIP_3
RRING_3
RGND_3
PhDIN
RCLKOUT
DVDD_3_4_5 RGND_4
TRING_4
RCLK_4
RCLK_5
RVDD_5
TVDD_5
TRING_5
DGND_DRV
ICT
2
AGND_BIAS DGND_3_4_5
TVDD_1 DGND_DRV
DGND_1_2
TGND_2
RPOS_2
RPOS_3
TGND_3
NC
AVDD_BIAS DVDD_DRV
TGND_4
RPOS_4
RPOS_5
TGND_5
TMS
TEST
TPOS_5
TPOS_4
RVDD_6 MCLKOUT_T1 MCLKIN MCLKOUT_E1 MCLKE1xN
8
DGND_6_7 TTIP_6 RNEG_6 GNDPLL_22 GNDPLL_21
TRING_7 TRING_6 TVDD_6
TCLK_10 DGND_PRE RPOS_7 TGND_7 DVDD_6_7 TGND_6 RPOS_6
TTIP_7
TVDD_7
11
RGND_7 RGND_6 RRING_6
12
TPOS_12 TNEG_11 DVDD_DRV DVDD_UP RNEG_13 TTIP_13 DVDD_13_0 TTIP_0 RNEG_0
A[7]
RD_WE TPOS_9
VDDPLL_21 RCLK_7
TNEG_7 VDDPLL_22 RNEG_7
TCLK_7
13
RTIP_7 RRING_7
14
RXON TPOS_11 TPOS_13 VDDPLL_12 DGND_UP RCLK_13 TVDD_13 TRING_13 TRING_0 TVDD_0
A[6]
A[1]
CS2
ALE_AS TNEG_8 TCLK_9
TPOS_8 TNEG_9 TNEG_10
TCLK_8 TPOS_10 TPOS_7 DGND_DRV RVDD_7
19
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
REV. 1.0.1
RGND_10
22
23
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
PIN OUT OF THE XRT83VSH314
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
TABLE OF CONTENTS
GENERAL DESCRIPTION .................................................................................................1
APPLICATIONS ...........................................................................................................................................1
FIGURE 1. BLOCK DIAGRAM OF THE XRT83VSH314 ........................................................................................................................ 1
FEATURES ......................................................................................................................................................2
PRODUCT ORDERING INFORMATION ..................................................................................................2
PIN OUT OF THE XRT83VSH314 ......................................................................................3
TABLE OF CONTENTS ............................................................................................................I
1.0 PIN DESCRIPTIONS ..............................................................................................................................4
MICROPROCESSOR.........................................................................................................................................4
RECEIVER SECTION ........................................................................................................................................6
TRANSMITTER SECTION ..................................................................................................................................9
CONTROL FUNCTION ....................................................................................................................................11
CLOCK SECTION ..........................................................................................................................................11
JTAG SECTION ............................................................................................................................................12
POWER AND GROUND ..................................................................................................................................13
NO CONNECTS .............................................................................................................................................15
2.0 CLOCK SYNTHESIZER .......................................................................................................................16
TABLE 1: INPUT CLOCK SOURCE SELECT........................................................................................................................................ 16
FIGURE 2. SIMPLIFIED BLOCK DIAGRAM OF THE CLOCK SYNTHESIZER ............................................................................................ 16
3.0 RECEIVE PATH LINE INTERFACE .....................................................................................................17
FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE PATH ...................................................................................................... 17
3.1 LINE TERMINATION (RTIP/RRING) .............................................................................................................. 17
3.1.1 INTERNAL TERMINATION ......................................................................................................................................... 17
TABLE 2: SELECTING THE INTERNAL IMPEDANCE ............................................................................................................................. 17
FIGURE 4. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION .................................................................................... 17
TABLE 3: RECEIVE TERMINATIONS .................................................................................................................................................. 18
3.2
CLOCK AND DATA RECOVERY .................................................................................................................. 18
FIGURE 5. RECEIVE DATA UPDATED ON THE RISING EDGE OF RCLK .............................................................................................. 19
FIGURE 6. RECEIVE DATA UPDATED ON THE FALLING EDGE OF RCLK ............................................................................................ 19
TABLE 4: TIMING SPECIFICATIONS FOR RCLK/RPOS/RNEG .......................................................................................................... 19
3.2.1 RECEIVE SENSITIVITY .............................................................................................................................................. 20
FIGURE 7. TEST CONFIGURATION FOR MEASURING RECEIVE SENSITIVITY ........................................................................................ 20
3.2.2 INTERFERENCE MARGIN ......................................................................................................................................... 20
FIGURE 8. TEST CONFIGURATION FOR MEASURING INTERFERENCE MARGIN .................................................................................... 20
3.2.3 GENERAL ALARM DETECTION AND INTERRUPT GENERATION ........................................................................ 21
FIGURE 9. INTERRUPT GENERATION PROCESS BLOCK..................................................................................................................... 21
3.2.4 FLSD (FIFO LIMIT STATUS DETECTION) ................................................................................................................ 22
3.3 JITTER ATTENUATOR ................................................................................................................................... 23
3.4 HDB3/B8ZS DECODER .................................................................................................................................. 23
FIGURE 10. SINGLE RAIL MODE WITH A FIXED REPEATING "0011" PATTERN ................................................................................... 23
FIGURE 11. DUAL RAIL MODE WITH A FIXED REPEATING "0011" PATTERN ...................................................................................... 23
3.5 RXMUTE (RECEIVER LOS WITH DATA MUTING) ....................................................................................... 24
FIGURE 12. SIMPLIFIED BLOCK DIAGRAM OF THE RXMUTE FUNCTION ............................................................................................ 24
4.0 TRANSMIT PATH LINE INTERFACE ..................................................................................................25
FIGURE 13. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT PATH ................................................................................................... 25
4.1 TCLK/TPOS/TNEG DIGITAL INPUTS ............................................................................................................ 25
FIGURE 14. TRANSMIT DATA SAMPLED ON FALLING EDGE OF TCLK ............................................................................................... 25
FIGURE 15. TRANSMIT DATA SAMPLED ON RISING EDGE OF TCLK ................................................................................................. 25
TABLE 5: TIMING SPECIFICATIONS FOR TCLK/TPOS/TNEG ........................................................................................................... 26
4.2 HDB3/B8ZS ENCODER .................................................................................................................................. 26
TABLE 6: EXAMPLES OF HDB3 ENCODING ...................................................................................................................................... 26
TABLE 7: EXAMPLES OF B8ZS ENCODING ...................................................................................................................................... 26
4.3 JITTER ATTENUATOR ................................................................................................................................... 27
TABLE 8: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS .................................................................................... 27
4.4 TAOS (TRANSMIT ALL ONES) ...................................................................................................................... 27
FIGURE 16. TAOS (TRANSMIT ALL ONES) ...................................................................................................................................... 27
4.5 TRANSMIT DIAGNOSTIC FEATURES .......................................................................................................... 27
4.5.1 ATAOS (AUTOMATIC TRANSMIT ALL ONES)......................................................................................................... 28
FIGURE 17. SIMPLIFIED BLOCK DIAGRAM OF THE ATAOS FUNCTION ............................................................................................... 28
I
XRT83VSH314
REV. 1.0.1
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
4.5.2 QRSS/PRBS GENERATION....................................................................................................................................... 28
TABLE 9: RANDOM BIT SEQUENCE POLYNOMIALS ........................................................................................................................... 28
4.6 TRANSMIT PULSE SHAPER AND FILTER ................................................................................................... 28
4.6.1 T1 SHORT HAUL LINE BUILD OUT (LBO) ............................................................................................................... 28
TABLE 10: SHORT HAUL LINE BUILD OUT ....................................................................................................................................... 28
4.6.2 ARBITRARY PULSE GENERATOR FOR T1 AND E1............................................................................................... 29
FIGURE 18. ARBITRARY PULSE SEGMENT ASSIGNMENT .................................................................................................................. 29
4.6.3 SETTING REGISTERS TO SELECT AN ARIBTRARY PULSE ................................................................................. 29
TABLE 11: TYPICAL ROM VALUES.................................................................................................................................................. 30
4.7 DMO (DIGITAL MONITOR OUTPUT) ............................................................................................................. 30
4.8 LINE TERMINATION (TTIP/TRING) ............................................................................................................... 30
FIGURE 19. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION ................................................................................... 30
5.0 T1/E1 APPLICATIONS ........................................................................................................................ 31
5.1 LOOPBACK DIAGNOSTICS .......................................................................................................................... 31
5.1.1 LOCAL ANALOG LOOPBACK .................................................................................................................................. 31
FIGURE 20. SIMPLIFIED BLOCK DIAGRAM OF LOCAL ANALOG LOOPBACK ......................................................................................... 31
5.1.2 REMOTE LOOPBACK ................................................................................................................................................ 31
FIGURE 21. SIMPLIFIED BLOCK DIAGRAM OF REMOTE LOOPBACK .................................................................................................... 31
5.1.3 DIGITAL LOOPBACK ................................................................................................................................................. 32
FIGURE 22. SIMPLIFIED BLOCK DIAGRAM OF DIGITAL LOOPBACK ..................................................................................................... 32
5.1.4 DUAL LOOPBACK ..................................................................................................................................................... 32
FIGURE 23. SIMPLIFIED BLOCK DIAGRAM OF DUAL LOOPBACK ........................................................................................................ 32
5.2 84-CHANNEL T1/E1 MULTIPLEXER/MAPPER APPLICATIONS ................................................................. 33
FIGURE 24. SIMPLIFIED BLOCK DIAGRAM OF AN 84-CHANNEL APPLICATION ..................................................................................... 33
TABLE 12: CHIP SELECT ASSIGNMENTS .......................................................................................................................................... 33
5.3 LINE CARD REDUNDANCY .......................................................................................................................... 34
5.3.1 1:1 AND 1+1 REDUNDANCY WITHOUT RELAYS .................................................................................................... 34
5.3.2 TRANSMIT INTERFACE WITH 1:1 AND 1+1 REDUNDANCY .................................................................................. 34
FIGURE 25. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR 1:1 AND 1+1 REDUNDANCY ......................................... 34
5.3.3 RECEIVE INTERFACE WITH 1:1 AND 1+1 REDUNDANCY..................................................................................... 34
FIGURE 26. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR 1:1 AND 1+1 REDUNDANCY ........................................... 35
5.3.4 N+1 REDUNDANCY USING EXTERNAL RELAYS ................................................................................................... 35
5.3.5 TRANSMIT INTERFACE WITH N+1 REDUNDANCY ................................................................................................ 36
FIGURE 27. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR N+1 REDUNDANCY ...................................................... 36
5.3.6 RECEIVE INTERFACE WITH N+1 REDUNDANCY ................................................................................................... 37
FIGURE 28. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR N+1 REDUNDANCY ........................................................ 37
5.4 POWER FAILURE PROTECTION .................................................................................................................. 38
5.5 OVERVOLTAGE AND OVERCURRENT PROTECTION ............................................................................... 38
5.6 NON-INTRUSIVE MONITORING .................................................................................................................... 38
FIGURE 29. SIMPLIFIED BLOCK DIAGRAM OF A NON-INTRUSIVE MONITORING APPLICATION .............................................................. 38
5.7 ANALOG BOARD CONTINUITY CHECK ...................................................................................................... 39
FIGURE 30. ATP TESTING BLOCK DIAGRAM ..................................................................................................................................... 39
FIGURE 31. TIMING DIAGRAM FOR ATP TESTING ........................................................................................................................... 39
5.7.1 TRANSMITTER TTIP AND TRING TESTING............................................................................................................. 39
5.7.2 RECEIVER RTIP AND RRING .................................................................................................................................... 40
6.0 MICROPROCESSOR INTERFACE BLOCK ....................................................................................... 41
TABLE 13: SELECTING THE MICROPROCESSOR INTERFACE MODE ................................................................................................... 41
FIGURE 32. SIMPLIFIED BLOCK DIAGRAM OF THE MICROPROCESSOR INTERFACE BLOCK .................................................................. 41
6.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ......................................................................... 42
TABLE 14: XRT84SH314S MICROPROCESSOR INTERFACE SIGNALS COMMON TO BOTH INTEL AND MOTOROLA MODES.................... 42
TABLE 15: INTEL MODE: MICROPROCESSOR INTERFACE SIGNALS .................................................................................................... 42
TABLE 16: MOTOROLA MODE: MICROPROCESSOR INTERFACE SIGNALS ........................................................................................... 43
6.2 INTEL MODE PROGRAMMED I/O ACCESS (ASYNCHRONOUS) .............................................................. 44
FIGURE 33. INTEL µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS ............................................ 45
TABLE 17: INTEL MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS ........................................................................................ 45
6.3 MPC86X MODE PROGRAMMED I/O ACCESS (SYNCHRONOUS) ............................................................. 46
FIGURE 34. MOTOROLA MPC86X µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS .................... 47
TABLE 18: MOTOROLA MPC86X MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS ................................................................ 47
FIGURE 35. MOTOROLA 68K µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS ............................ 48
TABLE 19: MOTOROLA 68K MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS ........................................................................ 48
7.0 REGISTER DESCRIPTIONS ............................................................................................................... 49
TABLE 20: MICROPROCESSOR REGISTER ADDRESS (ADDR[7:0]) ................................................................................................... 49
TABLE 21: MICROPROCESSOR REGISTER CHANNEL DESCRIPTION ................................................................................................... 49
TABLE 22: MICROPROCESSOR REGISTER GLOBAL DESCRIPTION ..................................................................................................... 50
II
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
TABLE 23: MICROPROCESSOR REGISTER 0X00H BIT DESCRIPTION ................................................................................................. 51
TABLE 24: CABLE LENGTH SETTINGS ............................................................................................................................................. 52
TABLE 25: MICROPROCESSOR REGISTER 0X01H BIT DESCRIPTION ................................................................................................. 53
TABLE 26: MICROPROCESSOR REGISTER 0X02H BIT DESCRIPTION ................................................................................................. 54
TABLE 27: MICROPROCESSOR REGISTER 0X03H BIT DESCRIPTION ................................................................................................. 55
TABLE 28: MICROPROCESSOR REGISTER 0X04H BIT DESCRIPTION ................................................................................................. 56
TABLE 29: MICROPROCESSOR REGISTER 0X05H BIT DESCRIPTION ................................................................................................. 57
TABLE 30: MICROPROCESSOR REGISTER 0X06H BIT DESCRIPTION ................................................................................................. 58
TABLE 31: MICROPROCESSOR REGISTER 0X07H BIT DESCRIPTION ................................................................................................. 59
TABLE 32: MICROPROCESSOR REGISTER 0X08H BIT DESCRIPTION ................................................................................................. 59
TABLE 33: MICROPROCESSOR REGISTER 0X09H BIT DESCRIPTION ................................................................................................. 60
TABLE 34: MICROPROCESSOR REGISTER 0X0AH BIT DESCRIPTION ................................................................................................. 60
TABLE 35: MICROPROCESSOR REGISTER 0X0BH BIT DESCRIPTION ................................................................................................. 60
TABLE 36: MICROPROCESSOR REGISTER 0X0CH BIT DESCRIPTION ................................................................................................. 60
TABLE 37: MICROPROCESSOR REGISTER 0X0DH BIT DESCRIPTION ................................................................................................. 61
TABLE 38: MICROPROCESSOR REGISTER 0X0EH BIT DESCRIPTION ................................................................................................. 61
TABLE 39: MICROPROCESSOR REGISTER 0X0FH BIT DESCRIPTION ................................................................................................. 61
TABLE 40: MICROPROCESSOR REGISTER 0XE0H BIT DESCRIPTION ................................................................................................. 61
TABLE 41: MICROPROCESSOR REGISTER 0XE1H BIT DESCRIPTION ................................................................................................. 62
TABLE 42: MICROPROCESSOR REGISTER 0XE2H BIT DESCRIPTION ................................................................................................. 63
TABLE 43: MICROPROCESSOR REGISTER 0XE3H BIT DESCRIPTION ................................................................................................. 63
TABLE 44: MICROPROCESSOR REGISTER 0XE4H BIT DESCRIPTION ................................................................................................. 64
TABLE 45: MICROPROCESSOR REGISTER 0XE5H BIT DESCRIPTION ................................................................................................. 64
TABLE 46: MICROPROCESSOR REGISTER 0XE6H BIT DESCRIPTION ................................................................................................. 65
TABLE 47: MICROPROCESSOR REGISTER 0XE7H BIT DESCRIPTIO ................................................................................................... 66
TABLE 48: MICROPROCESSOR REGISTER 0XE8H BIT DESCRIPTION ................................................................................................. 67
CLOCK SELECT REGISTER .............................................................................................................................67
FIGURE 36. REGISTER 0XE9H SUB REGISTERS .............................................................................................................................. 67
TABLE 49: MICROPROCESSOR REGISTER 0XE9H BIT DESCRIPTION ................................................................................................. 68
TABLE 50: MICROPROCESSOR REGISTER 0XEAH BIT DESCRIPTION................................................................................................. 68
TABLE 51: MICROPROCESSOR REGISTER 0XEBH BIT DESCRIPTION................................................................................................. 69
TABLE 52: RECOVERED CLOCK SELECT ......................................................................................................................................... 70
TABLE 53: E1 ARBITRARY SELECT ................................................................................................................................................. 71
TABLE 54: MICROPROCESSOR REGISTER 0XFEH BIT DESCRIPTION ................................................................................................. 71
TABLE 55: MICROPROCESSOR REGISTER 0XFFH BIT DESCRIPTION ................................................................................................. 71
8.0 ELECTRICAL CHARACTERISTICS ....................................................................................................72
TABLE 56:
TABLE 57:
TABLE 58:
TABLE 59:
TABLE 60:
TABLE 61:
TABLE 62:
TABLE 63:
ABSOLUTE MAXIMUM RATINGS ....................................................................................................................................... 72
DC DIGITAL INPUT AND OUTPUT ELECTRICAL CHARACTERISTICS .................................................................................... 72
AC ELECTRICAL CHARACTERISTICS ............................................................................................................................... 72
POWER CONSUMPTION .................................................................................................................................................. 73
E1 RECEIVER ELECTRICAL CHARACTERISTICS ................................................................................................................ 73
T1 RECEIVER ELECTRICAL CHARACTERISTICS ................................................................................................................ 74
E1 TRANSMITTER ELECTRICAL CHARACTERISTICS .......................................................................................................... 74
T1 TRANSMITTER ELECTRICAL CHARACTERISTICS .......................................................................................................... 75
ORDERING INFORMATION.............................................................................................76
PACKAGE DIMENSIONS (BOTTOM VIEW) ..................................................................76
REVISION HISTORY .......................................................................................................................................77
III
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
1.0 PIN DESCRIPTIONS
MICROPROCESSOR
NAME
PIN
TYPE
DESCRIPTION
CS
A22
I
Chip Select Input
Active low signal. This signal enables the microprocessor interface by pulling
chip select "Low". The microprocessor interface is disabled when the chip
select signal returns "High".
NOTE: Internally pulled "High" with a 50k Ω resistor.
ALE_TS
C19
I
Address Latch Enable Input (Transfer Start)
See the Microprocessor section of this datasheet for a description.
NOTE: Internally pulled "Low" with a 50k Ω resistor.
WR_R/W
A20
I
Write Strobe Input (Read/Write)
See the Microprocessor section of this datasheet for a description.
NOTE: Internally pulled "Low" with a 50k Ω resistor.
RD_WE
D18
I
Read Strobe Input (Write Enable)
See the Microprocessor section of this datasheet for a description.
NOTE: Internally pulled "Low" with a 50k Ω resistor.
RDY_TA
AA3
O
Ready Output (Transfer Acknowledge)
See the Microprocessor section of this datasheet for a description.
INT
B3
O
Interrupt Output
Active low signal. This signal is asserted "Low" when a change in alarm status
occurs. Once the status registers have been read, the interrupt pin will return
"High". GIE (Global Interrupt Enable) must be set "High" in the appropriate
global register to enable interrupt generation.
NOTE: This pin is an open-drain output that requires an external 10KΩ pull-up
resistor.
µPCLK
AB2
I
Micro Processor Clock Input
In a synchronous microprocessor interface, µPCLK is used as the internal timing reference for programming the LIU.
NOTE: Internally pulled "Low" with a 50k Ω resistor.
4
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
MICROPROCESSOR
NAME
PIN
TYPE
DESCRIPTION
ADDR10
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
A23
E20
C22
Y18
AA19
AB20
AC21
AB21
AA20
Y19
AC22
I
Address Bus Input
ADDR[10:8] is used as a chip select decoder. The LIU has 5 chip select output
pins for enabling up to 5 additional devices for accessing internal registers.
The LIU has the option to select itself (master device), up to 5 additional
devices, or all 6 devices simultaneously by setting the ADDR[10:8] pins specified below. ADDR[7:0] is a direct address bus for permitting access to the
internal registers.
ADDR[10:8]
000 = Master Device
001 = Chip Select Output 1 (Pin B21)
010 = Chip Select Output 2 (Pin D19)
011 = Chip Select Output 3 (Pin C20)
100 = Chip Select Output 4 (Pin A21)
101 = Chip Select Output 5 (Pin B20)
110 = Reserved
111 = All Chip Selects Active Including the Master Device
NOTE: Internally pulled "Low" with a 50k Ω resistor.
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
AA4
AB3
AC3
AA5
Y6
AB4
AC4
AB5
I/O
µPTS2
µPTS1
µPTS0
AC23
AB22
AA21
I
Bi-directional Data Bus
DATA[7:0] is a bi-directional data bus used for read and write operations.
NOTE: Internally pulled "Low" with a 50k Ω resistor.
Microprocessor Type Select Input
µPTS[2:0] are used to select the microprocessor type interface.
000 = Intel 68HC11, 8051, 80C188 (Asynchronous)
001 = Motorola 68K (Asynchronous)
111 = Motorola MPC8260, MPC860 Power PC (Synchronous)
NOTE: Internally pulled "Low" with a 50k Ω resistor.
Reset
B22
I
Hardware Reset Input
Active low signal. When this pin is pulled "Low" for more than 10µS, the internal registers are set to their default state. See the register description for the
default values.
NOTE: Internally pulled "High" with a 50KΩ resistor.
CS5
CS4
CS3
CS2
CS1
B20
A21
C20
D19
B21
O
Chip Select Output
The XRT83VSH314 can be used to provide the necessary chip selects for up
to 5 additional devices by using the 3 MSBs ADDR[10:8] from the 11-Bit
address bus. The LIU allows up to 84-channel applications with only using one
chip select. See the ADDR[10:0] definition in the pin description.
5
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
RECEIVER SECTION
NAME
PIN
TYPE
DESCRIPTION
RxON
AB19
I
Receive On/Off Input
Upon power up, the receivers are powered off. Turning the receivers On or Off
can be selected through the microprocessor interface by programming the
appropriate channel register if the hardware pin is pulled "High". If the hardware pin is pulled "Low", all channels are automatically turned off.
NOTE: Internally pulled "Low" with a 50KΩ resistor.
RxTSEL
Y15
I
Receive Termination Control
Upon power up, the receivers are in "High" impedance. Switching to internal
termination can be selected through the microprocessor interface by programming the appropriate channel register. However, to switch control to the hardware pin, RxTCNTL must be programmed to "1" in the appropriate global
register. Once control has been granted to the hardware pin, it must be pulled
"High" to switch to internal termination.
NOTE: Internally pulled "Low" with a 50kΩ resistor.
RxTSEL (pin)
Rx Termination
0
External
1
Internal
Note: RxTCNTL (bit) must be set to "1"
RLOS
AB1
O
Receive Loss of Signal (Global Pin for All 14-Channels)
When a receive loss of signal occurs for any one of the 14-channels according
to ITU-T G.775, the RLOS pin will go "High" for a minimum of one RCLK cycle.
RLOS will remain "High" until the loss of signal condition clears. See the
Receive Loss of Signal section of this datasheet for more details.
NOTE: This pin is for redundancy applications to initiate an automatic switch to
the backup card. For individual channel RLOS, see the register map.
RCLK13
RCLK12
RCLK11
RCLK10
RCLK9
RCLK8
RCLK7
RCLK6
RCLK5
RCLK4
RCLK3
RCLK2
RCLK1
RCLK0
AB14
Y22
R22
P22
G22
F22
B14
B9
F2
G2
P2
R2
AA2
AA9
O
Receive Clock Output
RCLK is the recovered clock from the incoming data stream. If the incoming
signal is absent or RxON is pulled "Low", RCLK maintains its timing by using
an internal master clock as its reference. Software control (RCLKE) allows
RPOS/RNEG data to be updated on either edge of RCLK.
NOTE: RCLKE is a global setting that applies to all 14 channels.
6
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
RECEIVER SECTION
NAME
PIN
TYPE
DESCRIPTION
RCLKOUT
K1
O
Recovered Clock Output:
One of the 14 RCLKS is selected with the Recoved Clock Select [3:0] (register
0xEEh) bits and output through this pin.
See table below.
RPOS13
RPOS12
RPOS11
RPOS10
RPOS9
RPOS8
RPOS7
RPOS6
RPOS5
RPOS4
RPOS3
RPOS2
RPOS1
RPOS0
Y14
W20
P20
N20
H20
G20
D14
D10
G4
H4
N4
P4
W4
Y10
O
Recovered Clock
Select[3:0]
Selected
RCLK[13:0]
0000, 1111
No RCLK Selected
0001
RCLK 0
0010
RCLK 1
0011
RCLK 2
0100
RCLK 3
0101
RCLK 4
0110
RCLK 5
0111
RCLK 6
1000
RCLK 7
1001
RCLK 8
1010
RCLK 9
1011
RCLK 10
1100
RCLK 11
1101
RCLK 12
1110
RCLK 13
RPOS/RDATA Output
Receive digital output pin. In dual rail mode, this pin is the receive positive
data output. In single rail mode, this pin is the receive non-return to zero (NRZ)
data output.
7
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
RECEIVER SECTION
NAME
PIN
TYPE
DESCRIPTION
RNEG13
RNEG12
RNEG11
RNEG10
RNEG9
RNEG8
RNEG7
RNEG6
RNEG5
RNEG4
RNEG3
RNEG2
RNEG1
RNEG0
AA14
Y21
P21
N21
H21
G21
C14
C10
F3
G3
N3
P3
Y3
AA10
O
RNEG/LCV_OF Output
In dual rail mode, this pin is the receive negative data output. In single rail
mode, this pin can either be a Line Code Violation or Overflow indicator. If LCV
is selected by software and if a line code violation, a bi-polar violation, or
excessive zeros occur, the LCV pin will pull "High" for a minimum of one RCLK
cycle. LCV will remain "High" until there are no more violations. However, if
OF is selected the LCV pin will pull "High" if the internal LCV counter is saturated. The LCV pin will remain "High" until the LCV counter is reset.
RTIP13
RTIP12
RTIP11
RTIP10
RTIP9
RTIP8
RTIP7
RTIP6
RTIP5
RTIP4
RTIP3
RTIP2
RTIP1
RTIP0
AC14
Y23
T23
P23
G23
E23
A14
A9
E1
G1
P1
T1
Y1
AC9
I
Receive Differential Tip Input
RTIP is the positive differential input from the line interface. Along with the
RRING signal, these pins should be coupled to a 1:1 transformer for proper
operation.
RRING13
RRING12
RRING11
RRING10
RRING9
RRING8
RRING7
RRING6
RRING5
RRING4
RRING3
RRING2
RRING1
RRING0
AC13
W23
U23
N23
H23
D23
A13
A10
D1
H1
N1
U1
W1
AC10
I
Receive Differential Ring Input
RRING is the negative differential input from the line interface. Along with the
RTIP signal, these pins should be coupled to a 1:1 transformer for proper operation.
8
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
TRANSMITTER SECTION
NAME
PIN
TYPE
DESCRIPTION
TxON
AC20
I
Transmit On/Off Input
Upon power up, the transmitters are powered off. Turning the transmitters On
or Off is selected through the microprocessor interface by programming the
appropriate channel register if this pin is pulled "High". If the TxON pin is
pulled "Low", all 14 transmitters are powered off.
NOTES:
1. TxON is ideal for redundancy applications. See the Redundancy
Applications Section of this datasheet for more details.
2. Internally pulled "Low" with a 50KΩ resistor.
DMO
Y4
O
Digital Monitor Output (Global Pin for All 14-Channels)
When no transmit output pulse is detected for more than 128 TCLK cycles on
one of the 14-channels, the DMO pin will go "High" for a minimum of one TCLK
cycle. DMO will remain "High" until the transmitter sends a valid pulse.
NOTE: This pin is for redundancy applications to initiate an automatic switch to
the backup card. For individual channel DMO, see the register map.
TCLK13
TCLK12
TCLK11
TCLK10
TCLK9
TCLK8
TCLK7
TCLK6
TCLK5
TCLK4
TCLK3
TCLK2
TCLK1
TCLK0
Y16
Y17
AC18
D16
C17
A19
B16
D7
A3
B5
B6
AC6
AC5
AC7
I
TPOS13
TPOS12
TPOS11
TPOS10
TPOS9
TPOS8
TPOS7
TPOS6
TPOS5
TPOS4
TPOS3
TPOS2
TPOS1
TPOS0
AB17
AA18
AB18
A18
D17
B19
A17
B7
C4
B4
D6
AB6
AA6
Y8
I
Transmit Clock Input
TCLK is the input facility clock used to sample the incoming TPOS/TNEG data.
If TCLK is absent, pulled "Low", or pulled "High", the transmitter outputs at
TTIP/TRING can be selected to send an all ones or an all zero signal by programming TCLKCNL. In addition, software control (TCLKE) allows TPOS/
TNEG data to be sampled on either edge of TCLK.
NOTES:
1. TCLKE is a global setting that applies to all 14 channels.
2. Internally pulled "Low" with a 50k Ω resistor.
TPOS/TDATA Input
Transmit digital input pin. In dual rail mode, this pin is the transmit positive
data input. In single rail mode, this pin is the transmit non-return to zero (NRZ)
data input.
NOTE: Internally pulled "Low" with a 50KΩ resistor.
9
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
TRANSMITTER SECTION
NAME
PIN
TYPE
DESCRIPTION
TNEG13
TNEG12
TNEG11
TNEG10
TNEG9
TNEG8
TNEG7
TNEG6
TNEG5
TNEG4
TNEG3
TNEG2
TNEG1
TNEG0
AC17
AC19
AA17
B17
B18
C18
C16
C7
D5
C5
C6
AA7
Y7
AB7
I
Transmit Negative Data Input
In dual rail mode, this pin is the transmit negative data input. In single rail
mode, this pin can be left unconnected.
TTIP13
TTIP12
TTIP11
TTIP10
TTIP9
TTIP8
TTIP7
TTIP6
TTIP5
TTIP4
TTIP3
TTIP2
TTIP1
TTIP0
AA13
W21
R21
M21
J21
F21
C13
C11
E3
H3
M3
R3
W3
AA11
O
Transmit Differential Tip Output
TTIP is the positive differential output to the line interface. Along with the
TRING signal, these pins should be coupled to a 1:2 step up transformer for
proper operation.
TRING13
TRING12
TRING11
TRING10
TRING9
TRING8
TRING7
TRING6
TRING5
TRING4
TRING3
TRING2
TRING1
TRING0
AB12
V22
T20
M22
J22
D22
B12
B11
C2
H2
M2
U2
V3
AB11
O
Transmit Differential Ring Output
TRING is the negative differential output to the line interface. Along with the
TTIP signal, these pins should be coupled to a 1:2 step up transformer for
proper operation.
NOTE: Internally pulled "Low" with a 50KΩ resistor.
10
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
CONTROL FUNCTION
NAME
PIN
TYPE
TEST
D4
I
DESCRIPTION
Factory Test Mode
For normal operation, the TEST pin should be tied to ground.
NOTE: Internally pulled "Low" with a 50kΩ resistor.
ICT
A2
I
In Circuit Testing
When this pin is tied "Low", all output pins are forced to "High" impedance for
in circuit testing.
NOTE: Internally pulled "High" with a 50KΩ resistor.
PhDIN
L1
I
Test Pin
For testing purposes only. For normal operation leave this pin unconnected.
NOTE: Internally pulled "Low" with a 50kΩ resistor.
CMPOUT
K2
O
Test Pin
For testing purposes only. For normal operation leave this pin unconnected.
NAME
PIN
TYPE
DESCRIPTION
MCLKin
A6
I
Master Clock Input
The master clock input can accept a wide range of inputs that can be used to
generate T1 or E1 clock rates on a per channel basis. See the register map for
details.
CLOCK SECTION
NOTE: Internally pulled "Low" with a 50kΩ resistor.
8kHzOUT
D8
O
8kHz Output Clock
MCLKE1out
A5
O
2.048MHz Output Clock
MCLKE1Nout
A4
O
2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz Output Clock
See the register map for programming details.
MCLKT1out
A7
O
1.544MHz Output Clock
MCLKT1Nout
B8
O
1.544MHz, 3.088MHz, 6.176MHz, or 12.352MHz Output Clock
See the register map for programming details.
11
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
JTAG SECTION
NAME
PIN
TYPE
DESCRIPTION
ATP_TIP
ATP_RING
D21
K21
I/O
Analog Test Pin_TIP
Analog Test Pin_RING
These pins are used to check continuity of the Transmit and Receive TIP and
RING connections on the assembled board.
NOTE: See “Section 5.7, Analog Board Continuity Check” on page 39
for more detailed description.
TMS
E4
I
Test Mode Select
This pin is used as the input mode select for the boundary scan chain.
NOTE: Internally pulled "High" with a 50KΩ resistor.
TCK
B1
I
Test Clock Input
This pin is used as the input clock source for the boundary scan chain.
NOTE: Internally pulled "High" with a 50KΩ resistor.
TDI
A1
I
Test Data In
This pin is used as the input data pin for the boundary scan chain.
NOTE: Internally pulled "High" with a 50KΩ resistor.
TDO
D3
O
Test Data Out
This pin is used as the output data pin for the boundary scan chain.
12
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
POWER AND GROUND
NAME
PIN
TYPE
DESCRIPTION
TVDD13
TVDD12
TVDD11
TVDD10
TVDD9
TVDD8
TVDD7
TVDD6
TVDD5
TVDD4
TVDD3
TVDD2
TVDD1
TVDD0
AB13
V21
T21
N22
H22
E21
B13
B10
D2
J3
N2
T3
U4
AB10
PWR
Transmit Analog Power Supply (3.3V ±5%)
TVDD can be shared with DVDD. However, it is recommended that TVDD be
isolated from the analog power supply RVDD. For best results, use an internal
power plane for isolation. If an internal power plane is not available, a ferrite
bead can be used. Each power supply pin should be bypassed to ground
through an external 0.1µF capacitor.
RVDD13
RVDD12
RVDD11
RVDD10
RVDD9
RVDD8
RVDD7
RVDD6
RVDD5
RVDD4
RVDD3
RVDD2
RVDD1
RVDD0
AC15
AA23
T22
R23
F23
E22
A15
A8
E2
F1
R1
T2
Y2
AB9
PWR
Receive Analog Power Supply (3.3V ±5%)
RVDD should not be shared with other power supplies. It is recommended that
RVDD be isolated from the digital power supply DVDD and the analog power
supply TVDD. For best results, use an internal power plane for isolation. If an
internal power plane is not available, a ferrite bead can be used. Each power
supply pin should be bypassed to ground through an external 0.1µF capacitor.
DVDD_DRV
DVDD_DRV
DVDD_DRV
DVDD_DRV
DVDD_DRV
AC2
K3
U22
C21
AA16
PWR
Digital Power Supply (3.3V ±5%)
DVDD should be isolated from the analog power supplies. For best results,
use an internal power plane for isolation. If an internal power plane is not available, a ferrite bead can be used. Every two DVDD power supply pins should
be bypassed to ground through at least one 0.1µF capacitor.
DVDD_PRE
DVDD_PRE
DVDD_PRE
DVDD_PRE
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD_µP
Y5
C3
D20
Y20
J2
V2
D12
AA12
U21
K23
AA15
PWR
Digital Power Supply (1.8V ±5%)
DVDD should be isolated from the analog power supplies. For best results,
use an internal power plane for isolation. If an internal power plane is not available, a ferrite bead can be used. Every two DVDD power supply pins should
be bypassed to ground through at least one 0.1µF capacitor.
13
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
POWER AND GROUND
NAME
PIN
TYPE
DESCRIPTION
AVDD_BIAS
AVDD_PLL22
AVDD_PLL21
AVDD_PLL12
AVDD_PLL11
K4
C15
B15
AB16
AC16
PWR
Analog Power Supply (1.8V ±5%)
AVDD should be isolated from the digital power supplies. For best results, use
an internal power plane for isolation. If an internal power plane is not available,
a ferrite bead can be used. Each power supply pin should be bypassed to
ground through at least one 0.1µF capacitor.
TGND13
TGND12
TGND11
TGND10
TGND9
TGND8
TGND7
TGND6
TGND5
TGND4
TGND3
TGND2
TGND1
TGND0
Y13
V20
R20
M20
J20
F20
D13
D11
F4
J4
M4
R4
V4
Y11
GND
Transmit Analog Ground
It’s recommended that all ground pins of this device be tied together.
RGND13
RGND12
RGND11
RGND10
RGND9
RGND8
RGND7
RGND6
RGND5
RGND4
RGND3
RGND2
RGND1
RGND0
AC12
W22
V23
M23
J23
C23
A12
A11
C1
J1
M1
V1
W2
AC11
GND
Receive Analog Ground
It’s recommended that all ground pins of this device be tied together.
DGND
DGND
DGND
DGND
DGND
DGND
L2
T4
C12
Y12
U20
L23
GND
Digital Ground
It’s recommended that all ground pins of this device be tied together.
14
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
POWER AND GROUND
NAME
PIN
TYPE
DESCRIPTION
DGND_DRV
DGND_DRV
DGND_DRV
DGND_DRV
DGND_DRV
DGND_PRE
DGND_PRE
DGND_PRE
DGND_UP
B2
U3
A16
AA8
AB23
D15
AB8
L20
AB15
GND
Digital Ground
It’s recommended that all ground pins of this device be tied together.
AGND_BIAS
AGND_PLL22
AGND_PLL21
AGND_PLL12
AGND_PLL11
L3
C9
C8
Y9
AC8
GND
Analog Ground
It’s recommended that all ground pins of this device be tied together.
NAME
PIN
TYPE
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
AA1
AC1
K20
K22
L22
AA22
B23
L4
L21
D9
NC
NO CONNECTS
DESCRIPTION
No Connect
These pins can be left floating or tied to ground.
15
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
2.0 CLOCK SYNTHESIZER
In system design, fewer clocks on the network card could reduce noise and interference. Network cards that
support both T1 and E1 modes must be able to produce 1.544MHz and 2.048MHz transmission data. The
XRT83VSH314 has a built in clock synthesizer that requires only one input clock reference by programming
CLKSEL[3:0] in the appropriate global register. A list of the input clock options is shown in Table 1.
TABLE 1: INPUT CLOCK SOURCE SELECT
CLKSEL[3:0]
INPUT CLOCK REFERENCE
0h (0000)
2.048 MHz
1h (0001)
1.544MHz
8h (1000)
4.096 MHz
9h (1001)
3.088 MHz
Ah (1010)
8.192 MHz
Bh (1011)
6.176 MHz
Ch (1100)
16.384 MHz
Dh (1101)
12.352 MHz
Eh (1110)
2.048 MHz
Fh (1111)
1.544 MHz
The single input clock reference is used to generate multiple timing references. The first objective of the clock
synthesizer is to generate 1.544MHz and 2.048MHz for each of the 14 channels. This allows each channel to
operate in either T1 or E1 mode independent from the other channels. The state of the equalizer control bits in
the appropriate channel registers determine whether the LIU operates in T1 or E1 mode. The second objective
is to generate additional output clock references for system use. The available output clock references are
shown in Figure 2.
FIGURE 2. SIMPLIFIED BLOCK DIAGRAM OF THE CLOCK SYNTHESIZER
Input Clock
Clock
Synthesizer
Internal
Reference
1.544MHz
2.048MHz
8kHzOUT
8kHz
MCLKT1out
1.544Mhz
2.048MHz
MCLKE1out
MCLKE1Nout
MCLKT1Nout
Programmable
Programmable
16
2.048/4.096/8.192/16.384 MHz
1.544/3.088/6.176/12.352MHz
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
3.0 RECEIVE PATH LINE INTERFACE
The receive path of the XRT83VSH314 LIU consists of 14 independent T1/E1/J1 receivers. The following
section describes the complete receive path from RTIP/RRING inputs to RCLK/RPOS/RNEG outputs. A
simplified block diagram of the receive path is shown in Figure 3.
FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE PATH
RCLK
RPOS
RNEG
3.1
3.1.1
HDB3/B8ZS
Decoder
Rx Jitter
Attenuator
Clock & Data
Recovery
Peak Detector
& Slicer
RTIP
RRING
Line Termination (RTIP/RRING)
Internal Termination
The input stage of the receive path accepts standard T1/E1/J1 twisted pair or E1 coaxial cable inputs through
RTIP and RRING. The physical interface is optimized by placing the terminating impedance inside the LIU.
This allows one bill of materials for all modes of operation reducing the number of external components
necessary in system design. The receive termination impedance (along with the transmit impedance) is
selected by programming TERSEL[1:0] to match the line impedance. Selecting the internal impedance is
shown in Table 2.
TABLE 2: SELECTING THE INTERNAL IMPEDANCE
TERSEL[1:0]
RECEIVE TERMINATION
0h (00)
100Ω
1h (01)
110Ω
2h (10)
75Ω
3h (11)
120Ω
The XRT83VSH314 has the ability to switch the internal termination to "High" impedance by programming
RxTSEL in the appropriate channel register. For internal termination, set RxTSEL to "1". By default, RxTSEL
is set to "0" ("High" impedance). For redundancy applications, a dedicated hardware pin (RxTSEL) is also
available to control the receive termination for all channels simultaneously. This hardware pin takes priority
over the register setting if RxTCNTL is set to "1" in the appropriate global register. If RxTCNTL is set to "0", the
state of this pin is ignored. See Figure 4 for a typical connection diagram using the internal termination.
FIGURE 4. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION
XRT83VSH314 LIU
Receiver
Input
RTIP
1:1
Line Interface T1/E1/J1
RRING
One Bill of Materials
Internal Impedance
17
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
TABLE 3: RECEIVE TERMINATIONS
RXTSEL
TERSEL1
TERSEL0
RXRES1
RXRES0
Rext
Rint
MODE
0
x
x
x
x
Rext
∞
T1/E1/J1
1
0
0
0
0
∞
100Ω
T1
1
0
1
0
0
∞
110Ω
J1
1
1
0
0
0
∞
75Ω
E1
1
1
1
0
0
∞
120Ω
E1
1
0
0
0
1
240Ω
172Ω
T1
1
0
1
0
1
240Ω
204Ω
J1
1
1
0
0
1
240Ω
108Ω
E1
1
1
1
0
1
240Ω
240Ω
E1
1
0
0
1
0
210Ω
192Ω
T1
1
0
1
1
0
210Ω
232Ω
J1
1
1
0
1
0
210Ω
116Ω
E1
1
1
1
1
0
210Ω
280Ω
E1
1
0
0
1
1
150Ω
300Ω
T1
1
0
1
1
1
150Ω
412Ω
J1
1
1
0
1
1
150Ω
150Ω
E1
1
1
1
1
1
150Ω
600Ω
E1
3.2
Clock and Data Recovery
The receive clock (RCLK) is recovered by the clock and data recovery circuitry. An internal PLL locks on the
incoming data stream and outputs a clock that’s in phase with the incoming signal. This allows for multichannel T1/E1/J1 signals to arrive from different timing sources and remain independent. In the absence of an
incoming signal, RCLK maintains its timing by using the internal master clock as its reference. The recovered
data can be updated on either edge of RCLK. By default, data is updated on the rising edge of RCLK. To
update data on the falling edge of RCLK, set RCLKE to "1" in the appropriate global register. Figure 5 is a
timing diagram of the receive data updated on the rising edge of RCLK. Figure 6 is a timing diagram of the
receive data updated on the falling edge of RCLK. The timing specifications are shown in Table 4.
18
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
FIGURE 5. RECEIVE DATA UPDATED ON THE RISING EDGE OF RCLK
R C LK R
R DY
R C LK F
R C LK
RPOS
or
RNEG
R OH
FIGURE 6. RECEIVE DATA UPDATED ON THE FALLING EDGE OF RCLK
RCLKF
RDY
RCLKR
RCLK
RPOS
or
RNEG
ROH
TABLE 4: TIMING SPECIFICATIONS FOR RCLK/RPOS/RNEG
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
RCDU
45
50
55
%
Receive Data Setup Time
RSU
150
-
-
ns
Receive Data Hold Time
RHO
150
-
-
ns
RCLK to Data Delay
RDY
-
-
40
ns
RCLK Rise Time (10% to 90%) with 25pF Loading
RCLKR
-
-
40
ns
RCLK Fall Time (90% to 10%) with 25pF Loading
RCLKF
-
-
40
ns
RCLK Duty Cycle
NOTE: VDD=3.3V ±5%, VDDc=1.8V ±5%, TA=25°C, Unless Otherwise Specified
19
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
3.2.1
Receive Sensitivity
To meet short haul requirements, the XRT83VSH314 can accept T1/E1/J1 signals that have been attenuated
by 6dB of cable loss plus 6db of flat loss . Although data integrity is maintained, the RLOS function (if enabled)
will report an RLOS condition according to the receiver loss of signal section in this datasheet. The test
configuration for measuring the receive sensitivity is shown in Figure 7.
FIGURE 7. TEST CONFIGURATION FOR MEASURING RECEIVE SENSITIVITY
W&G ANT20
Tx
Cable Loss
Network
Analyzer
Flat Loss
Rx
Rx
Tx
External Loopback
XRT83VSH314
14-Channel
Long Haul LIU
E1 = PRBS 215 - 1
T1 = PRBS 223 - 1
3.2.2
Interference Margin
The test configuration for measuring the interference margin is shown in Figure 8.
FIGURE 8. TEST CONFIGURATION FOR MEASURING INTERFERENCE MARGIN
E1 = 1,024kHz
T1 = 772kHz
Sinewave
Generator
Flat Loss
E1 = PRBS 215 - 1
T1 = PRBS 223 - 1
W&G ANT20
Network
Analyzer
Rx
Tx
External Loopback
Cable Loss
Rx
Tx
20
XRT83VSH314
14-Channel LIU
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
3.2.3
REV. 1.0.1
General Alarm Detection and Interrupt Generation
The receive path detects RLOS, AIS, QRPD and FLS. These alarms can be individually masked to prevent the
alarm from triggering an interrupt. To enable interrupt generation, the Global Interrupt Enable (GIE) bit must be
set "High" in the appropriate global register. Any time a change in status occurs (it the alarms are enabled), the
interrupt pin will pull "Low" to indicate an alarm has occurred. Once the status registers have been read, the
INT pin will return "High". The status registers are Reset Upon Read (RUR). The interrupts are categorized in
a hierarchical process block. Figure 9 is a simplified block diagram of the interrupt generation process.
FIGURE 9. INTERRUPT GENERATION PROCESS BLOCK
Global Interrupt
Enable (GIE="1")
Global Channel Interrupt Status
(Indicates Which Channel(s) Experienced a Change in
Status)
Individual Alarm Status Change
(Indicates Which Alarm Experienced a Change)
Individual Alarm Indication
(Indicates the Alarm Condition Active/Inactive)
NOTE: The interrupt pin is an open-drain output that requires a 10kΩ external pull-up resistor.
21
XRT83VSH314
REV. 1.0.1
3.2.3.1
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
RLOS (Receiver Loss of Signal)
The XRT83VSH314supports both G.775 or ETSI-300-233 RLOS detection scheme.
In G.775 mode, RLOS is declared when the received signal is less than 375mV for 32 consecutive pulse
periods (typical). The device clears RLOS when the receive signal achieves 12.5% ones density with no more
than 15 consecutive zeros in a 32 bit sliding window and the signal level exceeds 425mV (typical).
In ETSI-300-233 mode the device declares RLOS when the input level drops below 375mV (typical) for more
than 2048 pulse periods (1msec).
The device exits RLOS when the input signal exceeds 425mV (typical) and has transitions for more than 32
pulse periods with 12.5% ones density with no more than 15 consecutive zero’s in a 32 bit sliding window.
ETSI-300-233 RLOS detection method is only available in Host mode.
In T1 mode RLOS is declared when the received signal is less than 320mV for 175 consecutive pulse period
(typical). The device clears RLOS when the receive signal achieves 12.5% ones density with no more than 100
consecutive zeros in a 128 bit sliding window and the signal level exceeds 425mV (typical).
3.2.3.2
EXLOS (Extended Loss of Signal)
By enabling the extended loss of signal by programming the appropriate channel register, the digital RLOS is
extended to count 4,096 consecutive zeros before declaring RLOS in T1 and E1 mode. By default, EXLOS is
disabled and RLOS operates in normal mode.
3.2.3.3
AIS (Alarm Indication Signal)
The XRT83VSH314 adheres to the ITU-T G.775 specification for an all ones pattern. The alarm indication
signal is set to "1" if an all ones pattern (at least 99.9% ones density) is present for T, where T is 3ms to 75ms
in T1 mode. AIS will clear when the ones density is not met within the same time period T. In E1 mode, the
AIS is set to "1" if the incoming signal has 2 or less zeros in a 512-bit window. AIS will clear when the incoming
signal has 3 or more zeros in the 512-bit window.
3.2.4
FLSD (FIFO Limit Status Detection)
The purpose of the FIFO limit status is to indicate when the Read and Write FIFO pointers are within a predetermined range (over-flow or under-flow indication). The FLSD is set to "1" if the FIFO Read and Write
Pointers are within ±3-Bits.
3.2.4.1
LCVD (Line Code Violation Detection)
The LIU contains 14 independent, 16-bit LCV counters. When the counters reach full-scale, they remain
saturated at FFFFh until they are reset globally or on a per channel basis. For performance monitoring, the
counters can be updated globally or on a per channel basis to place the contents of the counters into holding
registers. The LIU uses an indirect address bus to access a counter for a given channel. Once the contents of
the counters have been placed in holding registers, they can be individually read out from register 0xE8h 8-bits
at a time according to the BYTEsel bit in the appropriate global register. By default, the LSB byte is in register
0xE8h until the BYTEsel is pulled "High" where upon the MSB byte will be placed in the register for read back.
Once both bytes have been read, the next channel may be selected for read back.
By default, the LCV_OFD will be set to a "1" if the receiver is currently detecting line code violations or
excessive zeros for HDB3 (E1 mode) or B8ZS (T1 mode). In AMI mode, the LCVD will be set to a "1" if the
receiver is currently detecting bipolar violations or excessive zeros. However, if the LIU is configured to
monitor the 16-bit LCV counter by programming the appropriate global register, the LCV_OFD will be set to a
"1" if the counter saturates.
22
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
3.3
REV. 1.0.1
Jitter Attenuator
The jitter attenuator reduces phase and frequency jitter in the recovered clock if it is selected in the receive
path. The jitter attenuator uses a data FIFO (First In First Out) with a programmable depth of 32-bit or 64-bit. If
the LIU is used for line synchronization (loop timing systems), the JA should be enabled in the receive path.
When the Read and Write pointers of the FIFO are within 2-Bits of over-flowing or under-flowing, the bandwidth
of the jitter attenuator is widened to track the short term input jitter, thereby avoiding data corruption. When this
condition occurs, the jitter attenuator will not attenuate input jitter until the Read/Write pointer’s position is
outside the 2-Bit window. In T1 mode, the bandwidth of the JA is always set to 3Hz. In E1 mode, the
bandwidth is programmable to either 10Hz or 1.5Hz (1.5Hz automatically selects the 64-Bit FIFO depth). The
JA has a clock delay equal to ½ of the FIFO bit depth.
NOTE: If the LIU is used in a multiplexer/mapper application where stuffing bits are typically removed, the jitter attenuator
can be selected in the transmit path to smooth out the gapped clock. See the Transmit Section of this datasheet.
3.4
HDB3/B8ZS Decoder
In single rail mode, RPOS can decode AMI or HDB3/B8ZS signals. For E1 mode, HDB3 is defined as any
block of 4 successive zeros replaced with 000V or B00V, so that two successive V pulses are of opposite
polarity to prevent a DC component. In T1 mode, 8 successive zeros are replaced with 000VB0VB. If the
HDB3/B8ZS decoder is selected, the receive path removes the V and B pulses so that the original data is
output to RPOS.
3.4.0.1
RPOS/RNEG/RCLK
The digital output data can be programmed to either single rail or dual rail formats. Figure 10 is a timing
diagram of a repeating "0011" pattern in single-rail mode. Figure 11 is a timing diagram of the same fixed
pattern in dual rail mode.
FIGURE 10. SINGLE RAIL MODE WITH A FIXED REPEATING "0011" PATTERN
0
0
1
1
0
1
0
RCLK
RPOS
FIGURE 11. DUAL RAIL MODE WITH A FIXED REPEATING "0011" PATTERN
0
0
1
RCLK
RPOS
RNEG
23
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
3.5
RxMUTE (Receiver LOS with Data Muting)
The receive muting function can be selected by setting RxMUTE to "1" in the appropriate global register. If
selected, any channel that experiences an RLOS condition will automatically pull RPOS and RNEG "Low" to
prevent data chattering. If RLOS does not occur, the RxMUTE will remain inactive until an RLOS on a given
channel occurs. The default setting for RxMUTE is "0" which is disabled. A simplified block diagram of the
RxMUTE function is shown in Figure 12.
FIGURE 12. SIMPLIFIED BLOCK DIAGRAM OF THE RXMUTE FUNCTION
RPOS
RNEG
RxMUTE
RLOS
24
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
4.0 TRANSMIT PATH LINE INTERFACE
The transmit path of the XRT83VSH314 LIU consists of 14 independent T1/E1/J1 transmitters. The following
section describes the complete transmit path from TCLK/TPOS/TNEG inputs to TTIP/TRING outputs. A
simplified block diagram of the transmit path is shown in Figure 13.
FIGURE 13. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT PATH
TCLK
TPOS
TNEG
4.1
HDB3/B8ZS
Encoder
Tx Jitter
Attenuator
Timing
Control
Tx Pulse Shaper
& Pattern Gen
TTIP
Line Driver
TRING
TCLK/TPOS/TNEG Digital Inputs
In dual rail mode, TPOS and TNEG are the digital inputs for the transmit path. In single rail mode, TNEG has
no function and can be left unconnected. The XRT83VSH314 can be programmed to sample the inputs on
either edge of TCLK. By default, data is sampled on the falling edge of TCLK. To sample data on the rising
edge of TCLK, set TCLKE to "1" in the appropriate global register. Figure 14 is a timing diagram of the transmit
input data sampled on the falling edge of TCLK. Figure 15 is a timing diagram of the transmit input data
sampled on the rising edge of TCLK. The timing specifications are shown in Table 5.
FIGURE 14. TRANSMIT DATA SAMPLED ON FALLING EDGE OF TCLK
TCLKR
TCLKF
TCLKF
TCLKR
TCLK
TPOS
or
TNEG
TSU
THO
FIGURE 15. TRANSMIT DATA SAMPLED ON RISING EDGE OF TCLK
TCLK
TPOS
or
TNEG
T SU
T HO
25
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
TABLE 5: TIMING SPECIFICATIONS FOR TCLK/TPOS/TNEG
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
TCLK Duty Cycle
TCDU
30
50
70
%
Transmit Data Setup Time
TSU
50
-
-
ns
Transmit Data Hold Time
THO
30
-
-
ns
TCLK Rise Time (10% to 90%)
TCLKR
-
-
40
ns
TCLK Fall Time (90% to 10%)
TCLKF
-
-
40
ns
NOTE: VDD=3.3V ±5%, VDDc=1.8V ±5%, TA=25°C, Unless Otherwise Specified
4.2
HDB3/B8ZS Encoder
In single rail mode, the LIU can encode the TPOS input signal to AMI or HDB3/B8ZS data. In E1 mode and
HDB3 encoding selected, any sequence with four or more consecutive zeros in the input will be replaced with
000V or B00V, where "B" indicates a pulse conforming to the bipolar rule and "V" representing a pulse violating
the rule. An example of HDB3 encoding is shown in Table 6. In T1 mode and B8ZS encoding selected, an
input data sequence with eight or more consecutive zeros will be replaced using the B8ZS encoding rule. An
example with Bipolar with 8 Zero Substitution is shown in Table 7.
TABLE 6: EXAMPLES OF HDB3 ENCODING
NUMBER OF PULSES BEFORE
NEXT 4 ZEROS
Input
0000
HDB3 (Case 1)
Odd
000V
HDB3 (Case 2)
Even
B00V
TABLE 7: EXAMPLES OF B8ZS ENCODING
CASE
PRECEDING PULSE
NEXT 8 BITS
Case 1
+
00000000
B8ZS
AMI Output
000VB0VB
+
000+-0-+
-
00000000
Case 2
Input
B8ZS
AMI Output
000VB0VB
-
26
000-+0+-
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
4.3
REV. 1.0.1
Jitter Attenuator
The XRT83VSH314 LIU is ideal for multiplexer or mapper applications where the network data crosses
multiple timing domains. As the higher data rates are de-multiplexed down to T1 or E1 data, stuffing bits are
typically removed which can leave gaps in the incoming data stream. The jitter attenuator can be selected in
the transmit path with a 32-Bit or 64-Bit FIFO that is used to smooth the gapped clock into a steady T1 or E1
output. The maximum gap width of the 14-Channel LIU is shown in Table 8.
TABLE 8: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS
FIFO DEPTH
MAXIMUM GAP WIDTH
32-Bit
9 UI
64-Bit
9 UI
NOTE: If the LIU is used in a loop timing system, the jitter attenuator can be selected in the receive path. See the Receive
Section of this datasheet.
4.4
TAOS (Transmit All Ones)
The XRT83VSH314 has the ability to transmit all ones on a per channel basis by programming the appropriate
channel register. This function takes priority over the digital data present on the TPOS/TNEG inputs. For
example: If a fixed "0011" pattern is present on TPOS in single rail mode and TAOS is enabled, the transmitter
will output all ones. In addition, if digital or dual loopback is selected, the data on the RPOS output will be
equal to the data on the TPOS input. Figure 16 is a diagram showing the all ones signal at TTIP and TRING.
FIGURE 16. TAOS (TRANSMIT ALL ONES)
1
1
1
TAOS
4.5
Transmit Diagnostic Features
In addition to TAOS, the XRT83VSH314 offers multiple diagnostic features for analyzing network integrity such
as ATAOS and QRSS on a per channel basis by programming the appropriate registers. These diagnostic
features take priority over the digital data present on TPOS/TNEG inputs. The transmitters will send the
diagnostic code to the line and will be maintained in the digital loopback if selected. When the LIU is
responsible for sending diagnostic patterns, the LIU is automatically placed in the single rail mode.
NOTE: Dual and Remote Loopback have priority over TAOS.
27
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
4.5.1
ATAOS (Automatic Transmit All Ones)
If ATAOS is selected by programming the appropriate global register, an AMI all ones signal will be transmitted
for each channel that experiences an RLOS condition. If RLOS does not occur, the ATAOS will remain inactive
until an RLOS on a given channel occurs. A simplified block diagram of the ATAOS function is shown in
Figure 17.
FIGURE 17. SIMPLIFIED BLOCK DIAGRAM OF THE ATAOS FUNCTION
TTIP
Tx
TRING
TAOS
ATAOS
RLOS
4.5.2
QRSS/PRBS Generation
The XRT83VSH314 can transmit a QRSS/PRBS random sequence to a remote location from TTIP/TRING. To
select QRSS or PRBS, see the register map for programming details. The polynomial is shown in Table 9.
TABLE 9: RANDOM BIT SEQUENCE POLYNOMIALS
4.6
RANDOM PATTERN
T1
E1
QRSS
220 - 1
220 - 1
PRBS
215 - 1
215 - 1
Transmit Pulse Shaper and Filter
If TCLK is not present, pulled "Low", or pulled "High" the transmitter outputs at TTIP/TRING will automatically
send an all ones or an all zero signal to the line by programming the appropriate global register. By default, the
transmitters will send all zeros. To send all ones, the TCLKCNL bit must be set "High".
4.6.1
T1 Short Haul Line Build Out (LBO)
The short haul transmitter output pulses are generated using a 7-Bit internal DAC (6-Bit plus the MSB sign bit).
The line build out can be set to interface to five different ranges of cable attenuation by programming the
appropriate channel register. The pulse shape is divided into eight discrete time segments which are set to
fixed values to comply with the pulse template. The short haul LBO settings are shown in Table 10.
TABLE 10: SHORT HAUL LINE BUILD OUT
LBO SETTING EQC[4:0]
RANGE OF CABLE ATTENUATION
08h (01000)
0 - 133 Feet
09h (01001)
133 - 266 Feet
0Ah (01010)
266 - 399 Feet
0Bh (01011)
399 - 533 Feet
0Ch (01100)
533 - 655 Feet
28
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
4.6.2
REV. 1.0.1
Arbitrary Pulse Generator For T1 and E1
The arbitrary pulse generator divides the pulse into eight individual segments. Each segment is set by a 7-Bit
binary word by programming the appropriate channel register. This allows the system designer to set the
overshoot, amplitude, and undershoot for a unique line build out. The MSB (bit 7) is a sign-bit. If the sign-bit is
set to "0", the segment will move in a positive direction relative to a flat line (zero) condition. If this sign-bit is
set to "1", the segment will move in a negative direction relative to a flat line condition. The resolution of the
DAC is typically 45mV per LSB. Thus, writing 7-bit = 1111111 will clamp the output at either voltage rail
corresponding to a maximum amplitude. A pulse with numbered segments is shown in Figure 18.
FIGURE 18. ARBITRARY PULSE SEGMENT ASSIGNMENT
1
2
3
Segment
1
2
3
4
5
6
7
8
4
Register
0xn8
0xn9
0xna
0xnb
0xnc
0xnd
0xne
0xnf
8
7
6
5
NOTE: By default, the arbitrary segments are programmed to 0x00h. The transmitter outputs will result in an all zero
pattern to the line interface.
4.6.3
Setting Registers to select an Aribtrary Pulse
For T1: Address:0x0D hex
For E1: Address: 0xF4 hex, bit D0
To program the transmit output pulse, once the arbitrary pulse has been selected, write the appropriate values
into the segment registers in Table 11.
The transmit output pulse is divided into eight individual segments. Segment 1 corresponds to the beginning of
the pulse and segment 8 to end the pulse. The value for each segment can be programed individually through
a corresponding 8-bit register. In normal operation, i.e., non-arbitrary mode, codes are stored in an internal
ROM are used to generate the pulse shape, as shown in Table 11. Typical ROM values are given below in Hex.
29
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
TABLE 11: TYPICAL ROM VALUES
LINE DISTANCE
SEGMENT #
FEET
1
2
3
4
5
6
7
8
0 - 133
24
21
20
20
4C
47
44
42
133 - 266
29
23
22
21
4E
4A
47
43
266 - 399
30
25
24
23
59
40
48
44
399 - 525
34
26
24
23
5F
50
48
44
525 - 655
39
28
25
23
59
50
48
44
E1
2C
2A
2A
00
00
00
00
00
NOTE: The same register bank (eight registers in total) holds the values for any given line length. In other words , the user
can not load all the desired values for all the line lengths into the device at one time. If the line length is changed, a
new code must be loaded into the register bank.
4.7
DMO (Digital Monitor Output)
The driver monitor circuit is used to detect transmit driver failures by monitoring the activities at TTIP/TRING
outputs. Driver failure may be caused by a short circuit in the primary transformer or system problems at the
transmit inputs. If the transmitter of a channel has no output for more than 128 clock cycles, DMO goes "High"
until a valid transmit pulse is detected. If the DMO interrupt is enabled, the change in status of DMO will cause
the interrupt pin to go "Low". Once the status register is read, the interrupt pin will return "High" and the status
register will be reset (RUR).
4.8
Line Termination (TTIP/TRING)
The output stage of the transmit path generates standard return-to-zero (RZ) signals to the line interface for T1/
E1/J1 twisted pair or E1 coaxial cable. The physical interface is optimized by placing the terminating
impedance inside the LIU. This allows one bill of materials for all modes of operation reducing the number of
external components necessary in system design. The transmitter outputs only require one DC blocking
capacitor of 0.68µF. For redundancy applications (or simply to tri-state the transmitters), set TxTSEL to a "1" in
the appropriate channel register. A typical transmit interface is shown in Figure 19.
FIGURE 19. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION
XRT83VSH314 LIU
TTIP
Transmitter
Output
1:2
C=0.68uF
Line Interface T1/E1/J1
TRING
One Bill of Materials
Internal Impedance
30
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
5.0 T1/E1 APPLICATIONS
This applications section describes common T1/E1 system considerations along with references to application
notes available for reference where applicable.
5.1
Loopback Diagnostics
The XRT83VSH314 supports several loopback modes for diagnostic testing. The following section describes
the local analog loopback, remote loopback, digital loopback, and dual loopback modes.
5.1.1
Local Analog Loopback
With local analog loopback activated, the transmit output data at TTIP/TRING is internally looped back to the
analog inputs at RTIP/RRING. External inputs at RTIP/RRING are ignored while valid transmit output data
continues to be sent to the line. A simplified block diagram of local analog loopback is shown in Figure 20.
FIGURE 20. SIMPLIFIED BLOCK DIAGRAM OF LOCAL ANALOG LOOPBACK
QRSS/PRBS
TAOS
TCLK
TPOS
TNEG
Encoder
JA
Timing
Control
RCLK
RPOS
RNEG
Decoder
JA
Data and
Clock
Recovery
TTIP
TRING
Tx
Rx
RTIP
RRING
NOTE: The transmit diagnostic features such as TAOS and QRSS take priority over the transmit input data at TCLK/TPOS/
TNEG.
5.1.2
Remote Loopback
With remote loopback activated, the receive input data at RTIP/RRING is internally looped back to the transmit
output data at TTIP/TRING. The remote loopback includes the Receive JA (if enabled). The transmit input
data at TCLK/TPOS/TNEG are ignored while valid receive output data continues to be sent to the system. A
simplified block diagram of remote loopback is shown in Figure 21.
FIGURE 21. SIMPLIFIED BLOCK DIAGRAM OF REMOTE LOOPBACK
QRSS/PRBS
TAOS
TCLK
TPOS
TNEG
Encoder
JA
Timing
Control
RCLK
RPOS
RNEG
Decoder
JA
Data and
Clock
Recovery
31
TTIP
TRING
Tx
Rx
RTIP
RRING
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
5.1.3
Digital Loopback
With digital loopback activated, the transmit input data at TCLK/TPOS/TNEG is looped back to the receive
output data at RCLK/RPOS/RNEG. The digital loopback mode includes the Transmit JA (if enabled). The
receive input data at RTIP/RRING is ignored while valid transmit output data continues to be sent to the line. A
simplified block diagram of digital loopback is shown in Figure 22.
FIGURE 22. SIMPLIFIED BLOCK DIAGRAM OF DIGITAL LOOPBACK
QRSS/PRBS
5.1.4
TAOS
TCLK
TPOS
TNEG
Encoder
JA
Timing
Control
RCLK
RPOS
RNEG
Decoder
JA
Data and
Clock
Recovery
TTIP
TRING
Tx
Rx
RTIP
RRING
Dual Loopback
With dual loopback activated, the remote loopback is combined with the digital loopback. A simplified block
diagram of dual loopback is shown in Figure 23.
FIGURE 23. SIMPLIFIED BLOCK DIAGRAM OF DUAL LOOPBACK
QRSS/PRBS
TAOS
TCLK
TPOS
TNEG
Encoder
JA
Timing
Control
RCLK
RPOS
RNEG
Decoder
JA
Data and
Clock
Recovery
32
Tx
Rx
TTIP
TRING
RTIP
RRING
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
5.2
REV. 1.0.1
84-Channel T1/E1 Multiplexer/Mapper Applications
The XRT83VSH314 has the capability of providing the necessary chip selects for multiple 14-channel LIU
devices. The LIU is responsible for selecting itself, up to 5 additional LIU devices, or all 6 devices
simultaneously for permitting access to internal registers. The state of the chip select output pins is
determined by a chip select decoder controlled by the 3 MSBs of the address bus ADDR[10:8]. Only one LIU
(Master) requires the ADDR[10:8]. The other 5 LIU devices use the 8 LSBs for the direct address bus
ADDR[7:0]. Figure 24 is a simplified block diagram of connecting six 14-channel LIU devices for 84-channel
applications. Selection of the chip select outputs using ADDR[10:8] is shown in Table 12.
FIGURE 24. SIMPLIFIED BLOCK DIAGRAM OF AN 84-CHANNEL APPLICATION
Master
CS[5:1]
CS
XRT83VSH314
Slave
0
Slave
CS
XRT83VSH314
CS
1
Slave
2
Slave
CS
XRT83VSH314
XRT83VSH314
3
Data [7:0]
Address A[7:0]
Chip Address A[10:8]
TABLE 12: CHIP SELECT ASSIGNMENTS
ADDR[10:8]
ACTIVE CHIP SELECT
0h (000)
Current Device (Master)
1h (001)
Chip 1
2h (010)
Chip 2
3h (011)
Chip 3
4h (100)
Chip 4
5h (101)
Chip 5
6h (110)
Reserved
7h (111)
All Devices Active
33
CS
XRT83VSH314
Slave
XRT83VSH314
4
5
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
5.3
Line Card Redundancy
Telecommunication system design requires signal integrity and reliability. When a T1/E1 primary line card has
a failure, it must be swapped with a backup line card while maintaining connectivity to a backplane without
losing data. System designers can achieve this by implementing common redundancy schemes with the
XRT83VSH314 LIU. EXAR offers features that are tailored to redundancy applications while reducing the
number of components and providing system designers with solid reference designs.
RLOS and DMO
If an RLOS or DMO condition occurs, the XRT83VSH314 reports the alarm to the individual status registers on
a per channel basis. However, for redundancy applications, an RLOS or DMO alarm can be used to initiate an
automatic switch to the back up card. For this application, two global pins RLOS and DMO are used to indicate
that one of the 14-channels has an RLOS or DMO condition.
Typical Redundancy Schemes
• 1:1 One backup card for every primary card (Facility Protection)
• 1+1 One backup card for every primary card (Line Protection)
• ·N+1 One backup card for N primary cards
5.3.1
1:1 and 1+1 Redundancy Without Relays
The 1:1 facility protection and 1+1 line protection have one backup card for every primary card. When using
1:1 or 1+1 redundancy, the backup card has its transmitters tri-stated and its receivers in high impedance. This
eliminates the need for external relays and provides one bill of materials for all interface modes of operation.
For 1+1 line protection, the receiver inputs on the backup card have the ability to monitor the line for bit errors
while in high impedance. The transmit and receive sections of the LIU device are described separately.
5.3.2
Transmit Interface with 1:1 and 1+1 Redundancy
The transmitters on the backup card should be tri-stated. Select the appropriate impedance for the desired
mode of operation, T1/E1/J1. A 0.68uF capacitor is used in series with TTIP for blocking DC bias. See
Figure 25. for a simplified block diagram of the transmit section for a 1:1 and 1+1 redundancy.
FIGURE 25. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR 1:1 AND 1+1 REDUNDANCY
Backplane Interface
Primary Card
XRT83VSH314
1:2
Tx
0.68uF
T1/E1 Line
Internal Impedence
XRT83VSH314
Backup Card
1:2
Tx
0.68uF
Internal Impedence
5.3.3
Receive Interface with 1:1 and 1+1 Redundancy
The receivers on the backup card should be programmed for "High" impedance. Since there is no external
resistor in the circuit, the receivers on the backup card will not load down the line interface. This key design
feature eliminates the need for relays and provides one bill of materials for all interface modes of operation.
34
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
Select the impedance for the desired mode of operation, T1/E1/J1. To swap the primary card, set the backup
card to internal impedance, then the primary card to "High" impedance. See Figure 26. for a simplified block
diagram of the receive section for a 1:1 redundancy scheme.
FIGURE 26. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR 1:1 AND 1+1 REDUNDANCY
Backplane Interface
Primary Card
XRT83VSH314
1:1
T1/E1 Line
Rx
Internal Impedence
XRT83VSH314
Backup Card
1:1
Rx
"High" Impedence
5.3.4
N+1 Redundancy Using External Relays
N+1 redundancy has one backup card for N primary cards. Due to impedance mismatch and signal
contention, external relays are necessary when using this redundancy scheme. The relays create complete
isolation between the primary cards and the backup card. This allows all transmitters and receivers on the
primary cards to be configured in internal impedance, providing one bill of materials for all interface modes of
operation. The transmit and receive sections of the LIU device are described separately.
35
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
5.3.5
Transmit Interface with N+1 Redundancy
For N+1 redundancy, the transmitters on all cards should be programmed for internal impedance. The
transmitters on the backup card do not have to be tri-stated. To swap the primary card, close the desired
relays, and tri-state the transmitters on the failed primary card. A 0.68uF capacitor is used in series with TTIP
for blocking DC bias. See Figure 27 for a simplified block diagram of the transmit section for an N+1
redundancy scheme.
FIGURE 27. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR N+1 REDUNDANCY
Backplane Interface
Line Interface Card
Primary Card
XRT83VSH314
1:2
Tx
0.68uF
T1/E1 Line
Internal
Impedence
XRT83VSH314
Primary Card
1:2
Tx
0.68uF
T1/E1 Line
Internal
Impedence
XRT83VSH314
Primary Card
1:2
Tx
0.68uF
T1/E1 Line
Internal
Impedence
XRT83VSH314
Backup Card
Tx
0.68uF
Internal
Impedence
36
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
5.3.6
REV. 1.0.1
Receive Interface with N+1 Redundancy
For N+1 redundancy, the receivers on the primary cards should be programmed for internal impedance. The
receivers on the backup card should be programmed for "High" impedance mode. To swap the primary card,
set the backup card to internal impedance, then the primary card to "High" impedance. See Figure 28 for a
simplified block diagram of the receive section for a N+1 redundancy scheme.
FIGURE 28. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR N+1 REDUNDANCY
Backplane Interface
Line Interface Card
Primary Card
XRT83VSH314
1:1
Rx
T1/E1 Line
Internal
Impedence
Primary Card
XRT83VSH314
1:1
T1/E1 Line
Rx
Internal
Impedence
Primary Card
XRT83VSH314
1:1
Rx
T1/E1 Line
Internal
Impedence
Backup Card
XRT83VSH314
Rx
"High"
Impedence
37
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
5.4
Power Failure Protection
For 1:1 or 1+1 line card redundancy in T1/E1 applications, power failure could cause a line card to change the
characteristics of the line impedance, causing a degradation in system performance. The XRT83VSH314 was
designed to ensure reliability during power failures. The LIU has patented high impedance circuits that allow
the receiver inputs and the transmitter outputs to be in "High" impedance when the LIU experiences a power
failure or when the LIU is powered off.
NOTE: For power failure protection, a transformer must be used to couple to the line interface. See the TAN-56 application
note for more details.
5.5
Overvoltage and Overcurrent Protection
Physical layer devices such as LIUs that interface to telecommunications lines are exposed to overvoltage
transients posed by environmental threats. An Overvoltage transient is a pulse of energy concentrated over a
small period of time, usually under a few milliseconds. These pulses are random and exceed the operating
conditions of CMOS transceiver ICs. Electronic equipment connecting to data lines are susceptible to many
forms of overvoltage transients such as lightning, AC power faults and electrostatic discharge (ESD). There
are three important standards when designing a telecommunications system to withstand overvoltage
transients.
• UL1950 and FCC Part 68
• Telcordia (Bellcore) GR-1089
• ITU-T K.20, K.21 and K.41
NOTE: For a reference design and performance, see the TAN-54 application note for more details.
5.6
Non-Intrusive Monitoring
In non-intrusive monitoring applications, the transmitters are shut off by setting TxON "Low". The receivers
must be actively receiving data without interfering with the line impedance. The XRT83VSH314’s internal
termination ensures that the line termination meets T1/E1 specifications for 75Ω, 100Ω or 120Ω while
monitoring the data stream. System integrity is maintained by placing the non-intrusive receiver in "High"
impedance, equivalent to that of a 1+1 redundancy application. A simplified block diagram of non-intrusive
monitoring is shown in Figure 29.
FIGURE 29. SIMPLIFIED BLOCK DIAGRAM OF A NON-INTRUSIVE MONITORING APPLICATION
XRT83VSH314
Data Traffic
Line Card Transceiver
Node
XRT83VSH314
Non-Intrusive Receiver
38
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
5.7
REV. 1.0.1
Analog Board Continuity Check
This test verifies the per-channel continuity from the Line Side of TIP and RING for both the transmitters and
receivers, through the transformers on the assembly and LIU. Inside the LIU, a MUX and Control logic using
TMS and TCK as reset and clock, successively connect each TIP and RING on the XRT83VSH314 side to two
Analog Test Pins, (ATP_TIP and ATP_RING). Simplified block and timing diagrams are shown in Figure 30
and Figure 31.
FIGURE 30. ATP TESTING BLOCK DIAGRAM
TTIP_n
ATP_TIP
1:2
TTIP
LINE SIDE Tx
TRING_n
ATP_RING
MU
X
&
Control Logic
TRING
RTIP_n
1:1
RTIP
LINE SIDE
Rx
RRING
TMS
RRING_n
TCK
XRT83VSH31
XRT83SH314
4
S
n = 0:13
FIGURE 31. TIMING DIAGRAM FOR ATP TESTING
TMS
1
2
3
15
4
16
17
18
19
30
TCK
Reset
5.7.1
Tx0
Tx1
Tx2
Tx13
Rx0
Rx1
Rx2
RX13
Transmitter TTIP and TRING Testing
Testing of each channel must be done in sequence. With a clock signal applied to TCK, Setting TMS to “0” will
begin the test sequence. On the falling edge of the 1st clock pulse after TMS is set to “0”, the sequence will
reset as shown in Figure 31 above. On the 2nd falling clock edge the signal on ATP_TIP and ATP_RING will be
TTIP_0 and TRING_0, respectively. On the falling edge of the 17th clock pulse the signal on ATP_TIP and
ATP_RING wiill be connected to RTIP_0 and RRING_0, respectively. After the 30th clock pulse TMS can be
returned to a “1” and all channels will return to their normal state.
Device side testing is implemented via the ATP_TIP and ATP_RING pins. The Line side Testing is done via the
Line Side Receive and Transmit TIP and RING connections.
Each channel of the device can be tested from the line side by doing the following:
1. Apply a differental 2Vpp, 1MHz signal to the Tx Line Side channel TIP and RING pins.
2. Measure the signal at the device ATP_TIP and ATP_RING pins.
3. If the voltage measured ATP_TTIP/TRING pins is 1Vpp±20%, your assembly is correct.
39
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
NOTE: The Transmitter Line Side uses a 2:1 transformer.
4. If the measured signal is absent, there is either an open or short on the board.
5. A 1MHz signal applied to the Line Side TTIP pin should appear unattenuated on the Line Side TRING pin if
there is no open. This could also be indicitive of a short.
6. A 1MHz signal applied to the ATP_TIP pin should appear unattenuated on the ATP_RING pin if the line side
TTIP/TRING are appropriately terminated and there is no open. This could also be indicative of a short.
5.7.2
Receiver RTIP and RRING
Each channel of the device can be tested from the line side by doing the following, using the TMS and TCK as
describe above:
1. Apply a differential 2Vpp, 1MHz signal to the Rx Line Side channel TIP and RING pins.
2. Measure the signal at the device ATP_TIP and ATP_RING pins.
3. If the voltaged measured on the ATP_TTIP ATP_TRING pins is 2Vpp±20%, your assembly is correct.
NOTE: The Receiverr Line Side uses a 1:1 transformer.
4. If the measured signal is absent, there is either an open or short on the board.
5. A 1 MHZ or 1kHZ signal applied to the Line Side RTIP pin should appear attenuated on the Line Side
RRING pin if there is no open. This could also be indicative of a short.
6. A 1kHZ signal applied to the ATP_TIP pin should appear slightly attenuated on the ATP_RING pin if the line
side RTIP/RRING are appropriately terminated and there is no open. This could also be indicitive of a short.
The Receiver Device Side transformer is center tapped and capacitively connected to ground which would
cause a 1MHz signal to be severely attenuated.
40
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
6.0 MICROPROCESSOR INTERFACE BLOCK
The Microprocessor Interface section supports communication between the local microprocessor (µP) and the
LIU. The XRT83VSH314 supports an Intel asynchronous interface, Motorola 68K asynchronous, and a
Motorola Power PC interface. The microprocessor interface is selected by the state of the µPTS[2:0] input
pins. Selecting the microprocessor interface is shown in Table 13.
TABLE 13: SELECTING THE MICROPROCESSOR INTERFACE MODE
µPTS[2:0]
MICROPROCESSOR MODE
0h (000)
Intel 68HC11, 8051, 80C188
(Asynchronous)
1h (001)
Motorola 68K (Asynchronous)
7h (111)
Motorola MPC8260, MPC860
Power PC (Synchronous)
The XRT83VSH314 uses multipurpose pins to configure the device appropriately. The local µP configures the
LIU by writing data into specific addressable, on-chip Read/Write registers. The microprocessor interface
provides the signals which are required for a general purpose microprocessor to read or write data into these
registers. The microprocessor interface also supports polled and interrupt driven environments. A simplified
block diagram of the microprocessor is shown in Figure 32.
FIGURE 32. SIMPLIFIED BLOCK DIAGRAM OF THE MICROPROCESSOR INTERFACE BLOCK
CS
WR_R/W
RD_WE
ALE
ADDR[10:0]
DATA[7:0]
µPclk
Microprocessor
Interface
µPType [2:0]
CS5
CS4
CS3
CS2
CS1
Reset
RDY_TA
INT
41
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
6.1
The Microprocessor Interface Block Signals
The LIU may be configured into different operating modes and have its performance monitored by software
through a standard microprocessor using data, address and control signals. These interface signals are
described below in Table 14, Table 15, and Table 16. The microprocessor interface can be configured to
operate in Intel mode or Motorola mode. When the microprocessor interface is operating in Intel mode, some
of the control signals function in a manner required by the Intel 80xx family of microprocessors. Likewise, when
the microprocessor interface is operating in Motorola mode, then these control signals function in a manner as
required by the Motorola Power PC family of microprocessors. (For using a Motorola 68K asynchronous
processor, see Figure 35 and Table 19) Table 14 lists and describes those microprocessor interface signals
whose role is constant across the two modes. Table 15 describes the role of some of these signals when the
microprocessor interface is operating in the Intel mode. Likewise, Table 16 describes the role of these signals
when the microprocessor interface is operating in the Motorola Power PC mode.
TABLE 14: XRT84SH314S MICROPROCESSOR INTERFACE SIGNALS COMMON TO BOTH INTEL AND MOTOROLA
MODES
PIN NAME
TYPE
DESCRIPTION
µPTS[2:0]
I
Microprocessor Interface Mode Select Input pins
These three pins are used to specify the microprocessor interface mode. The relationship
between the state of these three input pins, and the corresponding microprocessor mode is
presented in Table 13.
DATA[7:0]
I/O
ADDR[10:8]
I
Bi-Directional Data Bus for register "Read" or "Write" Operations.
Three-Bit Address Bus Inputs
The 3 MSBs of the address bits are used as a chip select decoder. The state of these 3 pins
enable the Chip Selects for additional LIU devices.
NOTE: See the 84-Channel Application Section of this datasheet.
ADDR[7:0]
I
Eight-Bit Address Bus Inputs
The XRT83VSH314 LIU microprocessor interface uses a direct address bus. This address bus
is provided to permit the user to select an on-chip register for Read/Write access.
CS
I
Chip Select Input
This active low signal selects the microprocessor interface of the XRT83VSH314 LIU and
enables Read/Write operations with the on-chip register locations.
TABLE 15: INTEL MODE: MICROPROCESSOR INTERFACE SIGNALS
XRT83VSH314
INTEL
PIN NAME EQUIVALENT PIN
TYPE
DESCRIPTION
ALE_TS
ALE
I
Address-Latch Enable: This active high signal is used to latch the contents on
the address bus ADDR[7:0]. The contents of the address bus are latched into the
ADDR[7:0] inputs on the falling edge of ALE.
RD_WE
RD
I
Read Signal: This active low input functions as the read signal from the local µP.
When this pin is pulled “Low” (if CS is “Low”) the LIU is informed that a read operation has been requested and begins the process of the read cycle.
WR_R/W
WR
I
Write Signal: This active low input functions as the write signal from the local µP.
When this pin is pulled “Low” (if CS is “Low”) the LIU is informed that a write
operation has been requested and begins the process of the write cycle.
RDY_TA
RDY
O
Ready Output: This active low signal is provided by the LIU device. It indicates
that the current read or write cycle is complete, and the LIU is waiting for the next
command.
42
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
TABLE 16: MOTOROLA MODE: MICROPROCESSOR INTERFACE SIGNALS
XRT83VSH314 MOTOROLA
PIN NAME EQUIVALENT PIN
TYPE
DESCRIPTION
ALE_TS
TS
I
Transfer Start: This active high signal is used to latch the contents on the
address bus ADDR[7:0]. The contents of the address bus are latched into the
ADDR[7:0] inputs on the falling edge of TS.
WR_R/W
R/W
I
Read/Write: This input pin from the local µP is used to inform the LIU
whether a Read or Write operation has been requested. When this pin is
pulled “High”, WE will initiate a read operation. When this pin is pulled
“Low”, WE will initiate a write operation.
RD_WE
WE
I
Write Enable: This active low input functions as the read or write signal from the
local µP dependent on the state of R/W. When WE is pulled “Low” (If CS
is “Low”) the LIU begins the read or write operation.
No Pin
OE
I
Output Enable: This signal is not necessary for the XRT83VSH314 to interface
to the MPC8260 or MPC860 Power PCs.
µPCLK
CLKOUT
I
Synchronous Processor Clock: This signal is used as the timing reference for
the Power PC synchronous mode.
RDY_TA
TA
O
Transfer Acknowledge: This active low signal is provided by the LIU device. It
indicates that the current read or write cycle is complete, and the LIU is waiting
for the next command.
43
XRT83VSH314
REV. 1.0.1
6.2
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
Intel Mode Programmed I/O Access (Asynchronous)
If the LIU is interfaced to an Intel type µP, then it should be configured to operate in the Intel mode. Intel type
Read and Write operations are described below.
Intel Mode Read Cycle
Whenever an Intel-type µP wishes to read the contents of a register, it should do the following.
1. Place the address of the target register on the address bus input pins ADDR[10:0].
2. While the µP is placing this address value on the address bus, the address decoding circuitry should
assert the CS pin of the LIU, by toggling it "Low". This action enables further communication between the
µP and the LIU microprocessor interface block.
3. Toggle the ALE input pin "High". This step enables the address bus input drivers, within the microprocessor interface block of the LIU.
4. The µP should then toggle the ALE pin "Low". This step causes the LIU to latch the contents of the address
bus into its internal circuitry. At this point, the address of the register has now been selected.
5. Next, the µP should indicate that this current bus cycle is a Read operation by toggling the RD input pin
"Low". This action also enables the bi-directional data bus output drivers of the LIU.
6. After the µP toggles the Read signal "Low", the LIU will toggle the RDY output pin "Low". The LIU does this
in order to inform the µP that the data is available to be read by the µP, and that it is ready for the next command.
7. After the µP detects the RDY signal and has read the data, it can terminate the Read Cycle by toggling the
RD input pin "High".
NOTE: ALE can be tied “High” if this signal is not available.
The Intel Mode Write Cycle
Whenever an Intel type µP wishes to write a byte or word of data into a register within the LIU, it should do the
following.
1. Place the address of the target register on the address bus input pins ADDR[10:0].
2. While the µP is placing this address value on the address bus, the address decoding circuitry should
assert the CS pin of the LIU, by toggling it "Low". This action enables further communication between the
µP and the LIU microprocessor interface block.
3. Toggle the ALE input pin "High". This step enables the address bus input drivers, within the microprocessor interface block of the LIU.
4. The µP should then toggle the ALE pin "Low". This step causes the LIU to latch the contents of the address
bus into its internal circuitry. At this point, the address of the register has now been selected.
5. The µP should then place the byte or word that it intends to write into the target register, on the bi-directional data bus DATA[7:0].
6. Next, the µP should indicate that this current bus cycle is a Write operation by toggling the WR input pin
"Low". This action also enables the bi-directional data bus input drivers of the LIU.
7. After the µP toggles the Write signal "Low", the LIU will toggle the RDY output pin "Low". The LIU does this
in order to inform the µP that the data has been written into the internal register location, and that it is ready
for the next command.
NOTE: ALE can be tied “High” if this signal is not available.
The Intel Read and Write timing diagram is shown in Figure 33. The timing specifications are shown in
Table 17.
44
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
FIGURE 33. INTEL µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS
READ OPERATION
ALE = 1
WRITE OPERATION
t0
t0
ADDR[10:0]
Valid Address
Valid Address
CS
DATA[7:0]
Valid Data for Readback
Data Available to Write Into the LIU
t1
RD
t3
WR
t2
t4
RDY
TABLE 17: INTEL MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS
SYMBOL
PARAMETER
MIN
MAX
UNITS
t0
Valid Address to CS Falling Edge
0
-
ns
t1
CS Falling Edge to RD Assert
65
-
ns
t2
RD Assert to RDY Assert
-
90
ns
RD Pulse Width (t2)
90
-
ns
t3
CS Falling Edge to WR Assert
65
-
ns
t4
WR Assert to RDY Assert
-
90
ns
90
-
ns
NA
NA
WR Pulse Width (t4)
45
XRT83VSH314
REV. 1.0.1
6.3
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
MPC86X Mode Programmed I/O Access (Synchronous)
If the LIU is interfaced to a MPC86X type µP, it should be configured to operate in the MPC86X mode.
MPC86X Read and Write operations are described below.
MPC86X Mode Read Cycle
1. Place the address of the target register on the address bus input pins ADDR[10:0].
2. While the µP is placing this address value on the address bus, the address decoding circuitry should
assert the CS pin of the LIU, by toggling it "Low". This action enables further communication between the
µP and the LIU microprocessor interface block.
3. Next, the µP should indicate that this current bus cycle is a Read operation by pulling the R/W input pin
"High".
4. The LIU will toggle the TA output pin "Low". The LIU does this in order to inform the µP that the data is
available to be read by the µP.
5. After the µP detects the TA signal and has read the data, it can terminate the Read Cycle by toggling the
CS input pin "High".
MPC86X Mode Write Cycle
1. Place the address of the target register on the address bus input pins ADDR[10:0].
2. While the µP is placing this address value on the address bus, the address decoding circuitry should
assert the CS pin of the LIU, by toggling it "Low". This action enables further communication between the
µP and the LIU microprocessor interface block.
3. Next, the µP should indicate that this current bus cycle is a Write operation by pulling the R/W input pin
"Low".
4. Toggle the WE input pin "Low".
5. After the µP toggles the WE signal "Low", the LIU will toggle the TA output pin "Low". The LIU does this in
order to inform the µP that the data has been written into the internal register location.
6. After the µP detects the TA signal, the Write operation is completed by toggling both WE and CS pins
“High”.
The Motorola Read and Write timing diagram is shown in Figure 34. The timing specifications are shown in
Table 18.
46
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
FIGURE 34. MOTOROLA MPC86X µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS
READ OPERATION
WRITE OPERATION
tdc
uPCLK
tcp
t0
t0
Valid Address
ADDR[10:0]
Valid Address
CS
Valid Data for Readback
DATA[7:0]
Data Available to Write Into the LIU
t1
WE
R/W
TA
t2
TABLE 18: MOTOROLA MPC86X MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS
SYMBOL
PARAMETER
MIN
MAX
UNITS
t0
Valid Address to CS Falling Edge
0
-
ns
t1
CS Falling Edge to WE Assert
0
-
ns
t2
WE Assert to TA Assert
-
90
ns
tdc
µPCLK Duty Cycle
40
60
%
tcp
µPCLK Clock Period
20
47
ns
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
FIGURE 35. MOTOROLA 68K µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS
MOTOROLA ASYCHRONOUS MODE
READ OPERATION
ALE_TS
WRITE OPERATION
t0
t0
Valid Address
ADDR[10:0]
Valid Address
t3
t3
CS
Valid Data for Readback
DATA[7:0]
t1
Data Available to Write Into the LIU
t1
RD_WE
WR_R/W
t2
RDY_DTACK
t2
TABLE 19: MOTOROLA 68K MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS
SYMBOL
PARAMETER
MIN
MAX
UNITS
t0
Valid Address to CS Falling Edge
0
-
ns
t1
CS Falling Edge to DS (Pin RD_WE) Assert
65
-
ns
t2
DS Assert to DTACK Assert
-
90
ns
DS Pulse Width (t2)
90
-
ns
CS Falling Edge to AS (Pin ALE_TS) Falling Edge
0
-
ns
NA
t3
48
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
7.0 REGISTER DESCRIPTIONS
TABLE 20: MICROPROCESSOR REGISTER ADDRESS (ADDR[7:0])
REGISTER
NUMBER
ADDRESS (HEX)
0 - 15
0x00 - 0x0F
Channel 0 Control Registers
16 - 31
0x10 - 0x1F
Channel 1 Control Registers
32 - 47
0x20 - 0x2F
Channel 2 Control Registers
48 - 63
0x30 - 0x3F
Channel 3 Control Registers
64 - 79
0x40 - 0x4F
Channel 4 Control Registers
80 - 95
0x50 - 0x5F
Channel 5 Control Registers
96 - 111
0x60 - 0x6F
Channel 6 Control Registers
112 - 127
0x70 - 0x7F
Channel 7 Control Registers
128 - 143
0x80 - 0x8F
Channel 8 Control Registers
144 - 159
0x90 - 0x9F
Channel 9 Control Registers
160 - 175
0xA0 - 0xAF
Channel 10 Control Registers
176 - 191
0xB0 - 0xBF
Channel 11 Control Registers
192 - 207
0xC0 - 0xCF
Channel 12 Control Registers
208 - 223
0xD0 - 0xDF
Channel 13 Control Registers
224 - 235
0xE0 - 0xEB
Global Control Registers Applied to All 14 Channels
236 - 237
0xEC - 0xED
Registers Reserved
238
0xEE
239 - 242
0xEF - 0xF3
244
0xF4
245 - 253
0XF5 - OxFD
254
0xFE
Device "ID"
255
0xFF
Device "Revision ID"
FUNCTION
RCLKOUTPUT Control
Registers Reserved
Global Control Register
Registers Reserved for Testing
TABLE 21: MICROPROCESSOR REGISTER CHANNEL DESCRIPTION
REG
ADDR TYPE
D7
D6
D5
D4
D3
D2
D1
D0
Channel 0 Control Registers (0x00 - 0x0F)
0
0x00
R/W
QRSS/
PRBS
PRBS_Rx/
Tx
RxON
EQC4
EQC3
EQC2
EQC1
EQC0
1
0x01
R/W
RxTSEL
TxTSEL
TERSEL1
TERSEL0
JASEL1
JASEL0
JABW
FIFOS
2
0x02
R/W INVQRSS
TxTEST2
TxTEST1
TxTEST0
TxON
LOOP2
LOOP1
LOOP0
3
0x03
R/W
Reserved
CODES
RxRES1
RxRES0
INSBPV
INSBER
Reserved
Reserved
49
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
TABLE 21: MICROPROCESSOR REGISTER CHANNEL DESCRIPTION
REG
ADDR TYPE
D7
D6
D5
D4
D3
D2
D1
D0
4
0x04
R/W
Reserved
DMOIE
FLSIE
LCV_OFIE
Reserved
AISDIE
RLOSIE
QRPDIE
5
0x05
RO
Reserved
DMO
FLS
LCV_OF
Reserved
AISD
RLOS
QRPD
6
0x06
DMOIS
FLSIS
LCV_OFIS
Reserved
AISDIS
RLOSIS
QRPDIS
7
0x07
RO
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
8
0x08
R/W
Reserved
1SEG6
1SEG5
1SEG4
1SEG3
1SEG2
1SEG1
1SEG0
9
0x09
R/W
Reserved
2SEG6
2SEG5
2SEG4
2SEG3
2SEG2
2SEG1
2SEG0
10
0x0A
R/W
Reserved
3SEG6
3SEG5
3SEG4
3SEG3
3SEG2
3SEG1
3SEG0
11
0x0B
R/W
Reserved
4SEG6
4SEG5
4SEG4
4SEG3
4SEG2
4SEG1
4SEG0
12
0x0C
R/W
Reserved
5SEG6
5SEG5
5SEG4
5SEG3
5SEG2
5SEG1
5SEG0
13
0x0D
R/W
Reserved
6SEG6
6SEG5
6SEG4
6SEG3
6SEG2
6SEG1
6SEG0
14
0x0E
R/W
Reserved
7SEG6
7SEG5
7SEG4
7SEG3
7SEG2
7SEG1
7SEG0
15
0x0F
R/W
Reserved
8SEG6
8SEG5
8SEG4
8SEG3
8SEG2
8SEG1
8SEG0
RUR Reserved
Channel (1 - 13) Control Registers (0xN0 - 0xNF) See Channel 0
TABLE 22: MICROPROCESSOR REGISTER GLOBAL DESCRIPTION
REG
ADDR TYPE
D7
D6
D5
D4
D3
D2
D1
D0
Global Control Registers for All 14 Channels
224
0xE0
R/W
SR/DR
ATAOS
RCLKE
TCLKE
DATAP
Reserved
GIE
SRESET
225
0xE1
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
RxMUTE
EXLOS
ICT
226
0xE2
R/W
Reserved
RxTCNTL
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
227
0xE3
R/W
Reserved
Reserved
Reserved
Reserved
SL<1>
SL<0>
Reserved
Reserved
228
0xE4
R/W
MCLKT1out1
MCLKT1out0
MCLKE1out1
MCLKE1out0
Reserved
Reserved
Reserved
Reserved
229
0xE5
R/W
LCV_OFLW
CNTRDEN
Reserved
Reserved
LCVCH3
LCVCH2
LCVCH1
LCVCH0
230
0xE6
R/W
Reserved
Reserved
Reserved
allRST
allUPDATE
BYTEsel
chUPDATE
chRST
231
0xE7
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
232
0xE8
RO
LCVCNT7
LCVCNT6
LCVCNT5
LCVCNT4
LCVCNT3
LCVCNT2
LCVCNT1
LCVCNT0
233
0xE9
R/W
Reserved
Reserved
Reserved
TCLKCNL
CLKSEL3
CLKSEL2
CLKSEL1
CLKSEL0
234
0xEA
RUR
GCHIS7
GCHIS6
GCHIS5
GCHIS4
GCHIS3
GCHIS2
GCHIS1
GCHIS0
235
0xEB
RUR
Reserved
Reserved
GCHIS13
GCHIS12
GCHIS11
GCHIS10
GCHIS9
GCHIS8
236237
0xEC
0xED
RO
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
238
0xEE
R/W
Reserved
Reserved
Reserved
Reserved
50
Recovered Clock Selects [3:0]
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
TABLE 22: MICROPROCESSOR REGISTER GLOBAL DESCRIPTION
REG
ADDR TYPE
D7
D6
D5
D4
D3
D2
D1
D0
239242
0xEF
0xF2
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
244
245
0xF4
0xF5
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
E1Arben
246253
0xF6
0xFD
R/W
Reserved for
Testing
Reserved for
Testing
Reserved for
Testing
Reserved for
Testing
Reserved for
Testing
Reserved for
Testing
Reserved for
Testing
Reserved for
Testing
Register
Type
Default
Value
(HW reset)
R/W Registers Reserved for Testing (0xEC - 0xFD), Excluding 0xF4h
254
0xFE
RO
Device "ID"
255
0xFF
RO
Device "Revision ID"
TABLE 23: MICROPROCESSOR REGISTER 0X00H BIT DESCRIPTION
CHANNEL 0-13 (0X00H-0XD0H)
BIT
NAME
FUNCTION
D7
QRSS/PRBS QRSS/PRBS Select Bits
These bits are used to select between QRSS and PRBS.
0 = PRBS
1 = QRSS
R/W
0
D6
PRBS_Rx/Tx PRBS Receive/Transmit Select:
This bit is used to select where the output of the PRBS Generator
is directed if PRBS generation is enabled.
0 = Normal Operation - PRBS generator is output on TTIP and
TRING if PRBS generation is enabled.
1 = PRBS Generator is output on RPOS; RNEG is internally
grounded, if PRBS generation is enabled.
R/W
0
Bit 6 = "0"
+
PBRS
Generator
TTIP
-
Tx
TRING
Bit 6 = "1"
+
PBRS
Generator
RPOS
Rx
-
RNEG
NOTE: If PRBS generation is disabled, user should set this bit to ’0’
for normal operation.
51
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
TABLE 23: MICROPROCESSOR REGISTER 0X00H BIT DESCRIPTION
CHANNEL 0-13 (0X00H-0XD0H)
Register
Type
Default
Value
(HW reset)
Receiver ON/OFF
Upon power up, the receiver is powered OFF. RxON is used to
turn the receiver ON or OFF if the hardware pin RxON is pulled
"High". If the hardware pin is pulled "Low", all receivers are turned
off.
0 = Receiver is Powered Off
1 = Receiver is Powered On
R/W
0
Cable Length Settings
R/W
0
0
0
0
0
BIT
NAME
FUNCTION
D5
RxON
D4
D3
D2
D1
D0
EQC4
EQC3
EQC2
EQC1
EQC0
The Cable Length Settting bits are shown in Table 24 below.
TABLE 24: CABLE LENGTH SETTINGS
EQC[4:0]
T1/E1 MODE/RECEIVE SENSITIVITY
TRANSMIT LBO
CABLE
CODING
0x08h
T1 Short Haul
0 to 133 feet (0.6dB)
100Ω TP
B8ZS
0x09h
T1 Short Haul
133 to 266 feet (1.2dB)
100Ω TP
B8ZS
0x0Ah
T1 Short Haul
266 to 399 feet (1.8dB)
100Ω TP
B8ZS
0x0Bh
T1 Short Haul
399 to 533 feet (2.4dB)
100Ω TP
B8ZS
0x0Ch
T1 Short Haul
533 to 655 feet (3.0dB)
100Ω TP
B8ZS
0x0Dh
T1 Short Haul
Arbitrary Pulse
100Ω TP
B8ZS
0x1Ch
E1 Short Haul
ITU G.703
75Ω Coax
HDB3
0x1Dh
E1 Short Haul
ITU G.703
120Ω TP
HDB3
52
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
TABLE 25: MICROPROCESSOR REGISTER 0X01H BIT DESCRIPTION
CHANNEL 0-13 (0X01H-0XD1H)
Register
Type
Default
Value
(HW reset)
Receive Termination Select
Upon power up, the receiver is in "High" impedance. RxTSEL is
used to switch between the internal termination and "High" impedance.
0 = External Termination
1 = Internal Termination
R/W
0
TxTSEL
Transmit Termination Select
Upon power up, the transmitter is in "High" impedance. TxTSEL is
used to switch between the internal termination and "High" impedance.
0 = "High" Impedance
1 = Internal Termination
R/W
0
TERSEL1
TERSEL0
Receive Line Impedance Select
TERSEL[1:0] are used to select the line impedance for T1/J1/E1.
R/W
0
0
R/W
0
BIT
NAME
FUNCTION
D7
RxTSEL
D6
D5
D4
D3
D2
JASEL1
JASEL0
TERSEL1
TERSEL0
LINE IMPEDANCE
0
0
100Ω
0
1
110Ω
1
0
75Ω
1
1
120Ω
Jitter Attenuator Select
JASEL[1:0] are used to enable the jitter attenuator in the receive or
transmit path. By default, the jitter attenuator is disabled.
JASEL1
JASEL0
JA PATH
0
0
Disabled
0
1
Transmit Path
1
0
Receive Path
1
1
Receive Path
53
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
TABLE 25: MICROPROCESSOR REGISTER 0X01H BIT DESCRIPTION
CHANNEL 0-13 (0X01H-0XD1H)
Register
Type
Default
Value
(HW reset)
Jitter Bandwidth (E1 Mode Only, T1 is permanently set to 3Hz)
The jitter bandwidth is a global setting that is applied to both the
receiver and transmitter jitter attenuator.
0 = 10Hz
1 = 1.5Hz
R/W
0
FIFO Depth Select
The FIFO depth select is used to configure the part for a 32-bit or
64-bit FIFO (within the jitter attenuator blocks). The delay of the
FIFO is equal to ½ the FIFO depth. This is a global setting that is
applied to both the receiver and transmitter FIFO.
0 = 32-Bit
1 = 64-Bit
R/W
0
Register
Type
Default
Value
(HW reset)
BIT
NAME
FUNCTION
D1
JABW
D0
FIFOS
TABLE 26: MICROPROCESSOR REGISTER 0X02H BIT DESCRIPTION
CHANNEL 0-13 (0X02H-0XD2H)
BIT
NAME
FUNCTION
D7
INVQRSS
QRSS inversion
INVQRSS is used to invert the transmit QRSS or PRBS pattern set
by the TxTEST[2:0] bits. By default (bit D7=0), INVQRSS is disabled for PRBS and enabled for QRSS.
0 = Disabled for PRBS
0 = Enabled for QRSS
1 = Disabled for QRSS
1 = Enabled for PRBS
R/W
0
D6
D5
D4
TxTEST2
TxTEST1
TxTEST0
Test Code Pattern
TxTEST[2:0] are used to select a diagnostic test pattern to the line
(transmit outputs).
0XX = No Pattern
100 = Tx QRSS
101 = Tx TAOS
110 = Reserved
111 = Reserved
R/W
0
0
0
54
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
TABLE 26: MICROPROCESSOR REGISTER 0X02H BIT DESCRIPTION
CHANNEL 0-13 (0X02H-0XD2H)
Register
Type
Default
Value
(HW reset)
Transmit ON/OFF
Upon power up, the transmitters are powered off. This bit is used
to turn the transmitter for this channel On or Off if the TxON pin is
pulled "High". If the TxON pin is pulled "Low", all 14 transmitters
are powered off.
0 = Transmitter is Powered OFF
1 = Transmitter is Powered ON
R/W
0
Loopback Diagnostic Select
LOOP[2:0] are used to select the loopback mode.
0XX = No Loopback
100 = Dual Loopback
101 = Analog Loopback
110 = Remote Loopback
111 = Digital Loopback
R/W
0
0
0
Register
Type
Default
Value
(HW reset)
These Bits are Reserved.
R/W
0
0
BIT
NAME
FUNCTION
D3
TxOn
D2
D1
D0
LOOP2
LOOP1
LOOP0
TABLE 27: MICROPROCESSOR REGISTER 0X03H BIT DESCRIPTION
CHANNEL 0-13 (0X03H-0XD3H)
BIT
NAME
FUNCTION
D7
D6
Reserved
D5
CODES
Encoding/Decoding Select (Single Rail Mode Only)
0 = HDB3 (E1), B8ZS (T1)
1 = AMI Coding
R/W
0
D4
D3
RxRES1
RxRES0
Receive External Fixed Resistor
RxRES[1:0] are used to select the value for a high precision external resistor to improve return loss.
00 = None
01 = 240Ω
10 = 210Ω
11 = 150Ω
R/W
0
0
D2
INSBPV
Insert Bipolar Violation
When this bit transitions from a "0" to a "1", a bipolar violation will
be inserted in the transmitted data from TPOS, QRSS/PRBS pattern. The state of this bit will be sampled on the rising edge of
TCLK. To ensure proper operation, it is recommended to write a
"0" to this bit before writing a "1".
R/W
0
55
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
TABLE 27: MICROPROCESSOR REGISTER 0X03H BIT DESCRIPTION
CHANNEL 0-13 (0X03H-0XD3H)
Register
Type
Default
Value
(HW reset)
Insert Bit Error
When this bit transitions from a "0" to a "1", a bit error will be
inserted in the transmitted QRSS/PRBS pattern. The state of this
bit will be sampled on the rising edge of TCLK. To ensure proper
operation, it is recommended to write a "0" to this bit before writing
a "1".
R/W
0
This Bit is Reserved
R/W
0
Register
Type
Default
Value
(HW reset)
This Bit is Reserved
R/W
0
BIT
NAME
FUNCTION
D1
INSBER
D0
Reserved
TABLE 28: MICROPROCESSOR REGISTER 0X04H BIT DESCRIPTION
CHANNEL 0-13 (0X04H-0XD4H)
BIT
NAME
FUNCTION
D7
Reserved
D6
DMOIE
Digital Monitor Output Interrupt Enable
0 = Masks the DMO function
1 = Enables Interrupt Generation
R/W
0
D5
FLSIE
FIFO Limit Status Interrupt Enable
0 = Masks the FLS function
1 = Enables Interrupt Generation
R/W
0
D4
LCV_OFIE Line Code Violation / Counter Overflow Interrupt Enable
0 = Masks the LCV/OF function
1 = Enables Interrupt Generation
R/W
0
D3
Reserved
This Bit is Reserved
R/W
0
D2
AISDIE
Alarm Indication Signal Detection Interrupt Enable
0 = Masks the AIS function
1 = Enables Interrupt Generation
R/W
0
D1
RLOSIE
Receiver Loss of Signal Interrupt Enable
0 = Masks the RLOS function
1 = Enables Interrupt Generation
R/W
0
D0
QRPDIE
Quasi Random Pattern Detect Interrupt Enable
0 = Masks the QRPD function
1 = Enables Interrupt Generation
R/W
0
56
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
NOTE: The GIE bit in the global register 0xE0h must be set to "1" in addition to the individual register bits to enable the
interrupt pin.
TABLE 29: MICROPROCESSOR REGISTER 0X05H BIT DESCRIPTION
CHANNEL 0-13 (0X05H-0XD5H)
Register
Type
Default
Value
(HW reset)
This Bit is Reserved
RO
0
DMO
Digital Monitor Output
The digital monitor output is always active regardless if the interrupt generation is disabled. This bit indicates the DMO activity. An
interrupt will not occur unless the DMOIE is set to "1" in the channel register 0x04h and GIE is set to "1" in the global register
0xE0h.
0 = No Alarm
1 = Transmit output driver has failures
RO
0
D5
FLS
FIFO Limit Status
The FIFO limit status is always active regardless if the interrupt
generation is disabled. This bit indicates whether the RD/WR
pointers are within 3-Bits. An interrupt will not occur unless the
FLSIE is set to "1" in the channel register 0x04h and GIE is set to
"1" in the global register 0xE0h.
0 = No Alarm
1 = RD/WR FIFO pointers are within ±3-Bits
RO
0
D4
LCV_OF
Line Code Violation / Counter Overflow
This bit serves a dual purpose. By default, this bit monitors the line
code violation activity. However, if bit 7 in register 0xE5h is set to a
"1", this bit monitors the overflow status of the internal LCV
counter. An interrupt will not occur unless the LCV_OFIE is set to
"1" in the channel register 0x04h and GIE is set to "1" in the global
register 0xE0h.
0 = No Alarm
1 = A line code violation, bipolar violation, or excessive zeros has
occurred
RO
0
D3
Reserved
This Bit is Reserved
RO
0
D2
AISD
Alarm Indication Signal Detection
The alarm indication signal detection is always active regardless if
the interrupt generation is disabled. This bit indicates the AIS
activity. An interrupt will not occur unless the AISIE is set to "1" in
the channel register 0x04h and GIE is set to "1" in the global register 0xE0h.
0 = No Alarm
1 = An all ones signal is detected
RO
0
BIT
NAME
D7
Reserved
D6
FUNCTION
57
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
NOTE: The GIE bit in the global register 0xE0h must be set to "1" in addition to the individual register bits to enable the
interrupt pin.
TABLE 29: MICROPROCESSOR REGISTER 0X05H BIT DESCRIPTION
CHANNEL 0-13 (0X05H-0XD5H)
Register
Type
Default
Value
(HW reset)
Receiver Loss of Signal
The receiver loss of signal detection is always active regardless if
the interrupt generation is disabled. This bit indicates the RLOS
activity. An interrupt will not occur unless the RLOSIE is set to "1"
in the channel register 0x04h and GIE is set to "1" in the global
register 0xE0h.
0 = No Alarm
1 = An RLOS condition is present
RO
0
Quasi Random Pattern Detection
The quasi random pattern detection is always active regardless if
the interrupt generation is disabled. This bit indicates that a QRPD
has been detected. An interrupt will not occur unless the QRPDIE
is set to "1" in the channel register 0x04h and GIE is set to "1" in
the global register 0xE0h.
0 = No Alarm
1 = A QRP is detected
RO
0
Register
Type
Default
Value
(HW reset)
This Bit is Reserved
RUR
0
BIT
NAME
FUNCTION
D1
RLOS
D0
QRPD
TABLE 30: MICROPROCESSOR REGISTER 0X06H BIT DESCRIPTION
CHANNEL 0-13 (0X06H-0XD6H)
BIT
NAME
FUNCTION
D7
Reserved
D6
DMOIS
Digital Monitor Output Interrupt Status
0 = No change
1 = Change in status occurred
RUR
0
D5
FLSIS
FIFO Limit Interrupt Status
0 = No change
1 = Change in status occurred
RUR
0
D4
LCV_OFIS Line Code Violation / Overflow Interrupt Status
0 = No change
1 = Change in status occurred
RUR
0
D3
Reserved
This Bit is Reserved
RUR
0
D2
AISDIS
Alarm Indication Signal Detection Interrupt Status
0 = No change
1 = Change in status occurred
RUR
0
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TABLE 30: MICROPROCESSOR REGISTER 0X06H BIT DESCRIPTION
CHANNEL 0-13 (0X06H-0XD6H)
BIT
NAME
D1
RLOSIS
D0
QRPDIS
Register
Type
Default
Value
(HW reset)
Receiver Loss of Signal Interrupt Status
0 = No change
1 = Change in status occurred
RUR
0
Quasi Random Pattern Detection Interrupt Status
0 = No change
1 = Change in status occurred
RUR
0
FUNCTION
NOTE: Any change in status will generate an interrupt (if enabled in channel register 0x04h and GIE is set to "1" in the
global register 0xE0h). The status registers are reset upon read (RUR).
TABLE 31: MICROPROCESSOR REGISTER 0X07H BIT DESCRIPTION
CHANNEL 0-13 (0X07H-0XD7H)
BIT
NAME
D[7:0]
Reserved
FUNCTION
These Bits are Reserved
Register
Type
Default
Value
(HW reset)
RO
0
Register
Type
Default
Value
(HW reset)
X
0
R/W
0
0
0
0
0
0
0
TABLE 32: MICROPROCESSOR REGISTER 0X08H BIT DESCRIPTION
CHANNEL 0-13 (0X08H-0XD8H)
BIT
NAME
D7
Reserved
D6
D5
D4
D3
D2
D1
D0
1SEG6
1SEG5
1SEG4
1SEG3
1SEG2
1SEG1
1SEG0
FUNCTION
This Register Bit is Not Used
Arbitrary Pulse Generation
The transmit output pulse is divided into 8 individual segments.
This register is used to program the first segment which corresponds to the overshoot of the pulse amplitude. There are four
segments for the top portion of the pulse and four segments for the
bottom portion of the pulse. Segment number 5 corresponds to
the undershoot of the pulse. The MSB of each segment is the sign
bit.
Bit 6 = 0 = Negative Direction
Bit 6 = 1 = Positive Direction
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TABLE 33: MICROPROCESSOR REGISTER 0X09H BIT DESCRIPTION
CHANNEL 0-13 (0X09H-0XD9H)
BIT
NAME
FUNCTION
D7
Reserved
This Register Bit is Not Used
D[6:0]
2SEG[6:0]
Segment Number Two, Same Description as Register 0x08h
Register
Type
Default
Value
(HW reset)
X
0
R/W
TABLE 34: MICROPROCESSOR REGISTER 0X0AH BIT DESCRIPTION
CHANNEL 0-13 (0X0AH-0XDAH)
BIT
NAME
FUNCTION
D7
Reserved
This Register Bit is Not Used
D[6:0]
3SEG[6:0]
Segment Number Three, Same Description as Register 0x08h
Register
Type
Default
Value
(HW reset)
X
0
R/W
TABLE 35: MICROPROCESSOR REGISTER 0X0BH BIT DESCRIPTION
CHANNEL 0-13 (0X0BH-0XDBH)
BIT
NAME
FUNCTION
D7
Reserved
This Register Bit is Not Used
D[6:0]
4SEG[6:0]
Segment Number Four, Same Description as Register 0x08h
Register
Type
Default
Value
(HW reset)
X
0
R/W
TABLE 36: MICROPROCESSOR REGISTER 0X0CH BIT DESCRIPTION
CHANNEL 0-13 (0X0CH-0XDCH)
BIT
NAME
FUNCTION
D7
Reserved
This Register Bit is Not Used
D[6:0]
5SEG[6:0]
Segment Number Five, Same Description as Register 0x08h
60
Register
Type
Default
Value
(HW reset)
X
0
R/W
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REV. 1.0.1
TABLE 37: MICROPROCESSOR REGISTER 0X0DH BIT DESCRIPTION
CHANNEL 0-13 (0X0DH-0XDDH)
BIT
NAME
FUNCTION
D7
Reserved
This Register Bit is Not Used
D[6:0]
6SEG[6:0]
Segment Number Six, Same Description as Register 0x08h
Register
Type
Default
Value
(HW reset)
X
0
R/W
TABLE 38: MICROPROCESSOR REGISTER 0X0EH BIT DESCRIPTION
CHANNEL 0-13 (0X0EH-0XDEH)
BIT
NAME
FUNCTION
D7
Reserved
This Register Bit is Not Used
D[6:0]
7SEG[6:0]
Segment Number Seven, Same Description as Register 0x08h
Register
Type
Default
Value
(HW reset)
X
0
R/W
TABLE 39: MICROPROCESSOR REGISTER 0X0FH BIT DESCRIPTION
CHANNEL 0-13 (0X0FH-0XDFH)
BIT
NAME
FUNCTION
D7
Reserved
This Register Bit is Not Used
D[6:0]
8SEG[6:0]
Segment Number Eight, Same Description as Register 0x08h
Register
Type
Default
Value
(HW reset)
X
0
R/W
TABLE 40: MICROPROCESSOR REGISTER 0XE0H BIT DESCRIPTION
GLOBAL REGISTER (0XE0H)
Register
Type
Default
Value
(HW reset)
Single Rail/Dual Rail Mode
This bit sets the LIU to receive and transmit digital data in a single
rail or a dual rail format.
0 = Dual Rail Mode
1 = Single Rail Mode
R/W
0
Automatic Transmit All Ones
If ATAOS is selected, an all ones pattern will be transmitted on any
channel that experiences an RLOS condition. If an RLOS condition does not occur, TAOS will remain inactive.
0 = Disabled
1 = Enabled
R/W
0
BIT
NAME
FUNCTION
D7
SR/DR
D6
ATAOS
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TABLE 40: MICROPROCESSOR REGISTER 0XE0H BIT DESCRIPTION
GLOBAL REGISTER (0XE0H)
Register
Type
Default
Value
(HW reset)
Receive Clock Data
0 = RPOS/RNEG data is updated on the rising edge of RCLK
1 = RPOS/RNEG data is updated on the falling edge of RCLK
R/W
0
TCLKE
Transmit Clock Data
0 = TPOS/TNEG data is sampled on the falling edge of TCLK
1 = TPOS/TNEG data is sampled on the rising edge of TCLK
R/W
0
D3
DATAP
Data Polarity
0 = Transmit input and receive output data is active "High"
1 = Transmit input and receive output data is active "Low"
R/W
0
D2
Reserved
This Register Bit is Not Used
R/W
0
D1
GIE
Global Interrupt Enable
The global interrupt enable is used to enable/disable all interrupt
activity for all 14 channels. This bit must be set "High" for the interrupt pin to operate.
0 = Disable all interrupt generation
1 = Enable interrupt generation to the individual channel registers
R/W
0
D0
SRESET
Software Reset
Writing a "1" to this bit for more than 10µS initiates a device reset
for all internal circuits except the microprocessor register bits. To
reset the registers to their default setting, use the Hardware Reset
pin (See the pin description for more details).
R/W
0
Register
Type
Default
Value
(HW reset)
BIT
NAME
D5
RCLKE
D4
FUNCTION
TABLE 41: MICROPROCESSOR REGISTER 0XE1H BIT DESCRIPTION
GLOBAL REGISTER (0XE1H)
BIT
NAME
FUNCTION
D7 - D3
Reserved
These Register Bits are Not Used
R/W
0
D2
RxMUTE
Receiver Output Mute Enable
If RxMUTE is selected, RPOS/RNEG will be pulled "Low" for any
channel that experiences an RLOS condition. If an RLOS condition does not occur, RxMUTE will remain inactive.
0 = Disabled
1 = Enabled
R/W
0
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TABLE 41: MICROPROCESSOR REGISTER 0XE1H BIT DESCRIPTION
GLOBAL REGISTER (0XE1H)
Register
Type
Default
Value
(HW reset)
Extended Loss of Zeros
The number of zeros required to declare a Digital Loss of Signal is
extended to 4,096.
0 = Normal Operation
1 = Enables the EXLOS function
R/W
0
In Circuit Testing
0 = Normal Operation
1 = Sets all output pins to "High" impedance for in circuit testing
R/W
0
Register
Type
Default
Value
(HW reset)
BIT
NAME
FUNCTION
D1
EXLOS
D0
ICT
TABLE 42: MICROPROCESSOR REGISTER 0XE2H BIT DESCRIPTION
GLOBAL REGISTER (0XE2H)
BIT
NAME
FUNCTION
D7
Reserved
This Register Bit is Not Used
R/W
0
D6
RxTCNTL
Receive Termination Select Control
This bit sets the LIU to control the RxTSEL function with either the
individual channel register bit or the global hardware pin.
0 = Control of the receive termination is set to the register bits
1 = Control of the receive termination is set to the hardware pin
R/W
0
D[5:0]
Reserved
These Bits are Reserved
R/W
0
Register
Type
Default
Value
(HW reset)
These Register Bits are Not Used
R/W
0
Slicer Level Select
00 = 60%
01 = 65%
10 = 70%
11 = 55%
R/W
0
0
These Register Bits are Not Used
R/W
0
TABLE 43: MICROPROCESSOR REGISTER 0XE3H BIT DESCRIPTION
GLOBAL REGISTER (0XE3H)
BIT
NAME
D[7:4]
Reserved
D3
D2
SL<1>
SL<0>
D[7:0]
Reserved
FUNCTION
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TABLE 44: MICROPROCESSOR REGISTER 0XE4H BIT DESCRIPTION
GLOBAL REGISTER (0XE4H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
D6
MCLKT1out1 MCLKT1Nout Select
MCLKT1out0 MclkT1out[1:0] is used to program the MCLKT1out pin. By default,
the output clock is 1.544MHz.
00 = 1.544MHz
01 = 3.088MHz
10 = 6.176MHz
11 = 12.352MHz
R/W
0
0
D5
D4
MCLKE1out1 MCLKE1Nout Select
MCLKE1out0 MclkE1out[1:0] is used to program the MCLKE1Nout pin.
default, the output clock is 2.048MHz.
00 = 2.048MHz
01 = 4.096MHz
10 = 8.192MHz
11 = 16.384MHz
R/W
0
0
R/W
0
Register
Type
Default
Value
(HW reset)
R/W
0
R/W
0
R/W
0
D[3:0]
Reserved
By
These Register Bits are Not Used
TABLE 45: MICROPROCESSOR REGISTER 0XE5H BIT DESCRIPTION
GLOBAL REGISTER (0XE5H)
BIT
D7
NAME
FUNCTION
LCV_OFLW Line Code Violation / Counter Overflow Monitor Select
This bit is used to select the monitoring activity between the LCV
and the counter overflow status. When the 16-bit LCV counter saturates, the counter overflow condition is activated. By default, the
LCV activity is monitored by bit D4 in register 0x05h.
0 = Monitoring LCV
1 = Monitoring the counter overflow status
D6
Reserved
D5
Reserved
This Register Bit is Not Used
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TABLE 45: MICROPROCESSOR REGISTER 0XE5H BIT DESCRIPTION
GLOBAL REGISTER (0XE5H)
Register
Type
Default
Value
(HW reset)
This Register Bit is Not Used
R/W
0
Line Code Violation Counter Select
These bits are used to select which channel is to be addressed for
reading the contents in register 0xE8h. It is also used to address
the counter for a given channel when performing an update or
reset on a per channel basis. By default, Channel 0 is selected.
0000, 1111 = None
0001 = Channel 0
0010 = Channel 1
0011 = Channel 2
0100 = Channel 3
0101 = Channel 4
0110 = Channel 5
0111 = Channel 6
1000 = Channel 7
1001 = Channel 8
1010 = Channel 9
1011 = Channel 10
1100 = Channel 11
1101 = Channel 12
1110 = Channel 13
R/W
0
0
0
0
Register
Type
Default
Value
(HW reset)
These Register Bits are Not Used
R/W
0
LCV Counter Reset for All Channels
This bit is used to reset all internal LCV counters to their default
state 0000h. This bit must be set to "1" for 1µS.
0 = Normal Operation
1 = Resets all Counters
R/W
0
allUPDATE LCV Counter Update for All Channels
This bit is used to latch the contents of all 14 counters into holding
registers so that the value of each counter can be read. The channel is addressed by using bits D[3:0] in register 0xE5h.
0 = Normal Operation
1 = Updates all Counters
R/W
0
BIT
NAME
D4
Reserved
D3
D2
D1
D0
LCVCH3
LCVCH2
LCVCH1
LCVCH0
FUNCTION
TABLE 46: MICROPROCESSOR REGISTER 0XE6H BIT DESCRIPTION
GLOBAL REGISTER (0XE6H)
BIT
NAME
D[7:5]
Reserved
D4
allRST
D3
FUNCTION
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TABLE 46: MICROPROCESSOR REGISTER 0XE6H BIT DESCRIPTION
GLOBAL REGISTER (0XE6H)
Register
Type
Default
Value
(HW reset)
LCV Counter Byte Select
This bit is used to select the MSB or LSB for Reading the contents
of the LCV counter for a given channel. The channel is addressed
by using bits D[3:0] in register 0xE5h. By default, the LSB byte is
selected.
0 = Low Byte
1 = High Byte
R/W
0
chUPDATE LCV Counter Update Per Channel
This bit is used to latch the contents of the counter for a given
channel into a holding register so that the value of the counter can
be read. The channel is addressed by using bits D[3:0] in register
0xE5h.
0 = Normal Operation
1 = Updates the Selected Channel
R/W
0
R/W
0
Register
Type
Default
Value
(HW reset)
R/W
0
BIT
NAME
FUNCTION
D2
BYTEsel
D1
D0
ChRST
LCV Counter Reset Per Channel
This bit is used to reset the LCV counter of a given channel to its
default state 0000h. The channel is addressed by using bits D[3:0]
in register 0xE5h. This bit must be set to "1" for 1µS.
0 = Normal Operation
1 = Resets the Selected Channel
n
TABLE 47: MICROPROCESSOR REGISTER 0XE7H BIT DESCRIPTIO
GLOBAL REGISTER (0XE7H)
BIT
NAME
D[7:0]
Reserved
FUNCTION
These Register Bits are Not Used
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TABLE 48: MICROPROCESSOR REGISTER 0XE8H BIT DESCRIPTION
GLOBAL REGISTER (0XE8H)
BIT
NAME
D7
D6
D5
D4
D3
D2
D1
D0
LCVCNT7
LCVCNT6
LCVCNT5
LCVCNT4
LCVCNT3
LCVCNT2
LCVCNT1
LCVCNT0
FUNCTION
Line Code Violation Byte Contents
These bits contain the LCV counter contents of the Byte selected
by bit D2 in register 0xE6h for a given channel. The channel is
addressed by using bits D[3:0] in register 0xE5h. By default, the
contents contain the LSB, however no channel is selected..
Register
Type
Default
Value
(HW reset)
R/W
0
0
0
0
0
0
0
0
CLOCK SELECT REGISTER
The input clock source is used to generate all the necessary clock references internally to the LIU. The
microprocessor timing is derived from a PLL output which is chosen by programming the Clock Select Bits in
register 0xE9h. Therefore, if the clock selection bits are being programmed, the frequency of the PLL output
will be adjusted accordingly. During this adjustment, it is important to "Not" write to any other bit location within
the same register while selecting the input/output clock frequency. For best results, register 0xE9h can be
broken down into two sub-registers with the MSB being bit D4 and the LSB being bits D[3:0] as shown in
Figure 36.
NOTE: Bits D[7:5] are reserved.
FIGURE 36. REGISTER 0XE9H SUB REGISTERS
MSB
D7
D6
Reserved,
D5
LSB
D4
D3
TCLKCNTL
D2
D1
D0
Clock Selection Bits
Programming Examples:
Example 1: Changing bits D[7:4]
If bit D4 is the only values within the register that will change in a WRITE process, the microprocessor only
needs to initiate ONE write operation.
Example 2: Changing bits D[3:0]
If bits D[3:0] are the only values within the register that will change in a WRITE process, the microprocessor
only needs to initiate ONE write operation.
Example 3: Changing bits within the MSB and LSB
In this scenario, one must initiate TWO write operations such that the MSB and LSB do not change within ONE
write cycle. It is recommended that the MSB and LSB be treated as two independent sub-registers. One can
either change the clock selection bits D[3:0] (LSB) and then change bit D4 (MSB) on the SECOND write, or
vice-versa. No order or sequence is necessary.
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TABLE 49: MICROPROCESSOR REGISTER 0XE9H BIT DESCRIPTION
GLOBAL REGISTER (0XE9H)
Register
Type
Default
Value
(HW reset)
These Register Bits are Not Used
R/W
0
TCLKCNL
Transmit Clock Control
When this bit is pulled "High" and there is no TCLK signal present
on the transmit input path, TTIP/TRING will Transmit All "Ones"
(TAOS). By default, TTIP/TRING will Transmit All Zeros.
0 = All Zeros
1 = All Ones
R/W
0
CLKSEL3
CLKSEL2
CLKSEL1
CLKSEL0
Clock Input Select
CLKSEL[3:0] is used to select the input clock source used as the
internal timing reference.
0000 = 2.048 MHz
0001 = 1.544 MHz
1000 = 4.096 Mhz
1001 = 3.088 Mhz
1010 = 8.192 Mhz
1011 = 6.176 Mhz
1100 = 16.384 Mhz
1101 = 12.352 Mhz
1110 = 2.048 Mhz
1111 = 1.544 Mhz
R/W
0
0
0
0
Register
Type
Default
Value
(HW reset)
BIT
NAME
D7 - D5
Reserved
D4
D3
D2
D1
D0
FUNCTION
TABLE 50: MICROPROCESSOR REGISTER 0XEAH BIT DESCRIPTION
GLOBAL REGISTER (0XEAH)
BIT
NAME
FUNCTION
D7
GCHIS7
Global Channel Interrupt Status for Channel 7
0 = No interrupt activity from channel 7
1 = Interrupt was generated from channel 7
RUR
0
D6
GCHIS6
Global Channel Interrupt Status for Channel 6
0 = No interrupt activity from channel 6
1 = Interrupt was generated from channel 6
RUR
0
D5
GCHIS5
Global Channel Interrupt Status for Channel 5
0 = No interrupt activity from channel 5
1 = Interrupt was generated from channel 5
RUR
0
D4
GCHIS4
Global Channel Interrupt Status for Channel 4
0 = No interrupt activity from channel 4
1 = Interrupt was generated from channel 4
RUR
0
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TABLE 50: MICROPROCESSOR REGISTER 0XEAH BIT DESCRIPTION
GLOBAL REGISTER (0XEAH)
Register
Type
Default
Value
(HW reset)
Global Channel Interrupt Status for Channel 3
0 = No interrupt activity from channel 3
1 = Interrupt was generated from channel 3
RUR
0
GCHIS2
Global Channel Interrupt Status for Channel 2
0 = No interrupt activity from channel 2
1 = Interrupt was generated from channel 2
RUR
0
D1
GCHIS1
Global Channel Interrupt Status for Channel 1
0 = No interrupt activity from channel 1
1 = Interrupt was generated from channel 1
RUR
0
D0
GCHIS0
Global Channel Interrupt Status for Channel 0
0 = No interrupt activity from channel 0
1 = Interrupt was generated from channel 0
RUR
0
Register
Type
Default
Value
(HW reset)
BIT
NAME
D3
GCHIS3
D2
FUNCTION
TABLE 51: MICROPROCESSOR REGISTER 0XEBH BIT DESCRIPTION
GLOBAL REGISTER (0XEBH)
BIT
NAME
FUNCTION
D7
Reserved
This Register Bit is Not Used
RUR
0
D6
Reserved
This Register Bit is Not Used
RUR
0
D5
GCHIS13
Global Channel Interrupt Status for Channel 13
0 = No interrupt activity from channel 13
1 = Interrupt was generated from channel 13
RUR
0
D4
GCHIS12
Global Channel Interrupt Status for Channel 12
0 = No interrupt activity from channel 12
1 = Interrupt was generated from channel 12
RUR
0
D3
GCHIS11
Global Channel Interrupt Status for Channel 11
0 = No interrupt activity from channel 11
1 = Interrupt was generated from channel 11
RUR
0
D2
GCHIS10
Global Channel Interrupt Status for Channel 10
0 = No interrupt activity from channel 10
1 = Interrupt was generated from channel 10
RUR
0
D1
GCHIS9
Global Channel Interrupt Status for Channel 9
0 = No interrupt activity from channel 9
1 = Interrupt was generated from channel 9
RUR
0
D0
GCHIS8
Global Channel Interrupt Status for Channel 8
0 = No interrupt activity from channel 8
1 = Interrupt was generated from channel 8
RUR
0
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TABLE 52: RECOVERED CLOCK SELECT
RECOVERED CLOCK SELECT REGISTER (0XEEH)
BIT
NAME
FUNCTION
D[7:4]
Reserved
D[3:0]
RCLKOUT Recovered Clock Select
These register bits are used to select the recovered clock from one
of the RCLK[13:0] lines and output it on the RCLKOUT pin.
Recovered Clock
Select[3:0]
Selected RCLK
0000, 1111
No RCLK Selected
0001
RCLK 0
0010
RCLK 1
0011
RCLK 2
0100
RCLK 3
0101
RCLK 4
0110
RCLK 5
0111
RCLK 6
1000
RCLK 7
1001
RCLK 8
1010
RCLK 9
1011
RCLK 10
1100
RCLK 11
1101
RCLK 12
1110
RCLK 13
70
Register
Type
Default
Value
(HW reset)
R/W
0
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REV. 1.0.1
TABLE 53: E1 ARBITRARY SELECT
E1 ARBITRARY SELECT REGISTER (0XF4H)
BIT
NAME
D[7:1]
Reserved
D0
E1Arben
FUNCTION
E1 Arbitrary Pulse Enable
This bit is used to enable the Arbitrary Pulse Generators for shaping the transmit pulse shape when E1 mode is selected. If this bit
is set to "1", all 14 channels will be configured for the Arbitrary
Mode. However, each channel is individually controlled by programming the channel registers 0xn8 through 0xnF, where n is the
number of the channel.
"0" = Disabled (Normal E1 Pulse Shape ITU G.703)
"1" = Arbitrary Pulse Enabled
Register
Type
Default
Value
(HW reset)
R/W
0
Register
Type
Default
Value
(HW reset)
RO
1
1
1
1
0
0
1
0
Register
Type
Default
Value
(HW reset)
RO
0
0
0
0
0
0
0
1
TABLE 54: MICROPROCESSOR REGISTER 0XFEH BIT DESCRIPTION
DEVICE "ID" REGISTER (0XFEH)
BIT
D7
D6
D5
D4
D3
D2
D1
D0
NAME
FUNCTION
Device "ID" The device "ID" of the XRT83VSH314 short haul LIU is 0xF2h.
Along with the revision "ID", the device "ID" is used to enable software to identify the silicon adding flexibility for system control and
debug.
TABLE 55: MICROPROCESSOR REGISTER 0XFFH BIT DESCRIPTION
REVISION "ID" REGISTER (0XFFH)
BIT
NAME
FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
Revision
"ID"
The revision "ID" of the XRT83VSH314 LIU is used to enable software to identify which revision of silicon is currently being tested.
The revision "ID" for the first revision of silicon will be 0x01h.
NOTE: The value contained in this register is subject to change
when a newer revision of the silicon has been issued.
71
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
8.0 ELECTRICAL CHARACTERISTICS
TABLE 56: ABSOLUTE MAXIMUM RATINGS
Storage Temperature
-65°C to +150°C
Operating Temperature
-40°C to +85°C
Supply Voltage
-0.5V to +3.8V
Vin
-0.5V to +5.5V
TABLE 57: DC DIGITAL INPUT AND OUTPUT ELECTRICAL CHARACTERISTICS
VDD=3.3V ±5%, TA=25°C, UNLESS OTHERWISE SPECIFIED
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
VDD
3.13
3.3
3.46
V
Input High Voltage
VIH
2.0
-
5.0
V
Input Low Voltage
VIL
-0.5
-
0.8
V
Output High Voltage IOH=-2.0mA
VOH
2.4
-
Output Low Voltage IOL=2.0mA
VOL
-
-
0.4
V
Input Leakage Current
IL
-
-
±10
µA
Input Capacitance
CI
-
5.0
Output Lead Capacitance
CL
-
-
Power Supply Voltage
V
pF
25
pF
NOTE: Input leakage current excludes pins that are internally pulled "Low" or "High"
TABLE 58: AC ELECTRICAL CHARACTERISTICS
VDD=3.3V ±5%, TA=25°C, UNLESS OTHERWISE SPECIFIED
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
MCLKin Clock Duty Cycle
40
-
60
%
MCLKin Clock Tolerance
-
±50
-
ppm
72
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
TABLE 59: POWER CONSUMPTION
VDD=3.3V ±5%, TA=25°C, INTERNAL IMPEDANCE, UNLESS OTHERWISE SPECIFIED
MODE
SUPPLY
VOLTAGE
IMPEDANCE
RECEIVER
TRANSMITTER
TYP
E1
3.3V
75Ω
1:1
1:2
2.145
1.551
W
100% ones
50% ones
E1
3.3V
120Ω
1:1
1:2
1.881
1.419
W
100% ones
50% ones
T1
3.3V
100Ω
1:1
1:2
2.937
1.881
W
100% ones
50% ones
MAX
UNIT
TEST
CONDITION
NOTE: The typical power consumption of the 1.8V supply represents ~ 72mW of the above listed.
TABLE 60: E1 RECEIVER ELECTRICAL CHARACTERISTICS
(VDD=3.3V±5%, TA=25°C UNLESS OTHERWISE SPECIFIED)
PARAMETER
MIN
TYP.
MAX
UNIT
TEST CONDITIONS
Number of consecutive
zeros before LOS is set
-
32
-
bit
Input signal level at LOS
13
16
-
dB
RLOS Clear
12.5
-
-
% ones
Receiver Sensitivity
Cable + Flat Loss
6+6
-
-
dB
With nominal pulse amplitude of 3.0V for
120Ω and 2.37V for 75Ω application.
Interference Margin
-18
-14
-
dB
With 6dB cable loss
Input Impedance
15
-
KΩ
Jitter Tolerance:
1 Hz
10KHz---100KHz
37
0.3
-
-
UIpp
UIpp
-
20
36
0.5
KHz
dB
-
10
1.5
-
Hz
Hz
12
8
8
-
-
dB
dB
dB
Receiver loss of signal:
Recovered Clock Jitter
Transfer Corner Frequency
Peaking Amplitude
Jitter Attenuator Corner
Frequency(-3dB curve)
JABW=0
JSBW=1
Return Loss:
51KHz --- 102KHz
102KHz --- 2048KHz
2048KHz --- 3072KHz
Cable attenuation @1024KHz
ITU-G.775, ETS1 300 233
ITU G.823
ITU G.736
ITU G.736
73
ITU G.703
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
TABLE 61: T1 RECEIVER ELECTRICAL CHARACTERISTICS
VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5%, TA=25°C, unless otherwise specified
PARAMETER
MIN.
TYP.
MAX.
UNIT
TEST CONDITIONS
Receiver loss of signal:
Number of consecutive zeros before
RLOS is set
Input signal level at RLOS
175
13
16
-
dB
RLOS Clear
12.5
-
-
% ones
Receiver Sensitivity
Cable + Flat Loss
6+6
-
-
Interference Margin
-18
-14
Input Impedance
15
Jitter Tolerance:
1Hz
10kHz - 100kHz
Recovered Clock Jitter
Transfer Corner Frequency
Peaking Amplitude
Jitter Attenuator Corner Frequency
(-3dB curve)
Return Loss:
51kHz - 102kHz
102kHz - 2048kHz
2048kHz - 3072kHz
Cable attenuation @772kHz
ITU-G.775, ETSI 300 233
dB
With nominal pulse amplitude of 3.0V
for 100Ω termination
-
dB
With 6db of cable loss
-
-
kW
138
0.4
-
-
UIpp
AT&T Pub 62411
-
10
0.1
KHz
dB
TR-TSY-000499
-
3
Hz
AT&T Pub 62411
14
20
16
-
-
dB
dB
dB
TABLE 62: E1 TRANSMITTER ELECTRICAL CHARACTERISTICS
VDD=3.3V ±5%, TA=25°C, UNLESS OTHERWISE SPECIFIED
PARAMETER
MIN
TYP
MAX
UNIT
AMI Output Pulse Amplitude
75Ω
120Ω
2.13
2.70
2.37
3.00
2.60
3.30
V
V
Output Pulse Width
224
244
264
ns
Output Pulse Width Ratio
0.95
-
1.05
ITU-G.703
Output Pulse Amplitude Ratio
0.95
-
1.05
ITU-G.703
74
TEST CONDITION
1:2 Transformer
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
TABLE 62: E1 TRANSMITTER ELECTRICAL CHARACTERISTICS
VDD=3.3V ±5%, TA=25°C, UNLESS OTHERWISE SPECIFIED
PARAMETER
MIN
TYP
MAX
UNIT
TEST CONDITION
Jitter Added by the Transmitter
Output
-
0.025
0.05
UIp-p
Broad Band with jitter free TCLK
applied to the input.
15
9
8
-
-
dB
dB
dB
Output Return Loss
51kHz - 102kHz
102kHz - 2048kHz
2048kHz - 3072kHz
ETSI 300 166
TABLE 63: T1 TRANSMITTER ELECTRICAL CHARACTERISTICS
VDD=3.3V ±5%, TA=25°C, UNLESS OTHERWISE SPECIFIED
PARAMETER
MIN
TYP
MAX
UNIT
AMI Output Pulse Amplitude
2.4
3.0
3.6
V
1:2 Transformer measured at
DSX-1
Output Pulse Width
338
350
362
ns
ANSI T1.102
Output Pulse Width Imbalance
-
-
20
Output Pulse Amplitude Imbalance
-
-
±200
mV
Jitter Added by the Transmitter
Output
-
0.025
0.05
UIp-p
17
12
10
-
-
dB
dB
dB
Output Return Loss
51kHz - 102kHz
102kHz - 2048kHz
2048kHz - 3072kHz
75
TEST CONDITION
ANSI T1.102
ANSI T1.102
Broad Band with jitter free TCLK
applied to the input.
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
ORDERING INFORMATION
PRODUCT NUMBER
PACKAGE
OPERATING TEMPERATURE RANGE
XRT83VSH314IB
304 LEAD PBGA
-400C to +850C
PACKAGE DIMENSIONS (BOTTOM VIEW)
304 Ball Plastic Ball Grid Array
(31.0 mm x 31.0 mm, 1.27mm pitch PBGA)
Rev. 1.00
22
23
20
21
18
19
16
17
14
15
12
13
10
11
8
9
6
7
4
5
A1
Feature/Mark
2
3
1
A
B
C
D
E
F
G
H
J
K
L
D
D1
M
N
P
R
T
U
V
W
Y
AA
AB
AC
D1
D
(A1 corner feature is mfger option)
SEATING PLANE
e
A1
A
A2
b
Note: The control dimension is in millimeter.
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.051
0.098
1.30
2.50
A1
0.014
0.028
0.35
0.70
A2
0.010
0.024
0.25
0.60
D
1.213
1.228
30.80
31.20
D1
b
e
1.100 BSC
0.024
0.035
0.050 BSC
76
27.94 BSC
0.60
0.90
1.27 BSC
XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
REVISION HISTORY
REVISION #
DATE
DESCRIPTION
P1.0.0
06/22/04
First release of the 14-Channel LIU Preliminary Datasheet
P1.0.1
10/25/04
Made changes to the pin-out, pin descriptions (RCLKOUT, CMPOUT, PhDIN,
power pins swapped DVDD_PRE and DVDD_DRV, NC pins L4 and L21) and
register tables. Modfied table 3.
P1.0.2
12/08/04
Made corrections to pinout diagram.
P1.0.3
1/26/05
Various text edits. Corrected register information. Added pull-up/pull-down information for some pins.
P1.0.4
3/4/05
Various text edits in Register Descriptions.
P1.0.5
07/20/05
Changed definition of pins D21 and K21.Added description for ATP_TIP and
ATP_RING., section 3.6.3. Updated table 3, (receive terminations).
P1.0.6
07/27/05
Corrected Device ID; Corrected Register 0x00, bit 6 description.
P1.0.7
08/15/05
Corrected Motorola Synchronous Microprocessor Mode PCLK timing.
P1.0.8
01/19/06
Corrected electrical tables. Removed 83sh314s references. Various edits and corrections.
1.0.0
07/11/06
Corrected power consumption numbers. Removed reference to on chip frequency
multiplier. Release to production.
1.0.1
09/27/06
Edited QRSS/PRBS and INVQRSS definition in the register descriptions.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2006 EXAR Corporation
Datasheet September 2006.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
77