HANBit HSD8M64D8H Synchronous DRAM Module 64Mbyte (8Mx64bit), DIMM based on 8Mx8,4Banks, 4K Ref., 3.3V Part No. HSD8M64D8H GENERAL DESCRIPTION The HSD8M64D8H is a 8M x 64 bit Synchronous Dynamic RAM high density memory module. The module consists of eight CMOS 2M x 8 bit x 4banks Synchronous DRAMs in TSOP-II 400mil packages on a 168-pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The HSD8M64D8H is a DIMM(Dual in line Memory Module) and is intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible. FEATURES • Part Identification HSD8M64D8H-10 : 100MHz (CL=2) HSD8M64D8H-10L : 100MHz (CL=3) HSD8M64D8H-13 : 133MHz (CL=3) • Burst mode operation • Auto & self refresh capability (4096 Cycles/64ms) • LVTTL compatible inputs and outputs • Single 3.3V ±0.3V power supply • MRS cycle with address key programs - Latency (Access from column address) - Burst length (1, 2, 4, 8 & Full page) - Data scramble (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock • The used device is 2M x 8bit x 4Banks SDRAM URL:www.hbe.co.kr REV.1.0(August.2002) 1 HANBit Electronics Co.,Ltd. HANBit HSD8M64D8H PIN ASSIGNMENT PIN Symbol PIN Symbol PIN Symbol PIN Symbol PIN Symbol PIN Symbol 1 Vss 29 DQM1 57 DQ18 85 Vss 113 DQM5 141 DQ50 2 DQ0 30 /CS0 58 DQ19 86 DQ32 114 NC 142 DQ51 3 DQ1 31 NC 59 Vcc 87 DQ33 115 /RAS 143 Vcc 4 DQ2 32 Vss 60 DQ20 88 DQ34 116 Vss 144 DQ52 5 DQ3 33 A0 61 NC 89 DQ35 117 A1 145 NC 6 Vcc 34 A2 62 NC 90 Vcc 118 A3 146 NC 7 DQ4 35 A4 63 NC 91 DQ36 119 A5 147 NC 8 DQ5 36 A6 64 Vss 92 DQ37 120 A7 148 Vss 9 DQ6 37 A8 65 DQ21 93 DQ38 121 A9 149 DQ53 10 DQ7 38 A10 66 DQ22 94 DQ39 122 BA0 150 DQ54 11 DQ8 39 BA1 67 DQ23 95 DQ40 123 A11 151 DQ55 12 Vss 40 Vcc 68 Vss 96 Vss 124 Vcc 152 Vss 13 DQ9 41 Vcc 69 DQ24 97 DQ41 125 CLK1 153 DQ56 14 DQ10 42 CLK0 70 DQ25 98 DQ42 126 NC 154 DQ57 15 DQ11 43 Vss 71 DQ26 99 DQ43 127 Vss 155 DQ58 16 DQ12 44 NC 72 DQ27 100 DQ44 128 CKE0 156 DQ59 17 DQ13 45 /CS2 73 Vcc 101 DQ45 129 NC 157 Vcc 18 Vcc 46 DQM2 74 DQ28 102 Vcc 130 DQM6 158 DQ60 19 DQ14 47 DQM3 75 DQ29 103 DQ46 131 DQM7 159 DQ61 20 48 NC 76 DQ30 104 NC 160 DQ62 49 Vcc 77 DQ31 105 133 Vcc 161 DQ63 50 NC 78 Vss 106 134 NC 162 Vss 51 79 CLK2 107 DQ47 NC (CB4) NC (CB5) Vss 132 23 DQ15 NC (CB0) NC (CB1) Vss 135 163 CLK3 24 NC 52 80 NC 108 NC 136 164 NC 25 NC 53 81 WP 109 NC 137 165 SA0 21 22 26 Vcc 54 NC NC (CB2) NC (CB3) Vss 82 SDA 110 Vcc 138 NC NC (CB6) NC (CB7) Vss 166 SA1 27 /WE 55 DQ16 83 SCL 111 /CAS 139 DQ48 167 SA2 28 DQM0 56 DQ17 84 Vcc 112 DQM4 140 DQ49 168 Vcc URL:www.hbe.co.kr REV.1.0(August.2002) 2 HANBit Electronics Co.,Ltd. HANBit HSD8M64D8H FUNCTIONAL BLOCK DIAGRAM DQ0-63 CKE0 /CAS CKE CAS /RAS RAS /CS0 CE U1 WE A0-A11 CKE CAS U4 RAS /CS2 CE WE A0-A11 CKE CAS U6 RAS CE WE A0-A11 CKE CAS U8 RAS CE WE A0-A11 CKE CAS U2 RAS CE WE A0-A11 CKE CAS U5 RAS CE WE A0-A11 CKE CAS U7 RAS CE WE A0-A11 CKE CAS U9 RAS CE WE A0-A11 CLK DQ0-7 CLKA DQM0 DQM0 BA0-1 CLKB CLK DQ16-23 DQM2 DQM2 BA0-1 CLK DQ32-39 DQM4 DQM4 BA0-1 CLK DQ48-55 DQM6 DQM6 BA0-1 CLK DQ8-15 DQM1 DQM1 BA0-1 CLK DQ24-31 DQM3 DQM3 BA0-1 CLK DQ40-47 DQM5 DQM5 BA0-1 CLK DQ56-63 DQM7 DQM7 BA0-1 /WE A0 - A11 BA0-1 Vcc Two 0.1uF Capacitors per each SDRAM VSS URL:www.hbe.co.kr REV.1.0(August.2002) 3 HANBit Electronics Co.,Ltd. HANBit HSD8M64D8H PIN FUNCTION DESCRIPTION PIN NAME INPUTT FUNCTION CLK System clock Active on the positive going edge to sample all inputs. /CE Chip enable Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. A0 ~ A11 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA8 BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. /RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. /CAS /WE Column address Latches column addresses on the positive going edge of the CLK with CAS low. strobe Enables column access. Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQM0 ~ 7 Data input/output Makes data output Hi-Z, tSHZ after the clock and masks the output. mask Blocks data input when DQM active. (Byte masking) DQ0 ~ 63 Data input/output Data inputs/outputs are multiplexed on the same pins. VDD/VSS Power Power and ground for the input buffers and the core logic. supply/ground ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING VIN ,OUT -1V to 4.6V Voltage on Vcc Supply Relative to Vss Vcc -1V to 4.6V Power Dissipation PD 8W TSTG -55oC to 150oC Voltage on Any Pin Relative to Vss Storage Temperature Short Circuit Output Current IOS 50mA Notes: Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. URL:www.hbe.co.kr REV.1.0(August.2002) 4 HANBit Electronics Co.,Ltd. HANBit HSD8M64D8H DC OPERATING CONDITIONS (Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70° C) ) PARAMETER SYMBOL MIN TYP. MAX UNIT NOTE Supply Voltage Vcc 3.0 3.3 3.6 V Input High Voltage VIH 2.0 3.0 Vcc+0.3 V 1 Input Low Voltage VIL -0.3 0 0.8 V 2 Output High Voltage VOH 2.4 - - V IOH = -2mA Output Low Voltage VOL - - 0.4 V IOL = 2mA Input leakage current I LI -10 10 uA Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. 3 CAPACITANCE (VCC = 3.3V, TA = 23° C, f = 1MHz, VREF =1.4V ± 200 mV) DESCRIPTION SYMBOL MIN MAX UNITS CCLK 15 21 pF CIN 25 45 pF Address CADD 25 45 pF DQ (DQ0 ~ DQ7) COUT 9 12 pF Clock /RAS, /CAS,/WE,/CS, CKE, DQM DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70° C) TEST PARAMETER VERSION NOT SYMBOL UNIT CONDITION -13 -10 10L 600 560 560 E Burst length = 1 Operating current ICC1 (One bank active) tRC ≥ tRC(min) mA IO = 0mA Precharge standby ICC2P current in power-down mode ICC2PS CKE ≤ VIL(max) 8 mA 8 mA tCC=10ns CKE & CLK ≤ VIL(max) tCC=∞ CKE ≥ VIH(min) Precharge standby ICC2N CS* ≥ VIH(min), tCC=10ns current in one time during 20ns non power-down mode CKE ≥ VIH(min) ICC2NS 120 Input signals are changed CLK ≤ VIL(max), tCC=∞ mA 48 Input signals are stable URL:www.hbe.co.kr REV.1.0(August.2002) 5 HANBit Electronics Co.,Ltd. 1 HANBit HSD8M64D8H Active standby current in ICC3P CKE ≤ VIL(max), tCC=10ns 24 power-down mode ICC3PS CKE&CLK ≤ VIL(max),tCC=∞ 24 mA CKE≥VIH(min), Active standby current in CS*≥VIH(min), ICC3N tCC=10ns 200 Input signals are changed non power-down mode one time during 20ns (One bank active) CKE≥VIH(min) CLK ≤VIL(max), ICC3NS mA tCC=∞ 120 Input signals are stable IO = 0 mA Operating current Page burst ICC4 (Burst mode) 920 760 760 mA 1 1080 1000 1000 mA 2 4Banks Activated tCCD = 2CLKs Refresh current ICC5 Self refresh current ICC6 tRC ≥ tRC(min) CKE ≤ 0.2V 8 mA Notes: 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ). AC OPERATING TEST CONDITIONS (vcc = 3.3V ± 0.3V, TA = 0 to 70° C) PARAMETER Value UNIT 2.4/0.4 V 1.4 V tr/tf = 1/1 ns 1.4 V AC Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition See Fig. 2 +3.3V Vtt=1.4V 1200Ω 50Ω DOUT 870Ω DOUT 50pF* Z0=50Ω 50pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA (Fig. 2) AC output load circuit (Fig. 1) DC output load circuit URL:www.hbe.co.kr REV.1.0(August.2002) 6 HANBit Electronics Co.,Ltd. HANBit HSD8M64D8H OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) PARAMETER SYMBOL Row active to row active delay RAS to CAS delay Row precharge time tRRD(min) tRP(min) tRP(min) tRAS(min) tRAS(max) Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data VERSION -10 20 20 20 50 100 70 2 2 CLK + 20 ns 1 1 1 2 -13 15 20 20 45 tRC(min) tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3 65 CAS latency=2 - -10L 20 20 20 50 70 1 UNIT NOTE ns ns ns ns ns ns CLK CLK CLK CLK 1 1 1 1 ea 4 1 2 2 2 3 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. .5. For -8/H/L/10, tRDL=1CLK and tDAL=1CLK+20ns is also supported . ( recommend : tRDL=2CLK and tDAL=2CLK + 20ns.) AC CHARACTERISTICS (AC operating conditions unless otherwise noted) PARAMETER CAS latency=3 CAS latency=2 CLK to valid CAS output delay latency=3 CAS latency=2 Output data CAS hold time latency=3 CAS latency=2 CLK high pulse width SYMBOL CLK cycle time -13 MIN -10 MAX 7.5 tCC MIN MAX MIN 10 1000 - -10L MAX UNIT NOTE ns 1 ns 1,2 ns 2 10 1000 10 1000 12 5.4 6 6 - 6 7 tSAC 2.7 3 3 - 3 3 tOH tCH 2.5 3 3 ns 3 CLK low pulse width tCL 2.5 3 3 ns 3 Input setup time tSS 1.5 2 2 ns 3 Input hold time tSH 0.8 1 1 ns 3 CLK to output in Low-Z tSLZ 1 1 1 ns 3 2 CLK to output in Hi-Z CAS latency=3 CAS latency=2 5.4 6 6 ns - 6 7 ns tSHZ Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered ie., [(tr + tf)/2-1]ns should be added to the parameter. URL:www.hbe.co.kr REV.1.0(August.2002) 7 HANBit Electronics Co.,Ltd. HANBit HSD8M64D8H SIMPLIFIED TRUTH TABLE (V=Valid, X=Don't care, H=Logic high, L=Logic low) COMMAND Register Mode register set Auto refresh Entry Refresh Self refresh Exit Bank active & row addr. Auto Read & Auto address CK E n /C S /R A S /C A S /W E D Q M H X L L L L X OP code L L L H X X L H H H H X X X X X L L H H H H L L H H X X BA 0,1 V precharge disable column CK E n-1 precharge H X L H L H X Auto column address Auto H X L H L L X H Precharge Clock suspend or active power down Precharge power mode down X H X Entry H L Exit L H All banks Entry Exit 3 3 3 3 Column H (A0 ~ A8) L Address H L DQM H No operation command H 4,5 L H L L L L H H L L H X X X L V V V X X X X H X X X L H H H H X X X L V V V X X H L X H X H X H X X X 8 4 (A0 ~ A8) 4,5 X V L X H 6 X X X X X X V X X X Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) URL:www.hbe.co.kr REV.1.0(August.2002) 4 Address H enable Bank selection 1,2 L V precharge Burst Stop NOTE Column precharge disable A11 A9~A0 Row address V disable Write & A10 / AP HANBit Electronics Co.,Ltd. 7 HANBit HSD8M64D8H PACKAGING INFORMATION Unit : mm Front View Rear View URL:www.hbe.co.kr REV.1.0(August.2002) 9 HANBit Electronics Co.,Ltd. HANBit HSD8M64D8H ORDERING INFORMATION Part Number Density Org. Package Ref. Vcc MODE HSD8M64D8H-13 64Byte 8M x 64 168 Pin-DIMM 4K 3.3V SDRAM HSD8M64D8H-10L 64Byte 8M x 64 168 Pin-DIMM 4K 3.3V SDRAM HSD8M64D8H-10 64Byte 8M x 64 168 Pin-DIMM 4K 3.3V SDRAM URL:www.hbe.co.kr REV.1.0(August.2002) 10 MAX.frq CL3 133MHz CL3 100MHz CL2 100MHz HANBit Electronics Co.,Ltd.