HOLTEK HT48R01

HT48R01/HT48R02/HT48R03
10-Pin MSOP I/O Type 8-Bit OTP MCU
Technical Document
· Tools Information
· FAQs
· Application Note
-
HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM
HA0016E Writing and Reading to the HT24 EEPROM with the HT48 MCU Series
HA0018E Controlling the HT1621 LCD Controller with the HT48 MCU Series
HA0049E Read and Write Control of the HT1380
Features
· Operating voltage:
· Watchdog Timer
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
fSYS=12MHz: 4.5V~5.5V
· Program memory ROM: Up to 4096´15
· Data memory RAM: Up to 160´8
· Buzzer driving pair and PFD supported
· 7 bidirectional I/O lines and 1 input
· Power-down and wake-up functions reduce power
· Interrupt input shared with I/O line
consumption
· 4 oscillator configuration options
-
· Up to 0.5ms instruction cycle with 8MHz system clock
External crystal OSC
External RC OSC
Internal RC+I/O (PA5, PA6)
Internal RC+RTC OSC (32768Hz)
at VDD=5V
· All instructions executed within one or two machine
cycles
· 14-bit or 15-bit table read instruction
· Internal RC oscillator
· Up to 8-levels of subroutine nesting
- 3 frequency selections: 4MHz/8MHz/12MHz
- 4MHz with ±10% variation (2.2V~5.5V, 25°C)
· Bit manipulation instruction
· Low voltage reset function
- 8MHz with ±10% variation (3.3V~5.5V, 25°C)
- 12MHz with ±10% variation (4.5V~5.5V, 25°C)
· 10-pin MSOP package
General Description
The HT48R01/HT48R02/HT48R03 are 8-bit high performance, RISC architecture microcontroller devices
specifically designed for I/O control.
wake-up functions, Watchdog Timer, buzzer driver, as
well as low cost, enhance the versatility of these devices
to suit a wide range of application possibilities such as
industrial control, consumer products, subsystem controllers, etc.
The advantages of low power consumption, I/O flexibility, timer functions, oscillator options, Power-down and
Selection Table
Part No.
VDD
Program
Memory
Data
Memory
I/O
Timer
External
Interrupt
Buzzer
Stack
Package
Types
HT48R01
2.2V~5.5V
1K´14
64´8
7 I/O,
1 Input
8-bit´1
1
Ö
4
10MSOP
HT48R02
2.2V~5.5V
2K´14
96´8
7 I/O,
1 Input
8-bit´2
1
Ö
6
10MSOP
HT48R03
2.2V~5.5V
4K´15
160´8
7 I/O,
1 Input
8-bit´2
1
Ö
8
10MSOP
Rev. 1.00
1
December 20, 2006
HT48R01/HT48R02/HT48R03
Block Diagram
P A 3 /IN T
P ro g ra m
C o u n te r
M
T M R 0
M
M P
U
X
D a ta
M e m o ry
M
S T A T U S
A L U
O S
P A
R E
V D
V S
S
S
D
P A C
S h ifte r
P o rt A
P A
C 1
6
A C C
P A 2 /T M R 0
X
U
fS
Y S
X
U
fS
Y S
/4
R T C
X
O S C
W D T O S C
P A 1 , P A 3
M U X
In s tr u c tio n
D e c o d e r
U
M
P r e s c a le r
B Z 0
W D T
p r e s c a le r
O S C 2
P A 5
/4
X
P A 4 /T M R 1
X
Y S
IN T C
T M R 0 C
T im in g
G e n e ra to r
fS
U
B Z 1
S T A C K
In s tr u c tio n
R e g is te r
U
T M R 1
In te rru p t
C ir c u it
P ro g ra m
R O M
M
M
T M R 1 C
L V R
P A 0
P A 1
P A 2
P A 3
P A 4
P A 5
P A 6
P A 7
/B
/B
/T
/IN
/T
/O
/O
/R
Z
Z
M R
T
M R
S C
S C
E S
1
0
2
1
In te rn a l
R C O S C
Pin Assignment
1
2
P A 1 /B Z
3
P A 0 /B Z
4
V S S
5
1 0
P A 3 /IN T
P A 2 /T M R 0
P A 4
9
8
7
6
1
P A 2 /T M R 0
2
P A 6 /O S C 1
P A 1 /B Z
3
P A 7 /R E S
P A 0 /B Z
4
V S S
5
V D D
H T 4 8 R 0 1
1 0 M S O P -A
Rev. 1.00
1 0
P A 3 /IN T
P A 5 /O S C 2
P A 4 /T M R 1
9
P A 5 /O S C 2
8
P A 6 /O S C 1
7
6
P A 7 /R E S
V D D
H T 4 8 R 0 2 /H T 4 8 R 0 3
1 0 M S O P -A
2
December 20, 2006
HT48R01/HT48R02/HT48R03
Pin Description
Pin Name
I/O
Configuration
Options
Description
PA0/BZ
PA1/BZ
I/O
¾
Bidirectional 2-line I/O. Each pin can be setup as a wake-up input using a software register. Software instructions determine if each pin is a CMOS output or a
Schmitt trigger input. Pull-high resistors can be connected using a pull-high software register. PA0/PA1 are pin-shared with the BZ and BZ buzzer function pins.
PA2/TMR0
I/O
¾
Bidirectional single line I/O. PA2 can be setup as a wake-up input using a software register. Software instructions determine if the pin is a CMOS output or
Schmitt trigger input. A pull-high resistor can be connected using a pull-high software register. This line is pin-shared with the Timer/event 0 counter input.
¾
Bidirectional single line I/O. PA3 can be setup as a wake-up input using a software register. Software instructions determine if the pin is a CMOS output or
Schmitt trigger input. A pull-high resistor can be connected using a pull-high software register. This line is pin-shared with INT.
¾
Bidirectional single line I/O. PA4 can be setup as a wake-up input using a software register. Software instructions determine if the pin is a CMOS output or
Schmitt trigger input. A pull-high resistor can be connected using a pull-high software register. This line is pin-shared with the Timer/event counter 1 input.
PA3/INT
PA4/TMR1
OSC1/PA6
OSC2/PA5
I/O
I/O
I/O
Bidirectional 2-line I/O and oscillator pins. If configured as I/Os, software instructions determine if each pin is a CMOS output or a Schmitt trigger input. Pull-high
resistors can be connected using a pull-high software register. A configuration
option determines the choice of oscillator mode and I/O function. The four oscillator modes are:
RC, Crystal, 1. Internal RC OSC: both pins configured as I/Os
RTC or I/O 2. External crystal OSC: both pins configured as OSC1/OSC2
3. Internal RC + RTC OSC: both pins configured as OSC2, OSC1.
4. External RC OSC+PA5: PA6 configured as OSC1 pin, PA5 configured as I/O
Note: When the system clock is sourced from the internal RC OSC, there are 3
frequency options ® 12MHz, 8MHz and 4MHz.
PA7/RES
I
PA7 or RES Active low schmitt trigger reset input or PA7 input.
VDD
¾
¾
Positive power supply
VSS
¾
¾
Negative power supply, ground
* All pull-high resistors are controlled by an register option bit.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
Operating Temperature...........................-40°C to 85°C
IOL Total ..............................................................150mA
IOH Total............................................................-100mA
Total Power Dissipation .....................................500mW
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.00
3
December 20, 2006
HT48R01/HT48R02/HT48R03
D.C. Characteristics
Symbol
VDD
IDD1
IDD2
Parameter
Operating Voltage
Operating Current
(Crystal OSC, RC OSC)
Operating Current
(Crystal OSC, RC OSC)
IDD3
Operating Current
(Crystal OSC, RC OSC)
IDD4
Operating Current (Internal
RC+RTC OSC, Normal Mode)
IDD5
Operating Current (Internal
RC+RTC OSC, Normal Mode)
IDD6
Operating Current (Internal
RC+RTC OSC, Normal Mode)
IDD7
Operating Current (Internal
RC+RTC OSC, Slow Mode)
Ta=25°C
Test Conditions
Conditions
VDD
Min.
Typ.
Max.
Unit
¾
fSYS=4MHz
2.2
¾
5.5
V
¾
fSYS=8MHz
3.3
¾
5.5
V
¾
fSYS=12MHz
4.5
¾
5.5
V
¾
1
2
mA
¾
2.5
5
mA
¾
2
4
mA
¾
4
8
mA
¾
6
12
mA
¾
1
2
mA
¾
2.5
5
mA
¾
2
4
mA
¾
4
8
mA
¾
6
12
mA
¾
10
20
mA
¾
20
40
mA
¾
¾
5
mA
¾
¾
10
mA
¾
¾
1
mA
¾
¾
2
mA
¾
¾
5
mA
¾
¾
10
mA
3V
No load, fSYS=4MHz
5V
3V
No load, fSYS=8MHz
5V
5V
3V
No load, fSYS=12MHz
No load, fSYS=4MHz
5V
3V
No load, fSYS=8MHz
5V
5V
3V
No load, fSYS=12MHz
No load, fSYS=32768Hz
5V
Standby Current
(WDT Enabled, RTC Off)
3V
Standby Current
(WDT Disabled, RTC Off)
3V
Standby Current
(WDT Disabled, RTC On)
3V
VIL1
Input Low Voltage for PA0~PA6,
TMR0, TMR1 and INT
¾
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage forPA0~PA6,
TMR0, TMR1 and INT
¾
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (PA7/RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (PA7/RES)
¾
¾
0.9VDD
¾
VDD
V
VLVR1
Low Voltage Reset 1
¾
Configuration option: 4.2V
3.98
4.2
4.42
V
VLVR2
Low Voltage Reset 2
¾
Configuration option: 3.15V
2.98
3.15
3.32
V
VLVR3
Low Voltage Reset 3
¾
Configuration option: 2.1V
1.98
2.1
2.22
V
IOL
4
8
¾
mA
I/O Port Sink Current
10
20
¾
mA
-2
-4
¾
mA
-5
-10
¾
mA
20
60
100
kW
10
30
50
kW
ISTB1
ISTB2
ISTB3
No load, system HALT
5V
No load, system HALT
5V
No load, system HALT
5V
3V
VOL=0.1VDD
5V
IOH
3V
I/O Port Source Current
VOH=0.9VDD
5V
RPH
3V
¾
Pull-high Resistance
5V
Rev. 1.00
4
December 20, 2006
HT48R01/HT48R02/HT48R03
A.C. Characteristics
Symbol
fSYS1
fSYS2
fSYS3
fTIMER
tWDTOSC
Parameter
System Clock
(Crystal OSC, RC OSC)
System Clock (Internal RC OSC)
(±10%)
System Clock (32768 Crystal)
Timer I/P Frequency (TMR)
Ta=25°C
Test Conditions
Conditions
VDD
Min.
Typ.
Max.
Unit
¾
2.2V~5.5V
400
¾
4000
kHz
¾
3.3V~5.5V
400
¾
8000
kHz
¾
4.5V~5.5V
400
¾
12000
kHz
4.5V~
12MHz, Ta=25°C
5.5V
10800
12000
13200
kHz
3.3V~
8MHz, Ta=25°C
5.5V
7200
8000
8800
kHz
2.2V~
4MHz, Ta=25°C
5.5V
3600
4000
4400
kHz
¾
32768
¾
Hz
¾
¾
¾
2.2V~5.5V
0
¾
4000
kHz
¾
3.3V~5.5V
0
¾
8000
kHz
¾
4.5V~5.5V
0
¾
12000
kHz
3V
¾
45
90
180
ms
5V
¾
32
65
130
ms
Watchdog Oscillator Period
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer Period
¾
Wake-up from HALT
¾
1024
¾
tSYS
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
tLVR
Low Voltage Width to Reset
¾
¾
0.25
1
2
ms
VPOR
VDD Start Voltage to Ensure
Power-on Reset
¾
¾
¾
¾
100
mV
RPOR
VDD Rise Rate to Ensure
Power-on Reset
¾
¾
0.035
¾
¾
V/ms
Note: tSYS=1/fSYS1, 1/fSYS2 or 1/fSYS3
Rev. 1.00
5
December 20, 2006
HT48R01/HT48R02/HT48R03
Functional Description
Execution Flow
incremented by one. The program counter then points to
the memory word containing the next instruction code.
The system clock for the microcontroller is derived from
either a crystal or an RC oscillator. The system clock is
internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from
subroutine, the PC manipulates the program transfer by
loading the address corresponding to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed with the next instruction.
The lower byte of the program counter (PCL) is a readable and writable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.
Program Counter - PC
The program counter controls the sequence in which the
instructions stored in program memory are executed
and its contents specify the full range of program memory.
When a control transfer takes place, an additional
dummy cycle is required.
After accessing a program memory word to fetch an instruction code, the contents of the program counter are
S y s te m
C lo c k
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
O S C 2 ( R C o n ly )
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Program Counter
Mode
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
External Interrupt
0
0
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter Overflow
0
0
0
0
0
0
0
0
1
0
0
0
@3
@2
@1
@0
Skip
Program Counter+2
Loading PCL
*11
*10
*9
*8
@7
@6
@5
@4
Jump, Call Branch
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note: *11~*0: Program Counter bits
S11~S0: Stack register bits
#11~#0: Instruction code bits
@7~@0: PCL bits
For HT48R01, the Program Counter is 10 bits wide, i.e. from *9~*0
For HT48R02, the Program Counter is 11 bits wide, i.e. from *10~*0
For HT48R03, the Program Counter is 12 bits wide, i.e. from *11~*0
Rev. 1.00
6
December 20, 2006
HT48R01/HT48R02/HT48R03
· Location 008H
Program Memory - ROM
This location is reserved for the Timer/Event Counter
0 interrupt service program. If a timer interrupt results
from a Timer/Event Counter 0 overflow, and the interrupt is enabled and the stack is not full, the program
begins execution at location 008H.
The program memory is used to store the program instructions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
1024´14 bits for the HT48R01, 2048´14 bits for the
HT48R02 or 4096´15 bits for the HT48R03, addressed
by the program counter and table pointer.
· Location 00CH (HT48R02/HT48R03 only)
This location is reserved for the Timer/Event Counter
1 interrupt service program. If a timer interrupt results
from a Timer/Event Counter 1 overflow, and the interrupt is enabled and the stack is not full, the program
begins execution at location 00CH.
Certain locations in the program memory are reserved
for special usage:
· Location 000H
This area is reserved for program initialization. After
chip reset, the program always begins execution at location 000H.
· Table location
Any location in the program memory can be used as
look-up tables. The instructions ²TABRDC [m]² (the
current page) and ²TABRDL [m]² (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH
(08H). Only the destination of the lower-order byte in
the table is well-defined, the other bits of the table
· Location 004H
This area is reserved for the external interrupt service
program. If the INT input pin is activated, the interrupt
is enabled and the stack is not full, the program begins
execution at location 004H.
0 0 0 H
0 0 4 H
0 0 8 H
H T 4 8 R 0 1
H T 4 8 R 0 2
0 0 0 H
D e v ic e In itia liz a tio n P r o g r a m
0 0 4 H
E x te r n a l In te r r u p t S u b r o u tin e
0 0 8 H
T im e r /E v e n t C o u n te r 0 In te r r u p t S u b r o u tin e
0 0 C H
0 0 0 H
D e v ic e In itia liz a tio n P r o g r a m
0 0 4 H
E x te r n a l In te r r u p t S u b r o u tin e
0 0 8 H
T im e r /E v e n t C o u n te r 0 In te r r u p t S u b r o u tin e
0 0 C H
T im e r /E v e n t C o u n te r 1 In te r r u p t S u b r o u tin e
H T 4 8 R 0 3
D e v ic e In itia liz a tio n P r o g r a m
E x te r n a l In te r r u p t S u b r o u tin e
T im e r /E v e n t C o u n te r 0 In te r r u p t S u b r o u tin e
T im e r /E v e n t C o u n te r 1 In te r r u p t S u b r o u tin e
P ro g ra m
M e m o ry
n 0 0 H
n F F H
P ro g ra m
M e m o ry
L o o k - u p T a b le ( 2 5 6 w o r d s )
n 0 0 H
3 0 0 H
3 F F H
n F F H
L o o k - u p T a b le ( 2 5 6 w o r d s )
1 4 b its
N o te : n ra n g e s fro m 0 to 3
7 0 0 H
7 F F H
n 0 0 H
L o o k - u p T a b le ( 2 5 6 w o r d s )
n F F H
P ro g ra m
M e m o ry
L o o k - u p T a b le ( 2 5 6 w o r d s )
L o o k - u p T a b le ( 2 5 6 w o r d s )
1 4 b its
N o te : n ra n g e s fro m 0 to 7
F 0 0 H
F F F H
L o o k - u p T a b le ( 2 5 6 w o r d s )
1 5 b its
N o te : n ra n g e s fro m 0 to F
Program Memory
Instruction
Table Location
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note: *11~*0: Table location bits
P11~P8: Current program counter bits
@7~@0: Table pointer bits
For the HT48R01, the table address location is 10 bits, i.e. from *9~*0
For the HT48R02, the table address location is 11 bits, i.e. from *10~*0
For the HT48R03, the table address location is 12 bits, i.e. from *11~*0
Rev. 1.00
7
December 20, 2006
HT48R01/HT48R02/HT48R03
The unused space before 20H is reserved for future expanded usage and reading these locations will get
²00H². The general purpose data memory, addressed
from 20H to 5FH (HT48R01), 20H to 7FH (HT48R02)
or 20H to BFH (HT48R03), is used for data and control
information under instruction commands.
word are transferred to the lower portion of TBLH, and
the remaining 2 bits are read as ²0². The Table
Higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register (07H),
which indicates the table location. Before accessing
the table, the location must be placed in TBLP. The
TBLH is read only and cannot be restored. If the main
routine and the ISR (Interrupt Service Routine) both
employ the table read instruction, the contents of the
TBLH in the main routine are likely to be changed by
the table read instruction used in the ISR, and errors
may occur. Therefore, using the table read instruction
in the main routine and the ISR simultaneously should
be avoided. However, if the table read instruction has
to be applied in both the main routine and the ISR, the
interrupt is supposed to be disabled prior to the table
read instruction. It will not be enabled until the TBLH
has been backed up. All table related instructions require two cycles to complete the operation. These areas may function as normal program memory
depending upon the requirements.
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the
data memory can be set and reset by ²SET [m].i² and
²CLR [m].i². They are also indirectly accessible through
memory pointer register (MP;01H).
Indirect Addressing Register
Location 00H/02H are indirect addressing registers that
are not physically implemented. Any read/write operation of [00H]/[02H] accesses data memory pointed to by
MP0 (01H)/MP1 (03H). Reading location 00H itself indirectly will return the result 00H. Writing indirectly results
in no operation.
The memory pointer registers (MP0/MP1) are 7-bit
registers (HT48R01/HT48R02) or 8 bit registers
(HT48R03). The bit 7 of MP0/MP1 (HT48R01/
HT48R02) are undefined and reading will return the
result ²1². Any writing operation to MP0/MP1 will only
transfer the lower 7-bit data to MP.
Stack Register - STACK
This is a special part of the memory which is used to save
the contents of the Program Counter only. The stack is organised up to 8 levels and is neither part of the data nor
part of the program space, and is neither readable nor
writable. The activated level is indexed by the stack
pointer (SP) and is neither readable nor writeable. At a
subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack.
At the end of a subroutine or an interrupt routine, signaled
by a return RET or RETI instruction, the program counter
is restored to its previous value from the stack. After a
chip reset, the SP will point to the top of the stack.
Accumulator
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
Arithmetic and Logic Unit - ALU
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decremented by RET or RETI, the interrupt will
be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. In a
similar case, if the stack is full and a ²CALL² is subsequently executed, a stack overflow occurs and the first
entry will be los. Only the most recent 4 return addresses are stored.
This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of data operations
but also changes the status register.
Data Memory - RAM
The data memory is divided into two functional groups:
special function registers and general purpose data
memory 64´8 for the HT48R01, 96´8 for the HT48R02
or 160´8 for the HT48R03. Most are read/write, but
some are read only.
Rev. 1.00
8
December 20, 2006
HT48R01/HT48R02/HT48R03
H T 4 8 R 0 1
0 0 H
H T 4 8 R 0 2
In d ir e c t A d d r e s s in g R e g is te r 0
0 0 H
0 1 H
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
0 4 H
H T 4 8 R 0 3
In d ir e c t A d d r e s s in g R e g is te r 0
0 0 H
0 1 H
M P 0
0 1 H
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
0 3 H
M P 1
0 4 H
In d ir e c t A d d r e s s in g R e g is te r 0
0 4 H
0 5 H
A C C
0 5 H
A C C
0 5 H
0 6 H
P C L
0 6 H
P C L
0 6 H
P C L
0 7 H
T B L P
0 7 H
T B L P
0 7 H
T B L P
0 8 H
T B L H
0 8 H
T B L H
0 8 H
T B L H
0 9 H
W D T S
0 9 H
W D T S
0 9 H
W D T S
0 A H
S T A T U S
0 A H
S T A T U S
0 A H
S T A T U S
0 B H
IN T C 0
0 B H
IN T C 0
0 B H
IN T C 0
0 C H
0 D H
T M R 0
0 C H
0 D H
T M R 0
0 C H
0 D H
T M R 0
0 E H
T M R 0 C
0 E H
T M R 0 C
0 E H
T M R 0 C
0 F H
S p e c ia l P u r p o s e
D a ta M e m o ry
1 0 H
0 F H
1 0 H
T M R 1
S p e c ia l P u r p o s e
D a ta M e m o ry
A C C
0 F H
1 0 H
T M R 1
T M R 1 C
1 1 H
T M R 1 C
1 1 H
1 2 H
P A
1 2 H
P A
1 2 H
P A
1 3 H
P A C
1 3 H
P A C
1 3 H
P A C
1 4 H
P A P U
1 4 H
P A P U
1 4 H
P A P U
1 5 H
P A W K
1 5 H
P A W K
1 5 H
P A W K
1 6 H
C T R L
1 6 H
C T R L
1 6 H
C T R L
1 7 H
W C O N
1 7 H
W C O N
1 7 H
W C O N
1 1 H
1 8 H
1 8 H
1 9 H
1 9 H
1 9 H
1 A H
1 A H
1 A H
1 8 H
1 B H
1 C H
1 B H
1 C H
1 B H
1 C H
1 D H
1 D H
1 D H
1 E H
1 E H
1 E H
1 F H
2 0 H
1 F H
2 0 H
G e n e ra l P u rp o s e
D a ta M e m o ry
(6 4 B y te s )
5 F H
S p e c ia l P u r p o s e
D a ta M e m o ry
1 F H
2 0 H
G e n e ra l P u rp o s e
D a ta M e m o ry
(9 6 B y te s )
: U n u s e d ,
re a d a s "0 0 "
7 F H
: U n u s e d ,
re a d a s "0 0 "
B F H
G e n e ra l P u rp o s e
D a ta M e m o ry
(1 6 0 B y te s )
: U n u s e d ,
re a d a s "0 0 "
RAM Mapping
Status Register - STATUS
will not change the TO or PDF flag. In addition operations related to the status register may give different results from those intended. The TO flag can be affected
only by system power-up, a WDT time-out or executing
the ²CLR WDT² or ²HALT² instruction. The PDF flag
can be affected only by executing the ²HALT² or ²CLR
WDT² instruction or a system power-up.
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF), and watchdog time-out flag
(TO). It also records the status information and controls
the operation sequence.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
Bit No.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
Label
Function
0
C
C is set if the operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
1
AC
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
3
OV
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared by system power-up or executing the ²CLR WDT² instruction.
PDF is set by executing the ²HALT² instruction.
5
TO
TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction.
TO is set by a WDT time-out.
6~7
¾
Unused bit, read as ²0²
Status (0AH) Register
Rev. 1.00
9
December 20, 2006
HT48R01/HT48R02/HT48R03
In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status are important and if the subroutine can corrupt the status register, precautions must be taken to
save it properly.
System Control Register
Bit No.
0
1
2
3
Label
Clock mode selection - select the system clock source
0: High speed clock as system clock - internal RC
CLKMOD
1: Low speed clock as system clock - 32.768kHz, and RC oscillator stop
Note: This selection is used only in internal RC + RTC mode.
QOSC
32768Hz OSC quick start-up oscillating setting
0: quickly startup
1: slow startup
BZEN0
BZEN1
BZ/BZ enable/disable
00: both disabled
01: Reserved
10: BZ only enabled
11: BZ and BZ enabled
When BZ or BZ are disabled, the I/O port will have general I/O functions. If enabled, the BZ or
BZ outputs will still be controlled by the related I/O port control and data settings. Refer to the
I/O chapter for details.
4~5
¾
6
BZCS
7
Function
Unused bit, read as ²0²
BZCS, buzzer clock source, 0/1: Timer0/Timer1
Unused bit, read as ²0²
CTRL (16H) Register
Note: For the HT48R01, BZCS is always 0 no matter what value is written into it; i.e., clock source for Buzzer is only
from timer0.
Interrupt
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at specified location in the program memory. Only the program counter is pushed onto
the stack. If the contents of the register or status register
are altered by the interrupt service program which corrupts the desired control sequence, the contents should
be saved in advance.
The device provides an external interrupt and internal
timer/event counter interrupts. The Interrupt Control Register (INTC;0BH) contains the interrupt control bits to set
the enable or disable and the interrupt request flags.
Once an interrupt subroutine is serviced, all the other interrupts will be blocked, by clearing the EMI bit. This
scheme may prevent any further interrupt nesting. Other
interrupt requests may happen during this interval but
only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the
EMI bit and the corresponding bit in the INTC register
may be set to allow interrupt nesting. If the stack is full,
the interrupt request will not be acknowledged, even if
the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must
be prevented from becoming full.
Rev. 1.00
External interrupts are triggered by a high to low transition of INT and the related interrupt request flag (EIF; bit
4 of INTC) will be set. When the interrupt is enabled, the
stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (EIF) and EMI bits will be cleared to disable
other interrupts.
10
December 20, 2006
HT48R01/HT48R02/HT48R03
Interrupt Source
The internal timer/event counter interrupt is initialised by
setting the timer/event counter interrupt request flag
(TF; bit 5 of INTC), caused by a timer overflow. When
the interrupt is enabled, the stack is not full and the TF
bit is set, a subroutine call to location 08H will occur. The
related interrupt request flag,TF, will be reset and the
EMI bit cleared to disable further interrupts.
Vector
External Interrupt
1
04H
Timer/Event Counter 0 Overflow
2
08H
External Interrupt
1
04H
Timer/Event Counter 0 Overflow
2
08H
Timer/Event Counter 1 Overflow
3
0CH
Once the interrupt request flags (T0F/ T1F, EIF) are set,
they will remain in the INTC register until the interrupts
are serviced or cleared by a software instruction. It is
recommended that a program does not use the ²CALL
subroutine² within the interrupt subroutine. Interrupts
often occur in an unpredictable manner or need to be
serviced immediately in some applications. If only one
stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged
once the ²CALL² operates in the interrupt subroutine.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Priority
Vector
Interrupt Subroutine Vector for HT48R02/HT48R03
During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the ²RETI²
instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (of course, if the stack is
not full). To return from the interrupt subroutine, ²RET²
or ²RETI² may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not.
Interrupt Source
Priority
Oscillator Configuration
There are 4 different oscillator modes implemented in
the microcontroller, which are selected by configuration
options. All of them are designed for system clocks,
namely the external RC oscillator (ERC), external crystal oscillator (ECRY), internal RC oscillator with I/O(IRC)
and internal RC oscillator with RTC OSC (IRC+RTC).
No matter what oscillator type is selected, the signal
provides the system clock. The Power-down mode
stops the system oscillator, except for the RTC oscillator, and resists external signals to conserve power.
Interrupt Subroutine Vector for HT48R01
Bit No.
Label
Function
0
EMI
Controls the master (global) interrupt (1= enabled; 0= disabled)
1
EEI
Controls the external interrupt (1= enabled; 0= disabled)
2
ET0I
Controls the timer/event counter 0 interrupt (1= enabled; 0= disabled)
3, 6~7
¾
Unused bit, read as ²0²
4
EIF
External interrupt request flag (1= active; 0= inactive)
5
T0F
Internal timer/event counter 0 request flag (1= active; 0= inactive)
INTC 0 (0BH) Register for HT48R01
Bit No.
Label
Function
0
EMI
Controls the master (global) interrupt (1= enabled; 0= disabled)
1
EEI
Controls the external interrupt (1= enabled; 0= disabled)
2
ET0I
Controls the timer/event counter 0 interrupt (1= enabled; 0= disabled)
3
ET1I
Controls the timer/event counter 1 interrupt (1= enabled; 0= disabled)
4
EIF
External interrupt request flag (1= active; 0= inactive)
5
T0F
Internal timer/event counter 0 request flag (1= active; 0= inactive)
5
T1F
Internal timer/event counter 1 request flag (1= active; 0= inactive)
7
¾
Unused bit, read as ²0²
INTC 0 (0BH) Register for HT48R02/HT48R03
Rev. 1.00
11
December 20, 2006
HT48R01/HT48R02/HT48R03
Watchdog Timer - WDT
If the configuration options select the IRC+RTC, the device supports two kinds of system clock. When combined with the Power-down function, it forms three
operation modes. The two kinds of system clock are internal RC oscillator or RTC OSC (32768Hz) which is selected by the CTRL register CLKMOD bit. The three
operation modes are named as Normal, Slow, or Idle
mode. The following tables shows their relationship.
The WDT clock source may come from a dedicated RC
oscillator (WDT oscillator), RTC clock or instruction
clock (system clock divided by 4) which is determined by
option. This timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The Watchdog Timer can
be disabled by options. If the Watchdog Timer is disabled, all the executions related to the WDT result in no
operation. The RTC clock is enabled only in the internal
RC+RTC mode.
If an RC oscillator is used, an external resistor between
OSC1 and VDD is required whose resistance must
range from 24kW to 1.5MW. The RC oscillator provides
the most cost effective solution. The frequency of oscillation may vary with VDD, temperatures and the chip itself due to process variations. It is, therefore, not
suitable for timing sensitive operations where an accurate oscillator frequency is desired.
The WDT clock (fS) is further divided by an internal
counter to give longer watchdog time-outs.
Once the internal WDT oscillator (RC oscillator with a
period of 65ms at 5V normally) is selected, it is first divided by 256 (8-stage) to get the nominal time-out period of approximately 17ms at 5V. This time-out period
may vary with temperatures, VDD and process variations. By invoking the WDT prescaler, longer time-out
periods can be realized. Writing data to WS2, WS1,
WS0 (bit 2,1,0 of the WDTS) can give different time-out
periods. If WS2, WS1 and WS0 are all equal to ²1², the
division ratio is up to 1:128, and the maximum time-out
period is 2.1s at 5V seconds. If the WDT oscillator is disabled, the WDT clock may still come from the instruction
clock and operate in the same manner except that in the
HALT state the WDT may stop counting and lose its protecting purpose. In this situation the logic can only be restarted by external logic.
If the crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
shift required for the oscillator, and no other external
components are demanded. Instead of a crystal, a resonator can also be connected between OSC1 and OSC2
to obtain a frequency reference, but two external capacitors connected to OSC1 and OSC2 are required. If an
internal RC oscillator is used, OSC1 and OSC2 can be
selected as general I/O lines or as a 32768Hz crystal
(RTC) oscillator. The frequencies of internal oscillator
can be 12MHz, 8MHz and 4MHz which is selected by
configuration options.
The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDT oscillator still works with a
period of approximately 65ms at 5V. The WDT oscillator
can be disabled by configuration options to conserve
power.
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock.
Bit No.
Label
Function
0~2
WS0~
WS2
3~7
¾
WDT prescaler rate select
Unused bit, read as ²0²
WDTS (09H) Register
HALT Instruction
During run state (HALT not execute)
During run state (HALT execute)
CLKMOD
RC Oscillator
32768Hz
System Clock
Mode
0
On
On
RC oscillator
Normal
1
Off
On
32768Hz
Slow
x
Off
On
HALT
Idle
V
D D
O S C 1
O S C 1
P A 6
O S C 2
P A 5
P A 5
C r y s ta l O s c illa to r
( In c lu d e 3 2 7 6 8 H z )
R C
O s c illa to r
In te rn a l R C
O s c illa to r
System Oscillator
Rev. 1.00
12
December 20, 2006
HT48R01/HT48R02/HT48R03
fS
Y S
/4
fS
R O M
C o d e
O p tio n
fR T C
W D T O S C
W D T P r e s c a le r
8 - b it C o u n te r
7 - b it C o u n te r
8 -to -1 M U X
W S 0 ~ W S 2
W D T T im e - o u t
Watchdog Timer
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
Bit No.
6~7
0~3
The HALT mode is initialised by the ²HALT² instruction
and results in the following...
· The system oscillator will be turned off but the WDT
oscillator keeps running (if the WDT oscillator is selected).
· The contents of the on chip RAM and registers remain
unchanged.
· WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT oscillator).
· All of the I/O ports maintain their original status.
· The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset
causes a device initialisation and the WDT overflow performs a ²warm reset². After the TO and PDF flags are
examined, the reason for chip reset can be determined.
The PDF flag is cleared by system power-up or executing the ²CLR WDT² instruction and is set when executing the ²HALT² instruction. The TO flag is set if the WDT
time-out occurs, and causes a wake-up that only resets
the Program Counter and Stack Pointer; the others keep
their original status.
Both port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by options. Awakening from an I/O port stimulus,
the program will resume execution of the next instruction. If it is awakened by an interrupt, two sequences
may happen. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will
resume execution at the next instruction. If the interrupt
is enabled and the stack is not full, the regular interrupt
response takes place. If an interrupt request flag is set to
Function
Bit3~0, WDTEN3~WDTEN0=
1010B: WDT disable
WDTEN0~ others: enable (using 0101B to
WDTEN3 enable WDT is strongly recommended for the highest noise immunity)
4~5
Rev. 1.00
¾
External interrupt edge selection
(default=10)
INTES0~ 00: disable
INTES1 01: rising edge trigger
10: falling edge trigger
11: dual edge trigger
Power Down Operation - HALT
The WDT control register contains 4 bits of WDT enable
bits. WDT can be enable by either WDT mask option or
WDT control register (WDTEN[3:0]=0101B) and be disable by both being disable.
Label
Function
WCON (17H) Register
The WDT overflow under normal operation will initialise
a ²chip reset² and set the status bit ²TO². But in the
HALT mode, the overflow will initialise a ²warm reset²,
and only the Program Counter and SP are reset to zero.
To clear the contents of WDT (including the WDT
prescaler), three methods are adopted; external reset (a
low level to RES), software instruction and a ²HALT² instruction. The software instruction include ²CLR WDT²
and the other set - ²CLR WDT1² and ²CLR WDT2². Of
these two types of instruction, only one can be active depending on the option - ²CLR WDT times selection option². If the ²CLR WDT² is selected (i.e. CLRWDT times
equal one), any execution of the ²CLR WDT² instruction
will clear the WDT. In the case that ²CLR WDT1² and
²CLR WDT2² are chosen (i.e. CLRWDT times equal
two), these two instructions must be executed to clear
the WDT; otherwise, the WDT may reset the chip as a
result of time-out.
Bit No.
Label
Unused bit, read as ²0²
13
December 20, 2006
HT48R01/HT48R02/HT48R03
²1² before entering the HALT mode, the wake-up function of the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 tSYS (system clock
period) to resume normal operation. In other words, a
dummy period will be inserted after wake-up. If the
wake-up results from an interrupt acknowledgment, the
actual interrupt subroutine execution will be delayed by
one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately
after the dummy period is finished.
The functional unit chip reset status are shown below.
To minimise power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Program Counter
000H
Interrupt
Disable
Prescaler
Clear
WDT
Clear. After master reset,
WDT begins counting
Timer/Event Counter
Off
Input/Output Ports
Input mode
Stack Pointer
Points to the top of the stack
Reset
V
There are three ways in which a reset can occur:
· RES reset during normal operation
0 .0 1 m F *
· RES reset during HALT
1 0 0 k W
· WDT time-out reset during normal operation
R E S
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re set² that resets only the Program Counter and SP, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions.
Most registers are reset to the ²initial condition² when
the reset conditions are met. By examining the PDF and
TO flags, the program can distinguish between different
²chip resets².
TO
PDF
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
D D
1 0 k W
0 .1 m F *
Reset Circuit
Note: ²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to
avoid noise interference.
RESET Conditions
V D D
R E S
tS
S T
S S T T im e - o u t
C h ip
Note: ²u² means ²unchanged²
To guarantee that the system oscillator is started and
stabilised, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the system reset (power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
R e s e t
Reset Timing Chart
H A L T
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will enable the SST delay.
W a rm
R e s e t
W D T
R E S
An extra option load time delay is added during a system
reset (power-up, WDT time-out during normal mode or
RES reset).
O S C 1
C o ld
R e s e t
S S T
1 0 - b it R ip p le
C o u n te r
S y s te m
R e s e t
Reset Configuration
Rev. 1.00
14
December 20, 2006
HT48R01/HT48R02/HT48R03
The register states are summarised in the following table.
Register
Program
Counter
Reset
(Power-on)
WDT time-out
RES Reset
(Normal Operation) (Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
000H
000H
000H
000H
000H
MP0
(HT48R01/02)
1xxx xxxx
1uuu uuuu
-uuu uuuu
-uuu uuuu
1uuu uuuu
MP1
(HT48R01/02)
1xxx xxxx
1uuu uuuu
-uuu uuuu
-uuu uuuu
1uuu uuuu
MP0
(HT48R03)
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
MP1
(HT48R03)
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
--xx xxxx
--uu uuuu
--uu uuuu
--uu uuuu
--uu uuuu
WDTS
---- -111
---- -111
---- -111
---- -111
---- -uuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC0
(HT48R01)
--00 -000
--00 -000
--00 -000
--00 -000
--uu -uuu
INTC0
(HT48R02/03)
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
TMR0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0C
0000 1000
0000 1000
0000 1000
0000 1000
uuuu uuuu
TMR1
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR1C
0000 1---
0000 1---
0000 1---
0000 1---
uuuu u---
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAPU
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
PAWK
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
CTRL
-0-- 0000
-0-- 0000
-0-- 0000
-0-- 0000
-u-- uuuu
WCON
10-- 1010
10-- 1010
10-- 1010
10-- 1010
uu-- uuuu
Note: ²*² means ²warm reset²
²-² not implement
²u² means ²unchanged²
²x² means ²unknown²
Rev. 1.00
15
December 20, 2006
HT48R01/HT48R02/HT48R03
Timer/Event Counter
In the event count or timer mode, once the timer/event
counter starts counting, it will count from the current
contents in the timer/event counter to FFH. Once an
overflow occurs, the counter is reloaded from the
timer/event counter preload register and generates an
interrupt request flag (T0F; bit 5 of INTC0 or T1F bit 6 of
INTC0) at the same time.
One or two timer/event counters are implemented in the
microcontroller. The timer/event counter contains an 8-bit
programmable count-up counter and the clock may come
from an external source, the system clock or RTC clock.
Using an external clock input allows the user to count
external events, measure time internals or pulse widths,
or generate an accurate time base, while using the internal clock allows the user to generate an accurate time
base.
In the pulse width measurement mode with the values of
T0ON and T0E ( T1ON and T1E) equal to 1, after the
TMR0 (TMR1) has received a low to high transient (or
high to low if T0E (T1E) is ²0²), it will start counting until
TMR0 (TMR1) returns to its original level and resets
T0ON (T1ON). The measured result remains in the
timer/event counter even if the activated transient occurs again. In other words, only a single cycle measurement can be implemented. Not until the T0ON (T1ON)
bit has been set again, will the cycle measurement function again as long as it receives further transient pulses.
Note that, in this operating mode, the timer/event counter starts counting not according to the logic level but according to the transient edges. In the case of counter
overflows, the counter is reloaded from the timer/event
counter preload register and issues the interrupt request
just like the other two modes. To enable the counting operation, the timer ON bit, T0ON (T1ON) should be set to
1. In the pulse width measurement mode, the T0ON
(T1ON) will be cleared automatically after the measurement cycle is completed. But in the other two modes the
T0ON (T1ON) can only be reset by instructions. The
overflow of the timer/event counter is one of the
wake-up sources. No matter what the operation mode
is, writing a 0 to ETI can disable the interrupt service.
The timer/event counter can generate a buzzer signal
by using an external or internal clock.
There are 2 registers related to the timer/event counter;
TMR0 [0DH], TMR0C [0EH] (TMR1 [10H]), TMR1C
[11H]). Two physical registers are mapped to the TMR location; writing TMR0 (TMR1) places the start value into
the timer/event counter preload register while reading
TMR0 (TMR1) retrieves the contents of the timer/event
counter. The TMR0C (TMR1C) is a timer/ event counter
control register, which defines some options.
The T0M0, T0M1 (T1M0, T1M1) bits define the operating mode. The event count mode is used to count external events, which means the clock source comes from
an external TMR0 (TMR1) pin. The timer mode functions as a normal timer with the clock source coming
from the fINT clock. The pulse width measurement mode
can be used to count the high or low level duration of the
external signal TMR0 (TMR1). The counting is based on
the fINT clock.
fS
M
Y S
R T C O S C
U
fT
P
7 - s ta g e P r e s c a le r
X
f IN
8 -1 M U X
D a ta B u s
T
T 0 M 1
T 0 M 0
T 0 S
T 0 P S C 2 ~ T 0 P S C 0
T M R 0
8 - b it T im e r /E v e n t C o u n te r R e lo a d
P r e lo a d R e g is te r
T 0 E
8 - b it T im e r /E v e n t
C o u n te r 0 (T M R 0 )
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
T 0 M 1
T 0 M 0
T 0 O N
O v e r flo w
to In te rru p t
1 /2
B Z 0
Timer/Event Counter 0
fS
R T C
Y S
/4
O S C
M
U
D a ta B u s
T 1 M 1
T 1 M 0
X
T 1 S
T M R 1
8 - b it T im e r /E v e n t C o u n te r R e lo a d
P r e lo a d R e g is te r
T 1 E
T 1 M 1
T 1 M 0
T 1 O N
8 - b it T im e r /E v e n t
C o u n te r 1 (T M R 1 )
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
O v e r flo w
to In te rru p t
1 /2
B Z 1
Timer/Event Counter 1 - HT48R02/HT48R03 only
Rev. 1.00
16
December 20, 2006
HT48R01/HT48R02/HT48R03
sults in a counting error, this must be taken into consideration by the programmer.
In the case of timer/event counter OFF condition, writing
data to the timer/event counter preload register will also
reload that data to the timer/event counter. But if the
timer/event counter is turned on, data written to it will
only be kept in the timer/event counter preload register.
The timer/event counter will still operate until overflow
occurs. When the timer/event counter is read, the clock
will be blocked to avoid errors. As clock blocking may reBit No.
0~2
Label
T0PSC0~
T0PSC2
3
T0E
4
T0ON
5
T0S
6
7
The bit 0~2 of the TMR0C can be used to define the
pre-scaling stages of the internal clock sources of the
timer/event counter. The definitions are as shown. The
timer/event counter overflow signals can be used to
generate signals for the buzzer.
T0M0
T0M1
Function
To define the prescaler stages, T0PSC2, T0PSC1, T0PSC0=
000: fINT=fTP
001: fINT=fTP/2
010: fINT=fTP/4
011: fINT=fTP/8
100: fINT=fTP/16
101: fINT=fTP/32
110: fINT=fTP/64
111: fINT=fTP/128
To define the TMR active edge of the timer/event counter
In event counter mode (T0M1,T0M0)=(0,1):
1: count on falling edge
0: count on rising edge
In pulse width measurement mode (T0M1,T0M0)=(1,1):
1: start counting on rising edge, stop on falling edge
0: start counting on falling edge, stop on rising edge
To enable or disable timer counting (0=disabled; 1=enabled)
Timer clock source selection
0: fSYS
1: RTC
To define the operating mode (T0M1, T0M0)
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR0C (0EH) Register
Bit No.
Label
0~2
¾
3
T1E
4
T1ON
5
T1S
6
7
T1M0
T1M1
Function
Unused bit, read as ²0²
To define the TMR active edge of the timer/event counter
In event counter mode (T1M1,T1M0)=(0,1):
1: count on falling edge
0: count on rising edge
In pulse width measurement mode (T1M1,T1M0)=(1,1):
1: start counting on rising edge, stop on falling edge
0: start counting on falling edge, stop on rising edge
To enable or disable timer counting (0=disabled; 1=enabled)
Timer clock source selection
0: fSYS/4
1: RTC
To define the operating mode (T1M1, T1M0)
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR1C (11H) Register
Rev. 1.00
17
December 20, 2006
HT48R01/HT48R02/HT48R03
and ²CLR [m].i² (m=12H) instructions. Some instructions first input data and then follow the output operations. For example, ²SET [m].i², ²CLR [m].i², ²CPL [m]²,
²CPLA [m]² read the entire port states into the CPU, execute the defined operations (bit-operation), and then
write the results back to the latches or the accumulator.
Input/Output Ports
There are 7 bi-directional input/output lines and 1 input
line in the microcontroller, labeled as PA, which are
mapped to the data memory of [12H]. All of the I/O ports
can be used for input or output operations. For input operation, these ports are non-latching, that is, the inputs
must be ready at the T2 rising edge of instruction ²MOV
A,[m]² (m=12H). For output operation, all the data is
latched and remains unchanged until the output latch is
rewritten. Each I/O line has its own control register
(PAC) to control the input/output configuration (PA7 for
input only). With this control register, a CMOS output or
Schmitt trigger input ( with or without pull-high resistor
structures) can be reconfigured dynamically (i.e.
on-the-fly) under software control ( the PA7 only provide
input mode). To function as an input, the corresponding
latch of the control register must write ²1². The input
source also depends on the control register. If the control register bit is ²1², the input will read the pad state. If
the control register bit is ²0², the contents of the latches
will move to the internal bus. The latter is possible in the
²read-modify-write² instruction. For output function,
CMOS is the only configuration. These control register
is mapped to locations 13H. After a chip reset, these input/output lines remain at high levels or floating state
(dependent on pull-high options). Each bit of these input/output latches can be set or cleared by ²SET [m].i²
· Wake up and pull-high function
Each line (except PA7) of PA port supports waking-up
MCU and pull-high function which are controlled by
PAWK, PAPU registers respectively. PA7 hasn¢t
wake-up and pull-high function.
Bit No.
Label
Function
PAWKn= 0, PAn wake-up is disPAWK0~ able
PAWK6 PAWKn=1, PAn wake-up is enable
0~6
¾
7
Unused bit, read as ²0²
PAWK (15H) Register
Bit No.
Label
Function
PAPU0~ PAPUn= 0, PAn pull-up is disable
PAPU6 PAPUn=1, PAn pull-up is enable
0~6
¾
7
Unused bit, read as ²0²
PAPU (14H) Register
V
D D
P A P U 6 ~ P A P U 0
C o n tr o l B it
Q
D
D a ta B u s
W r ite C o n tr o l R e g is te r
Q
C K
S
P A 0
P A 1
P A 2
P A 3
P A 4
P A 5
P A 6
C h ip R e s e t
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
D a ta B it
Q
D
C K
S
M
M
R e a d D a ta R e g is te r
R 0
R 1
C 2
C 1
Q
(P A 1 , P A 0 )
(B Z , B Z )
S y s te m
/B Z
/B Z
/T M
/IN T
/T M
/O S
/O S
U
B Z E N
U
X
(P A 0 /P A 1 )
X
W a k e - u p ( P A 0 ~ P A 6 o n ly )
P A W K 6 ~ P A W K 0
IN T fo r P A 3 o n ly
T M R fo r P A 2 o n ly
Input/Output Ports (PA0~PA6)
R e a d D a ta
D a ta B u s
P A 7
R E S fo r P A 7 o n ly
Input/Output Ports (PA7)
Rev. 1.00
18
December 20, 2006
HT48R01/HT48R02/HT48R03
· Buzzer Function
Low Voltage Reset - LVR
PA0 and PA1 are pin-shared with the BZ and BZ
buzzer signals, respectively. If the Buzzer option is selected, then if these pins are setup as outputs, the signals on PA0 (or PA1) will be the Buzzer signal. If setup
as inputs, they will always retain their original input
functions.
The buzzer output signals (in output mode) are controlled by the PA0 data register only. The truth table for
PA0/BZ and PA1/BZ are listed below. Port A also has
a CMOS or Schmitt trigger input configuration option
(All port A I/O lines are controlled by a option bit).
The truth table for PA0/BZ and PA1/BZ is as shown.
The microcontroller provides a low voltage reset circuit
in order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR, such as when changing the battery, the LVR
will automatically reset the device internally.
The LVR includes the following specifications:
· The low voltage (0.9V~VLVR) has to remain in this con-
dition for a time greater than 1ms. If the low voltage
state does not exceed 1ms, the LVR will ignore it and
will not perform a reset function.
· The LVR uses an ²OR² function with the external RES
signal to perform a chip reset.
PA0 I/O
I
PA1 I/O
I O O O I
PA0 Mode
x x x x C B B C B B B B
PA1 Mode
x C B B x x x C C C B B
PA0 Data
x x 0 1 D 0 1 D0 0 1 0 1
PA1 Data
x D x x x x x D1 D D x x
PA0 Pad Status I
I
I
I
I
I O O O O O O O O
The relationship between VDD and VLVR is shown below.
I I O O O O O
V D D
5 .5 V
V D D
5 .5 V
O P R
5 .5 V
V
I D 0 B D0 0 B 0 B
PA1 Pad Status I D 0 B I
V
V D D
5 .5 V
O P R
5 .5 V
V
L V R
2 .1 V
Note: I: input; O: output; D, D0, D1: data;
B: buzzer option, BZ or BZ; x: don't care
C: CMOS output
O P R
5 .5 V
V
L V R
4 .2 V
2 .2 V
0 .9 V
V
L V R
3 .1 5 V
2 .2 V
I I D1 D D 0 B
V
2 .2 V
0 .9 V
0 .9 V
Note: VOPR is the voltage range for proper chip operation with a 4MHz system clock.
V
D D
5 .5 V
V
L V R D e te c t V o lta g e
L V R
0 .9 V
0 V
R e s e t S ig n a l
N o r m a l O p e r a tio n
R e s e t
R e s e t
*1
*2
Low Voltage Reset
Note: *1: To make sure that the system oscillator has stabilised, the SST provides an extra delay of
1024 system clock pulses before entering normal operation.
*2: Since the low voltage has to be maintained in its original state and exceed tLVR, therefore a tLVR delay enters
the reset mode.
Rev. 1.00
19
December 20, 2006
HT48R01/HT48R02/HT48R03
Configuration Options
The following table shows the various configuration options for the microcontroller. All options must be defined for
proper system functioning.
Items
Options
System oscillator selection
· Internal RC + PA5/PA6
1
· Internal RC + RTC
· External Xtal
· External RC + PA5
2
Internal RC frequency selection: 4MHz, 8MHz or 12MHz
3
WDT function: enable or disable
4
WDT clock source: WDTOSC, fSYS/4 or RTC OSC
5
CLRWDT instruction(s): one or two clear WDT instruction(s)
6
LVR function: enable or disable
7
LVR selection: 2.1V/3.15V/4.2V
8
RES or PA7 input selection
Rev. 1.00
20
December 20, 2006
HT48R01/HT48R02/HT48R03
Application Circuits
V
D D
R
O S C
O S C 1
4 7 0 p F
P A 5
C 1
V
O S C 1
C 2
D D
0 .0 1 m F *
R C S y s te m O s c illa to r
2 4 k W < R O S C < 1 .5 M W
O S C 2
R 1
C r y s ta l S y s te m O s c illa to r
F o r C 1 , C 2 a n d R 1 v a lu e s ,
s e e ta b le b e lo w
V D D
1 0 0 k W
0 .1 m F
R E S /P A 7
1 0 k W
O S C 1
P A 0 /B Z
1 0 p F
P A 1 /B Z
P A 2 /T M R 0
0 .1 m F *
V S S
3 2 7 6 8 H z
O S C 2
P A 3 /IN T
P A 4 /T M R 1
O S C
C ir c u it
In te r n a l R C O s c illa to r
+ E x te rn a l R T C O S C
P A 5
O S C 1
P A 6
O S C 2
In te r n a l R C O s c illa to r
T w o p in s a r e c o n fig u r e d
a s I/O p in
S e e R ig h t S id e
H T 4 8 R 0 1 /H T 4 8 R 0 2 /H T 4 8 R 0 3
O S C
C ir c u it
Note: The resistance and capacitance for the reset circuit should be designed to ensure that VDD is stable and
remains in a valid range of the operating voltage before bringing RES high.
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise
interference.
The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For reference only)
Crystal or Resonator
8MHz Crystal & Resonator
C1, C2
R1
35pF
3.9kW
4MHz Crystal
10pF
10kW
4MHz Resonator
10pF
12kW
3.58MHz Crystal
10pF
12kW
3.58MHz Resonator
10pF
12kW
2MHz Crystal & Resonator
35pF
12kW
1MHz Crystal
68pF
18kW
480kHz Resonator
300pF
10kW
455kHz Resonator
300pF
10kW
429kHz Resonator
300pF
10kW
400kHz Resonator
300pF
10kW
The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage conditions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the
MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed.
Rev. 1.00
21
December 20, 2006
HT48R01/HT48R02/HT48R03
Instruction Set Summary
Description
Instruction
Cycle
Flag
Affected
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to data memory with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1
1
1(1)
1
1
1(1)
1
1(1)
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
1
1(1)
Z
Z
Z
Z
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1
1(1)
1
1(1)
1
1(1)
1
1(1)
None
None
C
C
None
None
C
C
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Mnemonic
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Rev. 1.00
22
December 20, 2006
HT48R01/HT48R02/HT48R03
Instruction
Cycle
Flag
Affected
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
(This instruction is not valid for HT48R05A-1/HT48C05)
2(1)
2(1)
None
None
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PDF
TO(4),PDF(4)
TO(4),PDF(4)
None
None
TO,PDF
Mnemonic
Description
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note: x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
:
(4)
and (2)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
²CLR WDT1² or ²CLR WDT2² instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.
Rev. 1.00
23
December 20, 2006
HT48R01/HT48R02/HT48R03
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
24
December 20, 2006
HT48R01/HT48R02/HT48R03
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ Program Counter+1
Program Counter ¬ addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
The contents of the specified data memory are cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
25
December 20, 2006
HT48R01/HT48R02/HT48R03
CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PDF and TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
0
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
26
December 20, 2006
HT48R01/HT48R02/HT48R03
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Data in the specified data memory is decremented by 1.
Operation
[m] ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
27
December 20, 2006
HT48R01/HT48R02/HT48R03
HALT
Enter power down mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation
Program Counter ¬ Program Counter+1
PDF ¬ 1
TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
1
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Data in the specified data memory is incremented by 1
Operation
[m] ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
Program Counter ¬addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV A,[m]
Move data memory to the accumulator
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
28
December 20, 2006
HT48R01/HT48R02/HT48R03
MOV A,x
Move immediate data to the accumulator
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ACC
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
Program Counter ¬ Program Counter+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ACC ²OR² [m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
29
December 20, 2006
HT48R01/HT48R02/HT48R03
RET
Return from subroutine
Description
The program counter is restored from the stack. This is a 2-cycle instruction.
Operation
Program Counter ¬ Stack
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
30
December 20, 2006
HT48R01/HT48R02/HT48R03
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
31
December 20, 2006
HT48R01/HT48R02/HT48R03
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
32
December 20, 2006
HT48R01/HT48R02/HT48R03
SET [m]
Set data memory
Description
Each bit of the specified data memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Bit i of the specified data memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
33
December 20, 2006
HT48R01/HT48R02/HT48R03
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
34
December 20, 2006
HT48R01/HT48R02/HT48R03
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Note that this instruction is not valid for HT48R05A-1/HT48C05
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
35
December 20, 2006
HT48R01/HT48R02/HT48R03
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
36
December 20, 2006
HT48R01/HT48R02/HT48R03
Package Information
10-pin MSOP Outline Dimensions
1 0
6
E 1
1
5
E
D
L
A
A 2
e
R
0 .1 0
B
C
q
A 1
L 1
(4 C O R N E R S )
Symbol
Nom.
Max.
¾
¾
1.1
A1
0
¾
0.15
A2
0.75
¾
0.95
A
Rev. 1.00
Dimensions in mm
Min.
B
0.17
¾
0.27
C
¾
¾
0.25
D
¾
3
¾
E
¾
4.9
¾
E1
¾
3
¾
e
¾
0.5
¾
L
0.4
¾
0.8
L1
¾
0.95
¾
q
0°
¾
8°
37
December 20, 2006
HT48R01/HT48R02/HT48R03
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shanghai Sales Office)
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: 86-21-6485-5560
Fax: 86-21-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District,
Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9533
Holtek Semiconductor Inc. (Beijing Sales Office)
Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752
Fax: 86-10-6641-0125
Holtek Semiconductor Inc. (Chengdu Sales Office)
709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016
Tel: 86-28-6653-6590
Fax: 86-28-6653-6591
Holmate Semiconductor, Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holmate.com
Copyright Ó 2006 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
38
December 20, 2006