HYNIX HY5DU56822AT-L

HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
256M-S DDR SDRAM
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.4/ May. 02
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
Revision History
1. Revision 0.2 (Jan. 02)
1) Define Preliminary Specification
2. Revision 0.3 (Mar. 02)
1) Define IDD Specification
2) Added programmable Cas Latrency 1.5
3) Changed VREF value from min (0.49*VDDQ) & max (0.51*VDDQ) to min (VDDQ/2-50mV) & max (VDDQ/2+50mV)
4) Changed ILI (Input Leakage Current) value from +/- 5uA to +/- 2uA
3. Revision 0.4 (May. 02)
1) Added comment of Cas Latrency 1.5 & 3
Rev. 0.4/ May. 02
2
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
PRELIMINARY
DESCRIPTION
The Hynix HY5DU56422, HY5DU56822 and HY5DU561622 are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth.
The Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
•
VDD, VDDQ = 2.5V +/- 0.2V
•
All inputs and outputs are compatible with SSTL_2
interface
•
Fully differential clock inputs (CK, /CK) operation
•
Double data rate interface
•
Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
•
x16 device has two bytewide data strobes (UDQS,
LDQS) per each x8 I/O
•
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
•
All addresses and control inputs except data, data
strobes and data masks latched on the rising edges
of the clock
•
Programmable CAS latency 1.5, 2, 2.5 and 3
supported
•
Programmable burst length 2 / 4 / 8 with both
sequential and interleave mode
•
Internal four bank operations with single pulsed
/RAS
•
tRAS Lock-out function supported
•
Auto refresh and Self refresh supported
•
8192 refresh cycles / 64ms
•
On chip DLL align DQ and DQS transition with CK
transition
•
JEDEC standard 400mil 66pin TSOP-II with 0.65mm
pin pitch
•
DM mask write data-in at the both rising and falling
edges of the data strobe
•
Full and Half strength driver option controlled by
EMRS
ORDERING INFORMATION
Part No.
Configuration
HY5DU56422A(L)T-X*
64Mx4
HY5DU56822A(L)T-X*
32Mx8
HY5DU561622A(L)T-X*
16Mx16
* X means speed grade
OPERATING FREQUENCY
Package
400mil
66pin
TSOP-II
Grade
CL2
CL2.5
Remark
(CL-tRCD-tRP)
-J
133MHz
166MHz
DDR333 (2.5-3-3)
-M
133MHz
133MHz
DDR266 (2-2-2)
-K
133MHz
133MHz
DDR266A (2-3-3)
-H
100MHz
133MHz
DDR266B (2.5-3-3)
-L
100MHz
125MHz
DDR200 (2-2-2)
* CL1.5 @ DDR200 supported
* CL3 supported
Rev. 0.4 / May. 02
3
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
PIN CONFIGURATION
x4
x8
VDD
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
NC
VDDQ
NC
NC
VDD
DNU
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
x16
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
DNU
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
DNU
LDM
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
400mil X 875mil
66pin TSOP -II
0.65mm pin pitch
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
x16
x8
x4
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
/CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
ROW AND COLUMN ADDRESS TABLE
ITEMS
64Mx4
32Mx8
16Mx16
Organization
16M x 4 x 4banks
8M x 8 x 4banks
4M x 16 x 4banks
Row Address
A0 - A12
A0 - A12
A0 - A12
Column Address
A0-A9, A11
A0-A9
A0-A8
Bank Address
BA0, BA1
BA0, BA1
BA0, BA1
Auto Precharge Flag
A10
A10
A10
Refresh
8K
8K
8K
Rev. 0.4/ May. 02
4
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
PIN DESCRIPTION
PIN
TYPE
CK, /CK
Input
Clock: CK and /CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of /CK. Output
(read) data is referenced to the crossings of CK and /CK (both directions of crossing).
CKE
Input
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER
DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF
REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE
must be maintained high throughout READ and WRITE accesses. Input buffers, excluding
CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are
disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW
level after Vdd is applied.
/CS
Input
Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All commands are masked when CS is registered high. CS provides for external bank selection on
systems with multiple banks. CS is considered part of the command code.
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRECHARGE command is being applied.
A0 ~ A12
Input
Address Inputs: Provide the row address for ACTIVE commands, and the column address
and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A10 is sampled during a precharge command to
determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10
HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The
address inputs also provide the op code during a MODE REGISTER SET command. BA0
and BA1 define which mode register is loaded during the MODE REGISTER SET command
(MRS or EMRS).
/RAS, /CAS, /WE
Input
Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being
entered.
DM
(LDM, UDM)
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH along with that input data during a WRITE access. DM is sampled
on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ
and DQS loading. For the x16, LDM corresponds to the data on DQ0-Q7; UDM corresponds to the data on DQ8-Q15.
DQS
(LDQS, UDQS)
I/O
Data Strobe: Output with read data, input with write data. Edge aligned with read data,
centered in write data. Used to capture write data. For the x16, LDQS corresponds to the
data on DQ0-Q7; UDQS corresponds to the data on DQ8-Q15.
DQ
I/O
Data input / output pin : Data bus
VDD/VSS
Supply
Power supply for internal circuits and input buffers.
VDDQ/VSSQ
Supply
Power supply for output buffers for noise immunity.
VREF
Supply
Reference voltage for inputs for SSTL interface.
NC
NC
Rev. 0.4/ May. 02
DESCRIPTION
No connection.
5
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
FUNCTIONAL BLOCK DIAGRAM (64Mx4)
4Banks x 16Mbit x 4 I/O Double Data Rate Synchronous DRAM
Input Buffer
4
Write Data Register
2-bit Prefetch Unit
8
16Mx4 / Bank0
16Mx4 / Bank2
8
16Mx4 / Bank3
Mode
Register
4
Output Buffer
16Mx4 / Bank1
Command
Decoder
2-bit Prefetch Unit
Bank
Control
Sense AMP
CLK
/CLK
CKE
/CS
/RAS
/CAS
/WE
DQS
DM
DQ[0:3]
Row
Decoder
Column Decoder
ADD
BA
DQS
Address
Buffer
Column Address
Counter
CLK_DLL
DQS
CLK,
/CLK
Data Strobe
Transmitter
Data Strobe
Receiver
DLL
Block
Mode
Register
Rev. 0.4/ May. 02
6
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
FUNCTIONAL BLOCK DIAGRAM (32Mx8)
4Banks x 8Mbit x 8 I/O Double Data Rate Synchronous DRAM
Input Buffer
8
Write Data Register
2-bit Prefetch Unit
16
8Mx8 / Bank0
8Mx8 / Bank2
16
8Mx8 / Bank3
Mode
Register
8
Output Buffer
8Mx8 / Bank1
Command
Decoder
2-bit Prefetch Unit
Bank
Control
Sense AMP
CLK
/CLK
CKE
/CS
/RAS
/CAS
/WE
DQS
DM
DQ[0:7]
Row
Decoder
Column Decoder
ADD
BA
DQS
Address
Buffer
Column Address
Counter
CLK_DLL
DQS
CLK,
/CLK
Data Strobe
Transmitter
Data Strobe
Receiver
DLL
Block
Mode
Register
Rev. 0.4/ May. 02
7
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
FUNCTIONAL BLOCK DIAGRAM (16Mx16)
4Banks x 4Mbit x 16 I/O Double Data Rate Synchronous DRAM
Input Buffer
16
Write Data Register
2-bit Prefetch Unit
32
4Mx16 / Bank0
4Mx16 / Bank2
32
4Mx16 / Bank3
Mode
Register
16
LDM, UDM
Output Buffer
4Mx16 / Bank1
Command
Decoder
2-bit Prefetch Unit
Bank
Control
Sense AMP
CLK
/CLK
CKE
/CS
/RAS
/CAS
/WE
LDQS, UDQS
DQ[0:15]
Row
Decoder
Column Decoder
ADD
BA
LDQS, UDQS
Address
Buffer
Column Address
Counter
CLK_DLL
LDQS
UDQS
CLK,
/CLK
Data Strobe
Transmitter
Data Strobe
Receiver
DLL
Block
Mode
Register
Rev. 0.4/ May. 02
8
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
SIMPLIFIED COMMAND TRUTH TABLE
A10/
AP
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
Extended Mode Register Set
H
X
L
L
L
L
OP code
1,2
Mode Register Set
H
X
L
L
L
L
OP code
1,2
H
X
H
X
X
X
L
H
H
H
X
1
H
X
L
L
H
H
H
X
L
H
L
H
CA
H
X
L
H
L
L
CA
H
X
L
L
H
L
X
Read Burst Stop
H
X
L
H
H
L
X
1
Auto Refresh
H
H
L
L
L
H
X
1
Entry
H
L
L
L
L
H
Exit
L
H
H
X
X
X
L
H
H
H
Entry
H
L
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
1
H
X
X
X
1
L
V
V
V
Device Deselect
No Operation
Bank Active
Read
Read with Autoprecharge
Write
Write with Autoprecharge
Precharge All Banks
Precharge selected Bank
Self Refresh
Precharge Power
Down Mode
Active Power
Down Mode
Exit
L
H
Entry
H
L
Exit
L
H
X
ADDR
RA
BA
V
L
H
L
H
V
V
Note
1
1
1,3
1
1,4
H
X
1,5
L
V
1
1
X
1
1
X
X
1
1
1
1
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )
Note :
1. LDM/UDM states are Don’t Care. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Register setting duing Extended MRS or MRS.
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Prechagre command.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+tRP).
4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time
(tWR) is needed to guarantee that the last data has been completely written.
5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be
precharged.
Rev. 0.4/ May. 02
9
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
WRITE MASK TRUTH TABLE
Function
ADD
R
A10/
AP
CKEn-1
CKEn
/CS, /RAS, /CAS, /WE
DM
BA
Note
Data Write
H
X
X
L
X
1
Data-In Mask
H
X
X
H
X
1
Note :
1.
Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related
with read data. In case of x16 data I/O, LDM and UDM control lower byte(DQ0~7) and Upper byte(DQ8~15)
respectively.
Rev. 0.4/ May. 02
10
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
OPERATION COMMAND TRUTH TABLE-I
Current
State
IDLE
ROW
ACTIVE
READ
WRITE
Rev. 0.4/ May. 02
/CS
/RAS
/CAS
/WE
Address
Command
Action
H
X
X
X
X
DSEL
NOP or power down3
L
H
H
H
X
NOP
NOP or power down3
L
H
H
L
X
BST
ILLEGAL4
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL4
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL4
L
L
H
H
BA, RA
ACT
Row Activation
L
L
H
L
BA, AP
PRE/PALL
NOP
L
L
L
H
X
AREF/SREF
Auto Refresh or Self Refresh5
L
L
L
L
OPCODE
MRS
Mode Register Set
H
X
X
X
X
DSEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
X
BST
ILLEGAL4
L
H
L
H
BA, CA, AP
READ/READAP
Begin read : optional AP6
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
Begin write : optional AP6
L
L
H
H
BA, RA
ACT
ILLEGAL4
L
L
H
L
BA, AP
PRE/PALL
Precharge7
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
Continue burst to end
L
H
H
H
X
NOP
Continue burst to end
L
H
H
L
X
BST
Terminate burst
L
H
L
H
BA, CA, AP
READ/READAP
Term burst, new read:optional AP8
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL4
L
L
H
L
BA, AP
PRE/PALL
Term burst, precharge
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
Continue burst to end
L
H
H
H
X
NOP
Continue burst to end
L
H
H
L
X
BST
ILLEGAL4
L
H
L
H
BA, CA, AP
READ/READAP
Term burst, new read:optional AP8
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
Term burst, new write:optional AP
11
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
OPERATION COMMAND TRUTH TABLE-II
Current
State
WRITE
READ
WITH
AUTOPRECHARGE
WRITE
AUTOPRECHARGE
PRECHARGE
Rev. 0.4/ May. 02
/CS
/RAS
/CAS
/WE
Address
Command
Action
L
L
H
H
BA, RA
ACT
ILLEGAL4
L
L
H
L
BA, AP
PRE/PALL
Term burst, precharge
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
Continue burst to end
L
H
H
H
X
NOP
Continue burst to end
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL10
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL10
L
L
H
H
BA, RA
ACT
ILLEGAL4,10
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL4,10
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
Continue burst to end
L
H
H
H
X
NOP
Continue burst to end
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL10
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL10
L
L
H
H
BA, RA
ACT
ILLEGAL4,10
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL4,10
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
NOP-Enter IDLE after tRP
L
H
H
H
X
NOP
NOP-Enter IDLE after tRP
L
H
H
L
X
BST
ILLEGAL4
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL4,10
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL4,10
L
L
H
H
BA, RA
ACT
ILLEGAL4,10
L
L
H
L
BA, AP
PRE/PALL
NOP-Enter IDLE after tRP
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
12
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
OPERATION COMMAND TRUTH TABLE-III
Current
State
ROW
ACTIVATING
WRITE
RECOVERING
WRITE
RECOVERING
WITH
AUTOPRECHARGE
REFRESHING
Rev. 0.4/ May. 02
/CS
/RAS
/CAS
/WE
Address
Command
Action
H
X
X
X
X
DSEL
NOP - Enter ROW ACT after tRCD
L
H
H
H
X
NOP
NOP - Enter ROW ACT after tRCD
L
H
H
L
X
BST
ILLEGAL4
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL4,10
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL4,10
L
L
H
H
BA, RA
ACT
ILLEGAL4,9,10
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL4,10
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
NOP - Enter ROW ACT after tWR
L
H
H
H
X
NOP
NOP - Enter ROW ACT after tWR
L
H
H
L
X
BST
ILLEGAL4
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL4,10
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL4,11
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
NOP - Enter precharge after tDPL
L
H
H
H
X
NOP
NOP - Enter precharge after tDPL
L
H
H
L
X
BST
ILLEGAL4
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL4,8,10
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL4,10
L
L
H
H
BA, RA
ACT
ILLEGAL4,10
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL4,11
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
NOP - Enter IDLE after tRC
L
H
H
H
X
NOP
NOP - Enter IDLE after tRC
L
H
H
L
X
BST
ILLEGAL11
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL11
13
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
OPERATION COMMAND TRUTH TABLE-IV
Current
State
WRITE
MODE
REGISTER
ACCESSING
/CS
/RAS
/CAS
/WE
Address
Command
Action
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL11
L
L
H
H
BA, RA
ACT
ILLEGAL11
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL11
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
NOP - Enter IDLE after tMRD
L
H
H
H
X
NOP
NOP - Enter IDLE after tMRD
L
H
H
L
X
BST
ILLEGAL11
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL11
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL11
L
L
H
H
BA, RA
ACT
ILLEGAL11
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL11
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
Note :
1. H - Logic High Level, L - Logic Low Level, X - Don’t Care, V - Valid Data Input,
BA - Bank Address, AP - AutoPrecharge Address, CA - Column Address, RA - Row Address, NOP - NO Operation.
2. All entries assume that CKE was active(high level) during the preceding clock cycle.
3. If both banks are idle and CKE is inactive(low level), then in power down mode.
4. Illegal to bank in specified state. Function may be legal in the bank indicated by Bank Address(BA) depending on the state of
that bank.
5. If both banks are idle and CKE is inactive(low level), then self refresh mode.
6. Illegal if tRCD is not met.
7. Illegal if tRAS is not met.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Illegal if tRRD is not met.
10. Illegal for single bank, but legal for other banks in multi-bank devices.
11. Illegal for all banks.
Rev. 0.4/ May. 02
14
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
CKE FUNCTION TRUTH TABLE
Current
State
CKEn1
CKEn
/CS
/RAS
/CAS
/WE
/ADD
Action
H
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
Exit self refresh, enter idle after tSREX
L
H
L
H
H
H
X
Exit self refresh, enter idle after tSREX
L
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP, continue self refresh
H
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
Exit power down, enter idle
L
H
L
H
H
H
X
Exit power down, enter idle
L
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP, continue power down mode
H
H
X
X
X
X
X
See operation command truth table
H
L
L
L
L
H
X
Enter self refresh
H
L
H
X
X
X
X
Exit power down
H
L
L
H
H
H
X
Exit power down
H
L
L
H
H
L
X
ILLEGAL
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
H
X
X
ILLEGAL
H
L
L
L
L
L
X
ILLEGAL
L
L
X
X
X
X
X
NOP
H
H
X
X
X
X
X
See operation command truth table
H
L
X
X
X
X
X
ILLEGAL5
L
H
X
X
X
X
X
INVALID
L
L
X
X
X
X
X
INVALID
SELF
REFRESH1
POWER
DOWN2
ALL BANKS
IDLE4
ANY STATE
OTHER
THAN
ABOVE
Note :
When CKE=L, all DQ and DQS must be in Hi-Z state.
1. CKE and /CS must be kept high for a minimum of 200 stable input clocks before issuing any command.
2. All command can be stored after 2 clocks from low to high transition of CKE.
3. Illegal if CLK is suspended or stopped during the power down mode.
4. Self refresh can be entered only from the all banks idle state.
5. Disabling CLK may cause malfunction of any bank which is in active state.
Rev. 0.4/ May. 02
15
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
SIMPLIFIED STATE DIAGRAM
MRS
MODE
REGISTER
SET
SREF
SELF
REFRESH
IDLE
SREX
PDEN
PDEX
AREF
ACT
POWER
DOWN
POWER
DOWN
AUTO
REFRESH
PDEN
BST
PDEX
BANK
ACTIVE
READ
WRITE
READ
WRITE
WRITEAP
WRITE
WITH
AUTOPRECHARGE
PRE(PALL)
READAP
READ
READAP
WITH
AUTOPRECHARGE WRITEAP
READ
WRITE
PRE(PALL)
PRE(PALL)
PRECHARGE
POWER-UP
Command Input
Automatic Sequence
POWER APPLIED
Rev. 0.4/ May. 02
16
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
POWER-UP SEQUENCE AND DEVICE INITIALIZATION
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those
specified may result in undefined operation. Except for CKE, inputs are not recognized as valid until after VREF is
applied. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after VDD is applied. Maintaining an LVCMOS
LOW level on CKE during power-up is required to guarantee that the DQ and DQS outputs will be in the High-Z state,
where they will remain until driven in normal operation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200us delay prior to applying an executable command.
Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be
brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a EXTENDED
MODE REGISTER SET command should be issued for the Extended Mode Register, to enable the DLL, then a MODE
REGISTER SET command should be issued for the Mode Register, to reset the DLL, and to program the operating
parameters. 200 clock cycles are required between the DLL reset and any command. During the 200 cycles of CK, for
DLL locking, executable commands are disallowed (a DESELECT or NOP command must be applied). After the 200
clock cycles, a PRECHARGE ALL command should be applied, placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a MODE REGISTER SET command
for the Mode Register, with the reset DLL bit deactivated (i.e. to program operating parameters without resetting the
DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation.
1.
Apply power - VDD, VDDQ, VTT, VREF in the following power up sequencing and attempt to maintain CKE at LVCMOS low state. (All the other input pins may be undefined.
No power sequencing is specified during power up or power down given the following cirteria :
• VDD and VDDQ are driven from a single power converter output.
• VTT is limited to 1.44V (reflecting VDDQ(max)/2 + 50mV VREF variation + 40mV VTT variation).
• VREF tracks VDDQ/2.
• A minimum resistance of 42 ohms (22 ohm series resistor + 22 ohm parallel resistor - 5% tolerance) limits the
input current from the VTT supply into any pin.
If the above criteria cannot be met by the system design, then the following sequencing and voltage relationship must
be adhered to during power up :
Voltage description
Sequencing
Voltage relationship to avoid latch-up
VDDQ
After or with VDD
< VDD + 0.3V
VTT
After or with VDDQ
< VDDQ + 0.3V
VREF
After or with VDDQ
< VDDQ + 0.3V
2.
Start clock and maintain stable clock for a minimum of 200usec.
3.
After stable power and clock, apply NOP condition and take CKE high.
4.
Issue Extended Mode Register Set (EMRS) to enable DLL.
5.
Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=high. (An additional 200
cycles of clock are required for locking DLL)
6.
Issue Precharge commands for all banks of the device.
Rev. 0.4/ May. 02
17
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
7.
Issue 2 or more Auto Refresh commands.
8.
Issue a Mode Register Set command to initialize the mode register with bit A8 = Low.
Power-Up Sequence
VDD
VDDQ
tVTD
VTT
VREF
DQ’s
CODE
≈ ≈
DQS
CODE
T=200usec
Power up
VDD and CK stable
tRP
Precharge All
≈ ≈
BA0,BA1
CODE
≈ ≈ ≈ ≈ ≈ ≈ ≈
A10
EMRS
≈ ≈
ADDR
PRE
≈ ≈ ≈ ≈ ≈ ≈ ≈
DM
NOP
≈ ≈
CMD
≈≈ ≈ ≈ ≈ ≈
CKE
tMRD
200 cycles of CK*
tRP
MRS
CODE
CODE
CODE
EMRS Set
MRS Set
Reset DLL
(with A8=H)
≈ ≈ ≈ ≈ ≈ ≈ ≈
tIS tIH
≈ ≈
CLK
≈ ≈ ≈ ≈ ≈ ≈ ≈
≈
/CLK
NOP
PRE
AREF
Precharge All
MRS
CODE
CODE
CODE
tRFC
2 or more
Auto Refresh
MRS Set
(with A8=L)
*200 cycles of CK are required (for DLL locking) before any executable command can be applied.
Rev. 0.4/ May. 02
18
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
MODE REGISTER SET (MRS)
The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length,
burst type, test mode, DLL reset. The mode register is programed via MRS command. This command is issued by the
low signals of /RAS, /CAS, /CS, /WE and BA0. This command can be issued only when all banks are in idle state and
CKE must be high at least one cycle before the Mode Register Set Command can be issued. Two cycles are required to
write the data in mode register. During the MRS cycle, any command cannot be issued. Once mode register field is
determined, the information will be held until resetted by another MRS command.
BA1
BA0
0
0
A12
A11
A10
A9
RFU
A8
A7
DR
TM
A6
A5
A4
CAS Latency
BA0
MRS Type
A8
DLL Reset
A7
Test Mode
0
MRS
0
No
0
Normal
1
EMRS
1
Yes
1
Test
A3
A2
BT
A1
A0
Burst Length
Burst Length
A2
Rev. 0.4/ May. 02
A1
A0
Sequential
Interleave
A6
A5
A4
CAS Latency
0
0
0
Reserved
Reserved
0
0
0
Reserved
0
0
1
2
2
0
0
1
Reserved
0
1
0
4
4
0
1
0
2
0
1
1
8
8
0
1
1
3
1
0
0
Reserved
Reserved
1
0
0
Reserved
1
0
1
Reserved
Reserved
1
0
1
1.5
1
1
0
Reserved
Reserved
1
1
0
2.5
1
1
1
Reserved
Reserved
1
1
1
Reserved
A3
Burst Type
0
Sequential
1
Interleave
19
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
BURST DEFINITION
Burst Length
Starting Address (A2,A1,A0)
Sequential
Interleave
XX0
0, 1
0, 1
XX1
1, 0
1, 0
X00
0, 1, 2, 3
0, 1, 2, 3
X01
1, 2, 3, 0
1, 0, 3, 2
X10
2, 3, 0, 1
2, 3, 0, 1
X11
3, 0, 1, 2
3, 2, 1, 0
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
011
3, 4, 5, 6, 7, 0, 1, 2
3, 2, 1, 0, 7, 6, 5, 4
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7, 0, 1, 2, 3, 4, 5
6, 7, 4, 5, 2, 3, 0, 1
111
0, 1, 2, 3, 4, 5, 6, 7
7, 6, 5, 4, 3, 2, 1, 0
2
4
8
BURST LENGTH & TYPE
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst
length determines the maximum number of column locations that can be accessed for a given Read or Write command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is
reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A 2 -Ai when the burst length
is set to four and by A 3 -Ai when the burst length is set to eight (where Ai is the most significant column address bit
for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location
within the block. The programmed burst length applies to both Read and Write bursts.
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the
burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the
burst type and the starting column address, as shown in Burst Definitionon Table
Rev. 0.4/ May. 02
20
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
CAS LATENCY
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and the
availability of the first burst of output data. The latency can be programmed 1.5, 2, 2.5 or 3 clocks.
If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident
with clock edge n + m.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
DLL RESET
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically
disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any
time the DLL is enabled, 200 clock cycles must occur to allow time for the internal clock to lock to the externally
applied clock before an any command can be issued.
OUTPUT DRIVER IMPEDANCE CONTROL
The normal drive strength for all outputs is specified to be SSTL_2, Class II. Hynix also supports a half strength driver
option, intended for lighter load and/or point-to-point environments. Selection of the half strength driver option will
reduce the output drive strength by 50% of that of the full strength driver. I-V curves for both the full strength driver
and the half strength driver are included in this document.
Rev. 0.4/ May. 02
21
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
EXTENDED MODE REGISTER SET (EMRS)
The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions include DLL enable/disable, output driver strength selection(optional). These functions are controlled via the bits
shown below. The Extended Mode Register is programmed via the Mode Register Set command ( BA0=1 and BA1=0)
and will retain the stored information until it is programmed again or the device loses power.
The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller
must wait the specified time before initiating any subsequent operation. Violating either of these requirements will
result in unspecified operation.
BA1
BA0
0
1
A12
A11
A10
A9
A8
A7
RFU*
BA0
MRS Type
0
MRS
1
EMRS
A6
A5
A4
A3
A2
A1
A0
0**
DS
DLL
A0
DLL enable
0
Enable
1
Diable
A1
Output Driver
Impedance Control
0
Full Strength Driver
1
Half Strength Driver
* All bits in RFU address fields must be programmed to Zero, all other states are reserved for future usage
** This part do not support /QFC function, A2 must be programmed to Zero.
Rev. 0.4/ May. 02
22
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Ambient Temperature
TA
0 ~ 70
Storage Temperature
TSTG
-55 ~ 125
oC
VIN, VOUT
-0.5 ~ 3.6
V
VDD
-0.5 ~ 3.6
V
VDDQ
-0.5 ~ 3.6
V
Output Short Circuit Current
IOS
50
mA
Power Dissipation
PD
1
W
TSOLDER
260 ⋅ 10
Voltage on Any Pin relative to VSS
Voltage on VDD relative to VSS
Voltage on VDDQ relative to VSS
Soldering Temperature ⋅ Time
Unit
o
o
C
C ⋅ sec
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Min
Typ.
Max
Unit
Power Supply Voltage
VDD
2.3
2.5
2.7
V
Power Supply Voltage
VDDQ
2.3
2.5
2.7
V
Input High Voltage
VIH
VREF + 0.15
-
VDDQ + 0.3
V
Input Low Voltage
VIL
-0.3
-
VREF - 0.15
V
Termination Voltage
VTT
VREF - 0.04
VREF
VREF + 0.04
V
Reference Voltage
VREF
VDDQ/2 50mV
VDDQ/2
VDDQ/2 +
50mV
V
Note
1
2
3
Note :
1. VDDQ must not exceed the level of VDD.
2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration.
3. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of the same.
Peak to peak noise on VREF may not exceed +/- 2% of the dc value.
DC CHARACTERISTICS I
Parameter
(TA=0 to 70°C, Voltage referenced to VSS = 0V)
Symbol
Min.
Max
Unit
Note
Input Leakage Current
ILI
-2
2
uA
1
Output Leakage Current
ILO
-5
5
uA
2
Output High Voltage
VOH
VTT + 0.76
-
V
IOH = -15.2mA
Output Low Voltage
VOL
-
VTT - 0.76
V
IOL = +15.2mA
Note : 1. VIN=0 to VDD, All other pins are not tested under VIN =0V. 2. DOUT is disabled, VOUT=0 to VDDQ
Rev. 0.4/ May. 02
23
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
DC CHARACTERISTICS II (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
64Mx4
Parameter
Symbol
Speed
Test Condition
-J
-M
-K
-H
-L
Unit Note
IDD0
One bank; Active - Precharge;
tRC=tRC(min); tCK=tCK(min); DQ,DM and
DQS inputs changing twice per clock cycle;
address and control inputs changing once
per clock cycle
105
95
90
mA
Operating Current
IDD1
One bank; Active - Read - Precharge;
Burst=2; tRC=tRC(min); tCK=tCK(min);
address and control inputs changing once
per clock cycle; IOUT=0mA
150
130
120
mA
Precharge Power
Down Standby
Current
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
Idle Standby Current
IDD2F
/CS=High, All banks idle; tCK=tCK(min);
CKE=High; address and control inputs
changing once per clock cycle.
VIN=VREF for DQ, DQS and DM
Active Power Down
Standby Current
IDD3P
One bank active; Power down mode ;
CKE=Low, tCK=tCK(min)
IDD3N
/CS=HIGH; CKE=HIGH; One bank; ActivePrecharge; tRC=tRAS(max); tCK=tCK(min);
DQ, DM and DQS inputs changing twice per
clock cycle; Address and other control inputs
changing once per clock cycle
60
50
50
mA
IDD4R
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing
once per clock cycle; tCK=tCK(min);
IOUT=0mA
280
240
180
mA
IDD4W
Burst=2; Writes; Continuous burst; One
bank active; Address and control inputs
changing once per clock cycle;
tCK=tCK(min); DQ, DM and DQS inputs
changing twice per clock cycle
280
240
180
mA
230
210
195
mA
Operating Current
Active Standby
Current
Operating Current
Operating Current
Auto Refresh Current
IDD5
tRC=tRFC(min); All banks active
Self Refresh Current
IDD6
CKE=<0.2V; External clock on;
tCK=tCK(min)
Operating Current Four Bank Operation
IDD7
Four bank interleaving with BL=4, Refer to
the following page for detailed test condition
Rev. 0.4/ May. 02
20
50
mA
40
35
25
mA
mA
Normal
3
mA
Low Power
1.5
mA
305
295
295
mA
24
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
DC CHARACTERISTICS II (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
32Mx8
Parameter
Symbol
Speed
Test Condition
-J
-M
-K
-H
-L
Unit Note
IDD0
One bank; Active - Precharge;
tRC=tRC(min); tCK=tCK(min); DQ,DM and
DQS inputs changing twice per clock cycle;
address and control inputs changing once
per clock cycle
105
95
90
mA
Operating Current
IDD1
One bank; Active - Read - Precharge;
Burst=2; tRC=tRC(min); tCK=tCK(min);
address and control inputs changing once
per clock cycle; IOUT=0mA
150
130
120
mA
Precharge Power
Down Standby
Current
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
Idle Standby Current
IDD2F
/CS=High, All banks idle; tCK=tCK(min);
CKE=High; address and control inputs
changing once per clock cycle.
VIN=VREF for DQ, DQS and DM
Active Power Down
Standby Current
IDD3P
One bank active; Power down mode ;
CKE=Low, tCK=tCK(min)
IDD3N
/CS=HIGH; CKE=HIGH; One bank; ActivePrecharge; tRC=tRAS(max); tCK=tCK(min);
DQ, DM and DQS inputs changing twice per
clock cycle; Address and other control inputs
changing once per clock cycle
60
50
50
mA
IDD4R
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing
once per clock cycle; tCK=tCK(min);
IOUT=0mA
290
250
190
mA
IDD4W
Burst=2; Writes; Continuous burst; One
bank active; Address and control inputs
changing once per clock cycle;
tCK=tCK(min); DQ, DM and DQS inputs
changing twice per clock cycle
290
250
190
mA
230
210
195
mA
Operating Current
Active Standby
Current
Operating Current
Operating Current
Auto Refresh Current
IDD5
tRC=tRFC(min); All banks active
Self Refresh Current
IDD6
CKE=<0.2V; External clock on;
tCK=tCK(min)
Operating Current Four Bank Operation
IDD7
Four bank interleaving with BL=4, Refer to
the following page for detailed test condition
Rev. 0.4/ May. 02
20
50
mA
40
35
25
mA
mA
Normal
3
mA
Low Power
1.5
mA
315
305
280
mA
25
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
DC CHARACTERISTICS II (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
16Mx16
Parameter
Symbol
Speed
Test Condition
-J
-M
-K
-H
-L
Unit Note
IDD0
One bank; Active - Precharge;
tRC=tRC(min); tCK=tCK(min); DQ,DM and
DQS inputs changing twice per clock cycle;
address and control inputs changing once
per clock cycle
105
95
90
mA
Operating Current
IDD1
One bank; Active - Read - Precharge;
Burst=2; tRC=tRC(min); tCK=tCK(min);
address and control inputs changing once
per clock cycle; IOUT=0mA
150
130
120
mA
Precharge Power
Down Standby
Current
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
Idle Standby Current
IDD2F
/CS=High, All banks idle; tCK=tCK(min);
CKE=High; address and control inputs
changing once per clock cycle.
VIN=VREF for DQ, DQS and DM
Active Power Down
Standby Current
IDD3P
One bank active; Power down mode ;
CKE=Low, tCK=tCK(min)
IDD3N
/CS=HIGH; CKE=HIGH; One bank; ActivePrecharge; tRC=tRAS(max); tCK=tCK(min);
DQ, DM and DQS inputs changing twice per
clock cycle; Address and other control inputs
changing once per clock cycle
60
50
50
mA
IDD4R
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing
once per clock cycle; tCK=tCK(min);
IOUT=0mA
290
250
190
mA
IDD4W
Burst=2; Writes; Continuous burst; One
bank active; Address and control inputs
changing once per clock cycle;
tCK=tCK(min); DQ, DM and DQS inputs
changing twice per clock cycle
290
250
190
mA
230
210
195
mA
Operating Current
Active Standby
Current
Operating Current
Operating Current
Auto Refresh Current
IDD5
tRC=tRFC(min); All banks active
Self Refresh Current
IDD6
CKE=<0.2V; External clock on;
tCK=tCK(min)
Operating Current Four Bank Operation
IDD7
Four bank interleaving with BL=4, Refer to
the following page for detailed test condition
Rev. 0.4/ May. 02
20
50
mA
40
35
25
mA
mA
Normal
3
mA
Low Power
1.5
mA
335
325
290
mA
26
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7
IDD1 : Operating current: One bank operation
1. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are
changing once per clock cycle. lout = 0mA
2. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=2, tRCD = 2*tCK, tRC = 10*tCK, tRAS = 5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
50% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=2, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 6*tCK
Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing
50% of data changing at every burst
- DDR266A(133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=2, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 6*tCK
Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing
50% of data changing at every burst
- DDR266(133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=2, tRCD = 2*tCK, tRC = 8*tCK, tRAS = 6*tCK
Read : A0 N R0 N N N P0 N A0 N - repeat the same timing with random address changing
50% of data changing at every burst
- DDR333(166Mhz, CL=2.5) : tCK = 6ns, CL=2, BL=2, tRCD = 3*tCK, tRC = 10*tCK, tRAS = 7*tCK
Read : A0 N N R0 N N N P0 N N A0 N - repeat the same timing with random address changing
50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
IDD7 : Operating current: Four bank operation
1. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not
changing. lout = 0mA
2. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRRD = 2*tCK, tRCD= 3*tCK, Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
- DDR266A(133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
- DDR333(166Mhz, CL=2.5) : tCK = 6ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
Rev. 0.4/ May. 02
27
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HY5DU561622A(L)T
AC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Min
Max
Input High (Logic 1) Voltage, DQ, DQS and DM signals
VIH(AC)
VREF + 0.31
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
VIL(AC)
Input Differential Voltage, CK and /CK inputs
VID(AC)
Input Crossing Point Voltage, CK and /CK inputs
VIX(AC)
Unit
Note
V
VREF - 0.31
V
0.7
VDDQ + 0.6
V
1
0.5*VDDQ-0.2
0.5*VDDQ+0.2
V
2
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Parameter
Value
Unit
Reference Voltage
VDDQ x 0.5
V
Termination Voltage
VDDQ x 0.5
V
AC Input High Level Voltage (VIH, min)
VREF + 0.31
V
AC Input Low Level Voltage (VIL, max)
VREF - 0.31
V
Input Timing Measurement Reference Level Voltage
VREF
V
Output Timing Measurement Reference Level Voltage
VTT
V
Input Signal maximum peak swing
1.5
V
Input minimum Signal Slew Rate
1
V/ns
Termination Resistor (RT)
50
Ω
Series Resistor (RS)
25
Ω
Output Load Capacitance for Access Time Measurement (CL)
30
pF
Rev. 0.4/ May. 02
28
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Parameter
Symbol
DDR333
DDR266
Min
Max
Min
Max
Unit
Row Cycle Time
tRC
60
-
60
-
ns
Auto Refresh Row Cycle Time
tRFC
72
-
75
-
ns
Row Active Time
tRAS
42
70K
45
120K
ns
Active to Read with Auto Precharge Delay
tRAP
tRCD or
tRPmin
-
tRCD or
tRPmin
-
ns
Row Address to Column Address Delay
tRCD
18
-
15
-
ns
Row Active to Row Active Delay
tRRD
12
-
15
-
ns
Column Address to Column Address Delay
tCCD
1
-
1
-
CK
Row Precharge Time
tRP
18
-
15
-
ns
Write Recovery Time
tWR
15
-
15
-
ns
Write to Read Command Delay
tWTR
1
-
1
-
CK
Auto Precharge Write Recovery + Precharge Time
tDAL
(tWR/tCK)
+
(tRP/tCK)
-
(tWR/tCK)
+
(tRP/tCK)
-
CK
6
12
7.5
12
ns
7.5
12
7.5
12
ns
System Clock Cycle Time
CL = 2.5
CL = 2
tCK
Note
16
15
Clock High Level Width
tCH
0.45
0.55
0.45
0.55
CK
Clock Low Level Width
tCL
0.45
0.55
0.45
0.55
CK
Data-Out edge to Clock edge Skew
tAC
-0.7
0.7
-0.75
0.75
ns
DQS-Out edge to Clock edge Skew
tDQSCK
-0.6
0.6
-0.75
0.75
ns
DQS-Out edge to Data-Out edge Skew
tDQSQ
-
0.45
-
0.5
ns
Data-Out hold time from DQS
tQH
tHP
-tQHS
-
tHP
-tQHS
-
ns
1,10
Clock Half Period
tHP
min
(tCL,tCH)
-
min
(tCL,tCH)
-
ns
1,9
tQHS
-
0.55
-
0.75
ns
10
Data Hold Skew Factor
Valid Data Output Window
tDV
Data-out high-impedance window from CK,/CK
tHZ
-0.7
0.7
-0.75
0.75
ns
Data-out low-impedance window from CK, /CK
tLZ
-0.7
0.7
-0.75
0.75
ns
Input Setup Time (fast slew rate)
tIS
0.75
-
0.9
-
ns
Input Hold Time (fast slew rate)
tIH
0.75
-
0.9
-
ns
Rev. 0.4/ May. 02
tQH-tDQSQ
tQH-tDQSQ
ns
17
2,3,5,6
29
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
Parameter
Symbol
DDR333
DDR266
Min
Max
Min
Max
Unit
Input Setup Time (slow slew rate)
tIS
0.8
-
1.0
-
ns
Input Hold Time (slow slew rate)
tIH
0.8
-
1.0
-
ns
tIPW
2.2
-
2.2
-
ns
Write DQS High Level Width
tDQSH
0.35
-
0.35
-
CK
Write DQS Low Level Width
tDQSL
0.35
-
0.35
-
CK
Clock to First Rising edge of DQS-In
tDQSS
0.75
1.25
0.72
1.28
CK
Data-In Setup Time to DQS-In (DQ & DM)
tDS
0.45
-
0.5
-
ns
Data-in Hold Time to DQS-In (DQ & DM)
tDH
0.45
-
0.5
-
ns
DQ & DM Input Pulse Width
tDIPW
1.75
-
1.75
-
ns
Read DQS Preamble Time
tRPRE
0.9
1.1
0.9
1.1
CK
Read DQS Postamble Time
tRPST
0.4
0.6
0.4
0.6
CK
Write DQS Preamble Setup Time
tWPRES
0
-
0
-
CK
Write DQS Preamble Hold Time
tWPREH
0.25
-
0.25
-
CK
Write DQS Postamble Time
tWPST
0.4
0.6
0.4
0.6
CK
Mode Register Set Delay
tMRD
2
-
2
-
CK
Exit Self Refresh to Any Execute Command
tXSC
200
-
200
-
CK
Average Periodic Refresh Interval
tREFI
-
7.8
-
7.8
us
Input Pulse Width
Rev. 0.4/ May. 02
Note
2,4,5,6
6
6,7,11,
12,13
8
30
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
Parameter
Symbol
DDR266A
DDR266B
DDR200
Min
Max
Min
Max
Min
Max
Unit
Row Cycle Time
tRC
65
-
65
-
70
-
ns
Auto Refresh Row Cycle Time
tRFC
75
-
75
-
80
-
ns
Row Active Time
tRAS
45
120K
45
120K
50
120K
ns
Active to Read with Auto Precharge Delay
tRAP
tRCD or
tRPmin
-
tRCD or
tRPmin
-
tRCD or
tRPmin
-
ns
Row Address to Column Address Delay
tRCD
20
-
20
-
20
-
ns
Row Active to Row Active Delay
tRRD
15
-
15
-
15
-
ns
Column Address to Column Address Delay
tCCD
1
-
1
-
1
-
CK
Row Precharge Time
tRP
20
-
20
-
20
-
ns
Write Recovery Time
tWR
15
-
15
-
15
-
ns
Write to Read Command Delay
tWTR
1
-
1
-
1
-
CK
Auto Precharge Write Recovery +
Precharge Time
tDAL
(tWR/tCK)
+
(tRP/tCK)
-
(tWR/tCK)
+
(tRP/tCK)
-
(tWR/tCK)
+
(tRP/tCK)
-
CK
7.5
12
7.5
12
8.0
12
ns
7.5
12
10
12
10
12
ns
System Clock Cycle Time
CL = 2.5
CL = 2
tCK
Note
16
15
Clock High Level Width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
CK
Clock Low Level Width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
CK
Data-Out edge to Clock edge Skew
tAC
-0.75
0.75
-0.75
0.75
-0.75
0.75
ns
DQS-Out edge to Clock edge Skew
tDQSCK
-0.75
0.75
-0.75
0.75
-0.75
0.75
ns
DQS-Out edge to Data-Out edge Skew
tDQSQ
-
0.5
-
0.5
-
0.6
ns
Data-Out hold time from DQS
tQH
tHP
-tQHS
-
tHP
-tQHS
-
tHP
-tQHS
-
ns
1,10
Clock Half Period
tHP
min
(tCL,tCH)
-
min
(tCL,tCH)
-
min
(tCL,tCH)
-
ns
1,9
tQHS
-
0.75
-
0.75
-
0.75
ns
10
Data Hold Skew Factor
Valid Data Output Window
tDV
Data-out high-impedance window from
CK,/CK
tHZ
-0.75
0.75
-0.75
0.75
-0.8
0.8
ns
17
Data-out low-impedance window from
CK, /CK
tLZ
-0.75
0.75
-0.75
0.75
-0.8
0.8
ns
17
Rev. 0.4/ May. 02
tQH-tDQSQ
tQH-tDQSQ
tQH-tDQSQ
ns
31
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
Parameter
Symbol
DDR266A
DDR266B
DDR200
Min
Max
Min
Max
Min
Max
Unit
Input Setup Time (fast slew rate)
tIS
0.9
-
0.9
-
1.1
-
ns
Input Hold Time (fast slew rate)
tIH
0.9
-
0.9
-
1.1
-
ns
Input Setup Time (slow slew rate)
tIS
1.0
-
1.0
-
1.1
-
ns
Input Hold Time (slow slew rate)
tIH
1.0
-
1.0
-
1.1
-
ns
tIPW
2.2
-
2.2
-
2.5
-
ns
Write DQS High Level Width
tDQSH
0.35
-
0.35
-
0.35
-
CK
Write DQS Low Level Width
tDQSL
0.35
-
0.35
-
0.35
-
CK
Clock to First Rising edge of DQS-In
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
CK
Data-In Setup Time to DQS-In (DQ & DM)
tDS
0.5
-
0.5
-
0.6
-
ns
Data-in Hold Time to DQS-In (DQ & DM)
tDH
0.5
-
0.5
-
0.6
-
ns
DQ & DM Input Pulse Width
tDIPW
1.75
-
1.75
-
2
-
ns
Read DQS Preamble Time
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
CK
Read DQS Postamble Time
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
CK
Write DQS Preamble Setup Time
tWPRES
0
-
0
-
0
-
CK
Write DQS Preamble Hold Time
tWPREH
0.25
-
0.25
-
0.25
-
CK
Write DQS Postamble Time
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
CK
Mode Register Set Delay
tMRD
2
-
2
-
2
-
CK
Exit Self Refresh to Any Execute Command
tXSC
200
-
200
-
200
-
CK
Average Periodic Refresh Interval
tREFI
-
7.8
-
7.8
-
7.8
us
Input Pulse Width
Rev. 0.4/ May. 02
Note
2,3,5,
6
2,4,5,
6
6
6,7,
11,12
,13
8
32
HY5DU56422A(L)T
HY5DU56822A(L)T
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Note :
1.
This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2.
Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3.
For command/address input slew rate>=1.0V/ns
4.
For command/address input slew rate>=0.5V/ns and <1.0V/ns
This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
Input Setup / Hold Slew-rate
Delta tIS
Delta tIH
V/ns
ps
ps
0.5
0
0
0.4
+50
0
0.3
+100
0
5.
CK, /CK slew rates are>=1.0V/ns
6.
These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by
design or tester correlation.
7.
Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.
8.
Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
9.
Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).
10. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of
tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects and p-channel to
n-channel variation of the output drivers.
11. This derating table is used to increase tDS/tDH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
Input Setup / Hold Slew-rate
Delta tDS
Delta tDH
V/ns
ps
ps
0.5
0
0
0.4
+75
+75
0.3
+150
+150
12. I/O Setup/Hold Plateau Derating. This derating table is used to increase tDS/tDH in case where the input level is flat below VREF
+/-310mV for a duration of up to 2ns.
I/O Input Level
Delta tDS
Delta tDH
mV
ps
ps
+280
+50
+50
13. I/O Setup/Hold Delta Inverse Slew Rate Derating. This derating table is used to increase tDS/tDH in case where the DQ and
DQS slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For example, if slew rate 1=
0.5V/ns and Slew Rate2=0.4V/n then the Delta Inverse Slew Rate=-0.5ns/V.
(1/SlewRate1)-(1/SlewRate2)
Delta tDS
Delta tDH
ns/V
ps
ps
Rev. 0.4/ May. 02
0
0
0
+/-0.25
+50
+50
+/- 0.5
+100
+100
33
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HY5DU561622A(L)T
14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal
transitions through the DC region must be monotonic.
15. tDAL = (tDPL / tCK ) + (tRP / tCK ). For each of the terms above, if not already an integer, round to the next highest integer.
tCK is equal to the actual system clock cycle time.
Example: For DDR266B at CL=2.5 and tCK = 7.5 ns,
tDAL = (15 ns / 7.5 ns) + (20 ns / 7.5 ns) = (2.00) + (2.67)
Round up each non-integer to the next highest integer: = (2) + (3), tDAL = 5 clocks
16. For the parts which do not has internal RAS lockout circuit, Active to Read with Auto precharge delay should be
tRAS - (BL/2) x tCK.
17. tHZ and tLZ transitions occur in the same access time windows as valid data trasitions. These parameters are not referenced
to a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ).
Rev. 0.4/ May. 02
34
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
CAPACITANCE (TA=25oC, f=100MHz )
Parameter
Pin
Symbol
Min
Max
Unit
Input Clock Capacitance
CK, /CK
CI1
2.0
3.0
pF
Delta Input Clock Capacitance
CK, /CK
Delta CI1
-
0.25
pF
Input Capacitance
All other input-only pins
CI1
2.0
3.0
pF
Delta Input Capacitance
All other input-only pins
Delta CI2
-
0.5
pF
Input / Output Capacitance
DQ, DQS, DM
CIO
4.0
5.0
pF
Delta Input / Output Capacitance
DQ, DQS, DM
Delta CIO
-
0.5
pF
Note :
1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V
2. Pins not under test are tied to GND.
3. These values are guaranteed by design and are tested on a sample basis only.
OUTPUT LOAD CIRCUIT
VTT
RT=50Ω
Output
Zo=50Ω
VREF
CL=30pF
Rev. 0.4/ May. 02
35
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
PACKAGE INFORMATION
400mil 66pin Thin Small Outline Package
Unit : mm(Inch)
11.94 (0.470)
11.79 (0.462)
10.26 (0.404)
10.05 (0.396)
BASE PLANE
22.33 (0.879)
22.12 (0.871)
0.65 (0.0256) BSC
1.194 (0.0470)
0.991 (0.0390)
0.35 (0.0138)
0.25 (0.0098)
0 ~ 5 Deg.
SEATING PLANE
0.15 (0.0059)
0.05 (0.0020)
0.597 (0.0235)
0.406 (0.0160)
0.210 (0.0083)
0.120 (0.0047)
Note : Package do not mold protrusion. Allowable protrusion of both sides is 0.4mm.
Rev. 0.4/ May. 02
36