ICMIC ICM7523M

ICM7563/7543/7523
12/10/8-Bit Low Power Quad DACs
With Serial Interface and Voltage Output
ICmic
IC MICROSYSTEMS
OVERVIEW
The ICM7563, ICM7543 and ICM7523 are 12-Bit, 10-Bit
and 8-Bit Voltage Output, Low Power, Quad DACs
respectively, with guaranteed monotonic behavior. These
DACs are available in 10 Lead MSOP package. They have
three
Software-Selectable
Power-Down
Output
Impedances (1 K Ohm, 100 K Ohm and Hi-Z) as additional
safety feature for applications that drive transducers or
valves. The operating supply range is 2.7V to 5.5V.
FEATURES
•
12/10/8-Bit Quad DAC in 10 Lead MSOP
Package
•
Ultra-Low Power Consumption
•
Guaranteed Monotonic
•
Wide Voltage Swing Output Buffer
•
Three-wire SPI/QSP and Microwire Interface
Compatible
•
Three Software-Selectable Power-Down Output
Impedances (1 K Ohm, 100 K Ohm and Hi-Z)
•
Schmitt-Triggered Inputs for Direct Interfacing to
Opto-couplers
The input interface is an easy to use three-wire SPI, QSPI
and Microwire compatible interface. The DAC has SchmittTriggered Inputs for Direct Interfacing to Opto-couplers
easily.
APPLICATION
•
Battery-Powered Applications
•
Industrial Process Control
•
Digital Gain and Offset Adjustment
BLOCK DIAGRAM
REFIN
ICM7563/7543/7523
x2
VOA
INPUT
REGISTER A
DAC
REGISTER A
DAC A
RESISTOR
NETWORK A
x2
VOB
INPUT
REGISTER B
DAC
REGISTER B
DAC B
RESISTOR
NETWORK B
x2
INPUT
REGISTER C
DAC
REGISTER C
VOC
DAC C
RESISTOR
NETWORK C
x2
INPUT
REGISTER D
DAC
REGISTER D
DAC D
RESISTOR
NETWORK D
INPUT CONTROL LOGIC, REGISTERS AND LATCHES
CS
Rev. A7
SDI
VOD
POWER DOWN CONTROL
SCK
ICmic reserves the right to change specifications without prior notice
ICM7563/7543/7523
PACKAGE
10 Lead MSOP
CS
SCK
1
10
VOD
2
9
VOC
VDD
3
8
VOB
GND
4
7
VOA
SDI
5
6
REFIN
TOP VIEW
PIN DESCRIPTION (10 Lead MSOP)
2
Pin
Name
I/O
Description
1
I
Active Low Chip Select (CMOS)
2
CS
SCK
I
Serial Clock Input (CMOS)
3
VDD
I
Supply Voltage
4
GND
I
Ground
5
SDI
I
Serial Data Input (CMOS)
6
REFIN
I
Reference Voltage Input to DAC A-B-C-D
7
VOA
O
DAC A Output Voltage
8
VOB
O
DAC B Output Voltage
9
VOC
O
DAC C Output Voltage
10
VOD
O
DAC D Output Voltage
Rev. A7
ICmic reserves the right to change specifications without prior notice
ICM7563/7543/7523
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VDD
Supply Voltage
-0.3 to 7.0
V
IIN
Input Current
VIN_
Digital Input Voltage (SCK, SDI , CLR , CS )
+/- 25.0
mA
-0.3 to 7.0
V
VIN_REF
Reference Input Voltage
-0.3 to 7.0
V
TSTG
Storage Temperature
-65 to +150
oC
TSOL
Soldering Temperature
300
oC
Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
ORDERING INFORMATION
Part
Operating Temperature Range
Package
ICM7563
-40 oC to 85 oC
10-Lead MSOP
ICM7543
-40 oC
to
85 oC
10-Lead MSOP
ICM7523
-40 oC
to
85 oC
10-Lead MSOP
DC ELECTRICAL CHARACTERISTICS
(VDD = 2.7V to 5.5V, VOUT unloaded; all specifications TMIN to TMAX unless otherwise noted)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
DC PERFORMANCE
ICM7563
N
Resolution
12
Bits
DNL
Differential Nonlinearity
(Notes 1 & 3)
0.4
+1.0
LSB
INL
Integral Nonlinearity
(Notes 1 & 3)
4.0
+12.0
LSB
ICM7543
N
Resolution
10
Bits
DNL
Differential Nonlinearity
(Notes 1 & 3)
0.1
+1.0
LSB
INL
Integral Nonlinearity
(Notes 1 & 3)
1.0
+3.0
LSB
ICM7523
N
Resolution
8
Bits
DNL
Differential Nonlinearity
(Notes 1 & 3)
0.05
+1.0
LSB
INL
Integral Nonlinearity
(Notes 1 & 3)
0.25
+0.75
LSB
STATIC ACCURACY
GE
Gain Error
+0.5
% of FS
OE
Offset Error
+25
mV
5
5.5
V
Full Scale at VDD=5..5
250
410
µA
Full Scale at VDD=3.6
210
390
µA
POWER REQUIREMENTS
VDD
Supply Voltage
IDD
Supply Current
Rev. A7
2.7
ICmic reserves the right to change specifications without prior notice
3
ICM7563/7543/7523
DC ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VOUT unloaded; all specifications TMIN to TMAX unless otherwise noted)
Symbol
Parameter
Test Conditions
Min
(Note 3)
0
Typ
Max
Unit
OUTPUT CHARACTERISTICS
Vout
Output Voltage Range
VOSC
Short Circuit Current
Rout
Output Impedance
VDD
V
60
150
mA
0.9
1
1.1
KΩ
Power-Down at 100 K Ohm
90
100
110
KΩ
VDD=2.7V to 5.5V
-3.0
0.4
3.0
mV/V
2.4
Power-Down at 1 K Ohm
Output Line Regulation
LOGIC INPUTS
VIH
Digital Input High
(Note 2)
VIL
Digital Input Low
(Note 2)
V
0.8
Digital Input Leakage
V
5
AC ELECTRICAL CHARACTERISTICS
(VDD = 2.7V to 5.5V, VOUT unloaded; all specifications TMIN to TMAX unless otherwise noted)
Symbol
SR
Parameter
Test Conditions
Min
Typ
Max
Unit
Slew Rate
2
V/µs
Settling Time
Mid-scale Transition Glitch
Energy
8
µs
nV-S
40
Linearity is defined from code 110 to 3990 (ICM7563)
Linearity is defined from code 16 to 1023 (ICM7543)
Linearity is defined from code 4 to 255 (ICM7523)
Guaranteed by design; not tested in production
See Applications Information
Note 1:
Note 2:
Note 3:
TIMING CHARACTERISTICS
(VDD = 2.7V to 5.5V, all specifications TMIN to TMAX unless otherwise noted)
Symbol
4
Parameter
Test Conditions
Min
Typ
Max
Unit
t1
SCK Cycle Time
(Note 2)
30
ns
t2
Data Setup Time
(Note 2)
10
ns
t3
Data Hold Time
(Note 2)
10
ns
t4
SCK Falling edge to
CS Rising
Edge
CS Falling Edge to SCK Rising Edge
(Note 2)
0
ns
t5
(Note 2)
15
ns
t6
CS Pulse Width
(Note 2)
20
ns
Rev. A7
ICmic reserves the right to change specifications without prior notice
ICM7563/7543/7523
SERIAL INTERFACE TIMING AND OPERATION DIAGRAM
t5
t1
t4
t6
CS
SCK
SDI
C3
t2
C2
C1
D0
t3
MSB
LSB
Figure 1. Serial Interface Timing Diagram
CS
(ENABLE
SCK)
(UPDATE
OUTPUT)
SCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SDI
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
MSB
D0
LSB
Figure 2. Serial Interface Operation Diagram
CONTENTS OF INPUT SHIFT REGISTER
DEVICE
BIT
CONTROL WORD
DATA WORD
MSB
LSB
ICM7563
12
C3
C2
C1
C0
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ICM7543
10
C3
C2
C1
C0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A1
A0
ICM7523
8
C3
C2
C1
C0
D7
D6
D5
D4
D3
D2
D1
D0
A3
A2
A1
A0
Figure 3. Contents of Input Shift Register
Rev. A7
ICmic reserves the right to change specifications without prior notice
5
ICM7563/7543/7523
0
0
0
0
DATA
(D11~D0)
(D9~D0)
(D7~D0
Data
A
Input Register transparent, data shifted to DAC register directly, VOA updated
0
0
0
1
Data
B
Input Register transparent, data shifted to DAC register directly, VOB updated
0
0
1
0
Data
C
Input Register transparent, data shifted to DAC register directly, VOC updated
0
0
1
1
Data
D
Input Register transparent, data shifted to DAC register directly, VOD updated
0
1
0
0
Data
A
Data Shifted to Input Register, VOA unchanged
0
1
0
1
Data
B
Data Shifted to Input Register, VOB unchanged
0
1
1
0
Data
C
Data Shifted to Input Register, VOC unchanged
0
1
1
1
Data
D
Data Shifted to Input Register, VOD unchanged
1
0
0
0
Data
A
Data Shifted from Input Register to DAC register, VOA updated
1
0
0
1
Data
B
Data Shifted from Input Register to DAC register, VOB updated
1
0
1
0
Data
C
Data Shifted from Input Register to DAC register, VOC updated
1
0
1
1
Data
D
Data Shifted from Input Register to DAC register, VOD updated
1
1
0
0
Data
All
Input Registers transparent, data shifted to DAC register directly, All OUT updated
1
1
0
1
Data
All
Data Shifted to Input Registers, All VOUT unchanged
1
1
1
0
Data
All
Data Shifted from Input Registers to DAC registers, All VOUT updated
1
1
1
1
X
All
Please see Power Down Mode Control Table
C3 C2 C1 C0
DAC
FUNCTION
Table 1. Serial Interface Input Word
CONTROL
DATA
C3 C2 C1 C0
D11~D5 D4
D9~D3 D2
D7~D1 D0
X
0
DAC
D3
D1
A3
0
D2
D0
A2
0
D1
A1
A1
0
D0 (7563)
A0 (7543)
A0 (7523)
0
FUNCTION
1
1
1
1
A
DAC O/P, wakeup
1
1
1
1
X
0
0
0
0
1
A
Floating Output
1
1
1
1
X
0
0
0
1
0
A
Output is terminated with 1KΩ
1
1
1
1
X
0
0
0
1
1
A
Output is terminated with100 KΩ
1
1
1
1
X
0
0
1
0
0
B
DAC O/P, wakeup
1
1
1
1
X
0
0
1
0
1
B
Floating Output
1
1
1
1
X
0
0
1
1
0
B
Output is terminated with 1KΩ
1
1
1
1
X
0
0
1
1
1
B
Output is terminated with100 KΩ
1
1
1
1
X
0
1
0
0
0
C
DAC O/P, wakeup
1
1
1
1
X
0
1
0
0
1
C
Floating Output
1
1
1
1
X
0
1
0
1
0
C
Output is terminated with 1KΩ
1
1
1
1
X
0
1
0
1
1
C
Output is terminated with100 KΩ
1
1
1
1
X
0
1
1
0
0
D
DAC O/P, wakeup
1
1
1
1
X
0
1
1
0
1
D
Floating Output
1
1
1
1
X
0
1
1
1
0
D
Output is terminated with 1KΩ
1
1
1
1
X
0
1
1
1
1
D
Output is terminated with100 KΩ
1
1
1
1
X
1
0
0
0
0
All
DAC O/P, wakeup
1
1
1
1
X
1
0
0
0
1
All
Floating Output
1
1
1
1
X
1
0
0
1
0
All
Output is terminated with 1KΩ
1
1
1
1
X
1
0
0
1
1
All
Output is terminated with100 KΩ
Table 2. Power Down Mode Control
6
Rev. A7
ICmic reserves the right to change specifications without prior notice
ICM7563/7543/7523
DETAILED DESCRIPTION
The ICM7563 is a 12-bit voltage output Quad DAC. The ICM7543 is the 10-bit version of this family and the ICM7523 is the 8-bit
version. These devices have a 16-bit input shift register and each DAC has a double buffered input.
This family of DACs has a guaranteed monotonic behavior. The operating supply range is from 2.7V to 5.5V.
Reference Input
The reference input accepts positive DC and AC signals. The voltage at REFIN sets the full-scale output voltage of all the DACs.
The reference input voltage range is from 0 to VDD-1.5V. The impedance at this pin is very high (greater than 10 M Ohm). Each
DACs output amplifier is configured in a gain of 2 configuration. This means that the full-scale output of each DAC will be 2x VREF.
To determine the output voltage for any code, use the following equation.
VOUT = 2 x (VREF x (D / (2n)))
Where D is the numeric value of DAC’s decimal input code, VREF is the reference voltage and n is number of bits, i.e. 12 for
ICM7563, 10 for ICM7543 and 8 for ICM7523.
Output Buffer Amplifier
The Quad DAC has 4 output amplifiers connected in a gain of 2 configuration. These amplifiers have a wide output voltage swing.
The actual swing of the output amplifiers will be limited by offset error and gain error. See the Applications Information Section for
a more detailed discussion.
The output amplifier can drive a load of 2.0 K Ω to VDD or GND in parallel with a 500 pF load capacitance.
The output amplifier has a full-scale typical settling time of 8 µs and it dissipates about 100 µA with a 3V supply voltage.
Serial Interface and Input Logic
This quad DAC family uses a standard 3-wire connection compatible with SPI/QSPI and Microwire interfaces. Data is always
loaded in 16-bit words which consist of 4 address and control bits (MSBs) followed by 12 bits (see Figure .3). The last 5 bits of
this 12 bit word are also used for power down control (see tables 1 and 2). Each DAC is double buffered with an input latch and
DAC latch.
Serial Data Input
SDI (Serial Data Input) pin is the data input pin for all DACs. Data is clocked in on the falling edge of SCK which has a Schmitt
trigger internally to allow for noise immunity on the SCK pin. This specially eases the use for opto-coupled interfaces.
The Chip Select pin which is the 1st pin of 10 MSOP package is active low. This pin frames the input data for synchronous loading
and must be low when data is being clocked into the part. There is an onboard counter on the clock input and after the 16th clock
pulse the data is automatically transferred to a 16-bit input latch and the 4 bit control word (C3~C0) is then decoded and the
appropriate DAC is updated or loaded depending on the control word (see Table 1). Chip Select pin must be pulled high (leveltriggered) and back low for the next data word to be loaded in. This pin also disables the SCK pin internally when pulled high.
The DAC has a double-buffered input with an input latch and a DAC latch. The DAC output will swing to its new value when data
is loaded into the DAC latch. The user has three options: loading only the input latch, updating the DAC with data previously
loaded into the input latch or loading the input latch and updating the DAC at the same time with a new code. The actual data that
gets loaded into the DAC latch is D11~D0 for the ICM7563, D9~D0 for the ICM7543 and D7~D0 for the ICM 7523.
Power-Down Mode
The DAC have three Software-Selectable Power-Down Output Impedances (1 K Ohm, 100 K Ohm and Hi-Z) as additional safety
feature for applications that drive transducers or valves. The power down can be done with loading the control word with 1111 (C0
to C3). Tthe selection of the Output Impedance of DAC is controlled by the last 5 bits. See Table 1 and Table 2 for details of
operation of this function.
Power-On Reset
There is a power-on reset on board that will clear the contents of all the latches to all 0s on power-up and the DAC voltage output
will go to ground.
APPLICATIONS INFORMATION
Rev. A7
ICmic reserves the right to change specifications without prior notice
7
ICM7563/7543/7523
Power Supply Bypassing and Layout Considerations
As in any precision circuit, careful consideration has to be given to layout of the supply and ground. The return path from the GND
to the supply ground should be short with low impedance. Using a ground plane would be ideal. The supply should have some
bypassing on it. A 10 µF tantalum capacitor in parallel with a 0.1 µF ceramic with a low ESR can be used. Ideally these would be
placed as close as possible to the device. Avoid crossing digital and analog signals, specially the reference, or running them close
to each other.
Output Swing Limitations
The ideal rail-to-rail DAC would swing from GND to VDD. However, offset and gain error limit this ability. Figure 4 illustrates how a
negative offset error will affect the output. The output will limit close to ground since this is single supply part, resulting in a deadband area. As a larger input is loaded into the DAC the output will eventually rise above ground. This is why the linearity is
specified for a starting code greater than zero.
Figure 5 illustrates how a gain error or positive offset error will affect the output when it is close to VDD. A positive gain error or
positive offset will cause the output to be limited to the positive supply voltage resulting in a dead-band of codes close to full-scale.
DEADBAND
NEGATIVE
OFFSET
Figure 4. Effect of Negative Offset
8
Rev. A7
ICmic reserves the right to change specifications without prior notice
ICM7563/7543/7523
OFFSET AND
GAIN ERROR
VDD
DEADBAND
POSITIVE
OFFSET
Figure 5. Effect of Gain Error and Positive Offset
Rev. A7
ICmic reserves the right to change specifications without prior notice
9
ICM7563/7543/7523
PACKAGE INFORMATION
10 Lead MSOP
10
Rev. A7
ICmic reserves the right to change specifications without prior notice
ICM7563/7543/7523
ORDERING INFORMATION
ICM75X3 P G
Device
6 - ICM7563
4 - ICM7543
2 - ICM7523
Rev. A7
G = RoHS Compliant Lead-Free package.
Blank = Standard package. Non lead-free.
Package
M = 10Lead MSOP
ICmic reserves the right to change specifications without prior notice
11