ETC CMI9738

CMI 9738
Integrated Multi-channel AC‘97
CMI9738 4CH Audio Codec
Preliminary
Specification
1. Description and Overview
Versatility
Alongside
CMI9738 is a 4CH AC97 CODEC, applicable for
packaging option, CMI9738 also offers SOP
currently mainstream MB chipsets of Intel, VIA,
24pin packaging, which helps to further cut the
Ali,
cost.
and
SIS.
CMI9738
is
ideal
for
offering
standard
LQFP
48pin
PC2001-compliant desktops, notebooks, and
More Audio Option
home entertainment PCs where high-quality
Last
audio is a must.
Sensaura® 3D audio option.
4CH Playback
the audio quality of CMI9738 is fabulous
The
specially-designed
4CH
hardware
but
not
least,
CMI9738
provides
In that regard,
beyond general expectation.
architecture of CMI9738 allows all types of south
bridge to playback 4CH audio, thus helping
commonplace south bridge get rid of the
limitation of 2CH audio playback capability
(patent pending both in Taiwan and United
States).
„Intel AC’97 Rev 2.2 compatible
„AC-Link Protocol compliance
„Full-Duplex Codec
„Earphone Buffer
Cost-effectiveness
As to the cost concern, CMI9738 integrates the
earphone buffer, analog CD differential interface,
and analog switch for rear channel audio to
Line-in.
Features
Simply by using 0.1uf decoupling
capacitor, CMI9738 meets PC2001 frequency
response requirements.
„Line-in/rear out share jack capability
„4 channels DAC
„48 LQFP Package and 24-Lead TSSOP
Package
„ Meet Microsoft’s  PC2001 requirements
„ Sensaura® 3D Enhancement(optional)
NC
AVdd2
REAR_OUT_L
TEST0#
REAR_OUT_R
AVss2
NC
NC
RESERVED
RESERVED
NC
NC
U2
CMI9738-LQFP-48
LINE_IN_R
LINE_IN_L
NC
MIC1
CD_R
CD_GND
CD_L
NC
NC
AUX_IN_R
AUX_IN_L
NC
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
SDATA_IN
SYNC
RESET#
AUX_IN_L
AUX_IN_R
CD_L
CD_GND
CD_R
MIC1
LINE_IN_L
LINE_IN_R
VREF_OUT
BIT_CLK
SDATA_OUT
XTL_OUT
XTL_IN
DVsdd
Vss
TEST0#
AVdd
LINE_OUT_R
LINE_OUT_L
XADCHR
XADCHL
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
DVdd1
XTL_IN
XTL_OUT
DVss1
SDATA_OUT
BIT_CLK
DVss2
SDATA_IN
DVdd2
SYNC
RESET#
NC
37
38
39
40
41
42
43
44
45
46
47
48
LINE_OUT_R
LINE_OUT_L
NC
NC
NC
NC
AFILT2
AFILT1
Vrefout
NC
AVss1
AVdd1
36
35
34
33
32
31
30
29
28
27
26
25
Pin Block Diagram
C-MEDIA Electronics Inc.
6F, 100, Sec. 4, Civil Boulevard, Taipei, Taiwan, R.O.C. 106
TEL: 886-2-8773-1100 FAX: 886-2-8773-2211 E-mail:[email protected]
Revision Date：Apr./2002
Revision
：1.1
CMI 9738
Integrated Multi-channel AC‘97
PIN DESCRIPTIONS
48-Pin LQFP
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Signal Name
DVdd1
XTL_IN
XTL_OUT
DVss1
SDATA_OUT
BIT_CLK
DVss2
SDATA_IN
DVdd2
SYNC
RESET#
NC
NC
AUX_IN_L
AUX_IN_R
NC
NC
CD_L
CD_GND
CD_R
MIC1
NC
LINE_IN_L
LINE_IN_R
24-Pin TSSOP
PIN #
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Signal Name
AVdd1
AVss1
NC
Vrefout
AFILT1
AFILT2
NC
NC
NC
NC
LINE_OUT_L
LINE_OUT_R
NC
AVdd2
REAR_OUT_L
TEST0#
REAR_OUT_R
AVss2
NC
NC
RESERVED
RESERVED
NC
NC
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Signal Name
SDATA_IN
SYNC
RESET#
AUX_IN_L
AUX_IN_R
CD_L
CD_GND
CD_R
MIC1
LINE_IN_L
LINE_IN_R
VREF_OUT
AFILT1
AFILT2
LINE_OUT_L
LINE_OUT_R
AVdd
TEST0#
Vss
DVsdd
XTL_IN
XTL_OUT
SDATA_OUT
BIT_CLK
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
C-MEDIA Electronics Inc.
6F, 100, Sec. 4, Civil Boulevard, Taipei, Taiwan, R.O.C. 106
TEL: 886-2-8773-1100 FAX: 886-2-8773-2211 E-mail:[email protected]
Revision Date：Apr./2002
Revision
：1.1
CMI 9738
Integrated Multi-channel AC‘97
CMI9738 Mixer Block Diagram
CD_L/R
CD_GND
LINE_IN_L/R
REAR OUT
18, 20
(6, 8)
19
(7)
23, 24
(10, 11)
21
(9)
SYNC
10
(2)
6
(24)
5
(23)
8
(1)
11
(3)
BIT_CLK
SDATA_OUT
SDATA_IN
RESET#
XTL_IN
XTL_OUT
2
(21)
3
(22)
FRONT OUT
SRC
DAC
Noise
Cancel
M
U
X
(LINE_IN/REAR_OUT)
BOOST
(+20dB)
MUTE
VOL
MUTE
VOL
MUTE
VOL
MUTE
VOL
MUTE
MASTER
VOLUME
/ MUTE
AC'97
Digital
Interface
OSC
Buf
39, 41
REAR_OUT_L/R
35, 36
(15, 16)
LINE_OUT_L/R
MUTE
Σ
MIC1
DAC
MUX
AUX_INL/R
14, 15
(4, 5)
SRC
MUX
Mixer Block Diagram
REAR OUT
Record
Gain
Control
Earphone
Buffer
XX : LQFP-48
(XX) : SSOP-24
MUTE
ADC
PCM IN
The CMI9738 mixer is designed to the AC’97 specification to manage playback and record
of all digital and analog audio sources in the PC environment. These include：
ŠSystem audio：digital PCM input and output for business, games, and multimedia
ŠCD/DVD：analog CD/DVD-ROM Redbook audio with internal connections to Codec mixer
ŠMono microphone：choice of desktop or headset mic, with programmable boost and gain
ŠSpeakerphone ： use of system mic & speakers for telephony, DSVD, and video
conferencing
ŠStereo line in：analog external line level source from consumer audio, video camera, etc
ŠAUX/synth：analog FM or wavetable synthesizer, or other internal source
SOURCE
FUNCTION
CONNECTION
MIC1
desktop microphone
from mic jack
LINE_IN
external audio source
from line in jack
CD
audio from CD-ROM drive
cable from CD-ROM
AUX
upgrade synth or other external source
internal connector
PCM out
digital audio output from AC '97 Controller
AC-link
Mix out
mix of all sources
AC ‘97 internal
LINE_OUT
stereo mix of all sources (front channel)
to output jack
REAR_OUT
stereo output of rear (surround) channel
to output jack
PCM in
digital audio input to AC '97 Controller
AC-link
C-MEDIA Electronics Inc.
6F, 100, Sec. 4, Civil Boulevard, Taipei, Taiwan, R.O.C. 106
TEL: 886-2-8773-1100 FAX: 886-2-8773-2211 E-mail:[email protected]
OUTPUT MIX SUPPORTS:
•stereo mix of all sources for LINE_OUT
•stereo output for REAR_OUT
INPUT MUX SUPPORTS:
•any mono or stereo source
•mono or stereo mix of all sources
Revision Date：Apr./2002
Revision
：1.1
CMI 9738
Integrated Multi-channel AC‘97
2. ORDERING INFORMATION
Part Number
CMI9738
CMI9738
Package
48-Pin LQFP
24 Pin-TSSOP
Outline Dimensions
9mm×7mm×1.6mm
7.9mm×6.5mm×1.1mm
Temperature Range
Supply Range
0 o C to +70 o C
0 o C to +70 o C
DVdd = 3.3V, AVdd = 5V
DVdd = 3.3V, AVdd = 5V
Dimensions shown in inches and （mm）
‹48-Lead Thin Plastic Quad Flatpack (LQFP)
‹24-Lead Plastic TSSOP
(ST-48)
(RU-24)
C-Media reserves the right to change specifications without notice.
C-MEDIA Electronics Inc.
6F, 100, Sec. 4, Civil Boulevard, Taipei, Taiwan, R.O.C. 106
TEL: 886-2-8773-1100 FAX: 886-2-8773-2211 E-mail:[email protected]
Revision Date：Apr./2002
Revision
：1.1
CMI 9738
Integrated Multi-channel AC‘97
TABLE OF CONTENTS
1. DESCRIPTION AND OVERVIEW
2. ORDERING INFORMATION
3. PIN/SIGNAL DESCRIPTIONS
3.1
3.1
3.2
3.3
1
4
8
8
8
8
9
10
10
10
10
11
12
14
17
19
20
20
21
22
28
29
29
29
29
30
31
32
32
33
33
33
34
34
35
35
DIGITAL I/O
ANALOG I/O
FILTER AND REFERENCE PINS
POWER AND GROUND SIGNALS
4. DIGITAL INTERFACE
4.1
4.2
4.3
4.4
4.5
4.6
AC_LINK
CLOCKING
RESETTING
AC-LINK DIGITAL SERIAL INTERFACE PROTOCOL
AC-LINK AUDIO INPUT FRAME（SDATA_IN）
AC-LINK AUDIO OUTPUT FRAME（SDATA_OUT）
4.7
AC-LINK LOW POWER MODE
5. CMI9738 MIXER
5.1
5.2
MIXER INPUT
MIXER OUTPUT
6. REGISTER INTERFACE
6.1
6.2
REGISTER DESCRIPTIONS
PIN DESCRIPTIONS
7. AC-LINK TIMING CHARACTERISTICS
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8.
8.1
8.2
8.3
8.4
8.5
8.6
COLD RESET
WARM RESET
CLOCKS
DATA SETUP AND HOLD
SIGNAL RISE AND FALL TIMES
AC-LINK LOW POWER MODE TIMING
ATE TEST MODE
ELECTRICAL SPECIFICATIONS
DC CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
MIXER CHARACTERISTICS
POWER CONSUMPTION
ANALOG PERFORMANCE CHARACTERISTICS
C-MEDIA Electronics Inc.
6F, 100, Sec. 4, Civil Boulevard, Taipei, Taiwan, R.O.C. 106
TEL: 886-2-8773-1100 FAX: 886-2-8773-2211 E-mail:[email protected]
Revision Date：Apr./2002
Revision
：1.1
9. REFERENCES
10. LIST OF FIGURES
CMI 9738
Integrated Multi-channel AC‘97
37
10
11
12
13
14
15
17
19
29
29
30
30
31
32
32
Figure 1. AC ‘97 connection to its companion controller
Figure 2. AC ‘97 Standard Bi-directional Audio Frame
Figure 3. AC-link Audio Input Frame
Figure 4. Start of an Audio Input Frame
Figure 5. AC-Link Audio Output Frame
Figure 6. Start of an Audio Output Frame
Figure 7. AC-link Powerdown Timing
Figure 8. CMI9738 Mixer Functional Diagram
Figure 9. Cold Reset timing diagram
Figure 10. Warm Reset
Figure 11. BIT_CLK to SYNC timing diagram
Figure 12. Data Setup and Hold
Figure 13. Signal rise and fall times diagram
Figure 14. AC-link low power mode timing diagram
Figure 15. ATE test mode timing diagram
11. LIST OF TABLES
8
8
9
9
20
22
28
28
29
30
30
31
31
32
32
33
33
33
34
35
Table 1. Digital Signal List
Table 2. Analog Signal List
Table 3. Filtering and Voltage References
Table 4. Power Signal List CMI9738
Table 5. Mixer Functional Connections
Table 6. Mixer Registers
Table 7. Cold Reset timing parameters
Table 8 Warm Reset
Table 9. Clocks
Table 10. Data setup and hold timing parameters
Table 11. Signal rise and fall times parameters
Table 12. AC-link low power mode timing parameters
Table 13. ATE test mode timing parameters
Table 14. DC Characteristics (relative to Vdd)
Table 15. DC Characteristics (3.3 V Operation as per PCI 2.2)
Table 16. Absolute Maximum Ratings
Table 17. Operating Conditions
Table 18. Mixer Characteristics
Table 19. Power Consumption
Table 20. Analog performance characteristics
C-MEDIA Electronics Inc.
6F, 100, Sec. 4, Civil Boulevard, Taipei, Taiwan, R.O.C. 106
TEL: 886-2-8773-1100 FAX: 886-2-8773-2211 E-mail:[email protected]
Revision Date：Apr./2002
Revision
：1.1
CMI 9738
Integrated Multi-channel AC‘97
3. PIN/SIGNAL DESCRIPTIONS
3.1 DIGITAL I/O
These signals connect the CMI9738 to its AC’97 Controller counterpart, an external crystal,
multi-codec selection and external audio amplifier.
Table 1. Digital Signal List
Signal Name
Type
Description
RESET#
I
AC’97 Master H/W Reset
XTL_IN
I
24.576 MHz Crystal
XTL_OUT
O
24.576 MHz Crystal
SYNC
I
48 kHz fixed rate sample sync
BIT_CLK
O
12.288 MHz serial data clock
SDATA_OUT
I
Serial, time division multiplexed, AC’97 input stream
SDATA_IN
O
Serial, time division multiplexed, AC’97 output stream
# denotes active low
3.2 ANALOG I/O
These signals connect the CMI9738 to analog sources and sinks, including microphones and
speakers.
Table 2. Analog Signal List
Signal Name Type
Description
AUX_IN_L
I
Aux Left Channel
AUX_IN_R
I
Aux Right Channel
CD_L
I
CD Audio Left Channel
CD_R
I
CD Audio Right Channel
CD_GND
I
CD Audio analog ground
MIC1
I
Desktop Microphone Input
LINE_IN_L
I
Line In Left Channel
LINE_IN_R
I
Line In Right Channel
LINE_OUT_L
O
Line Out Left Channel
LINEOUT_R
O
Line Out Right Channel
REAR_OUT_L O
Rear Out Left Channel
REAR_OUT_R O
Rear Out Right Channel
3.3 FILTERAND REFERENCE PINS
These signals are connected to resistors, capacitors, or specific voltages, or provide general
purpose I/O.
Table3. Filtering and Voltage References
Signal Name Type
Description
Vrefout
O
Reference Voltage out 5mA drive (intended for mic bias)
AFLIT1
O
Anti-Aliasing Filter Cap - ADC channel & Sampling hold
AFLIT2
O
Anti-Aliasing Filter Cap - ADC channel & Sampling hold
C-MEDIA Electronics Inc.
6F, 100, Sec. 4, Civil Boulevard, Taipei, Taiwan, R.O.C. 106
TEL: 886-2-8773-1100 FAX: 886-2-8773-2211 E-mail:[email protected]
Revision Date：Apr./2002
Revision
：1.1
CMI 9738
Integrated Multi-channel AC‘97
3.4 POWER AND GROUND SIGNALS
Table4. Power Signal List CMI9738
Description
Analog Vdd ＝ 5V
Signal Name
AVdd1
Type
I
AVdd2
I
Analog Vdd ＝ 5V
Avss1
I
Analog Gnd
Avss2
I
DVdd1
I
Analog Gnd
Digital Vdd ＝ 3.3V
DVdd2
I
Digital Vdd ＝ 3.3V
DVss1
I
Digital Gnd
DVss2
I
Digital Gnd
C-MEDIA Electronics Inc.
6F, 100, Sec. 4, Civil Boulevard, Taipei, Taiwan, R.O.C. 106
TEL: 886-2-8773-1100 FAX: 886-2-8773-2211 E-mail:[email protected]
Revision Date：Apr./2002
Revision
：1.1
CMI 9738
Integrated Multi-channel AC‘97
4. DIGITAL INTERFACE
4.1 AC-LINK
All digital audio streams, optional modem line Codec streams, and command/status information
are communicated over this AC-Link. A breakout of the signals connecting the two is shown in
Figure .
Figure1. AC ‘97 connection to its companion controller
Digital
DC’97
Controller
SYNC
BIT_CLK
SDTA_OUT
SDATA_IN
RESET#
XTAL_IN
AC’97
Codec
XTAL_OUT
4.2 CLOCKING
CMI9738 derives its clock internally from an externally connected 24.576 MHz crystal or an
oscillator through the XTAL_IN pin. Synchronization with the AC’97 controler is achieved
through the BIT_CLK pin at 12.288 MHz（half of crystal frequency）.
The beginning of all audio sample packets, or Audio Frames, transferred over AC-link is
synchronized to the rising edge of the “SYNC” signal. “SYNC” is driven by the AC ’97
Controller. Data is transitioned on AC-link on everyrising edge of BIT_CLK, and subsequently
sampled on the receiving side of AC-link on each immediately followingfalling edge of
BIT_CLK.
4.3 RESETTING
There are three types of reset as detailed under “Timing Characteristics”：
1. a cold reset where all CMI9738 logic (registers included) is initialized to its default state
2. a warm reset where the contents of the CMI9738 register set are left unaltered
3. a register reset which only initializes the CMI9738 registers to their default states
After signaling a reset to the CMI9738, the AC’97 Controller should not attempt to play or
capture audio data until it has sampled a “Codec Ready” indication via register 26h from the
CMI9738.
Notice：When the AC-link “Codec Ready” indicator bit (SDATA_IN slot 0, bit 15) is a 1 it
indicates that the AC-link and AC ‘97 control and status registers are in a fully
operational state.
C-MEDIA Electronics Inc.
6F, 100, Sec. 4, Civil Boulevard, Taipei, Taiwan, R.O.C. 106
TEL: 886-2-8773-1100 FAX: 886-2-8773-2211 E-mail:[email protected]
Revision Date：Apr./2002
Revision
：1.1
CMI 9738
Integrated Multi-channel AC‘97
4.4 AC-LINK DIGITAL SERIAL INTERFACE PROTOCOL
The CMI9738 communicates to the AC'97 controller via a 5-pin digital serial AC-Link
interface,which is a bi-directional, fixed rate, serial PCM digital stream. All digital audio streams,
commandsand status information are communicated over this point-to-point serial interconnect.
The AC-Linkhandles multiple inputs, and output audio streams, as well as control register
accesses using a timedivision multiplexed (TDM) scheme. The AC'97 controller synchronizes all
AC-Link data transaction.The following data streams are available on the CMI9738：
· SDATA_OUT TAG
1 output slot (0)
· SDATA_IN TAG
1 input slot (0)
· Status (STATUS ADDR & DATA) read port
2 input slots (1,2)
· PCM L & R DAC Playback
2 output slots (3,4)
· PCM L & R ADC Record
2 input slots (3,4)
Figure2. AC ‘97 Standard Bi-directional Audio Frame
Synchronization of all AC-Link data transactions is handled by the AC'97 controller. The
CMI9738 drives the serial bit clock onto AC-Link. The AC'97 controller then qualifies with a
synchronization signal to construct audio frames.
SYNC, fixed at 48 kHz, is derived by dividing down the serial bit clock (BIT_CLK). BIT_CLK,
fixed at 12.288 MHz, provides the necessary clocking granularity to support 12, 20-bit outgoing
and incoming time slots. AC-Link serial data is transitioned on each rising edge of BIT_CLK. The
receiver of AC-Link data, CMI9738 for outgoing data and AC'97 controller for incoming data,
samples each serial bit on the falling edges of BIT_CLK.
The AC-Link protocol provides for a special 16-bit (13-bits defined, with 3 reserved trailing bit
positions) time slot (Slot 0) wherein each bit conveys a valid tag for its corresponding time slot
within the current audio frame. A “1” in a given bit position of slot 0 indicates that the
corresponding time slot within the current audio frame has been assigned to a data stream, and
contains valid data. If a slot is “tagged” invalid, it is the responsibility of the source of the data
(CMI9738 for the input stream, AC'97 controller for the output stream) to stuff all bit positions
with 0’s during that slot’sactive time.
C-MEDIA Electronics Inc.
6F, 100, Sec. 4, Civil Boulevard, Taipei, Taiwan, R.O.C. 106
TEL: 886-2-8773-1100 FAX: 886-2-8773-2211 E-mail:[email protected]
Revision Date：Apr./2002
Revision
：1.1
CMI 9738
Integrated Multi-channel AC‘97
SYNC remains high for a total duration of 16 BIT_CLKs at the beginning of each audio frame.
Theportion of the audio frame where SYNC is high is defined as the “Tag Phase”. The remainder
of theaudio frame where SYNC is low is defined as the “Data Phase”.
Additionally, for power savings, all clock, sync, and data signals can be halted.
4.5 AC-LINK AUDIO INPUT FRAME（SDATA_IN）
The audio input frame data streams correspond to the multiplexed bundles of all digital input data
targeting the AC’97 Controller. As is the case for audio output frame, each AC-link audio input
frame consists of 12, 20-bit timeslots. Slot 0 is a special reserved time slot containing 16-bits
which are used for AC-link protocol infrastructure.
Within slot 0 the first bit is a global bit (SDATA_IN slot 0, bit 15) which flags whether CMI9738
is in the “CodecReady” state or not. If the “Codec Ready” bit is a 0, this indicates thatCMI9738 is
not ready for normal operation. This condition is normal following the deassertion of power on
reset for example, while CMI9738’s voltage references settle. When the AC-link “Codec Ready”
indicator bit is a 1 it indicates that the AC-link and CMI9738 control and status registers are in a
fully operational state. The AC ‘97 Controller must further probe the Powerdown Control/Status
Register (section 6.3) to determine exactly which subsections, if any, are ready.
Prior to any attempts at putting CMI9738 into operation the AC ’97 Controller should poll the
first bit in the audio input frame (SDATA_IN slot 0, bit 15) for an indication that CMI9738 has
gone “Codec Ready”. Once CMI9738 is sampled “Codec Ready”8 then the next 12 bit positions
sampled by the AC ’97 Controller indicate which of the corresponding 12 time slots are assigned
to input data streams, and that they contain valid data. The following diagram illustrates the time
slot-based AC-link protocol.
Figure3. AC-link Audio Input Frame
C-MEDIA Electronics Inc.
6F, 100, Sec. 4, Civil Boulevard, Taipei, Taiwan, R.O.C. 106
TEL: 886-2-8773-1100 FAX: 886-2-8773-2211 E-mail:[email protected]
Revision Date：Apr./2002
Revision
：1.1
CMI 9738
Integrated Multi-channel AC‘97
A new audio input frame begins with a low to high transition of SYNC. SYNC is synchronous to
the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, CMI9738
samples the assertion of SYNC. This falling edge marks the time when both sides of AC-link are
aware of the start of a new audio frame. On the next rising of BIT_CLK, the CMI9738 transitions
SDATA_IN into the first bit position of slot 0 (“Codec Ready” bit). Each new bit position is
presented to AC-link on a rising edge of BIT_CLK, and subsequently sampled by the AC ’97
Controller on the following falling edge of BIT_CLK. This sequence ensures that data transitions
and subsequent sample points for both incoming and outgoing data streams are time aligned.
Figure4. Start of an Audio Input Frame
SDATA_IN's composite stream is MSB justified (MSB first) with all non-valid bit positions (for
assigned and/or unassigned time slots) stuffed with 0's by CMI9738. SDATA_IN data is sampled
on the falling edges of BIT_CLK.
Slot 1: Status Address Port
The status port is used to monitor status for CMI9738 functions including, but not limited to,
mixer settings and power management (refer to section 6.3 of this specification).
Audio input frame slot 1’s stream echoes the control register index, for historical reference, for the
data to be returned in slot 2. (Assuming that slots 1 and 2 had been tagged “valid” by CMI9738
during slot 0.)
Status Address Port bit assignments:
Bit（19）
RESERVED
(Stuffed with 0)
Bit（18；12）Control Register Index (Echo of register index for which data is being returned)
Bit（11：0） RESERVED
(Stuffed with 0’s)
The first bit (MSB) generated by CMI9738 is always stuffed with a 0. The following 7 bit
positions communicate the associated control register address, and the trailing 12 bit positions are
stuffed with 0's by CMI9738.
Slot 2: Status Data Port
The status data port delivers 16-bit control register read data.
C-MEDIA Electronics Inc.
6F, 100, Sec. 4, Civil Boulevard, Taipei, Taiwan, R.O.C. 106
TEL: 886-2-8773-1100 FAX: 886-2-8773-2211 E-mail:[email protected]
Revision Date：Apr./2002
Revision
：1.1
CMI 9738
Integrated Multi-channel AC‘97
Bit（19：4）
Control Register Read Data
(Stuffed with 0’s if tagged “invalid”)
Bit（3：0）
RESERVED
(Stuffed with 0’s)
If Slot 2 is tagged invalid by CMI9738, then the entire slot will be stuffed with 0’s.
Slot 3: PCM Record Left Channel
Audio input frame slot 3 is the left channel output of CMI9738 input MUX, post-ADC.
CMI9738 ADCs are implemented to support 18-bit resolution.
CMI9738 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions
with 0's to fill out its 20-bit time slot.
Slot 4: PCM Record Right Channel
Audio input frame slot 4 is the right channel output of CMI9738 input MUX, post-ADC.
CMI9738 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions
with 0's to fill out its 20-bit time slot.
Slot 5: Optional Modem Line 1 ADC
Audio input frame slots 5-12 are not used by the CMI9738 and are always stuffed with 0's.
4.6 AC-LINK AUDIO OUTPUT FRAME（SDATA_OUT）
The audio output frame data streams correspond to the multiplexed bundles of all digital output
data targeting the CMI9738 DAC inputs, and control registers. Each audio output frame supports
up to 12 20-bit outgoing data time slots. Slot 0 is a special reserved time slot containing 16 bits
that are used for AC-Link protocol infrastructure.
Within slot 0, the first bit is a global bit (SDATA_OUT slot 0, bit 15) which flags the validity for
the entire audio frame. If the “Valid Frame” bit is a 1, this indicates that the current audio frame
contains at least one slot time of valid data. The next 12 bit positions sampled by the CMI9738
indicate which of the corresponding 12 times slots contain valid data. In this way data streams of
differing sample rates can be transmitted across AC-Link at its fixed 48kHz audio frame rate. The
following diagram illustrates the time slot based AC-Link protocol.
Figure5 . AC-Link Audio Output Frame
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Integrated Multi-channel AC‘97
A new audio output frame begins with a low to high transition of SYNC. SYNC is synchronous to
the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the
CMI9738 samples the assertion of SYNC. This following edge marks the time when both sides of
AC-Link are aware of the start of a new audio frame. On the next rising edge of BIT_CLK, the
AC'97 controller transitions SDATA_OUT into the first bit position of slot 0 (Valid Frame bit).
Each new bit position is presented to AC-Link on a rising edge of BIT_CLK, and subsequently
sampled by the CMI9738 on the following falling edge of BIT_CLK. This sequence ensures that
data transitions, and subsequent sample points for both incoming and outgoing data streams are
time aligned.
Figure 6. Start of an Audio Output Frame
SDATA_OUT’s composite stream is MSB justified (MSB first) with all non-valid slots’ bit
positions AC'97 controller. When mono audio sample streams are sent from the AC'97 controller
it is necessary that BOTH left and right sample stream time slots be filled with the same data.
Slot 1: Command Address Port
The command port is used to control features, and monitor status (see Audio Input Frame Slots 1
and 2) of the CMI9738 functions including, but not limited to, mixer settings, and power
management (refer to the control register section of this specification).
The control interface architecture supports up to 64 16-bit read/write registers, addressable on
even byte boundaries. Only the even registers (00h, 02h, etc.) are valid.
Audio output frame slot 1 communicates control register address, and write/read command
information to the CMI9738.
Command Address Port bit assignments：
Bit（19）
Read/Write command
(1=read, 0=write)
Bit（18：12） Control Register Index (64 16-bit locations, addressed on even byte boundaries)
Bit（11：0） Reserved
(Stuffed with 0’s)
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CMI 9738
Integrated Multi-channel AC‘97
The first bit (MSB) sampled by CMI9738 indicates whether the current control transaction is a
read or a write operation. The following 7 bit positions communicate the targeted control register
address. The trailing 12 bit positions within the slot are reserved and must be stuffed with 0’s by
the AC ’97 Controller.
Slot 2: Command Data Port
The command data port is used to deliver 16-bit control register write data in the event that the
current command port operation is a write cycle. (as indicated by Slot 1, bit 19)
Bit（19：4） Control Register Write Data
Bit（3：0） Reserved
(Stuffed with 0's if current operation is a read)
(Stuffed with 0's)
If the current command port operation is a read then the entire slot time must be stuffed with 0's
by the AC'97 controller.
Slot 3: PCM Playback Left Channel
“Games Compatible" PC this slot is composed of standard PCM (.wav) output samples digitally
mixed (by the AC'97 controller or host processor) with music synthesis output samples. If a
sample stream of resolution less than 20-bits is transferred, the AC'97 controller must stuff all
trailing non-valid bit positions within this time slot with 0's.
Slot 4: PCM Playback Right Channel
Audio output frame slot 4 is the composite digital audio right playback stream. In a typical
“Games Compatible" PC this slot is composed of standard PCM (.wav) output samples digitally
mixed (by the AC'97 controller or host processor) with music synthesis output samples. If a
sample stream of resolution less than 20-bits is transferred, the AC'97 controller must stuff all
trailing non-valid bit positions within this time slot with 0's.
Slot 5: Reserved
Audio output frame slot 5 is reserved for modem operation and is not used by the CMI9738.
Slot 6: PCM Center Channel
Audio output frame slot 6 is not used by the CMI9738.
Slot 7: PCM Left Surround Channel
Slot 7 carries PCM left surround data in 4 channel wave output.
Slot 8: PCM Right Surround Channel
Slot 8 carries PCM right surround data in 4 channel wave output.
Slot 9: PCM Low Frequency Channel
Audio output frame slot 9 is not used by the CMI9738.
Slot 10: PCM Alternate Left
Audio output frame slot 10 is not used by the CMI9738.
Slot 11: PCM Alternate Right
Audio output frame slot 11 is not used by the CMI9738.
Slot 12: Reserved
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CMI 9738
Integrated Multi-channel AC‘97
Audio output frame slot 12 is reserved for modem operations and is not used by the CMI9738.
4.7 AC-LINK LOW POWER MODE
The CMI9738 AC-Link can be placed in the low power mode by programming register 26h to the
appropriate value. Both BIT_CLK and SDATA_IN will be brought to, and held at a logic low
voltage level. The AC'97 controller can wake up the CMI9738 by providing the appropriate reset
signals.
Figure 7. AC-link Powerdown Timing
BIT_CLK and SDATA_IN are transitioned low immediately (within the maximum specified time)
following the decode of the write to the Powerdown Register (26h) with PR4. When the AC'97
controller driver is at the point where it is ready to program the AC-Link into its low power mode,
slots (1 and 2) are assumed to be the only valid stream in the audio output frame (all sources of
audio input have been neutralized).
The AC'97 controller should also drive SYNC and SDATA_OUT low after programming the
CMI9738 to this low power mode.
Waking up the AC-link
Once the CMI9738 has halted BIT_CLK, there are only two ways to “wake up” the AC-Link.
Both methods must be activated by the AC'97 controller. The AC-Link protocol provides for a
“Cold AC'97 Reset”, and a “Warm AC'97 Reset”. The current power down state would ultimately
dictate which form of reset is appropriate. Unless a “cold” or “register” reset (a write to the Reset
register) is performed, wherein the AC'97 registers are initialized to their default values, registers
are required to keep state during all power down modes. Once powered down, re-activation of the
AC-Link via re- assertion of the SYNC signal must not occur for a minimum of 4 audio frame
times following the frame in which the power down was triggered. When AC-Link powers up it
indicates readiness via the Codec Ready bit (input slot 0, bit 15).
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CMI 9738
Integrated Multi-channel AC‘97
Cold AC ‘97 Reset Î a cold reset is achieved by asserting RESET# for the minimum specified
time. By driving RESET# low, BIT_CLK, and SDATA_IN will be
activated, or re-activated as the case may be, and all CMI9738 control
registers will be initialized to their default power on reset values.
Note: RESET# is an asynchronous input.
# denotes active low
Warm AC’97 Reset Îa warm reset will re-activate the AC-Link without altering the current
CMI9738 register values. A warm reset is signaled by driving SYNC high
for a minimum of 1us in the absence of BIT_CLK.
Note: Within normal audio frames, SYNC is a synchronous input. However, in the absence of
BIT_CLK, SYNC is treated as an asynchronous input used in the generation of a warm reset
to the CMI9738.
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Revision Date：Apr./2002
Revision
：1.1
CMI 9738
Integrated Multi-channel AC‘97
5. CMI9738 MIXER
The CMI9738 mixer is designed to the AC’97 specification to manage playback and record of all
digital and analog audio sources in the PC environment. These include：
ŠSystem audio：digital PCM input and output for business, games, and multimedia
ŠCD/DVD：analog CD/DVD-ROM Redbook audio with internal connections to Codec mixer
ŠMono microphone：choice of desktop or headset mic, with programmable boost and gain
ŠSpeakerphone：use of system mic & speakers for telephony, DSVD, and video conferencing
ŠStereo line in：analog external line level source from consumer audio, video camera, etc
ŠAUX/synth：analog FM or wavetable synthesizer, or other internal source
Figure 8. CMI9738 Mixer Functional Diagram
CD_L/R
CD_GND
LINE_IN_L/R
REAR OUT
18, 20
(6, 8)
19
(7)
23, 24
(10, 11)
21
(9)
SYNC
10
(2)
6
(24)
5
(23)
8
(1)
11
(3)
BIT_CLK
SDATA_OUT
SDATA_IN
RESET#
XTL_IN
XTL_OUT
2
(21)
3
(22)
FRONT OUT
SRC
DAC
Noise
Cancel
M
U
X
(LINE_IN/REAR_OUT)
BOOST
(+20dB)
MUTE
VOL
MUTE
VOL
MUTE
VOL
MUTE
VOL
MUTE
MASTER
VOLUME
/ MUTE
AC'97
Digital
Interface
OSC
PCM IN
Buf
39, 41
REAR_OUT_L/R
35, 36
(15, 16)
LINE_OUT_L/R
MUTE
Σ
MIC1
DAC
MUX
AUX_INL/R
14, 15
(4, 5)
SRC
MUX
Mixer Block Diagram
REAR OUT
Record
Gain
Control
Earphone
Buffer
XX : LQFP-48
(XX) : SSOP-24
MUTE
ADC
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Revision
：1.1
CMI 9738
Integrated Multi-channel AC‘97
Table 5. Mixer Functional Connections
SOURCE
FUNCTION
CONNECTION
MIC1
LINE_IN
CD
AUX
PCM out
Mix out
LINE_OUT
REAR_OUT
PCM in
desktop microphone
external audio source
audio from CD-ROM drive
upgrade synth or other external source
digital audio output from AC '97 Controller
mix of all sources
stereo mix of all sources (also front channel)
stereo output of rear (surround) channel
digital audio input to AC '97 Controller
from mic jack
from line in jack
cable from CD-ROM
internal connector
AC-link
AC ‘97 internal
to output jack
to output jack
AC-link
OUTPUT MIX SUPPORTS:
•stereo mix of all sources for LINE_OUT
•stereo output for REAR_OUT
INPUT MUX SUPPORTS:
•any mono or stereo source
•mono or stereo mix of all sources
5.1 MIXER INPUT
The CMI9738’s mixer input is a MUX design which offers the capability to record audio sources or
the outgoing mix of all sources. This design is more efficient to implement than an independent
input mix, and offers simple monitoring when a mix is recorded: what you hear is what you get
(WYHIWYG). The CMI9738 supports the following input sources：
‹any mono or stereo source
‹mono or stereo mix of all sources
5.2 MIXER OUTPUT
The mixer generates two distinct outputs:
‹a stereo mix of all sources for output to the LINE_OUT
‹a stereo output of rear (surround) channel for REAR_OUT
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Revision Date：Apr./2002
Revision
：1.1
CMI 9738
Integrated Multi-channel AC‘97
6. REGISTER INTERFACE
Table 6. Mixer Registers
Reg
NUM
Name
00h Reset
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 Default
ID4
ID3
ID2
ID1
ID0
0000h
X
SE4
SE3
SE2
SE1
SE0
ID9
ID8
ID7
ID6
ID5
Mute
X
X
ML4
ML3
ML2
ML1
ML0
X
X
X
MR4 MR3 MR2 MR1 MR0
0000h
Mute
X
X
ML4
ML3
ML2
ML1
ML0
X
X
X
MR4 MR3 MR2 MR1 MR0
8000h
0Eh Mic Volume
Mute
X
X
X
X
X
X
X
X
20dB
X
X
GN3 GN2 GN1 GN0
8008h
10h LineIn Volume
Mute
X
X
X
GL3
GL2
GL1
GL0
X
X
X
X
GR3 GR2 GR1 GR0
8808h
12h CD Volume
Mute
X
X
X
GL3
GL2
GL1
GL0
X
X
X
X
GR3 GR2 GR1 GR0
8808h
16h Aux Volume
Mute
X
X
X
GL3
GL2
GL1
GL0
X
X
X
X
GR3 GR2 GR1 GR0
8808h
18h PCM Out Vol
Mute
X
X
X
GL3
GL2
GL1
GL0
X
X
X
X
GR3 GR2 GR1 GR0
8808h
1Ah Record Select
X
X
X
X
X
SL2
SL1
SL0
X
X
X
X
Mute
X
X
X
GL3
GL2
GL1
GL0
X
X
X
X
X
X
X
X
X
X
X
X
LPBK
X
X
X
X
X
PR6
PR5
PR4
PR3
PR2
PR1
PR0
X
X
X
X
REF
ID1
ID0
X
X
X
X
X
X
X
X
X
X
X
X
X
0080h
X
X
X
X
X
X
X
1000h
X
X
02h Master Volume
04h
Surround Mixer
Volume
1Ch Record Gain
20h General Purpose
26h
28h
2Ah
38h
5Ah
X
SR2
SR0
0000h
GR3 GR2 GR1 GR0
8000h
X
SR1
X
X
0000h
Powerdown
Ctrl/Stat
Extended Audio
ID
C
SDA
X
X
X
PRJ
X
X
X
X
C
4CH Vol:L,R Surr
RSR RSR RSR RSR RSR
Mute
X
X
LSR4 LSR3 LSR2 LSR1 LSR0 Mute
Vendor defined
Control
000Xh
SDA
Ext’d audio
Stat/Ctrl
ANL DAC ADC
8080h
4
3
2
1
0
S2LN
X
X
F2R
X
X
X
X
X
X
X
X
X
X
X
X
0000h
S7
S6
S5
S4
S3
S2
S1
S0
434Dh
I
7Ch Vendor ID1
F7
F6
F5
F4
F3
F2
F1
F0
7Eh Vendor ID2
T7
T6
T5
T4
T3
T2
T1
T0
REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0
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：1.1
4941h
CMI 9738
Integrated Multi-channel AC‘97
6.1 Register Descriptions
Reset Register (Index 00h) (Read Only)
Reg Name D15 D14 D13 D12 D11 D10 D9
00h Reset
X
D8
D7
D6
D5
D4
D3
D2
D1
D0 Default
SE4 SE3 SE2 SE1 SE0 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 0000h
No Hardware 3D : SE4…SE0 = 00000b
16 bit ADC & DAC : ID9…ID0 = 0000000000b
Writing this register will reset the mixer register.
Master Volume Registers (Index 02h, 04h and 06h)
Reg
Name
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
Mut
02h Master Volume
04h
e
Surround
Mut
Mixer Volume
e
X
X
X
X
ML ML ML ML ML
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
MR MR MR MR MR
4
3
2
1
0
X
X
X
X1
X
0000h
8000h
‹Each step corresponds to 1.5 dB. The MSB of the register is the mute bit. When this bit is set to 1
the level for that channel is set at －∞ dB.
‹Support for the MSB of the level is optional. If the MSB is not supported then AC ‘97 needs to
detect when that bit is set and set all four LSBs to 1s. Example: If AC ‘97 only supports 5 bits of
resolution in its mixer and the driver writes a 1xxxxx AC ‘97 must interpret that as x11111. It will
also respond when read with x11111 rather
‹then 1xxxxx, the value writen to it. The driver can use this feature to detect if support for the 6th
bit is there or not. The 02h default value is 0000h (0000 0000 0000 0000) , which corresponds to
+12 dB gain with mute off.
Mute
Mx5...Mx0
Function
0
000000
+12 dB gain
0
000001
+10.5 dB gain
0
001000
0 dB Attenuation
0
0
0
1
011110
011111
111111
xxxxxx
33.0dB Attenuation
46.5dB Attenuation
46.5dB Attenuation
∞ dB Attenuation
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：1.1
CMI 9738
Integrated Multi-channel AC‘97
Analog Mixer Input Gain Registers (Index 0Eh - 18h) (R/W)
Reg
Name
D15 D14 D13 D12 D11 D10 D9
D5
D4
X
X RM3 RM2 RM1 RM0 X 20dB X
X
GN3 GN2 GN1 GN0 8008h
Mute X
X
X GL3 GL2 GL1 GL0 X
X
X
X
GR3 GR2 GR1 GR0 8808h
CD Volume Mute X
X
X GL3 GL2 GL1 GL0 X
X
X
X
GR3 GR2 GR1 GR0 8808h
16h Aux Volume Mute X
X
X GL3 GL2 GL1 GL0 X
X
X
X
GR3 GR2 GR1 GR0 8808h
X
X GL3 GL2 GL1 GL0 X
X
X
X
GR3 GR2 GR1 GR0 8808h
0Eh Mic Volume Mute X
LineIn
Volume
10h
12h
PCM Out
Vol
18h
Mute X
D8
D7
D6
D3
D2
D1
D0 Default
The MSB of the register is the mute bit. When this bit is set to 1 the level for that channel is set at
－∞ dB.
Register 0Eh (Mic Volume Register) has an extra bit that is for a 20 dB boost. When bit 6 is set to 1
the 20 dB boost is on. The default value is 8008, which corresponds to 0 dB gain with mute on.
Mute
Mx3...Mx0
Function
0
0000
0 dB Attenuation
0
0001
2dB Attenuation
0
1111
32dB Attenuation
1
xxxx
∞ dB Attenuation
Record Select Control Register (Index 1Ah) (R/W)
Reg
Name
D15 D14 D13 D12 D11 D10 D9
1Ah Record Select
X
X
X
X
X
D8
D7
D6
D5
D4
D3
D2
D1
D0 Default
SL2 SL1 SL0
X
X
X
X
X
SR2 SR1 SR0 0000h
The default value is 0000h, which corresponds to Mic in.
SR2...SR0
Right Record Source
SL2...SL0
Left Record Source
0
Mic
0
Mic
1
CD In (R)
1
CD In (L)
2
N/A
2
N/A
3
Aux In (R)
3
Aux In (L)
4
Line In (R)
4
Line In (L)
5
Stereo Mix (R)
5
Stereo Mix (L)
6
Mono Mix
6
Mono Mix
7
N/A
7
N/A
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：1.1
CMI 9738
Integrated Multi-channel AC‘97
Record Gain Registers (Index 1Ch) (R/W)
Reg
Name
D15 D14 D13 D12 D11 D10 D9
1Ch Record Gain Mute X
X
D8
D7
D6
D5
D4
D3
D2
D1
D0 Default
X GL3 GL2 GL1 GL0 X
X
X
X GR3 GR2 GR1 GR0 8000h
Each step corresponds to 1.5 dB. 22.5dB corresponds to 0F0Fh and 000Fh respectively. The MSB
of the register is the mute bit. When this bit is set to 1 the level for that channel(s) is set at －∞ dB.
Mute
0
0
1
The default value is 8000h, which corresponds
to 0 dB gain with mute on.
Gx3...Gx0
1111
0000
xxxxx
Function
+22.5 dB gain
0 dB gain
−∞ dB gain
General Purpose Register (Index 20h) (R/W)
Reg
Name
D15 D14 D13 D12 D11 D10 D9
20h General Purpose X
X
X
Bit
LPBK
X
X
X
X
D8
D7
D6 D5 D4 D3 D2 D1 D0 Default
X LPBK X
X
X
X
X
X
X
0000h
D0
Defaul
t
Function
ADC/DAC loopback mode
Powerdown Control/Status Register (Index 26h) (R/W)
Reg
Name
26h
Powerdown
Ctrl/Stat
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3
X PR6 PR5 PR4 PR3 PR2 PR1 PR0 X
X
X
D2
D1
X REF ANL DAC ADC 000Xh
This read/write register is used to program powerdown states and monitor subsystem readiness.
The lower half of this register is read only status, a 1 indicating that the subsection is “ready”.
Ready is defined as the subsection able to perform in its nominal state. When this register is written
the bit values that come in on AC-link will have no effect on read only bits 0-7.
When the AC-link “Codec Ready” indicator bit (SDATA_IN slot 0, bit 15) is a 1 it indicates that the
AC-link and AC ‘97 control and status registers are in a fully operational state. The AC ‘97
Controller must further probe this Powerdown Control/Status Register to determine exactly which
subsections, if any, are ready.
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Revision Date：Apr./2002
Revision
：1.1
CMI 9738
Integrated Multi-channel AC‘97
Bit
Function
X
Reserved
REF
Vref’s up to nominal level
ANL
Analog mixers, etc. ready
DAC
DAC section ready to accept data
ADC
ADC section ready to transmit data
These bits are pseudo. Default are ready and controlled by PRX.
Bit
PR0
PR1
Function
PCM in ADC’s & Input Mux Powerdown
PCM out DACs Powerdown
PR2
Analog Mixer powerdown (Vref still on)
PR3
Analog Mixer powerdown (Vref off)
PR4
Digital Interface (AC-link) powerdown
(external clk off)
PR5
Internal Clk disable
PR6
HP amp powerdown
Except PR4, other bits are pseudo.
When set, corresponding bits will be not ready.
Ex. PR1 =1 causes DAC=0.
PRXX must set the volume to mute!!
PR4 when set will shut down the ACLINK.
Extended Audio ID Register (Index 28h) (Read Only)
Reg
Name
D15 D14 D13 D12 D11 D10 D9 D8
28h Extended Audio ID ID1 ID0 X
X
X
X
X
D7
D6 D5 D4 D3 D2 D1 D0 Default
X SDAC X
X
X
X
X
X
X
0080h
‹SDAC=1 indicates optional PCM Surround DAC is supported D15,D14:ID1,ID0 is always “00”.
Extended Audio Status and Control Register (Index 2Ah)
Reg
Name
2Ah
Ext’d audio
Stat/Ctrl
D15 D14 D13 D12 D11 D10 D9 D8
X
X
X PRJ X
X
X
D7
D6 D5 D4 D3 D2 D1 D0
X SDAC X
X
X
X
X
X
X
Default
1000h
Bits D7 is read only status of the extended audio feature readiness
‹SDAC=1 indicates the PCM Surround DACs are ready (4CH mode)
Bits D12 are read/write controls of the extended audio feature powerdown
C-MEDIA Electronics Inc.
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Revision Date：Apr./2002
Revision
：1.1
CMI 9738
Integrated Multi-channel AC‘97
‹PRJ=1 turns the PCM Surround DACs off (4CH mode)
The default value after cold or warm register reset for this register (xxxxh) is all extended features
disabled (D3-D0=0) and powered down (D12=1). The feature readiness status should always be
accurate (D7=x).
These bits are pseudo.
When 2Ch, 4CH, these bits are still visible.
PRXX must set volume to mute
4-Channel Volume Control Register (Index 38h) (R/W)
Reg
Name
D15
D1 D1
D12 D11 D10
4 3
4CH
38h Vol:L,R Mute X
Surr
D9
D8
D7 D6 D5
X LSR4 LSR3 LSR2 LSR1 LSR0 Mute X
D4
D3
D2
D1
D0
Default
X RSR4 RSR3 RSR2 RSR1 RSR0 8080h
These read/write registers control the output volume of the optional four PCM channels, and values
written to the fields behave the same as the Play Master Volume Register (Index 02h), which offers
attenuation but no gain. There is an independent mute (1=on) for each channel.
The default value after cold or warm register reset for this register (8080h) corresponds to 0 dB
attenuation with mute on.
When 2/4 CH, these registers are still visible and controllable.
The all bits of the reg38h are pseudo.
Vendor Defined Register (Index 5Ah) (R/W)
Reg
Name
Vendor
5Ah defined
Control
D15 D14 D13 D12 D11
X
X
F2R
X
X
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
S2LNI
X
X
X
X
X
X
X
X
X
X
0000h
S2LNI：Surround to Line in selection.
“0”：disable (default)
“1”：enable
F2R：Front channels are routed to rear channels.
“0”：disable (default)
“1”：enable
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TEL: 886-2-8773-1100 FAX: 886-2-8773-2211 E-mail:[email protected]
Revision Date：Apr./2002
Revision
：1.1
CMI 9738
Integrated Multi-channel AC‘97
Vendor ID Registers (Index 7Ch - 7Eh) (Read Only)
Reg Name D15 D14 D13 D12 D11 D10 D9 D8
Vendor
F7
ID1
Vendor
T7
7Eh
ID2
7Ch
D7
D6
D5
D4
D3
D2
D1
D0
Defaul
t
S7
S6
S5
S4
S3
S2
S1
S0
434Dh
F6
F5
F4
F3
F2
F1
F0
T6
T5
T4
T3
T2
T1
T0 REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 4941h
7Ch : 434Dh ASCII code : CM
7Eh : 4941h ASCII code: I A
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6F, 100, Sec. 4, Civil Boulevard, Taipei, Taiwan, R.O.C. 106
TEL: 886-2-8773-1100 FAX: 886-2-8773-2211 E-mail:[email protected]
Revision Date：Apr./2002
Revision
：1.1
CMI 9738
Integrated Multi-channel AC‘97
6.2 PIN DESCRIPTIONS
48-Pin LQFP
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Signal Name
DVdd1
XTL_IN
XTL_OUT
DVss1
SDATA_OUT
BIT_CLK
DVss2
SDATA_IN
DVdd2
SYNC
RESET#
NC
NC
AUX_IN_L
AUX_IN_R
NC
NC
CD_L
CD_GND
CD_R
MIC1
NC
LINE_IN_L
LINE_IN_R
24-Pin TSSOP
PIN #
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Signal Name
AVdd1
AVss1
NC
Vrefout
AFILT1
AFILT2
NC
NC
NC
NC
LINE_OUT_L
LINE_OUT_R
NC
AVdd2
REAR_OUT_L
TEST0#
REAR_OUT_R
AVss2
NC
NC
RESERVED
RESERVED
NC
NC
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Signal Name
SDATA_IN
SYNC
RESET#
AUX_IN_L
AUX_IN_R
CD_L
CD_GND
CD_R
MIC1
LINE_IN_L
LINE_IN_R
VREF_OUT
AFILT1
AFILT2
LINE_OUT_L
LINE_OUT_R
AVdd
TEST0#
Vss
DVsdd
XTL_IN
XTL_OUT
SDATA_OUT
BIT_CLK
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
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6F, 100, Sec. 4, Civil Boulevard, Taipei, Taiwan, R.O.C. 106
TEL: 886-2-8773-1100 FAX: 886-2-8773-2211 E-mail:[email protected]
Revision Date：Apr./2002
Revision
：1.1
CMI 9738
Integrated Multi-channel AC‘97
7. AC-LINK TIMING CHARACTERISTICS
(Tambient = 25 °C, AVdd = 5.0V ±5% , DVdd= 3.3V ±5%, AVss=DVss+0V; 50pF external load)
7.1 COLD RESET
Figure 9. Cold Reset timing diagram
Table 7. Cold Reset timing parameters
Parameter
Symbol
Min
Typ
Max
Units
RESET# active low pulse width
Tres_low
1.0
-
-
us
RESET# inactive to BIT_CLK startup delay
Trst2clk
162.8
-
-
ns
Symbol
Min
Typ
Max
Units
Tres_high
1.0
1.3
-
us
Trst2clk
162.8
-
-
ns
# denotes active low.
7.2 WARM RESET
Figure 10. Warm Reset
Table 8. Warm Reset
Parameter
SYNC active high pulse width
SYNC inactive to BIT_CLK startup delay
7.3 CLOCKS
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TEL: 886-2-8773-1100 FAX: 886-2-8773-2211 E-mail:[email protected]
Revision Date：Apr./2002
Revision
：1.1
CMI 9738
Integrated Multi-channel AC‘97
Figure 11. BIT_CLK to SYNC timing diagram
Table 9. Clocks
Parameter
Symbol
Min
Typ
Max
Units
-
12.288
-
MHz
-
81.4
-
ns
-
-
750
ps
BIT_CLK frequency
BIT_CLK period
Tclk_period
BIT_CLK output jitter
BLT_CLK high pulsewidth (note 1)
Tclk_high
36
40.7
45
ns
BIT_CLK low pulse width (note 1)
Tclk_low
36
40.7
45
ns
-
48.0
-
kHz
Tsync_period
-
20.8
-
us
SYNC high pulse width
Tsync_high
-
1.3
-
us
SYNC low_pulse width
Tsync_low
-
19.5
-
us
SYNC frequency
SYNC period
Notes: 1) Worst case duty cycle restricted to 45/55.
7.4 DATA SETUP AND HOLD (50pF external load)
Figure 12. Data Setup and Hold
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Revision Date：Apr./2002
Revision
：1.1
CMI 9738
Integrated Multi-channel AC‘97
Table 10. Data setup and hold timing parameters
Parameter
Symbol
Min
Typ
Max
Units
Setup to falling edge of BIT_CLK
Tsetup
10.0
-
-
ns
Hold from falling edge of BIT_CLK
Thold
10.0
-
-
ns
Note 1: Setup and hold time parameters for SDATA_IN are with respect to the AC ‘97 Controller.
7.5 SIGNAL RISE AND FALL TIMES
(50pF external load; from 10% to 90% of Vdd)
Figure 13. Signal rise and fall times diagram
Table 11. Signal rise and fall times parameters
Parameter
Symbol
Min
Typ
Max
Units
BIT_CLK rise time
Triseclk
2
-
6
ns
BIT_CLK fall time
Tfallclk
2
-
6
ns
SYNC rise time
Trisesync
2
-
6
ns
SYNC fall time
Tfallsync
2
-
6
ns
SDATA_IN rise time
Trisedin
2
-
6
ns
SDATA_IN fall time
Tfalldin
2
-
6
ns
SDATA_OUT rise time
Trisedout
2
-
6
ns
SDATA_OUT fall time
Tfalldout
2
-
6
ns
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6F, 100, Sec. 4, Civil Boulevard, Taipei, Taiwan, R.O.C. 106
TEL: 886-2-8773-1100 FAX: 886-2-8773-2211 E-mail:[email protected]
Revision Date：Apr./2002
Revision
：1.1
CMI 9738
Integrated Multi-channel AC‘97
7.6 AC-LINK LOW POWER MODE TIMING
Figure 14. AC-link low power mode timing diagram
Table 12. AC-link low power mode timing parameters
Parameter
End of Slot 2 to BIT_CLK, SDATA_IN low
Symbol
Min
Typ
Max
Units
Ts2_pdown
-
-
1.0
us
7.7 ATE TEST MODE
Figure 15. ATE test mode timing diagram
Table 13. ATE test mode timing parameters
Parameter
Symbol
Min
Typ
Max Units
Setup to trailing edge of RESET# (also applies to SYNC) Tsetup2rst 15.0
-
-
ns
Rising edge of RESET# to Hi-Z delay
-
25.0
ns
Toff
-
Notes:
nAll AC-Link signals are normally low through the trailing edge of RESET#. Bringing
SDATA_OUT high for the trailing edge of RESET# causes CMI9738’s AC-Link outputs
to go high impedance which is suitable for ATE in circuit testing.
oOnce either of the two test modes have been entered, the CMI9738 must be issued another
RESET# with all AC-Link signals low to return to the normal operating mode.
# denotes active low.
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Revision Date：Apr./2002
Revision
：1.1
CMI 9738
Integrated Multi-channel AC‘97
8. ELECTRICAL SPECIFICATIONS
8.1 DC CHARACTERISTICS
(Tambient = 25 0 C, AVdd = 5.0V +/-5%, DVdd = 3.3V +/- 5%; AVss = DVss = 0V; 50pF
external load)
Table 14. DC Characteristics (relative to Vdd)
Parameter
Symbol
Min
Typ
Max
Units
Input voltage range
Vin
-0.30
-
DVdd+0.30
V
Low level input voltage
Vil
-
-
0.40xVdd
V
High level input voltage
Vih
0.60xVdd
-
-
V
High level output voltage
Voh
0.70xVdd
-
-
V
Low level output voltage
Vol
-
-
0.30xVdd
V
Input Leakage Current (AC-link inputs)
-
-100
-
100
uA
Output Leakage Current (Hi-Z’d AC-link outputs)
-
-100
-
100
uA
※SDATA_IN＝8mA ※BIT_CLK＝24mA
NOTE:
It is recommended that the digital portion of the CMI9738 component be capable of operating at
either 3.3V (+/- 5%), depending on which DVdd is supplied.However, the following has been added
to simplify the implementation for those who do not support dual voltage (and possibly those who
do), by allowing 5.0 or 3.3 V parts to match the PCI 2.2 specifications for Vih, Vil, Voh, and Vol:
Table 15. DC Characteristics (3.3 V Operation)
Parameter
3.3 V Only Operation
Symbol
Min
Typ
Max Units
Input voltage range
Vin
-0.30
-
3.60
V
Low level input voltage
Vil
-
-
1.32
V
High level input voltage
Vih
1.98
-
-
V
High level output voltage
Voh
2.97
-
-
V
Low level output voltage
Vol
-
-
0.33
V
8.2 ABSOLUTE MAXIMUM RATINGS
Voltage on any pin relative to Ground
Vss - 0.3V TO Vdd + 0.3V
Operating Temperature
0 o C TO 70 o C
Storage Temperature
Soldering Temperature
-55 o C TO +125 o C
260 o C FOR 10 SECONDS
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Revision Date：Apr./2002
Revision
：1.1
CMI 9738
Integrated Multi-channel AC‘97
Table 16. Absolute Maximum Ratings
Parameter
Min
Typ
Max
Power Supplies
Units
V
+3.3V Digital
-3.0
+5V Analog
-4.5
（Supplies, Inputs, Outputs） -
Total Power Dissipation
3.3
5.0
3.6
5.0
-
500
mW
Input Current per Pin
Pins）
（Except Supply -100
-
+100
µA
Output Current per Pin
Pins）
（Except Supply -15
-
15
mA
Analog Input voltage
-0.3
-
AVdd+0.3
V
Digital Input voltage
Ambient Temperature
-0.3
-
DVdd+0.3
V
（Power Applied） -55
-
110
0
C
150
0
C
Storage Temperature
-65
-
8.3 RECOMMENDED OPERATING CONDITIONS
Table 17. Operating Conditions
Parameter
Min
Typ
Max
Units
3.135
4.75
3.3
5
3.465
5.25
V
V
10
20
20
30
mA
mA
0
-
70
Min
Typ
Max
Units
-
46.5
94.5
-
dB
-
1.5
-
dB
Power Supplies
+3.3V Digital
+5V Analog
Operating Current
+3.3V Digital
+5V Analog
Ambient Temperature
o
C
8.4 MIXER CHARACTERISTICS
Table 18. Mixer Characteristics
Parameter
Mixer Gain Range Span
LineIn, Aux, CD, Mic1
Line Out, Alternate Line Out
Step Size
All volume controls
8.5 POWER CONSUMPTION
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Revision Date：Apr./2002
Revision
：1.1
CMI 9738
Integrated Multi-channel AC‘97
Table 19. Power Consumption
Parameter
Digital Supply Current
Analog Supply Current
+3.3V Digital
+5V Analog
Min
-
Typ
10
20
Max
-
Units
mA
mA
8.6 ANALOG PERFORMANCE CHARACTERISTICS
(Standard test conditions unless otherwise noted: Tambient = 25 0 C; DVdd = 3.3 V +/- 5%; AVdd =
5.0 V +/-5%; Input Voltage Levels: Logic Low = 0.35*Vdd, Logic High = 0.65*Vdd; 1 kHz input
sine wave; Sample Frequency = 48 kHz; 0 dB = 1Vrms, 10KW/50pF load, Testbench
Characterization BW: 20 Hz – 20 kHz, 0 dB attenuation; tone and 3D disabled)
Notes:
(1) With +20 dB Boost on, 1.0 Vrms with Boost off
(2) ±1dB limits
(3) The ratio of the rms output level with 1kHz full scale input to the rms output level with all zeros
into the digital input. Measured "A wtd" over a 20 Hz to a 20 kHz bandwidth. (AES17-1991
Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio).
(4) 0 dB gain, 20 kHz BW, 48 kHz Sample Frequency
(5) +3 dB output into 32W load
(6) ±0.25 dB limits
(7) Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible
noise.
(8) The integrated Out-of-Band noise generated by the DAC process, during normal PCM audio
playback, over a bandwidth 28.8 to 100 kHz, with respect to a 1VRMS DAC output.
(9) Gain step size 1.5 dB is true for all attenuators except for PC_BEEP, which has 3.0dB step size.
C-MEDIA Electronics Inc.
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TEL: 886-2-8773-1100 FAX: 886-2-8773-2211 E-mail:[email protected]
Revision Date：Apr./2002
Revision
：1.1
CMI 9738
Integrated Multi-channel AC‘97
Table 20. Analog performance characteristics
Parameter
Full Scale Input Voltage:
Line Inputs
Mic Inputs
Full Scale Output Voltage:
LINE_OUT （Front Channel）@ 10KΩ Load
LINE_OUT （Front Channel）@ 32KΩ Load
SURROUND_OUT（Rear Channel）@ 10K Ω Load
Min
-
Analog Dynamic Range:
CD to LINE_OUT
Other to LINE_OUT
Analog Frequency Response
SNR
D/A
A/D
Total Harmonic Distortion:
Line Output
D/A & A/D Frequency Response
Crosstalk between Input channels @ 10kHz
Input Impedance
Input Capacitance
Vrefout
External Load Impedance
LINE_OUT （Front Channel）@ 32KΩ Load
SURROUND_OUT（Rear Channel）@ 10K Ω Load
-
Typ
Max
Units
1.0
0.1
-
Vrms
Vrms
Vrms
Vrms
Vrms
1
1
1
20
20
75k
-
88
88
-
20,000
dB
dB
Hz
82
72
-
dB
dB
0.04
85
15
2.25V
19,200
-
%
Hz
dB
KΩ
pF
V
KΩ
32Ω
C-MEDIA Electronics Inc.
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TEL: 886-2-8773-1100 FAX: 886-2-8773-2211 E-mail:[email protected]
10KΩ
Revision Date：Apr./2002
Revision
：1.1
CMI 9738
Integrated Multi-channel AC‘97
9. REFERENCES
Intel, Audio Codec ’97 Component Specification, Revision 2.2, September, 2000.
－Notes－
C-MEDIA ELECTRONICS INC.
6F., 100, Sec. 4, Civil Boulevard, Taipei, Taiwan, R.O.C.
TEL（886）：2-8773-1100
FAX（886）：2-8773-2211
E-mail：[email protected]
Homepage：http://www.cmedia.com.tw
C-MEDIA Electronics Inc.
6F, 100, Sec. 4, Civil Boulevard, Taipei, Taiwan, R.O.C. 106
TEL: 886-2-8773-1100 FAX: 886-2-8773-2211 E-mail:[email protected]
Revision Date：Apr./2002
Revision
：1.1