Commercial/ Industrial PEEL™ 22CV10AZ -25 CMOS Programmable Electrically Erasable Logic Device Features ■ Ultra Low Power Operation - VCC = 5 Volts ±10% - Icc = 10 µA (typical) at standby - Icc = 2 mA (typical) at 1 MHz - tPD = 25ns. ■ CMOS Electrically Erasable Technology - Superior factory testing - Reprogrammable in plastic package - Reduces retrofit and development costs ■ ■ Architectural Flexibility - 133 product terms x 44 input AND array - Up to 22 inputs and 10 I/O pins - 12 possible macrocell configurations - Synchronous preset, asynchronous clear - Independent output enables - Programmable clock source and polarity - 24-pin DIP/SOIC/TSSOP and 28-pin PLCC ■ Application Versatility - Replaces random logic - Pin and JEDEC compatible with 22V10 - Ideal for power-sensitive systems Development/Programmer Support - Third party software and programmers - ICT PLACE Development Software and PDS-3 programmer General Description The PEEL™22CV10AZ is a Programmable Electrically Erasable Logic (PEEL™) device that provides a low power alternative to ordinary PLDs. The PEEL™22CV10AZ is available in 24-pin DIP, SOIC, TSSOP and 28-pin PLCC packages (see Figure 19). A “zero-power” (100µA max. ICC) standby mode makes the PEEL™22CV10AZ ideal for power sensitive applications such as handheld meters, portable communication equipment and laptop computers/ peripherals. EE-reprogrammability provides the convenience of instant reprogramming for development and a reusable production inventory minimizing the impact of programming changes or errors. EEreprogrammability also improves factory testability, thus ensuring the highest quality possible. PLCC Development and programming support for the PEEL™22CV10AZ is provided by popular third-party programmers and development software. ICT also offers free PLACE development software and a low-cost development system (PDS-3). Figure 19 Block Diagram Figure 19 Pin Configuration DIP The PEEL™22CV10AZ is JEDEC file compatible with standard 22V10 PLDs. Eight additional configurations per macrocell (a total of 12) are also available by using the “+” software/programming option (i.e., 22CV10AZ+). The additional macrocell configurations allow more logic to be put into every device, potentially reducing the design's component count and lowering the power requirements even further. I/CLK 1 24 VCC I 2 23 I/O I 3 22 I/O I 4 21 I/O I 5 20 I/O I 6 19 I/O I 7 18 I/O I 8 17 I/O I 9 16 I/O I 10 15 I/O I 11 14 I/O GND 12 13 I TSSOP SOIC 1 of 10 PEEL™ 22CV10AZ (OPTIONAL) 132 0 ASYNCHRONOUS CLEAR (TO ALL MACROCELLS) 2 MACRO CELL 9 I/CLK (2) I/O (27) 10 MACRO CELL 20 I/O (26) I (3) 21 MACRO CELL 33 I/O (25) I (4) 34 MACRO CELL I/O (24) 48 I 49 (5) I/O MACRO CELL (23) MACRO CELL (21) MACRO CELL (20) 65 I (6) 66 I/O 82 I (7) 83 I/O 97 I (9) 98 MACRO CELL 110 I/O (19) I (10) 111 MACRO CELL 121 I/O (18) I (11) 124 MACRO CELL 130 I (12) I/O (17) SYNCHRONOUS PRESET (TO ALL MACROCELLS) 131 I I (16) (13) Figure 21 PEEL™22CV10AZ Logic Array Diagram 2 of 10 PEEL™ 22CV10AZ Function Description The implements logic functions as sum-of-products expressions in a programmable-AND/fixed-OR logic array. Userdefined functions are created by programming the connections of input signals into the array. User-configurable output structures in the form of I/O macrocells further increase logic flexibility. Architecture Overview When programming the PEEL™22CV10AZ, the device programmer first performs a bulk erase to remove the previous pattern. The erase cycle opens every logical connection in the array. The device is configured to perform the user-defined function by programming selected connections in the AND array. (Note that PEEL™ device programmers automatically program all of the connections on unused product terms so that they will have no effect on the output function). The architecture is illustrated in the block diagram of Figure 19. Twelve dedicated inputs and 10 I/Os provide up to 22 inputs and 10 outputs for creating logic functions (see Figure 21). At the core of the device is a programmable electrically-erasable AND array that drives a fixed OR array. With this structure, the PEEL™22CV10AZ can implement up to 10 sum-of-products logic expressions. Variable Product Term Distribution Associated with each of the ten OR functions is an I/O macrocell that can be independently programmed to one of four different configurations in standard 22V10 mode, or any one of 12 configurations using the special “Plus” mode. The programmable macrocells allow each I/O to be used to create sequential or combinatorial logic functions of activehigh or active-low polarity, while providing three different feedback paths into the AND array. Programmable I/O Macrocell AND/OR Logic Array Each I/O macrocell, as shown in Figure 20, consists of a Dtype flip-flop and two signal-select multiplexers. The configuration of the macrocell is determined by four EEPROM bits that control the multiplexers. These bits determine the output polarity, output type (registered or non-registered) and input-feedback path (bidirectional I/O, combinatorial feedback). Refer to Table 1. for details. Four of these macrocells duplicate the functionality of the industry-standard PAL22V10. (See Figure 21 and Table 1.) The programmable AND array of the PEEL™22CV10AZ (shown in Figure 21) is formed by input lines intersecting product terms. The input lines and product terms are used as follows: ■ 44 Input Lines: – 24 input lines carry the true and complement of the signals applied to the 12 input pins – 20 additional lines carry the true and complement values of feedback or input signals from the 10 I/Os ■ 133 Product Terms: – 120 product terms (arranged in 2 groups of 8, 10, 12, 14, and 16) are used to form sum of product functions – 10 output enable terms (one for each I/O) – 1 global synchronous preset term – 1 global asynchronous clear term – 1 programmable clock term The PEEL™22CV10AZ provides 120 product terms to drive the 10 OR functions. These product terms are distributed among the outputs in groups of 8, 10, 12, 14, and 16 to form logical sums (see Figure 21). This distribution allows optimum use of the device resources. The unique twelve-configuration output macrocell provides complete control over the architecture of each output. The ability to configure each output independently lets you to tailor the configuration of the PEEL™22CV10AZ to the precise requirements of your design. Macrocell Architecture Figure 20 Block Diagram of the PEEL™22CV10A I/O Macrocell At each input-line/product-term intersection, there is an EEPROM memory cell that determines whether or not there is a logical connection at that intersection. Each product term is essentially a 44-input AND gate. A product term that is connected to both the true and complement of an input signal will always be FALSE and therefore will not affect the OR function that it drives. When all the connections on a product term are opened, a “don’t care” state exists and that term will always be TRUE. 3 of 10 PEEL™ 22CV10AZ In addition to emulating the four PAL-type output structures (configurations 3, 4, 9, and 10), The macrocell provides eight additional configurations. Equivalent circuits for the twelve macrocell configurations are illustrated in Figure 22. These structures are accessed by specifying the PEEL™22CV10A+ or PEEL™22CV10A++ option when assembling the equations. Output Polarity Each macrocell can be configured to implement active-high or active-low logic. Programmable polarity eliminates the need for external inverters. Output Enable The output of each I/O macrocell can be enabled or disabled under the control of its associated programmable output enable product term. When the logical conditions programmed on the output enable term are satisfied, the output signal is propagated to the I/O pin. Otherwise, the output buffer is switched into the high-impedance state. Figure 21 Equivalent Circuits for the Four Configurations of the I/O Macrocell Under the control of the output enable term, the I/O pin can function as a dedicated input, a dedicated output, or a bidirectional I/O. Opening every connection on the output enable term will permanently enable the output buffer and yield a dedicated output. Conversely, if every connection is intact, the enable term will always be logically false and the I/O will function as a dedicated input. Input/Feedback Select When configuring an I/O macrocell to implement a registered function (configurations 1 and 2 in Figure 21), the Q output of the flip-flop drives the feedback term. When configuring an I/O macrocell to implement a combinatorial output (configurations 3 and 4 in Figure 21), the feedback term is taken from the I/O pin. In this case, the pin can be used as a dedicated input or a bi-directional I/O (Refer also to Table 1.) Table 1. PEEL™22CV10A Macrocell Configuration Bits Configuration # A B 1 0 0 2 1 0 3 0 1 4 Input/Feedback Select Output Select Programmable Clock Options Active Low Register Feedback Register Bi-Directional I/O Combinatorial Active High Active Low Active High A unique feature of the PEEL™22CV10AZ is a programmable clock multiplexer that allows you to select true or complement forms of either the input pin or a product-term clock source. This feature can be accessed by specifying the PEEL™22CV10A++ option when assembling the equations. When creating a PEEL™ device design, the desired macrocell configuration is generally specified explicitly in the design file. When the design is assembled or compiled, the macrocell configuration bits are defined in the last lines of the JEDEC programming file. Output Type The signal from the OR array can be fed directly to the output pin (combinatorial function) or latched in the D-type flipflop (registered function). The D-type flip-flop latches data on the rising edge of the clock and is controlled by the global preset and clear terms. When the synchronous preset term is satisfied, the Q output of the register is set HIGH at the next rising edge of the clock input. Satisfying the asynchronous clear sets Q LOW, regardless of the clock state. If both terms are satisfied simultaneously, the clear will override the preset. 4 of 10 PEEL™ 22CV10AZ Figure 22 Equivalent Circuits for the Twelve Configurations of the PEEL™22CV10AZ+ I/O Macrocell Table 1. I/O Macrocell Equivalent Circuits Configuration # A B C D 1 0 0 1 0 2 1 0 1 0 3 0 1 0 0 4 1 1 0 0 5 0 0 1 1 6 1 0 1 1 7 0 1 1 1 8 1 1 1 1 9 0 0 0 0 10 1 0 0 0 11 0 1 1 0 12 1 1 1 0 Input/Feedback Select Output Select Register Bi-directional I/O Combinatorial Register Combinatorial Feedback Combinatorial Register Register Feedback Combinatorial 5 of 10 Active Low Active High Active Low Active High Active Low Active High Active Low Active High Active Low Active High Active Low Active High PEEL™ 22CV10AZ Zero Power Feature Design Security The CMOS PEEL™22CV10AZ features “Zero-Power” standby operation for ultra-low power consumption. With the “Zero-Power” feature, transition-detection circuitry monitors the inputs, I/Os (including CLK) and feedbacks. If these signals do not change for a period of time greater than approximately two tPDs, the outputs are latched in their current state and the device automatically powers down. When the next signal transition is detected, the device will “wake up” for active operation until the signals stop switching long enough to trigger the next power-down. The PEEL™22CV10AZ provides a special EEPROM security bit that prevents unauthorized reading or copying of designs programmed into the device. The security bit is set by the PLD programmer, either at the conclusion of the programming cycle or as a separate step, after the device has been programmed. Once the security bit is set it is impossible to verify (read) or program the PEEL™ until the entire device has first been erased with the bulk-erase function. As a result of the “Zero-Power” feature, significant power savings can be realized for combinatorial or sequential operations when the inputs or clock change at a modest rate (see Figure 23). The signature word feature allows a 64-bit code to be programmed into the PEEL™22CV10AZ if the PEEL™22CV10AZ+ software option is used. The code can be read back even after the security bit has been set. The signature word can be used to identify the pattern programmed into the device or to record the design revision, etc. Figure 23 Typical ICC vs. Input Clock Frequency for the 22CV10AZ. Signature Word Programming Support 22CV10AZ Frequency vs. ICC ICT’s JEDEC file translator allows easy conversion of existing 24 pin PLD designs to the PEEL™22CV10AZ, without the need for redesign. ICT supports a broad range of popular third party design entry systems, including Data I/O Synario and Abel, Logical Devices CUPL and others. ICT also offers (for free) its proprietary PLACE software, an easy-to-use entry level PC-based software development system. 100 ICC in mA. 10 1 Programming support includes all the popular third party programmers; Data I/O, Logical Devices, and numerous others. ICT also provides a low cost development programmer system, the PDS-3. 0.1 0.01 0.001 0.001 0.01 0.1 1 10 Frequency in MHz 6 of 10 PEEL™ 22CV10AZ This device has been designed and tested for the specified operating ranges. Proper operation outside of these levels is not guaranteed. Exposure to absolute maximum ratings may cause permanent damage. Table 1. Absolute Maximum Ratings Symbol VCC Parameter Supply Voltage VI, VO Voltage Applied to Any Relative to Ground Pin2 Output Current IO TST Storage Temperature TLT Lead Temperature Conditions Relative to Ground1 Rating Unit -0.5 to + 7.0 V -0.5 to VCC + 0.6 V ±25 mA -65 to +150 °C +300 °C Per Pin (IOL, IOH) Soldering 10 Seconds Table 2. Operating Range Symbol Vcc Parameter Supply Voltage TA Ambient Temperature Conditions Min Max Unit Commercial 4.75 5.25 V Industrial 4.5 5.5 V 0 +70 °C -40 +85 °C ns Commercial Industrial TR Clock Rise Time See Note 3. 20 TF Clock Fall TIme See Note 3. 20 ns TRVCC VCC Rise Time See Note 3. 250 ms Table 3. D.C. Electrical Characteristics Over the operating range (Unless otherwise specified) Symbol VOH VOHC VOL VOLC Parameter Conditions Min VCC = Min, IOH = -4.0 mA 2.4 Output HIGH Voltage - CMOS VCC = Min, IOH = -10.0 µA VCC - 0.3 Output LOW Voltage - TTL VCC = Min, IOL = 16.0 mA 0.5 Output LOW Voltage - CMOS VCC = Min, IOL = 10.0 µA 0.15 V VCC + 0.3 V Input HIGH Voltage VIL Input LOW Voltage IIL Input and I/O Leakage Current VCC = Max, GND ≤ VIN ≤ VCC, I/O = High Z ISC Output Short Circuit Current VCC = Max, VO = 0.5V, TA = 25°C 2.0 -0.3 4 ICCS VCC Current, Standby VIN = 0V or V CC, All Outputs disabled ICC10 VCC Current, f=1MHz VIN = 0V or V CC, All Outputs disabled4 CIN7 Input Capacitance COUT Unit Output HIGH Voltage - TTL VIH 7 Max Output Capacitance TA = 25°C, VCC = 5.0V @ f = 1 MHz 7 of 10 V V V 0.8 V ±10 µA -30 -135 mA 10 (typ) 100 µA 2 (typ) 5 mA 6 pF 12 pF PEEL™ 22CV10AZ Over the operating range 8 Table 10. Symbol -25 Parameter tPD Input5 tOE Input5 tOD Input5 tCO1 Min Units Max 25 ns to output enable6 25 ns to output disable6 25 ns Clock to Output 15 ns tCO2 Clock to comb. output delay via internal registered feedback 35 ns tCF Clock to Feedback 9 ns tSC Input5 or feedback setup to clock tHC tCL, tCH tCP fMAX1 to non-registered output 5 ns 0 ns Clock low time, clock high time 13 ns Min clock period Ext (tSC + tCO1) 30 ns 41.6 MHz 33.3 MHz 38.4 MHz Input hold after clock 8 Internal feedback (1/tSC+tCF) 11 fMAX2 External Feedback fMAX3 No Feedback (1/tCL+tCH)11 tAW Asynchronous Reset Pulse Width tAP Input to Asynchronous Reset tAR Asynchronous Reset recovery time tRESET 15 (1/tCP)11 Power-on reset time for registers in clear state 25 12 ns 25 ns 25 ns 5 µs Switching Waveforms Inputs, I/O, Registered Feedback, Synchronous Preset Clock Asynchronous Reset Registered Outputs Combinatorial Outputs Notes: 1. Minimum DC input is -0.5V, however, inputs may undershoot to -2.0V for periods less than 20 ns. 2. VI and VO are not specified for program/verify operation. 3. Test Points for Clock and VCC in tR and tF are referenced at the 10% and 90% levels. 4. I/O pins are 0V and VCC. 5. “Input” refers to an input pin signal. 6. tOE is measured from input transition to VREF±0.1V, TOD is measured from input transition to VOH-0.1V or VOL+0.1V; VREF=VL. 7. Capacitances are tested on a sample basis. 8. Test conditions assume: signal transition times of 3ns or less from the 10% and 90% points, timing reference levels of 1.5V (Unless otherwise specified). 9. Test one output at a time for a duration of less than 1 second. 10. ICC for a typical application: This parameter is tested with the device programmed as a 10-bit Counter. 11. Parameters are not 100% tested. Specifications are based on initial characterization and are tested after any design process modification that might affect operational frequency. 12. All inputs at GND. 8 of 10 PEEL™ 22CV10AZ PEEL™ Device and Array Test Loads Standard Load 5V Thevenin Equivalent VL R1 RL Output Output CL CL R2 Technology R1 R2 RL VL CL CMOS 480kΩ 480kΩ 228kΩ 2.375V 33 pF TTL 235Ω 159Ω 95Ω 2.02V 33 pF Ordering Information Part Number Speed Temperature Package PEEL22CV10AZP-25 25ns Commercial 24-pin Plastic DIP 28-pin PLCC PEEL22CV10AZJ-25 25ns Commercial PEEL22CV10AZS-25 25ns Commercial 24-pin SOIC PEEL22CV10AZT-25 25ns Commercial 24-pin TSSOP PEEL22CV10AZPI-25 25ns Industrial 24-pin Plastic DIP 28-pin PLCC PEEL22CV10AZJI-25 25ns Industrial PEEL22CV10AZSI-25 25ns Industrial 24-pin SOIC PEEL22CV10AZTI-25 25ns Industrial 24-pin TSSOP Part Number Suffix Device PEEL™ 22CV10AZ PI-25 Speed –25 = 25ns tpd Package P = 24-pin Plastic 300mil DIP J = 28-pin Plastic (J) Leaded Chip Carrier (PLCC) S = 24-pin SOIC 300 mil Gullwing T = 24-pin TSSOP 170 mil Temperature Range (Blank) = Commercial 0 to +70°C I = Industrial -40 to +85°C 9 of 10 PEEL™ 22CV10AZ 10 of 10