MYSON TECHNOLOGY MTD516 (Preliminary) 16 Port 10M/100M Ethernet Switch FEATURES GENERAL DESCRIPTION • IEEE802.3 and IEEE802.3u compliant. • Provide 16 RMII (Reduced Media Independent Interface) ports. • Programmable 1K/8K MAC addresses filtering database. • Store and forward switching function and bad packet filtering function. • Optional back_pressure/802.3x flow control/ flooding control/broadcast control. • Optional EEPROM Interface for advanced switch configurations. • 4MB/2MB packet buffer with SGRAM/SDRAM flexible memory interface. • Port VLAN/trunking. • Link/Rx activity, packet buffer utilization LED display. • 83MHz for non-blocking 16 port switch. • Build in internal/external memory test function. • 208 pin PQFP package, 3.3V operation voltage. The MTD516 complies fully with the IEEE802.3, 802.3u and 802.3x specifications and is a non-blocking 16 port 10M/100M Ethernet switch device. Support 16 RMII ports for 10M/100M operation. 4MB memory interface provides maximum 2730 packet buffers for Ethernet packet buffering. Up to 8192 address entrys are provided by the MTD516, and the MTD516 use full Ethernet address compare algorithm to minimize hashing collision events. The MTD516 provides EEPROM interface to config port trunking, port VLAN, static entry, 802.3x flow control threshold, flooding port, broadcast control threshold. Each MTD516 ports support 10M/100M auto-negotiation by MII management interface. The MTD516 also provides 2 pins for Link/ RX activity, packet buffer utilization LED display function. BLOCK DIAGRAM SDRAM/ SGRAM Interface Memory Controller Memory Arbiter DMA0 MAC0 RMII0 DMA1 MAC1 RMII1 DMA2 MAC2 RMII2 DMA3 MAC3 RMII3 3~12 Port Switch Logic DMA4 MAC4 RMII12 DMA13 MAC13 RMII13 DMA14 MAC14 RMII14 DMA15 MAC15 RMII15 This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this procuts. No rights under any patent accompany the sales of the product. 1/27 MTD516 Revision 1.2 19/06/2000 MYSON TECHNOLOGY MTD516 (Preliminary) SYSTEM DIAGRAM (**Progr ammable) SGRAM (512kx32x2) (**OPTION) EEPROM MTD516 LEDs SGRAM (256kx32x2) RMII11-15 RMII0-7 OCTAL PHYsceiver OCTAL Transformer RJ45 MII management OCTAL PHYsceiver OCTAL Transformer RJ45 This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this procuts. No rights under any patent accompany the sales of the product. 2/27 MTD516 Revision 1.2 19/06/2000 MYSON TECHNOLOGY MTD516 (Preliminary) 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 DQ9 DQ8 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ16 DQ17 DQ18 DQ19 DQ20 VCC GND DQ21 DQ22 DQ23 WEB CASB RASB CS0B BA AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 VCC MEMCLK GND DQ63 DQ62 DQ61 DQ60 DQ59 DQ58 DQ57 DQ56 DQ47 DQ46 DQ45 DQ44 VCC GND DQ43 1.0 PIN CONNECTION 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 MTD516 DQ42 DQ41 DQ40 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 VCC GND DQ38 DQ39 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 VCC SYSCLK GND RXD15_1 RXD15_0 CRSDV15 TXEN15 TXD15_0 TXD15_1 RXD14_1 RXD14_0 CRSDV14 TXEN14 TXD14_0 TXD14_1 VCC GND RXD13_1 RXD13_0 CRSDV13 TXEN13 TXD13_0 TXD13_1 RXD12_1 RXD12_0 CRSDV12 TXEN12 TXD12_0 TXD12_1 RXD11_1 RXD11_0 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 TXD4_1 TXD4_0 TXEN4 CRSDV4 RXD4_0 RXD4_1 TXD5_1 TXD5_0 TXEN5 GND VCC CRSDV5 RXD5_0 RXD5_1 TXD6_1 TXD6_0 TXEN6 CRSDV6 RXD6_0 RXD6_1 TXD7_1 TXD7_0 TXEN7 CRSDV7 RXD7_0 RXD7_1 GND VCC TXD8_1 TXD8_0 TXEN8 CRSDV8 RXD8_0 RXD8_1 TXD9_1 TXD9_0 TXEN9 CRSDV9 RXD9_0 RXD9_1 GND VCC TXD10_1 TXD10_0 TXEN10 CRSDV10 RXD10_0 RXD10_1 TXD11_1 TXD11_0 TXEN11 CRSDV11 DQ10 DQ11 GND VCC DQ12 DQ13 DQ14 DQ15 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 LEDDATA LEDCLK EEDATA EECLK GND REFCLK VCC RESETB MDC MDIO TXD0_1 TXD0_0 TXEN0 CRSDV0 RXD0_0 RXD0_1 GND VCC TXD1_1 TXD1_0 TXEN1 CRSDV1 RXD1_0 RXD1_1 TXD2_1 TXD2_0 TXEN2 CRSDV2 RXD2_0 RXD2_1 TXD3_1 TXD3_0 TXEN3 CRSDV3 RXD3_0 RXD3_1 3/27 MTD516 Revision 1.2 19/06/2000 MYSON TECHNOLOGY MTD516 (Preliminary) 2.0 PIN DESCRIPTIONS RMII Port Interface Pins Name CRSDV0 RXD0_0 RXD0_1 TXEN0 TXD0_0 TXD0_1 CRSDV1 RXD1_0 RXD1_1 TXEN1 TXD1_0 TXD1_1 CRSDV2 RXD2_0 RXD2_1 TXEN2 TXD2_0 TXD2_1 CRSDV3 RXD3_0 RXD3_1 TXEN3 TXD3_0 TXD3_1 CRSDV4 RXD4_0 RXD4_1 TXEN4 TXD4_0 TXD4_1 CRSDV5 RXD5_0 RXD5_1 TXEN5 TXD5_0 TXD5_1 Pin Number 186 187 188 185 184 183 194 195 196 193 192 191 200 201 202 199 198 197 206 207 208 205 204 203 4 5 6 3 2 1 12 13 14 9 8 7 I/O Descriptions I Port0 RMII receive interface signal, CRSDV0 is asserted high when port0 media is non_idle. I Port0 RMII receive data bit_0. I O Port0 RMII receive data bit_1. Port0 RMII transmit enable signal. O Port0 RMII transmit data bit_0. O I I Port0 RMII transmit data bit_1. Port1 RMII receive interface signal, CRSDV1 is asserted high when port1 media is non_idle. Port1 RMII receive data bit_0. I O Port1 RMII receive data bit_1. Port1 RMII transmit enable signal. O Port1 RMII transmit data bit_0. O I I Port1 RMII transmit data bit_1. Port2 RMII receive interface signal, CRSDV2 is asserted high when port2 media is non_idle. Port2 RMII receive data bit_0. I O Port2 RMII receive data bit_1. Port2 RMII transmit enable signal. O Port2 RMII transmit data bit_0. O I I Port2 RMII transmit data bit_1. Port3 RMII receive interface signal, CRSDV0 is asserted high when port3 media is non_idle. Port3 RMII receive data bit_0. I O Port3 RMII receive data bit_1. Port3 RMII transmit enable signal. O Port3 RMII transmit data bit_0. O I Port3 RMII transmit data bit_1. Port4 RMII/MII receive interface signal, CRSDV4 is asserted high when I port4 media is non_idle. Port4 RMII/MII receive data bit_0. I O Port4 RMII/MII receive data bit_1. Port4 RMII transmit enable signal O Port4 RMII/MII transmit data bit_0. O I I Port4 RMII/MII transmit data bit_1. Port5 RMII receive interface signal, CRSDV5 is asserted high when port5 media is non_idle. Port5 RMII receive data bit_0. I O Port5 RMII receive data bit_1. Port5 RMII transmit enable signal. O Port5 RMII transmit data bit_0. O Port5 RMII transmit data bit_1. 4/27 MTD516 Revision 1.2 19/06/2000 MYSON TECHNOLOGY MTD516 (Preliminary) RMII Port Interface Pins Name CRSDV6 RXD6_0 RXD6_1 TXEN6 TXD6_0 TXD6_1 CRSDV7 RXD7_0 RXD7_1 TXEN7 TXD7_0 TXD7_1 CRSDV8 RXD8_0 RXD8_1 TXEN8 TXD8_0 TXD8_1 CRSDV9 RXD9_0 RXD9_1 TXEN9 TXD9_0 TXD9_1 CRSDV10 RXD10_0 RXD10_1 TXEN10 TXD10_0 TXD10_1 CRSDV11 RXD11_0 RXD11_1 TXEN11 TXD11_0 TXD11_1 Pin Number 18 19 20 17 16 15 24 25 26 23 22 21 32 33 34 31 30 29 38 39 40 37 36 35 46 47 48 45 44 43 52 53 54 51 50 49 I/O Descriptions I Port6 RMII receive interface signal, CRSDV6 is asserted high when port6 media is non_idle. I Port6 RMII receive data bit_0. I O Port6 RMII receive data bit_1. Port6 RMII transmit enable signal. O Port6 RMII transmit data bit_0. O I I Port6 RMII transmit data bit_1. Port7 RMII receive interface signal, CRSDV7 is asserted high when port7 media is non_idle. Port7 RMII receive data bit_0. I O Port7 RMII receive data bit_1. Port7 RMII transmit enable signal. O Port7 RMII transmit data bit_0. O I I Port7 RMII transmit data bit_1. Port8 RMII receive interface signal, CRSDV8 is asserted high when port8 media is non_idle. Port8 RMII receive data bit_0. I O Port8 RMII receive data bit_1. Port8 RMII transmit enable signal. O Port8 RMII transmit data bit_0. O I I Port8 RMII transmit data bit_1. Port9 RMII receive interface signal, CRSDV9 is asserted high when port9 media is non_idle. Port9 RMII receive data bit_0. I O Port9 RMII receive data bit_1. Port9 RMII transmit enable signal. O Port9 RMII transmit data bit_0. O I I Port9 RMII transmit data bit_1. Port10 RMII receive interface signal, CRSDV10 is asserted high when port10 media is non_idle. Port10 RMII receive data bit_0. I O Port10 RMII receive data bit_1. Port10 RMII transmit enable signal. O Port10 RMII transmit data bit_0. O I I Port10 RMII transmit data bit_1. Port11 RMII receive interface signal, CRSDV11 is asserted high when port11 media is non_idle. Port11 RMII receive data bit_0. I O Port11 RMII receive data bit_1. Port11 RMII transmit enable signal. O Port11 RMII transmit data bit_0. O Port11 RMII transmit data bit_1. 5/27 MTD516 Revision 1.2 19/06/2000 MYSON TECHNOLOGY MTD516 (Preliminary) RMII Port Interface Pins Name CRSDV12 Pin Number RXD12_0 59 60 RXD12_1 TXEN12 TXD12_0 TXD12_1 CRSDV13 RXD13_0 RXD13_1 TXEN13 TXD13_0 TXD13_1 CRSDV14 RXD14_0 RXD14_1 TXEN14 TXD14_0 TXD14_1 CRSDV15 RXD15_0 RXD15_1 TXEN15 TXD15_0 TXD15_1 58 57 56 55 64 65 66 63 62 61 72 73 74 71 70 69 78 79 80 77 76 75 I/O Descriptions I Port12 RMII receive interface signal, CRSDV12 is asserted high when port12 media is non_idle. I Port12 RMII receive data bit_0. I O Port12 RMII receive data bit_1. Port12 RMII transmit enable signal. O Port12 RMII transmit data bit_0. O I I Port12 RMII transmit data bit_1. Port13 RMII receive interface signal, CRSDV13 is asserted high when port13 media is non_idle. Port13 RMII receive data bit_0. I O Port13 RMII receive data bit_1. Port13 RMII transmit enable signal. O Port13 RMII transmit data bit_0. O I I Port13 RMII transmit data bit_1. Port14 RMII receive interface signal, CRSDV14 is asserted high when port14 media is non_idle. Port14 RMII receive data bit_0. I O Port14 RMII receive data bit_1. Port14 RMII transmit enable signal. O Port14 RMII transmit data bit_0. O I I Port14 RMII transmit data bit_1. Port15 RMII receive interface signal, CRSDV15 is asserted high when port15 media is non_idle. Port15 RMII receive data bit_0. I O Port15 RMII receive data bit_1. Port15 RMII transmit enable signal. O Port15 RMII transmit data bit_0. O Port15 RMII transmit data bit_1. 6/27 MTD516 Revision 1.2 19/06/2000 MYSON TECHNOLOGY MTD516 (Preliminary) Synchronous DRAM/GRAM Interface Pins Name AD[8:0] DQ[63:0] Pin Number I/O Descriptions O Memory row/column address bus outputs 123~131 AD[7:0] are row/column address [7:0]. 119~112, AD[8] : This pin should connect to SGRAM/SDRAM MSB address bit. I/O Memory data bus DQ[63:56] : 119~112 84~91, 111~108, DQ[55:48] : 84~91 105~102, DQ[43:40] : 105~102 DQ[47:44] : 111~108 92~93, DQ[39:38] : 92~93 96~101, DQ[37:32] : 96~101 172~165, DQ[31:24] : 172~165 137~139, DQ[23:21] : 137~139 142~146, DQ[20:16] : 142~146 164~161, DQ[15:12] : 164~161 158~155, DQ[11:8] : 158~155 147~154 DQ[7:0] : 147~154 RASB 134 O SGRAM/SDRAM row address select CASB 135 O SGRAM/SDRAM column address select WEB 136 O SGRAM/SDRAM write enable BA 132 O SGRAM/SDRAM bank select CS0B 133 O Memory chip select 0 MEMCLK 121 O Memory clock output. Note: SGRAM/SDRAM access time: 10 ns (max) Miscellaneous Pins Name RESETB SYSCLK REFCLK MDC MDIO EECLK/ SDC EEDATA/ SDIO LEDCLK Pin Number 180 82 178 181 182 176 175 174 I/O I I I I/O I/O I/O Descriptions System reset input, low active. Switch core system clock input RMII reference clock input MII management clock inout. MII management data inout After ResetB deassert to ? ms , this pin indicate EECLK, After 150 ms, it indicate SDC. I/O After ResetB deassert to ? ms , this pin be indicated EEDATA, After 150 ms, it indicate SDIO. I/O LED Clock. Using bursted clock for latching 32 display informations (one clock latch one information) , per burst have 32 continuous clocks (clock period = 320 ns); and the time between burst to burst is 655 us. 7/27 MTD516 Revision 1.2 19/06/2000 MYSON TECHNOLOGY MTD516 (Preliminary) Miscellaneous Pins Name LEDDATA Pin Number I/O I/O LED Data (high_active). Descriptions The serial output display informations using bursted styling ,per burst have 32 informations, as following: 173 VCC LEDCLK LEDDATA LEDCLK LEDDATA 01 P0_RxAct 17 Uti_1% 02 P1_RxAct 18 Uti_3% 03 P2_RxAct 19 Uti_5% 04 P3_RxAct 20 Uti_10% 05 P4_RxAct 21 Uti_15% 06 P5_RxAct 22 Uti_20% 07 P6_RxAct 23 Uti_30% 08 P7_RxAct 24 Uti_35% 09 P8_RxAct 25 Uti_40% 10 P9_RxAct 26 Uti_50% 11 P10_RxAct 27 Uti_60% 12 P11_RxAct 28 Uti_70% 13 P12_RxAct 29 Uti_80% 14 P13_RxAct 30 Uti_90% 15 P14_RxAct 31 BufferAlarm P15_RxAct 32 MemTestFail 16 11,28,42,68, PWR Power pins 83,95,107, 122,141,160, GND 179,190, 10,27,41,67, GND Ground pins 81,94,106, 120,140,159, 177,189, 8/27 MTD516 Revision 1.2 19/06/2000 MYSON TECHNOLOGY MTD516 (Preliminary) 3.0 Power on Setting Configuration Jumper Configuration After Power On Reset Pin Name Function MDC defa Descriptions ult 1 802.3x flow control function enable. FlowCtrlEn EECLK external pull_hgih =1, 802.3x flow control enable. 1 BakPsureEn EEDATA external pull_hgih =1, backpressure enable. 1 MiiPollEn LEDCLK AgingEn BISTEn FastMode ScanMode 8KAddrTblEn EEPROMEn BroadStormEn En12PortSW external pull_low = 0, broadcast storm protection disable. For 12 port switch, only Port11~Port0 enable. external pull_hgih =1, 12 port switch enable. 0 P15FXEn external pull_low = 0, auto load from EEPROM function disable. Broadcast storm protect function enable. external pull_hgih =1, broadcast storm protection enable. 0 TXEN7 external pull_low = 0, 8K address table disable; defaule is 1K entry. Auto_load from EEPROM function enable. external pull_hgih =1, auto load from EEPROM function enable. 0 TXEN8 external pull_low = 0, chip scan test mode disable. 8K entry address table enable. external pull_hgih =1, 8K address table enable. 0 TXEN9 external pull_low = 0, chip fast test mode disable. For chip test only. external pull_hgih =1, chip scan test mode enable. 0 TXEN10 external pull_low = 0, memory BIST disable. For chip test only. external pull_hgih =1, chip fast test mode enable. 0 TXEN11 external pull_low = 0, aging out function disable. Embbeded memory self-test function enable. external pull_hgih =1, memory BIST enable. 0 TXEN12 external pull_low = 0, PHY auto polling disable. Aging out function for address learning enable. external pull_hgih =1, aging out function enable. 1 TXEN13 external pull_low = 0, backpressure disable. Polling PHY device’s MII register function enable. external pull_hgih =1, PHY auto polling enable. 1 LEDDATA external pull_low = 0, 802.3x flow control disable. In Half duplex mode, backpressure function enable. external pull_low = 0, default is 16 port switch. Port 15 FX function indicator. external pull_hgih =1, port15 FX function enable. external pull_low = 0, port15 FX function disable. 9/27 MTD516 Revision 1.2 19/06/2000 MYSON TECHNOLOGY MTD516 (Preliminary) Jumper Configuration After Power On Reset Pin Name Function TXEN6 defa Descriptions ult 0 Port15 duplex ability indicator (under port15 configured in FX mode). P15Full TXEN5 external pull_hgih =1, port15 operate in full_duplex mode. 0 En1522 TXEN4 external pull_hgih =1, VLAN tag 1522 bytes acceptance enable. 0 FloodCtrlEn TXEN3 FloodID[3] FloodID[2] FloodID[1] external pull_low = 0. Flooding Port ID bit 1 external pull_hgih =1. 0 FloodID[0] external pull_low = 0. Flooding Port ID bit 2 external pull_hgih =1. 0 TXEN0 external pull_low = 0, flooding control function disable. Flooding Port ID bit 3 external pull_hgih =1. 0 TXEN1 external pull_low = 0, VLAN tag 1522 bytes acceptance enable disable. Flooding control function enable. external pull_hgih =1, flooding control function enable. 0 TXEN2 external pull_low = 0, port15 operate in half_duplex mode. VLAN tag 1522 bytes acceptance function enable. external pull_low = 0. Flooding Port ID bit 0 external pull_hgih =1. external pull_low = 0. 10/27 MTD516 Revision 1.2 19/06/2000 MYSON TECHNOLOGY MTD516 (Preliminary) 4.0 FUNCTIONAL DESCRIPTIONS The MTD516 is an 16 ports 10/100 Mbps fast Ethernet switch controller. It is a low cost solution for sixteen ports fast Ethernet SOHO switch design. No CPU interface is required; After power on reset, MTD516 provide an auto load configuration setting function through a 2 wire serial EEPROM interface to acess external EEPROM device, and MTD516 can easily be configured to support port_trunking, port_ VLAN, static entry, 802.3X flow control threshold setting , flooding port assignment ...etc functions. The following descriptions are MTD516’s major functional blocks overview. 4.1 Packet store and forwarding The MTD516 use simple store and forward algorithm as packet switching method. Input packet from ports will be stored to external memory first, while packet is good for forward (CRC chech ok, 64Bytes < length < 1518Bytes, not local packets, in the same VLAN group ) , if this packet’s DA hits, than forward this packet to the destination port, otherwise this packet will be broadcasted. 4.2 Learning and Routing The MTD516 supports 1K or 8K MAC entries for switching. Dynamic address learning is performed by each good unicast packet is completely received. The static address learning is achieved by EEPROM configuration. On the other hand, the routing process is performed whenever the packet’s DA is captured. If the DA can not get a hit result, the packet is going to switch broadcast or forward to the dedicated port according to the flooding control selction. 4.3 Aging Only the dynamic address entries are scheduled in the aging machine. If one station does not transmit any packet for a period of time, the belonging MAC address will be kicked out from the address table. The aging out time can be program through the EEPROM auto load configuration. (Default value is 300 seconds) 4.4 Buffer Queue Management The buffer queue manager is implemented to manage the external shared memory (use SDRAM/ SGRAM) for packet buffering. The main function of the buffer queue manager is to maintain the linked list consists of buffer IDs, which is used to show the corresponding memory address for each incoming packet. In addition, the buffer queue manager monitors the rested free spaces status of the external memory, If the packet storage achieve the predefined threshold value, the buffer queue manager will raise the alarm signal which is used to enable the flow control mechanism for avoiding transmission ID queue overflow happening. MTD516 provide 802.3x flow control in full duplex mode and back pressure control in half duplex mode. 4.5 Full Duplex 802.3x Flow Control In full duplex mode, MTD516 supports the standard flow control defined in IEEE802.3x standard. It enables the stopping of remote node transmissions via a PAUSE frame information interactoin. When the “802.3x flow control enable” bit is setted during power on reset (MDC pin is external pull_high), it enables MTD516 supporting 802.3x flow control function in full_duplex mode; When output port buffer queue’s on_using value reach the initialization setting threshold value(recommended XON_TH = 40’h under total free ID less then 100’h), MTD516 will send out a PAUSE packet with pause time equal to FFF to stop the remote node transmission; When the output port buffer queue’s on_using value reduce to the initialization threshold value(recommended Xoff_TH = 1C’h when using 2Mbytes external memory), MTD516 will also send a PAUSE packet with pause time equal to zero to inform the remote node to retransmit packet. 4.6 Half Duplex Back Pressure Control In half duplex mode, MTD516 provide a back pressure control mechanism to avoid dropping packets during network conjection situation. When the “back pressure control enable” bit is set during power on 11/27 MTD516 Revision 1.2 19/06/2000 MYSON TECHNOLOGY MTD516 (Preliminary) reset (EECLK pin is external pull_high), it enables MTD516 supporting back pressure function in half_duplex mode; When output port buffer queue’s on_using value reach the initialization setting threshold value (same with the Xon_TH value), MTD516 will send a JAM pattern in the input port when it senses an incoming packet , thus force a collision to inform the remote node transmission back off and will effectively avoid dropping packets. If the “back pressure control enable” bit is not set, and there is no free buffer queue available for the incoming packets, the incoming packets will be dropped. 4.7 MII Polling The MTD516 supports PHY management through the serial MDIO/MDC interface. After power on reset, the MTD516 write related abilities to the advertisement register 4 of connected PHY devices and restart the auto_negotiation prcedure via MDIO/MDC interface using the predefined PHY addresses increasingly from “01000”b to “10111”b. The MTD516 will periodically and continuously poll and update the link status and link partner’s ability which include speed, duplex mode, and 802.3x flow control capable status of the connected PHY devices through MDIO/MDC serial interface. 4.8 MAC and DMA engine The MTD516’s MAC performs all the functions in IEEE802.3 protocol, such as frame formatting, frame stripping, CRC checking, bad packet dropping, defering to line traffic, and collision handling. The MAC Rx_engine checks incoming packets and drops the bad packet which include CRC error, alignment error, short packet (less than 64 bytes), and long packet(more than 1518 bytes or 1522 bytes when the “VLAN tag 1522 bytes receive enable” bit is set during power on reset). Before transmission, The MAC Tx_engine will constantly monitor the line traffic using derfering precedure. Only if it has been idle for a 96 bits time (a minimum interpacket gap time, IPG time), actual transmmission can be started. For the half duplex mode, MAC engine will detect collision; if a collision is detected, the MAC Tx_engine will transmit a JAM pattern and then delay the re_transmission for a random time period determined by the back_off algorithm (MTD516 implements the truncated exponential back_off algorithm defined in IEEE 802.3 standard). For the full duplex mode, collision signal is ignored. The MTD516’s DMA engine performs the packets non_blocking transportation between MAC engine and external memory according to a high speed switching procedure. The switching procedure is completed by address learning/routing process and buffer queue management operation. 4.9 EEPROM interface MTD516 provide an auto load configuration setting function through a 2 wire serial EEPROM interface to acess external EEPROM device(24C02) after power on reset . MTD516 can easily be configured to support port_trunking, port_ VLAN, static entry, 802.3X flow control threshold setting , flooding port assignment ...etc functions. 4.10 Port Based VLAN The MTD516 supports VLAN configuration by port based methodology. One port select the certain ports to form its VLAN group by configuring the VLAN register. The packet (including broadcast packet) is not forwarding to the destination port whose VLAN group is different from the source port. 4.11 Port Trunking The port trunking function can also be implemented by VLAN registers. One trunk port isolates the packet transmitting and receiving from the other trunk ports, which performs a logical trunk topology. The non-trunk port should choose only one trunk port for transmitting, which can achieve the load balancing and maintain the packet sequences. 4.12 Memory Interface Two kinds of external memory interface can be selected by user -- 2M byte memory (256K32 x 2) and 4 M bytes ( 512K32 x 2). Maximum 4M byte external memory can be used for packet buffering. “-10 “ 12/27 MTD516 Revision 1.2 19/06/2000 MYSON TECHNOLOGY MTD516 (Preliminary) speed grade of SGRAM/SDRAM device is recommanded. The following table is the SGRAM application pin connection : Memory Type 256K32 512K32 Memory Chip No x2 x2 A[8] GND A8 A9 A8 4.13 Internal MII Registers Acess and Control The MTD516 support 2 serial pins (SDIO/SDC) for internal registers acess and control; The detailed registers informations are presented in Section5.0 (Internal MII Registers). 4.14 LED Display The MTD516 use 2 pins to output 2 kinds of LED display -- LEDDATA, LEDCLK, Using LEDCLK rising edge with 32 bits shift register to latch LEDDATA as DATA[31:0]. DATA[15:0] report Port15~0 link/receive activity led status. DATA[29:16] report packet buffer utilization rating, and DATA[31] report external memory test result(after power reset, MTD516 will test external SDRAM automatically), DATA[30] report the buffer almost full alarm signal . 13/27 MTD516 Revision 1.2 19/06/2000 MYSON TECHNOLOGY MTD516 (Preliminary) 5.0 Register Description Global Register : Control Register (addr = 5’h0) Bit 0 Name Port Reg Select enable 4-1 R/W R/W Descriptions “1” means Reg addr1-4 as Port Registers described as follows. R/W “0” means Reg addr1-4 as Global Registers described as follows. If bit0 = 0, bit[4:1] don’t care, and under bit[0] = 1, bit[4:1] = 0, Reg1-4 switch to Port0 Registers bit[4:1] = 1, Reg1-4 switch to Port1 Registers bit[4:1] = 2, Reg1-4 switch to Port2 Registers bit[4:1] = 3, Reg1-4 switch to Port3 Registers bit[4:1] = 4, Reg1-4 switch to Port4 Registers bit[4:1] = 5, Reg1-4 switch to Port5 Registers bit[4:1] = 6, Reg1-4 switch to Port6 Registers Port Reg Select bit[4:1] = 7, Reg1-4 switch to Port7 Registers bit[4:1] = 8, Reg1-4 switch to Port8 Registers bit[4:1] = 9, Reg1-4 switch to Port9 Registers bit[4:1] = a, Reg1-4 switch to Port10 Registers bit[4:1] = b, Reg1-4 switch to Port11 Registers bit[4:1] = c, Reg1-4 switch to Port12 Registers bit[4:1] = d, Reg1-4 switch to Port13 Registers bit[4:1] = e, Reg1-4 switch to Port14 Registers 5 Scan Mode Enable Scanout Group Select 13-10 Scanout Port Select 15-14 15-0 Default Value 9-6 R/W bit[4:1] = f, Reg1-4 switch to Port15 Registers “1” Enable R/W “0” Disable bit[9:6]= 0 means group 0 , etc ... R/W bit[13:10] = 0 means Port0, etc,... Reserved 16’h0000 Global Register : XON/XOFF Register (addr = 5’h1) Bit 7-0 15-8 15-0 Name XONTH XOFFTH Default Value R/W R/W R/W Descriptions XON threshold XOFF threshold XON threshold default is 8’d64(2M) XOFF threshold default is 8’h28(2M) P.S while EEPROM is enabled, this register’s content will be updated by EEPROM. 14/27 MTD516 Revision 1.2 19/06/2000 MYSON TECHNOLOGY MTD516 (Preliminary) Global Register : Aging Register (addr = 5’h2) Bit 15-0 15-0 Name AgeTH R/W R/W Default Value Descriptions Aging time. Default is 16’d300. P.S while EEPROM is enabled, this register’s content will be updated by EEPROM. Global Register : Uplink0 Register (addr = 5’h3) Bit 15 14-0 9-5 4-0 15-0 Name R/W Port2 ID Port1 ID Port0 ID R/W R/W R/W Default Value Descriptions Reserved Specify port2’s uplink port ID Specify port1’s uplink port ID Specify port0’s uplink port ID Default is 16’h001f. P.S this register’s writing sequence is Jumper setting ==> EEPROM ==>MII management command. Global Register : Uplink1 Register (addr = 5’h4) Bit 15 14-0 9-5 4-0 15-0 Name R/W Port5 ID Port4 ID Port3 ID R/W R/W R/W Default Value Descriptions Reserved Specify port5’s uplink port ID Specify port4’s uplink port ID Specify port3’s uplink port ID Default is 16’h0000. P.S this register’s writing sequence is Jumper setting ==> EEPROM ==>MII management command. Global Register : Uplink2 Register (addr = 5’h5) Bit 15 14-0 9-5 4-0 15-0 Name R/W Port8 ID Port7 ID Port6 ID R/W R/W R/W Default Value Descriptions Reserved Specify port8’s uplink port ID Specify port7’s uplink port ID Specify port6’s uplink port ID Default is 16’h0000. P.S this register’s writing sequence is Jumper setting ==> EEPROM ==>MII management command. 15/27 MTD516 Revision 1.2 19/06/2000 MYSON TECHNOLOGY MTD516 (Preliminary) Global Register : Uplink3 Register (addr = 5’h6) Bit 15 14-0 9-5 4-0 15-0 Name R/W Port11 ID Port10 ID Port9 ID R/W R/W R/W Default Value Descriptions Reserved Specify port11’s uplink port ID Specify port10’s uplink port ID Specify port9’s uplink port ID Default is 16’h0000. P.S this register’s writing sequence is Jumper setting ==> EEPROM ==>MII management command. Global Register : Uplink4 Register (addr = 5’h7) Bit 15 14-0 9-5 4-0 15-0 Name R/W Port14 ID Port13 ID Port12 ID R/W R/W R/W Default Value Descriptions Reserved Specify port14’s uplink port ID Specify port13’s uplink port ID Specify port12’s uplink port ID Default is 16’h0000. P.S this register’s writing sequence is Jumper setting ==> EEPROM ==>MII management command. Global Register : Uplink5 Register (addr = 5’h8) Bit 15-5 4-0 15-0 Name R/W Port15 ID R/W Default Value Descriptions Reserved Specify port15’s uplink port ID Default is 16’h0000. P.S this register’s writing sequence is Jumper setting ==> EEPROM ==>MII management command. Global Register : Brdcast Storm Threshold Register (addr = 5’h9) Bit 15-9 8 7-0 15-0 Name R/W Brdcast TH R/W R/W Default Value Descriptions Reserved Backpressure Enhance Mode Enable. Specify broadcast storm threshold Default is 16’h00ff. P.S this register’s writing sequence is Jumper setting ==> EEPROM ==>MII management command. 16/27 MTD516 Revision 1.2 19/06/2000 MYSON TECHNOLOGY MTD516 (Preliminary) Global Register : Status0 Register (addr = 5’ha) Bit 15-0 Name fifofull R/W R/O Descriptions output Port15-0 RXDMA fifofull signal Global Register : Status1 Register (addr = 5’hb) Bit 15-0 Name fifoempty R/W R/O Descriptions output Port15-0 TXDMA TPUR(fifoempty)signal Global Register : Status2 Register (addr = 5’hc) Bit Name 15-14 13 12 11 10 FreeCntIs0 9 EEDONE 8 MemBistErr 7 MemBistDone 6 LthTblBistErr 5 LthTblBistDone 4 AddrTblBistErr 3 AddTblBistDone 2 BufInitDone 1 BufBistErr 0 BufBistDone R/W R/O R/O R/O R/O R/O R/O R/O R/O R/O R/O R/O R/O Descriptions Reserved Reserved Reserved Reserved FreeCntIs0 EEDONE SGRAM Bist Error SGRAM Bist Done Length Table Bist Error Length Table Bist Done Internal 1K address table Bist Error Internal 1K address table Bist Done R/O R/O R/O Buffer link initialization Done Buffer Table Bist Error Buffer Table Bist Done Global Register : Control/Status0 Register (addr = 5’hd) Bit 15-0 15-0 Name FlowCtrl Default Value R/W R/W Descriptions Output MII polling port15-0 flow control information. P.S “1” means flow control is enabled when Polling disabled, default value is 16’hffff when Polling enabled, default value is 16’h0000. 17/27 MTD516 Revision 1.2 19/06/2000 MYSON TECHNOLOGY MTD516 (Preliminary) Global Register : Control/Status1 Register (addr = 5’he) Bit 15-0 15-0 Name R/W R/W Link Descriptions Output MII polling port15-0 link information. P.S “1” means link good when Polling disabled, default value is 16’hffff Default Value when Polling enabled, default value is 16’h0000. Global Register : Control/Status2 Register (addr = 5’hf) Bit 15-0 15-0 Name R/W R/W Speed Descriptions Output MII polling port15-0 speed information. P.S “1” means 100M when Polling disabled, default value is 16’hffff Default Value when Polling enabled, default value is 16’h0000. Global Register : Control/Status3 Register (addr = 5’h10) Bit 15-0 15-0 Name R/W R/W FullDuplex Descriptions Output MII polling port15-0 full duplex information. P.S “1” means full duplex when Polling disabled, default value is 16’hffff Default Value when Polling enabled, default value is 16’h0000. Global Register : DebugReg0 Register (addr = 5’h11) Bit 15-0 15-0 Name LocalFilter Default Value R/W R/W Descriptions “1” disable port15-0 local packet filter function. Default is 16’h0000 Global Register : DebugReg1 Register (addr = 5’h12) Bit 15-0 15-0 Name RXLengthChk Default Value R/W R/W Descriptions “1” disable port15-0 Rx Length Check function. Default is 16’h0000 18/27 MTD516 Revision 1.2 19/06/2000 MYSON TECHNOLOGY MTD516 (Preliminary) Global Register : DebugReg2 Register (addr = 5’h13) Bit 15-0 15-0 Name Reserved Default Value R/W R/W Descriptions Reserved Default is 16’h0000 Global Register : DebugReg3 Register (addr = 5’h14) Bit 15-0 15-0 Name CRCChk Default Value R/W R/W Descriptions “1” disable port15-0 CRC check function. Default is 16’h0000 Global Register : DebugReg4 Register (addr = 5’h15) Bit 15-0 15-0 Name Random# Default Value R/W R/W Descriptions “1” fix port15-0 random backoff number. Default is 16’h0000 Global Register : DebugReg5 Register (addr = 5’h16) Bit 15-0 15-0 Name Reserved Default Value R/W R/W Descriptions Reserved Default is 16’h0000 Global Register : FreeHead Register (addr = 5’h17) Bit 15-12 11-0 Name R/W FreeHead R/O Descriptions Reserved. Output Free List Head ID Global Register : FreeTail Register (addr = 5’h18) Bit 15-12 11-0 Name FreeTail R/W R/O Descriptions Reserved. Output Free List Tail ID Global Register : FreeCnt Register (addr = 5’h19) Bit 15-12 11-0 Name R/W FreeCnt R/O Descriptions Reserved. Output Free List Count Value. 19/27 MTD516 Revision 1.2 19/06/2000 MYSON TECHNOLOGY MTD516 (Preliminary) Global Register : PortEnable Register (addr = 5’h1a) Bit 15-0 15-0 Name PortEnable Default R/W R/W Descriptions “1” disable Port 15-0 Default value is 16’h0000 Port Register : TxLinkHead Register (addr = 5’h1) Bit 15-13 12-0 Name R/W TxLinkHead R/O Descriptions Reserved Output Port Tx Queue Head Value Port Register : TxLinkHead Register (addr = 5’h2) Bit 15-13 12-0 Name R/W TxLinkCnt R/O Descriptions Reserved Output Port Tx Queue Count Value Port Register : VLANReg Register (addr = 5’h3) Bit 15-0 Name VLANReg R/W R/W Descriptions Select Port VLAN Group. 6.0 EEPROM Content EEPROM Content Addr h0 h1 h2 h3 h4 h5 h6 h7 Name EOB AgeLow AgeHigh VLAN0L VLAN0H VLAN1L VLAN1H VLAN2L Descriptions Last EEPROM content address value Age Time bit 7-0. Age Time bit 15-8. Port0 VLAN Low Byte Register. Port0 VLAN Low Byte Register. Port1 VLAN Low Byte Register. Port1 VLAN Low Byte Register. Port2 VLAN Low Byte Register. 20/27 MTD516 Revision 1.2 19/06/2000 MYSON TECHNOLOGY MTD516 (Preliminary) EEPROM Content Addr h8 h9 ha hb hc hd he hf h10 h11 h12 h13 h14 h15 h16 h17 h18 h19 h1a h1b h1c h1d h1e h1f h20 h21 h22 h23 h24 h25 h26 h27 h28 h29 h2a h2b h2c h2d h2e h2f h30 h31 h32 Name VLAN2H VLAN3L VLAN3H VLAN4L VLAN4H VLAN5L VLAN5H VLAN6L VLAN6H VLAN7L VLAN7H VLAN8L VLAN8H VLAN9L VLAN9H VLAN10L VLAN10H VLAN11L VLAN11H VLAN12L VLAN12H VLAN13L VLAN13H VLAN14L VLAN14H VLAN15L VLAN15H Uplink0 Uplink1 Uplink2 Uplink3 Uplink4 Uplink5 Uplink6 Uplink7 Uplink8 Uplink9 Uplink10 Uplink11 Uplink12 Uplink13 Uplink14 Uplink15 Descriptions Port2 VLAN Low Byte Register. Port3 VLAN Low Byte Register. Port3 VLAN Low Byte Register. Port4 VLAN Low Byte Register. Port4 VLAN Low Byte Register. Port5 VLAN Low Byte Register. Port5 VLAN Low Byte Register. Port6 VLAN Low Byte Register. Port6 VLAN Low Byte Register. Port7 VLAN Low Byte Register. Port7 VLAN Low Byte Register. Port8 VLAN Low Byte Register. Port8 VLAN Low Byte Register. Port9 VLAN Low Byte Register. Port9 VLAN Low Byte Register. Port10 VLAN Low Byte Register. Port10 VLAN Low Byte Register. Port11 VLAN Low Byte Register. Port11 VLAN Low Byte Register. Port12 VLAN Low Byte Register. Port12 VLAN Low Byte Register. Port13 VLAN Low Byte Register. Port13 VLAN Low Byte Register. Port14 VLAN Low Byte Register. Port14 VLAN Low Byte Register. Port15 VLAN Low Byte Register. Port15 VLAN Low Byte Register. [4:0] Port 0 flooding port. [7:5] Reserved. [4:0] Port 1 flooding port. [7:5] Reserved. [4:0] Port 2 flooding port. [7:5] Reserved. [4:0] Port 3 flooding port. [7:5] Reserved. [4:0] Port 4 flooding port. [7:5] Reserved. [4:0] Port 5 flooding port. [7:5] Reserved. [4:0] Port 6 flooding port. [7:5] Reserved. [4:0] Port 7 flooding port. [7:5] Reserved. [4:0] Port 8 flooding port. [7:5] Reserved. [4:0] Port 9 flooding port. [7:5] Reserved. [4:0] Port 10 flooding port. [7:5] Reserved. [4:0] Port 11 flooding port. [7:5] Reserved. [4:0] Port 12 flooding port. [7:5] Reserved. [4:0] Port 13 flooding port. [7:5] Reserved. [4:0] Port 14 flooding port. [7:5] Reserved. [4:0] Port 15 flooding port. [7:5] Reserved. 21/27 MTD516 Revision 1.2 19/06/2000 MYSON TECHNOLOGY MTD516 (Preliminary) EEPROM Content Addr h33 h34 h35 h36 h37 h38 Name BrdcastTH XONTh XOFFTH DisPortL DisPortH CtrlEnable h39h3f h40h46 StaticSA1 h47h4d StaticSA2 Descriptions Broadcast Threshold XON Threshold XOFF Threshold Disable Port 7-0 Disable Port 15-8 System control byte bit0-- Enhance Backpressure Enable [7:1] Reserved. Reserved 45[7:0]~40[7:0] means Static SA[47:0], 46[3:0] means Port ID, 46[7:4] Reserved. 4c[7:0]~47[7:0] means Static SA[47:0], 47[3:0] means Port ID, 47[7:4] Reserved. 22/27 MTD516 Revision 1.2 19/06/2000 MYSON TECHNOLOGY MTD516 (Preliminary) 7.0 Electrical Characteristics 7.1 Absolute Maximum Ratings Symbol Parameter VCC Power Supply Voltage VIN VOUT TSTG RATING -0.3 to 3.6 Unit V Input Voltage -0.3 to Vcc+0.3 V Output Voltage -0.3 to Vcc+0.3 Storage Temperature V ο -55 to 150 C 7.2 Recommended Operating Conditions Symbol VCC Power Supply VIN Input Voltage Tj Parameter Commercial Junction Operating Temperature Industrial Junction Operating Temperature Min. 3.0 Typ. 3.3 Max. 3.6 0 - Vcc Unit V V 0 25 115 ο -40 25 125 ο C C 7.3 DC Electrical Characteristics Symbol Parameter IIL Input Leakage Current IOZ Tri-state Leakage Current CIN Conditions no pull-up or down Min. -1 Typ. -1 Input Capacitance Max. 1 Unit uA 1 uA 2.8 pF COUT Output Capacitance 2.7 4.9 pF CBID3 Bi-direction buffer Capacitance 2.7 4.9 pF 0.3*Vcc V VIL Input Low Voltage VIH Input High Voltage VOH Output High Voltage CMOS 0.7*Vcc IOL=2,4,8,12,16,24mA VOL Output Low Voltage IOH=2,4,8,12,16,24mA RI Input Pull-up/down resistance CMOS VIL=0V or VIH=VCC V 0.4 2.4 V V 75 KOhm (Under recommended operating conditions and Vcc = 3.0 ~ 3.6V, Tj = 0 to +115 oC) 23/27 MTD516 Revision 1.2 19/06/2000 MYSON TECHNOLOGY MTD516 (Preliminary) 7.4 Electrical Characteristics FIGURE 1. RMII timing T1 REFCLK T2 CRSDV RXD[1:0] Valid T3 TXEN TXD[1:0] Symbol T1 T2 T3 T4 T4 Valid Parameter RMII input setup time RMII input hold time RMII output setup time RMII output hold time Min. 1 1 3 5 Typ. Max. Unit nS nS nS nS Note Unit nS Note FIGURE 2. Memor y Wr ite Timing T5 MEMCLK T6 T7 RASB CASB T8 WEB T6 T6 T7 AD[8:0] Valid Valid T6 DQ[63:0] Symbol Parameter T5 Memory clock cycle Memory command/address/data T6 setup time Memory command/address/data T7 hold time T8 Row active to burst write T7 T7 Valid Min. 12 Typ. Max. 6 nS 2 nS 2 24/27 CLK MTD516 Revision 1.2 19/06/2000 MYSON TECHNOLOGY MTD516 (Preliminary) FIGURE 3. Memor y Read Timing T5 MEMCLK T6 T7 RASB CASB T8 WEB T6 T7 AD[8:0] T6 Valid T7 Valid T9 T10 DQ[63:0] Valid Symbol Parameter T10 Memory read data setup time T11 Memory ead data hold time Min. 2 2 Typ. Max. Unit nS nS Note Max. Unit uS nS nS Note FIGURE 4. EEPROM timing T11 EECLK T13 T12 EEDATA Symbol Parameter T11 EEPROM clock cycle T12 EEDATA input setup time T13 EEDATA input hold time Valid Min. 1 1 25/27 Typ. 10 MTD516 Revision 1.2 19/06/2000 MYSON TECHNOLOGY MTD516 (Preliminary) FIGURE 5. LED Inter face T14 LEDCLK T15 LEDDATA Valid Symbol Parameter T14 Led display strobe period T15 LEDCLK setup time T16 LEDCLK hold time T16 Valid Min. 26/27 Valid Typ. 20 5 5 Max. Unit uS uS uS Note MTD516 Revision 1.2 19/06/2000 MYSON TECHNOLOGY MTD516 (Preliminary) 8.0 208 pin PQFP Package Data A D A1 A2 D1 Norm Max Min Norm Max A - - 4.10 - - 0.161 A1 0.25 - - 0.010 - - A2 3.20 3.32 3.60 0.126 0.131 0.142 157 208 E2 E1 D 30.60 BSC 1.205 BSC D1 28.00 BSC 1.102 BSC D2 25.50 1.004 E 30.60 BSC 12.05 BSC E1 28.00 BSC 1.102 BSC E2 25.50 0.08 - 0.25 0.003 - R1 0.08 - - 0.003 - - 0o 3.5o 7o 0o 3.5o 7o - - 0o - - 1 0o 8o REF 2 0.09 0.15 0.20 0.004 0.006 0.008 L 0.45 0.60 0.75 0.018 0.024 0.030 S 1.30 REF 0.20 e L1 53 104 4x e bbb|H|A-B|O b 1 C aaa|C|A-B|O R2 8o REF c L1 105 0.010 8o REF 8o REF 3 52 1.004 R2 E 156 1 Dimension in inch Min -|0.05 s D2 Dimension in mm Symbol b - 0.052 REF - 0.008 0.50 BSC 0.17 0.20 - - 0.020 BSC 0.27 0.007 0.008 0.011 2 R1 O|ddd M |C|A-B s |D s GAGE PLANE -C|ccc|C SEATING PLANE See Detail A 0.25mm L 3 S y Detail Seating Plane 27/27 MTD516 Revision 1.2 19/06/2000