NT68520X,E XGA,SXGA Flat Panel Monitor Controller Ver.1.0 1 NT68520X,E 1 REVISION HISTORY ..................................................................................................... 3 2 FEATURES .................................................................................................................. 4 3 GENERAL DESCRIPTION ............................................................................................ 6 4 PIN CONFIGURATION .................................................................................................. 7 5 PAD CONFIGURATION................................................................................................. 8 6 BLOCK DIAGRAM ........................................................................................................ 9 7 PIN AND PAD DESCRIPTIONS .................................................................................. 10 8 FUNCTIONAL DESCRIPTION .................................................................................. 14 9 ABSOLUTE MAXIMUM RATINGS .............................................................................. 87 10 DC ELECTRICAL CHARACTERISTICS ................................................................... 88 11 AC ELECTRICAL CHARACTERISTICS ................................................................... 90 12 BONDING DIAGRAM ................................................................................................ 93 13 ORDERING INFORMATION .................................................................................... 94 14 PACKAGE INFORMATION ..................................................................................... 95 2003/4/15 2 Ver.1.0 NT68520X,E REVISION HISTORY Version 1.0 2003/4/15 NT68520 Specification Revision History Content Final sheet first version 3 Date Apr 2003 Ver.1.0 NT68520X,E FEATURES VGA Front End ♦ Built-in triple high-speed ADC, PLL, and pre-amplifier for analog RGB input ♦ Support both non-interlaced and interlaced RGB graphic input signals ♦ Internal generated programmable clamping pulse ♦ Gain control for input signal ranging from 0.5V~1.0V ♦ Support 32 steps of phase adjust ♦ ADC sampling rate up to 110 MHz for X type and135 MHz for E type ♦ VGA input resolution up to XGA 1024x768@75 for X type and SXGA 1280x1024@75Hz for E type YUV Front End ♦ Support ITU-R BT.656 8-bit Input ♦ Built-in YUV to RGB color space converter Video Processor ♦ Flexible de-interlacing unit for VGA and digital YUV video input data ♦ Independent Horizontal and Vertical zoom in/out algorithm ♦ Enhanced interpolation algorithm for optimal image quality ♦ RGB offset control for brightness adjust ♦ RGB gain control for contrast adjust ♦ 8-bit programmable gamma table for panel compensation ♦ Dithering function supports 24-bit quality for 18-bit panel ♦ Auto-calibration function for quick video centering, clock adjust, and phase adjust Sync Processor ♦ Signal type accepts separate, composite and TTL-Level Sync-On-Green (SOG) ♦ Polarity detection for HSYNCI and VSYNCI ♦ Fast mode change detection function Internal OSD Support ♦ 128 ROM fonts at the size of 12x18 ♦ 64 programmable RAM fonts ♦ Internal SRAM allows up to 320 characters, with programmable OSD frame size ♦ Programmable shadow or border control for each character ♦ Programmable blinking effect for each character 2003/4/15 4 Ver.1.0 NT68520X,E ♦ Support simultaneous display of up to 4 OSD windows ♦ Programmable shadow display for each window ♦ Each OSD row can be independently zoomed up to 4 times for horizontal and vertical axes ♦ Support transparent, translucent, and opaque effects ♦ 16 colors for foreground display and background display selected from internal color palette Display Interface ♦ Display resolution up to 1024x768@75Hz for X type and 1280x768@75Hz for E type ♦ Support single pixel mode (18-bit) and dual pixel mode (24-bit) MCU Interface ♦ Support serial 2-wire IIC bus Power ♦ 3.3V power supply ♦ Less than 2.5 W 2003/4/15 5 Ver.1.0 NT68520X,E GENERAL DESCRIPTION The NT68520 is a high-quality image and highly integrated LCD controller, which combines triple video pre-amplifier, triple ADC, de-interlacing, YUV to RGB color space converter, scaling engine, gamma, OSD, and digital gain/offset, and supports analog RGB input, digital RGB input, and video CCIR656 8-bit input. The video amplifier supports a full scale range of 0.5 ~ 1Vp-p with 0.8 ~ 2X gain and also provides a DC offset adjustment. The ADC supports up to 135MHz pixel rate and build in a low jitter PLL to sampling input video that provides a low-noise and more stabile image quality. The NT68520 also builds in a DSP engine to execute linear zoom-in, zoom-out function of image to fit different panel resolutions. The OSD provides 64 RAM font and 128 ROM font that is very simply to create customer OSD. The display interface supports single (24-bit) or dual (48-bit) pixel out format, and supports the 6-bit/color or 8-bit/color LCD panel. The built-in internal PLL locking to the reference clock generates all of the display timing to various LCD panels. 2003/4/15 6 Ver.1.0 NT68520X,E 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 DGND PLL_HS RSTn DEI IRQn SCL SDA R7 R6 I2C_ADDR1/R5 I2C_ADDR0/R4 VSYNCO HSYNCO CVDD_CAP VDD DVDD YUV_CLK/DVI_CLK Y7/R3 Y6/R2 Y5/R1 Y4/R0 Y3/G7 Y2/G6 Y1/G5 Y0/G4 DGND CVDD G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 DVDD PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 NT68520 –X , -E QFP 160 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 CVDD CGND DVDD BA0 BA1 BA2 BA3 BA4 BA5 BA6 BA7 DGND GA0 GA1 GA2 GA3 GA4 GA5 GA6 GA7 DVDD RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 DCLK NC DGND NC NC DGND NC NC DISP_HS VDD CVDD_CAP NC CVDD NC CGND DVDD DVDD BB0 BB1 BB2 BB3 BB4 BB5 BB6 BB7 DGND GB0 GB1 GB2 GB3 GB4 GB5 GB6 GB7 DVDD RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 NC NC DGND NC NC DVDD DISP_DE DISP_VS 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 PLL_GND PLL_VDD PLL_VAA VCON CZ PLL_GNDA BIAS_GNDA BIAS_VAA VREF TESTP TESTN ADC_RVAA ADC_RGNDA RVAA RIN RGNDA ADC_GVAA ADC_GGNDA VTOP VMID VBOT GVAA GIN GGNDA ADC_BVAA ADC_BGNDA BVAA BIN BGNDA VCC MDBIAS_GNDA DPP_VAA1 DPP_GNDA1 CGND OSCI OSCO NC HSYNCI SOGI VSYNCI 2003/4/15 7 Ver.1.0 NT68520X,E PAD CONFIGURATION DVDD 121 122 B0/B0 123 B1/B1 124 B2/B2 125 B3/B3 126 B4/B4 127 B5/B5 128 B6/B6 129 B7/B7 130 G0/G0 131 G1/G1 132 G2/G2 133 G3/G3 CVDD CVDD 134 CGND CGND DGND DGND 135 136 Y0/G4/G4 137 Y1/G5/G5 138 Y2/G6/G6 139 Y3/G7/G7 140 Y4/R0/R0 141 Y5/R1/R1 142 Y6/R2/R2 143 Y7/R3/R3 YUV_CLK/DVI_CLK 144 DVDD DVDD DVDD 145 VDD VDD 146 CVDD_CAP 147 CVDD_CAP HSYNCO 148 VSYNCO 149 150 R4/I2C_ADDR0/R4 151 R5/I2C_ADDR1/R5 152 R6/R6 153 R7/R7 SDA 154 SCL 155 IRQn 156 DEI 157 RSTn 158 PLL_HS 159 DGND 160 PLL_GND PLL_VDD PLL_VAA VCON CZ PLL_GNDA BIAS_GNDA BIAS_VAA VREF TESTP TESTN ADC_RVAA ADC_RVAA ADC_RGNDA ADC_RGNDA RVAA RIN RGNDA ADC_GVAA ADC_GVAA ADC_GGNDA ADC_GGNDA VTOP VMID VBOT GVAA GIN GGNDA ADC_BVAA ADC_BVAA ADC_BGNDA ADC_BGNDA BVAA BIN BGNDA VCC MDBIAS_GNDA DPP_VAA1 DPP_GNDA1 CGND DGND OSCI OSCO NC HSYNCI SOGI VSYNCI 1 2 3 4 5 6 7 8 9 10 11 12 120 119 118 117 116 115 114 113 112 111 110 13 14 15 16 17 18 NT68520 19 20 21 22 23 24 25 01-08-2002/WCSue 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 82 81 DVDD CVDD CVDD CGND CGND DVDD BA0 BA1 BA2 BA3 BA4 BA5 BA6 BA7 DGND DGND GA0 GA1 GA2 GA3 GA4 GA5 GA6 GA7 DVDD DVDD RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 DCLK NC DGND NC NC DGND NC NC DISP_HS VDD VDD CVDD_CAP CVDD_CAP 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 DISP_VS DISP_DE DVDD NC NC DGND NC NC RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 DVDD DVDD GB7 GB6 GB5 GB4 GB3 GB2 GB1 GB0 DGND DGND BB7 BB6 BB5 BB4 BB3 BB2 BB1 BB0 DVDD DVDD DVDD CGND CGND NC CVDD CVDD NC 2003/4/15 8 Ver.1.0 NT68520X,E BLOCK DIAGRAM SRAM Digital Video YUV Input YUV to RGB Analog RGB Pre-Amp ADC PLL Gamma Syncprocessor Display Interface OSD Auto calibration HSYNCI VSYNCI LCD Pannel Dithering DSP Processing Host Interface Gain and Offset I2C Bus 2003/4/15 9 Ver.1.0 NT68520X,E PIN AND PAD DESCRIPTIONS Pin No. 1 2 3 4 5 Pad No. 1 2 3 4 5 Name PLL_GND PLL_VDD PLL_VAA VCON CZ Type P P P I I 6 7 6 7 PLL_GNDA BIAS_GNDA P P 8 8 BIAS_VAA P 9 9 VREF P 10 11 12 10 11 12,13 TESTP TESTN ADC_RVAA O O P 13 14,15 ADC_RGNDA P 14 16 RVAA P 15 16 17 18 RIN RGNDA I P 17 19,20 ADC_GVAA P 18 21,22 ADC_GGNDA P 19 23 VTOP P 20 24 VMID P 21 25 VBOT P 22 26 GVAA P 23 24 27 28 GIN GGNDA I P 25 29,30 ADC_BVAA P 26 31,32 ADC_BGNDA P 27 33 BVAA P 28 34 BIN I 2003/4/15 10 Description ADC PLL digital ground ADC PLL digital power ADC PLL analog power PLL loop filter input PLL loop filter internal resister input ADC PLL analog ground Analog ground for ADC PLL internal bias circuit Analog power for ADC PLL internal bias circuit External reference voltage of 2.5V VGA output test pin VGA output test pin ADC analog power for R channel ADC analog ground for R channel Front-end analog power for R channel R channel analog video input Front-end analog ground for R channel ADC analog power for G channel ADC analog ground for G channel ADC resister ladder top de-couple input ADC resister ladder middle de-couple input ADC resister ladder bottom de-couple input Front-end analog power for G channel G channel analog video input Front-end analog ground for G channel ADC analog power for B channel ADC analog ground for B channel Front-end analog power for B channel B channel analog video input Ver.1.0 NT68520X,E 29 35 BGNDA P 30 36 VCC P 31 37 MDBIAS_GNDA P 32 33 34 DPP_VAA1 DPP_GNDA1 CGND DGND OSCI OSCO NC HSYNCI P P P 35 36 37 38 38 39 40 41 42 43 44 45 39 46 SOGI I 40 47 VSYNCI I 41 42 48 49,50 NC CVDD I P 43 44 45 46 47-54 55 56-63 64 65-72 73 74 75 76 77 78 79 51 52,53 54,55 56 57-64 65,66 67-74 75,76 77-84 85 86 87 88 89 90 91 NC CGND DVDD DVDD BB0 ~ BB7 DGND GB0 ~ GB7 DVDD RB0- RB7 NC NC DGND NC NC DVDD DISP_DE 80 81 92 93,94 DISP_VS CVDD_CAP O P 82 95,96 VDD P 83 84 97 98 DISP_HS NC O 2003/4/15 I O I P P P O P O P O P P P P O 11 Front-end analog ground for B channel Display PLL analog power supply Analog power for display PLL internal bias circuit Display PLL analog power Display PLL analog ground Core logic ground Crystal OSC input Crystal OSC output NC pin VGA port horizontal sync input with smith trigger VGA port Sync On Green input with smith trigger VGA port vertical sync input with smith trigger Connect to digital ground Core logic power de-couple pin. External capacitor (0.1uF) Connection is recommended. NC pin Core logic ground Display digital power supply Display digital power supply Port B, B channel output Display digital ground Port B, G channel output Display digital power supply Port B, R channel output NC pin NC pin Display digital ground Connect to digital ground Connect to digital ground Display digital power supply Panel display data enable signal Panel display vertical sync Internal regulator output pin. External regulating capacitor (10uF~100uF) connected is needed. Main power supply for internal regulator (3.3V) Panel display horizontal sync NC pin Ver.1.0 NT68520X,E 85 86 87 88 89 90 91 92-99 100 101-108 109 110-117 118 119 120 99 100 101 102 103 104 105 106-113 114,115 116-123 124,125 126-133 124 125,126 127 NC DGND NC NC DGND NC DCLK RA0 ~ RA7 DVDD GA0 ~ GA7 DGND BA0 ~ BA7 DVDD CGND CVDD O O P O P O P P P 121 122-133 134 128 129-140 141,142 DVDD B0~B7, G0~G3 CVDD P I P 135 136-143 143,144 145,146 147-154 P P I 144 155 CGND DGND Y0-Y7 G4~G7, R0~R3 YUV_CLK/DVI_CLK 145 146 156-158 159-160 DVDD VDD P P 147 161,162 CVDD_CAP P 148 163 HSYNCO O 149 164 VSYNCO O 150 165 I2C_ADDR0/R4 I 151 166 I2C_ADDR1/R5 I 152 153 167 168 R6 R7 2003/4/15 P P 12 I NC pin Display digital ground Connect to digital ground Connect to digital ground Display digital ground NC pin Display clock Port A, R channel output Display digital power supply Port A, G channel output Display digital ground Port A, B channel output Display digital power supply Core logic ground Core logic power de-couple pin. External capacitor (0.1uF) Connection is recommended. Display digital power supply Digital input B0~B7, G0~G7 Core logic power de-couple pin. External capacitor (0.1uF) Connection is recommended. Core logic ground Display digital ground Video data input of bit 0~7 Digital input G4~G7, R0~R3 1.Video port clock input 2.Digital RGB clock input Display digital power supply Main power supply for internal regulator (3.3V) Internal regulator output pin. External regulating capacitor (10uF~100uF) connection is needed. Sync-process horizontal sync output Sync-process vertical sync output 1.I2C slave address, Refer to Page 27 I2C slave address setting 2.Digital input R4 1.I2C slave address. Refer to Page 27 for I2C slave address setting 2.Digital input R5 Digital input R6 Digital input R7 Ver.1.0 NT68520X,E 154 169 SDA I/O 155 170 SCL I 156 157 158 159 160 171 172 173 174 175 IRQn DEI RSTn PLL_HS DGND I/O I I I P 2003/4/15 13 Host interface serial data in/out incorporate smith trigger Host interface serial clock incorporate smith trigger buffer & spike filter. Interrupt request output Digital input data enable signal System reset H sync input for PLL Display digital ground Ver.1.0 NT68520X,E FUNCTION DESCRIPTION VGA Front End The NT68520 provides a built-in video pre-amplifier, a clock-recovery circuit and an analog-to-digital converter to effectively save the cost of the required external expensive Pre-amp and ADCPLL. The pre-amplifier circuit is used to adjust the gain (Contrast) of input video amplitude and shift the DC offset voltage (Brightness). The clock-recovery circuit consisting of a high-speed phase lock loop (PLL) is used to generate the clock to sample analog RGB data. This circuit is locked to the HSYNC of the incoming video signal. The analog-to-digital converter (ADC) transfers the input analog RGB video to digital output data with each color 8-bit resolution. Pre-amplifier Unit RIN/GIN/BIN are high-impedance input pins that accept the RED, GREEN, and BLUE channel graphics signals. They accommodate input signals ranging from 0.5V to 1.0V full scale. Signals should be AC-couple to these pins. Due to AC coupling, clamping pulse is needed to define the time during which the input signal is clamped to ground, establishing a black reference. Typically, the clamping pulse is defined during the back porch period of the graphics signal. The NT68520 generates the clamping pulse internally and the position and duration are programmable. Clamping pulse-starting position is defined in register 0B[3:0], and pulse width is defined in 0B[7:4]. TCLP_Delay = Reg0B[3:0] * CKOUT TCLP_Width = Reg0B[7:4] * CKOUT Hsync Clamping Pulse TCLP_Delay TCLP_Width The NT68520 has three independent variable gain amplifiers for each channel with input 2003/4/15 14 Ver.1.0 NT68520X,E signal ranging from 0.5V to 1.0V（p-p）, the ADC’s full-scale input level is 1V（p-p）. Three independent registers are used to adjust the signal level (gain), the relation between the gain and register value is as follows: Gain = 0.8 + 1.2/ 255 * Gain <7:0> Gain<7:0> Gain Input Signal(0.5V~1.2V) Output Signal(1.0V) Phase-locked loop The internal PLL locks to the HSYNC input (frequency range 15~100 KHz) and derives a sampling clock (CKOUT) to internal ADC. The bandwidth of PLL is from 16 MHz to 135 MHz. Low Pass Filter Cp COAST CKEXT Cz VCON INV Cz 12 to 135Mhz HSYNC Phase Frequency Detector 32 Step Phase Adjust VCO Inverter CKOUT 5 bit 1 bit Polarity Select (1 bit) 11 bit Divider N 1 to 2048 PLL diagram 2003/4/15 15 Ver.1.0 NT68520X,E Divider The 11-bit value of Divider supports division ratios from 1 to 2048. The higher the value loaded in this register, the higher is the resulting clock frequency with respect to a fixed Hsync frequency. Users should program the corrective Divider value with respect to the incoming video frequency. An incorrectly set Divider value will usually produce one or more vertical noise bars on the display. The greater the error, the greater the number of bars produced. CKEXT This pin may be used to provide an external clock to the internal ADC in place of the clock internally generated from Hsync. When an external clock is used, all other internal functions are operated normally. When unused, this pin should be tied through a 10K resistor to ground. COAST This input is used to stop the pixel clock generator synchronizing with Hsync and continue producing a clock at its current frequency and phase. This is useful when processing composite sync that fails to produce horizontal sync pulses in the vertical interval. Analog-to-Digital Converter The ADC is 8-bit resolution for each R/G/B channel and maximum clock frequency is 135 MHz. The ADC’s input range is 1V(p-p) full-scale. There is one over-range bit for each channel (ROR、GOR and BOR). It will be set to ‘1’ when the signal is over the ADC’s full-scale range. There is one under-range bit for each channel (RUR、GUR and BUR). It will be set to ‘1’ when the signal is under the ADC’s black level. The phase adjustment for R/G/B as the same time to ensure signal is correctly sampled by sampling clock. CAPTURE INTERFACE The function of Capture Interface is to provide the interface between NT68520 and external input devices. It can process non-interlaced and interlaced RGB graphic input and digital YUV video input. It also contains the built-in YUV to RGB color space converter. Users should select the video input source (YUV or VGA) and the polarity of external control signal, then program the H/V to capture size registers to indicate the display area. Auto Tune Auto Tune function includes Auto Gain, Auto Position, and Auto Phase. With such auto 2003/4/15 16 Ver.1.0 NT68520X,E adjustment support, it is possible to measure the correct phase, frequency, gain, and offset of ADC. The horizontal and vertical back porches of input image and the horizontal and vertical active regions can also be measured. AUTO_DAE=0 CAP_HS CAP_HW CAP_VH CAP_VS AUTO_DAE=1 2003/4/15 17 Ver.1.0 NT68520X,E One-cycle calibration Vsync F/W set F/W read AUTO_EN AUTO_RDY H/W start F/W clear calibration AUTO_EN H/W Stop Auto-calibration Multi-cycle Calibration Vsync F/W set F/W read & clear F/W read & clear AUTO_EN AUTO_RDY AUTO_RDY 0 H/W start H/W restart H/W restart F/W clear calibration calibration calibration AUTO_EN H/W Stop Auto-calibration Auto Gain Gain value is the Minimum or Maximum pixel value within a specified input image region for each RGB channel. This function is useful for measuring the noise margin of input video or for auto-contrast calibrating by adjusting ADC’ s offset and gain. Programming Steps: 1. Assign the capture area 2. Enable the Auto Gain function 3. Waiting for AUTO_RDY bit 4. Read the Max/Min result Auto Position The NT68520 provides the Horizontal/Vertical back porch and active region information. Users can use these values to set input capture registers to aid centering the screen automatically, and adjust the ADCPLL’s divider value to figure out the correct input pixel frequency. 2003/4/15 18 Ver.1.0 NT68520X,E ! If the YUV input is enabled, the Auto Position will detect the video back-porch and active region values according to the YUV_HREF input signal instead of the RGB input data. Programming Steps: 1. Specify an area covering the back porch of input video. 2. Enable the Auto Gain function. 3. Get the max R/G/B value. 4. Set the R/G/B Noise Margin value. 5. Enable the Auto Position function in Single mode. 6. Wait for Ready bit. 7. Read the detected value. Auto Clock By setting the H Active Reference Count value and getting the Auto Position result, it is easy to get the frequency of input pixel clock. Programming Steps: 1 ~ 4. It is the same as above. 5. Set the H Active Reference Count value. Ex: If the input video resolution is 800x600, then program the H Active Reference Count register with 800 values. 6. Enable the Auto Position function in Burst mode. 7. Wait for Ready bit. 8. Read the Status Register [3:2] to decide whether to increase or decrease the ADCPLL’s divider value. 9. If Status Register [3:2] = 01 (Detected H width = H Reference Count), it means the correct input pixel clock is obtained. DISPLAY INTERFACE The NT68520 display interface supports a single (24-bit) or a dual (48-bit) pixel out format and a 6-bit/color or 8-bit/color LCD panel. The built-in internal PLL locking to the reference clock generates all of the display timing to various LCD panels. The NT68520 also provides the programmable display driving capacity to reduce EMI influence as well as programmable clock delay to compensate clock skew. 2003/4/15 19 Ver.1.0 NT68520X,E Horizontal Total Horizontal Sync End Horizontal Sync Start Vertical Display End Vertical Sync Start Vertical Sync End Vertical Total Horizontal Display End ACTIVE DISPLAY SCREEN VIDEO PROCESSOR A video processor includes Interpolation Control, RGB Gain Control, RGB Offset Control, Dithering Control, and Gamma Correction Control. The NT68520’s enhanced interpolation method makes the zoomed display image look smoother and more comfortable. Users can adjust the RGB Gain (Contrast) and RGB Offset (Brightness) by the registers in the ADCPLL block, or registers in the Video processor block. But for YUV video input, it is suitable to adjust Contrast and Brightness here. Dithering function can provide 16.7 million color spaces for the 6-bit/color panel. It is recommended to open the dithering function when a 6-bit panel is used. Sync Processor The architecture of the sync processor is shown in the Sync Processor Block Diagram. The functions of the modules include polarity detection, horizontal frequency counter, vertical frequency counter, and polarity controllable HSYNCO and VSYNCO outputs. It can accept various input sources, such as separate sync, composite sync, and 2003/4/15 20 Ver.1.0 NT68520X,E Sync-On-Green. The SYNCI_SEL1/0 bit in Sync Input Control register will determine the type of the input sync sources. All HSYNCI, VSYNCI, and SOGI inputs have internal Schmitt trigger to improve noise immunity. YUV HSYNCI 1 0 Interlace Mode Detector VIDEO_SEL(12H.1) YUV VSYNCI INTERCE (87H.4) 1 0 VIDEO_SEL(12H.1) H-Counter & V-Timer for INT_V(90H.6) for INT_H(90H.7) V-Pol Normalize VSYNCI SYNCO_SEL (88H.2) V in 1 V IN 1 0 V-Pol Normalize V ex V SEP_SEL 0 VO_POL(88H.0) EN_VOUT(88H.6) Vsync Output VSYNCO FREE EN_VRUN(88H.4) Free-run Gen EN_INS(88H.3) HSYNCI SYNCI_SEL1 (87H.7) EN_HRUN(88H.5) Separator & Insert 1 HFREE Hc 0 Hs H-Pol Normalize SOGI EN_FRUN(88H.7) 0 0 H IN 1 EN_HOUT(88H.7) Hsync Output HSYNCO 1 Fast Mute SYNCO_SEL (88H.2) HO_POL(88H.1) INT_FM(90H.0) SYNCI_SEL1 (87H.7) SEP_SEL SYNCI_SEL0 (87H.6) Polarity INT_HP(90H.2) INT_VP(90H.1) Block Diagram of Sync Processor Sync Inputs The video sync signals input from the pins HSYNCI, VSYNCI, and SOGI. All VSYNCI, HSYNCI and SOGI pins have Schmitt Trigger and digital filter to improve noise immunity. Any pulse shorter than 125ns is regarded as a glitch and ignored. 2003/4/15 SYNCI_SEL 1 SYNCI_SEL 0 0 - Composite Sync from SOGI 1 0 Composite Sync from HSYNCI Sync Source 21 Ver.1.0 NT68520X,E 1 1 Separate Sync from HSYNCI/VSYNCI Frequency detection Vsync counter: VCNT [13:0], the 14-bit READ ONLY register, contains information of the Vsync frequency. An internal counter counts the numbers of 8us pulse between two VSYNC pulses. When a next VSYNC signal is recognized, the counter is stopped and the VCNT register latches the counter value and then the counter counts from zero again for evaluating the next VSYNC time interval. The counted data can be converted to the time duration between two successive Vsync pulses by timing 8 us. If no VSYNC comes in, the counter will overflow and set the VCNTOV bit (in VCNT_HB register) to HIGH. Once the VCNTOV is set to HIGH, it will remain unchanged until the next counter cycle is completed for its update. That means the VCNTOV bit will be updated every Vsync Counter cycle. It is necessary for various applications to provide various overflow time intervals. They are selectable as shown in the following table. VOV_SEL1 VOV_SEL0 Time Interval 0 0 32.768ms 0 1 65.536ms 1 0 98.304ms 1 1 131.072ms Hsync counter: If the HGATE_SRC bit is set to Low, the internal counter counts the Hsync pulses between two Vsync pulses. The HCNT [11:0] control registers contain the numbers of Hsync pulse between two Vsync pulses. These data can determine if the Hsync frequency is valid or not to determine the accurate video mode. The system supports two other options of intervals for users to count the frequency of Hsync pulses. If users set the HGAT_SRC and the HGATE_TME bits properly, the internal counter counts the Hsync pulses during this system defined time interval. The time interval is defined below: 2003/4/15 HGATE_SR C HGATE_TM E Gate Time 0 - Vsync Period 1 0 16.384 ms 22 Ver.1.0 NT68520X,E 1 1 32.768 ms After system reset, this gate interval source will be disabled and the contents of the HGATE_SRC bits are '0'. When this function is disabled, the HCNT_LB/HB counter is working on the VSYNC pulse. Latching the Hsync counter: The counted value will be latched by the HCNT_HB/LB registers which are updated by Vsync pulse or user’s selected time interval. If the counter overflows, the HCNTOV bit (in HCNT_HB register) will be set to HIGH. It will not change until the next counter cycle is completed to update it. That means the HCNTOV bit will be updated every Gate cycle of Hsync counter. All counters are with 2-lay content latches for counting sync period/frequency, so users will get stable counter results even at the latch transient. Latch HCNT register Reset H sync. counter Start pulse counting Update HCNTOV Latch HCNT register Reset H sync. counter Start pulse counting Update HCNTOV HGATE_SRC=0 ● ● VSYNCI ● GATE_SRC=0 ● ● ● ● ● ● HSYNCI ● HGATE_SRC=1 16.384ms/32.768ms (HGATE_TME=0/1) ● HSYNCI ● 2003/4/15 23 Ver.1.0 NT68520X,E Extract Vsync from Composite/SOG Signal Vsync Hsync ORed XORed Single Serrated Double Serrated + Equal. Pre-Equal. Pulses Serration Pulses Post-Equal. Pulses Vertical Blanking Interval Extracted VSYNCO textract(VSYNCO) = fixed tPW(insert) twiden(VSYNCO) Extracted HSYNCO from SOGI EN_INST=1 Inserted Pulses tPW(insert) Extracted HSYNCO from HSYNCI EN_INST=1 Inserted Pulses H/V Sync Timing Polarity Detection The sync polarity detection circuit will measure the length of high period of sync and the length of the low period of sync. If the length of the low period is longer than 60% of the input sync period, the input polarity bit (HI_POL or VI_POL) will be one, indicating a positive polarity. If the length of the low period is shorter than 40% of the input sync period, the input polarity will be zero, indicating a negative polarity. The specifications of the polarity detection circuit are listed below. Spec. Table of H/V Polarity Detect Unit 2003/4/15 24 Ver.1.0 NT68520X,E Vsync Frequency from Separate VSYNCI input for Sync Processor 15 - 250 Hz Vsync Duty Cycle = 40% VSYNC input Pulse Width of Separate SYNC 0.150 - 32000 us Vsync Duty Cycle < 40% OMP) VSYNC input pulse width of Composite/SOG SYNC 0.150 - 2000 us Vsync Duty Cycle < 40% fHSYNC Hsync Input Frequency 15 - 250 KH z Hsync Duty Cycle = 40% tHPW(SE HSYNC input Pulse Width of Separate-Type SYNC 0.150 - 85 us Hsync Duty Cycle < 40% HSYNC input Pulse Width of Composite/SOG SYNC 0.150 - 20.8 us Hsync Duty Cycle < 40% fVSYNC (SEP) tVPW(SE P) tVPW(C P) tHPW(C OMP) T = Period tPW = Pulse Width Positive Polarity tPW < T * 40% Negative Polarity Polarity Definition of the Sync Pulse Clamp Pulse Output A block circuit called clamp pulse generator generates clamp pulse on the CLMPO, and outputs it to the video Pre-Amplifier for DC restoration. There are two input trigger sources of the clamp generator, one is the signal HSYNCI from separator and another is HFREE from the internal free-run block. If the bit SYNCO_SEL is 1 then the Hin input source will be selected, otherwise the HFREE will be selected. The polarity and the trigger edge of the CLMPO can be selected by using bit CLMP_POL and bit CLMP_EDG respectively. The trigger delay of the CLMPO (td_clmp) is less than 50ns. It is a fixed delay and independent from the input video timing. The output transient of the CLMPO will not cause any crosstalk and phase jitter. The pulse width of the CLMPO output may be selected by bit CLMP_PW0 and bit CLMP_PW1. Refer to the description of the CLMP_REG for details. 2003/4/15 25 Ver.1.0 NT68520X,E Clamp Pulse Timing HSYNCI / HFREE Positive Polarity HSYNCI / HFREE Negative Polarity Leading Edge Trailing Edge CLMPO CLMP_EDG=1 CLMP_POL=1 CLMPO CLMP_EDG=0 CLMP_POL=1 tPW_CLMP tD_CLMP CLMPO CLMP_EDG=1 CLMP_POL=0 CLMPO CLMP_EDG=0 CLMP_POL=0 Clamp Pulse Timing Free Running This Block can generate various free-running outputs to satisfy various application requirements. The pulse width of the HFREE output is fixed to 1us and the VFREE is 8 lines. Users can properly set the contents of the dot counters, DCNT_HB and DCNT_LB, to get the required frequency of the HREEE, and set the contents of the line counters, LCNT_HB and LCNT_LB, to get the frequency of the VFREE. Refer to the descriptions of the free-run registers DCNT_HB, DCNT_LB, LCNT_HB, and LCNT_LB for details. Refer to the descriptions of the DCNT register and the LCNT register for obtaining user’s required frequencies in details. The EN_FRUN bit can gate the 12MHz clock source to disable this block function and to save power consumption. The previous values will be preloaded into the DCNT/LCNT counters from the DCNT_HB, LB / LCNT_HB, LB at the transient of EN_FRUN from 0 to 1. Users also can disable the H/V free run output by clearing the EN_HRUN / EN_VRUN. When you want to set the H/V free-running frequency, remember to set the high byte 2003/4/15 26 Ver.1.0 NT68520X,E content registers (DCNT_HB, LCNT_HB) first, the H/V frequency will change after you set the low byte contents registers (DCNT_LB, LCNT_LB). DCNT_HB DCNT_LB Pre-Load (EN_FREE = 0 Auto Load 1) HFREE 1/DCNT 12MHz 1us EN_FRUN=1 EN_HRUN=1 VFREE 1/LCNT 8 lines EN_VRUN=1 Pre-Load Auto Load LCNT_LB LCNT_HB Free-Run Generator Note：The Pulse width of the HFREE is 1us, and that means it is equal to 12 dots under 12MHz OSC. Fast Mute 1. The block generates a fast mute interrupt, INT_FM, to indicate an actable state of horizontal frequency. The operations of this block are A H-Period Counter counts the 12MHz pulse number within a period of the horizontal sync, and gets the current value A 2. The previous stable H-Period Latch held the previous counter value B. 3. Subtract or obtains a difference C from A and B, then B will be replaced with A for updating the next previous value. 4. C is compared with the difference boundary value DIFF_VAL written by user. 2003/4/15 27 Ver.1.0 NT68520X,E 5. The result C<D loads the contents of the DIFF_CNT, value E, to the Down-Counter to indicate the Hsync input is under a stable condition. It does not affect the flag INT_FM. 6. The Down-Counter will decrease its content if the comparison result is C>D or C=D. 7. The flag INT_FM in the Interrupt Flag register will be set to 1 if the content of the Down-Counter is decreased to zero, then an INT_FM interrupt will occur when the enable bit INT_FM in the Interrupt Enable register is enabled. Stable H-Period Latch B C D C=ABS(A-B) Update Comparison C<D Current H-Period Counter C=D or C>D LOAD A DIFF_CNT DIFF_VAL DEC Down-Counter =0 INT_FM E 12MHz Gate H Pulse Block Diagram of Fast Mute IRQn Interrupt Sources The NT68520 provides an interrupt request output pin IRQn. The following figure shows the detailed structure of the IRQn sources. 2003/4/15 28 Ver.1.0 NT68520X,E Interrupt Control Detect Rising Edge Flags Enables INT_H Edge Detect INT_H INTH_EN INT_V Edge Detect INT_V INTV_EN INTHP_EN INT_HP Edge Detect INT_HP INT_VP Edge Detect INT_VP INTVP_EN INT_FM Edge Detect INT_FM INTFM_EN INT_OVER Edge Detect INT_OVER INTOVER_EN INT_UNDER Edge Detect INT_UNDER INTUNDER_EN OR IRQn Clear Flags IRQn Interrupt Source INTHV_IR Q Meaning INT_HP H-Polarity Change INT It will be activated when the Input Polarity of Hsync changes. INT_VP V-Polarity Change INT It will be activated when the Input Polarity of Vsync changes. INT_FM Fast-Mute INT It will be activated when the Fast-Mute block detects an actable Hsync period. INT_H Hsync Edge INT It will be activated when the Hsync edge is matched with the selected trigger edge. INT_V Vsync Edge INT It will be activated when the Vsync edge is matched with the selected trigger edge. Action OSD Function The NT68520 supports internal OSD with the following features: 1. Max frame size 320 font (640-byte SRAM) 2. 128 ROM Font, 64 RAM Font (12-dot x 18-dot for each font) 3. Four windows Control 4. Horizontal/Vertical zoom control 5. 16 palettes with 5-bit resolution for each R/G/B color 6. Shadow/Border/Blinking effect 2003/4/15 29 Ver.1.0 NT68520X,E 7. Translucent effect OSD Palette Format 15 14:10 9:5 Reserve R G d 4:0 B OSD Code Format 7:0 Font Index OSD Attribute Format 7:5 4:2 1 0 FG[2:0 BG[2:0] Mix Blink ] FG[2:0]: Foreground color palette index LSB 3 bits (MSB in RegABH[0]) BG[2:0]: Background color palette index LSB 3 bits (MSB in RegABH[1]) Mix: 0- Normal 1- Translucent ( (Display+OSD_BG)/2 ) BG : 0- Font will be background transparent Blink: 0- No blinking 1- Blinking DPLL Clock Control The NT68520 contains one PLL (Bandwidth 160MHz), each for SDRAM timing generator and Display timing generator. Users should carefully program the right divider value for normal operations. Formula: Fout = ((N+2) x Fref) / (M+2) Fref = 12 MHz MCU Interface The NT68520 supports two wires of I2C bus and one IRQ output to communicate with MCU. The I2C data rate is up to 400K bits/s. The NT68520’s I2C address can be selected in the range of B0~B5, the value of the address bit 1/2 depends on the level of pin I2C_ADDR0/I2C_ADDR1 while the NT68520 is on the reset state. 2003/4/15 30 Ver.1.0 NT68520X,E ٭If both I2C_ADDR0 and I2C_ADDR1 are pulled high, the NT68520 will go into the test mode after the reset. e.g. : IF the NT68520’s I2C_ADDR1,I2C_ADDR2 pins are pulled up by resisters, when the reset signal is going from low to high, the value of the two pins (‘1’) will be latched, and then the I2C address is determined as BXh. I2C Address: 1 0 1 1 0 X X R/W Depond on level of pin I2C_ADDR0 while reset is finished I2C_ADDR0 I2C_ARRD1 0 0 1 1 2003/4/15 0 1 0 1 B0h (I2C bus) B1h (I2C bus) B2h (I2C bus) Don't use (Pbus) 31 Depond on level of pin I2C_ADDR1 while reset is finished Ver.1.0 NT68520X,E I2C Protocol General Register R/W Byte Write Data Stop Register Address ACK ACK ACK Write Start Slave Address Sequential Write Data N Stop Data 2 ACK ACK Data 1 ACK Write ACK ACK Slave Address ACK Write Start Register Address Slave Address Byte Read Stop NAK ACK Slave Address Read ReStart ACK Start Register Address Data Sequential Read Data 2 (Data) Stop Data N NAK Data 2 ACK Data 1 ACK ACK ACK Slave Address Read ACK Register Address ReStart ACK Write Start Slave Address Internal SRAM Write ACK Register Address (E1) Stop ACK Data N (Data) ACK Data 3 (Data) ACK Register Address (E2) Data 1 (Data) ACK Register Address (E0) ACK ACK Write Start Slave Address Internal SRAM Read ACK NAK Stop 32 Data N (Data) Stop Read Data 1 (Data) ACK Slave Address Data 2 (Data) ACK Register Address (E1) ACK Data 1 (Data) ACK ACK ReStart Register Address (E2) ACK Write 2003/4/15 Register Address (E0) ACK Write Start Slave Address ACK Start Slave Address Ver.1.0 NT68520X,E Register Summary SCALER POWER CONTROL 00H: Power Down Control (R/W) Bits Name Description D7-1 Reserved D0 SYS_PD System Power Down Enable 0: Disable 1: Enable Default：XXXX XXX0B ADC INTERFACE 01H: ADCPLL Control (R/W) Bits Name Description D7 EN_intclp Clamp pulse source selection 0 : External clamp pulse. 1 : Internal clamp pulse. D6 CoastINV ADC coast inverter 0 : Non-inverter. 1 : Inverter. D5-4 Reserve D3 COAST_EN COAST function enable 0: Disable 1: Enable D2 HI_POL_SEL ADC Hsync input polarity select 0 : Non-invert polarity 1 : Invert polarity D1 REGvref ADCPLL reference voltage(2.5V) source select 0 : External (from VREF pin) 1 : Internal (from internal regulator) D0 CAP_CLK_EN Capture clock enable 0: Disable PLL output 1: Enable PLL output Default：00XX 0101B 02H: Red Channel Gain Control (R/W) Bits Name Description D7-0 RGAIN[7:0] The gain range from 0.8 to 2.0 for R-channel, the register is defined by 8-bits to produce 1V(p-p) output signal for ADC input. RGain = 0.8 + 1.2/255 * D[7:0] Default：0000 0000B 2003/4/15 33 Ver.1.0 NT68520X,E 03H: ADC Phase Control (R/W) Bits Name Description D7 PU_Amck1 1= Power-up ADC clock generator. D6 PU_Rvga1 1= Power-up R channel VGA circuit. D5 PU_Radc1 1= Power-up R channel A2D converter. D4-0 Reserve Default：1110 0000B 04H: Green Channel Gain Control (R/W) Bits Name Description D7-0 GGAIN[7:0] The gain ranges from 0.8 to 2.0 for the G-channel, the register is defined by 8-bits to produce the 1V(p-p) output signal for ADC input. GGain = 0.8 + 1.2/255 * D[7:0] Default：0000 0000B 05H: CKBO Channel Phase Control (R/W) Bits Name Description D7 PU_Omck1 1= Power-up CKBO clock generator. D6 PU_Gvga1 1= Power-up G channel VGA circuit. D5 PU_Gadc1 1= Power-up G channel A2D converter. D4-0 Oph[4:0] The Phase Adjust Control is defined by 5-bits, and the total step is 32 for phase shift （360°/ 32Step = 11.25°/Step） Default：1110 0000B 06H: Blue Channel Gain Control (R/W) Bits Name Description D7-0 BGAIN[7:0] The gain ranges from 0.8 to 2.0 for B-channel, the register is defined by 8-bits to produce 1V(p-p) output signal for ADC input. BGain = 0.8 + 1.2/255 * D[7:0] Default：0000 0000B 07H: VGA Control (R/W) Bits Name Description D7 Reserve D6 PU_Bvga1 1= Power-up B channel VGA circuit. D5 PU_Badc1 1= Power-up B channel A2D converter. D4-2 Reserve D1 CALDIS VGA DC offset adjust 0 : Auto adjust. 1 : User adjust. D0 DRVCTL VGA output driver 0 : Normal drive. 1 : Strong drive. Default：X11X XX00B 2003/4/15 34 Ver.1.0 NT68520X,E 08H: Reserve (R/W) Bits Name Description D7-0 Reserved Default：XXXX XXXXB 09H: ADC PLL Divider Value - High Byte (R/W) Bits Name Description D7-3 Reserved D2-0 DIV[10:8] The high byte[2:0] of PLL divider value. Write this register will transfer the data of double-buffered register 0AH to the actual position. N divider = Divider<10:0> + 1 Default：XXXX X101B 0AH: ADC PLL Divider Value - Low Byte (R/W) Bits Name Description D7-0 DIV The low byte[7:0] of PLL divider value. The register is double-buffered. [7:0] N divider = Divider<10:0> + 1 Default：0100 0000B 0BH: Clamp Pulse Control (R/W) Bits Name Description D7-4 Width[3:0] Clamp pulse width control, 0~15 pixel clocks width. D3-0 Dly [3:0] Clamp pulse starting position control, 0~15 pixel clocks away from trailing edge of Hsync pulse, 0 maps to the first pixel. Default：0101 0101B 0CH: VCO Gain Control (R/W) Bits Name Description D7-6 Hfrange[1:0] Frequency range 00 : 10~40 Mhz; Kvco~15MHz/V 01 : 37~64 Mhz; Kvco~30Mhz/V 10 : 59~106 Mhz; Kvco~60Mhz/V 11 : 97~167 Mhz; Kvco~100Mhz/V D5-4 HICP[1:0] Charge pump current 00 : 100uA 01 : 200uA 10 : 400uA 11 : 700uA D3-2 RCZ[1:0] PLL Low filter internal resister 00 : 8K 01 : 4K 10 : 2K 11 : 1K 2003/4/15 35 Ver.1.0 NT68520X,E D1-0 Reserved Default：0100 00XXB 0DH: Reserve(R/W) Bits Name Description D7 Reserved Default：XXXX XXXXB 0EH: ADC Status (R) Bits Name D7-6 D5 BUF D4 GUF D3 RUF D2 BOR D1 GOR D0 ROR Description Reserved ADC B-channel under range flag. 0: No under range 1: Under range ADC G-channel under range flag. 0: No under range 1: Under range ADC R-channel under range flag. 0: No under range 1: Under range ADC B-channel over range flag. 0: No over range 1: Over range ADC G-channel over range flag. 0: No over range 1: Over range ADC R-channel over range flag. 0: No over range 1: Over range Default：XXXX XXXXB 0FH: Red Channel DC Shift Control (R/W) Bits Name Description D7-5 Reserved D4-0 Rsf [4:0] Control the R channel DC shift value to compensate the color excursion. MSB is sign bit. 00000 ~ 01111 -> 0 ~ 15 11111 ~ 10000 -> 0 ~ -15 (1’s complement) Default：XXX0 0000B 10H: Green Channel DC Shift Control (R/W) Bits Name Description D7-5 Reserved D4-0 Gsf [4:0] Control the G channel DC shift value to compensate the color excursion. MSB is sign bit. 00000 ~ 01111 -> 0 ~ 15 2003/4/15 36 Ver.1.0 NT68520X,E 11111 ~ 10000 -> 0 ~ -15 (1’s complement) Default：XXX0 0000B 11H: Blue Channel DC Shift Control (R/W) Bits Name Description D7-5 Reserved D4-0 Bsf[4:0] Control the B channel DC shift value to compensate the color excursion. MSB is sign bit. 00000 ~ 01111 -> 0 ~ 15 11111 ~ 10000 -> 0 ~ -15 (1’s complement) Default：XXX0 0000 CAPTURE INTERFACE 12H: Capture Interface Control (R/W) Bits Name Description D7 FLASH_NOISE Flash noise detection data port, this is a double buffer and write action by writing any data to CR1F 1:Enable flash noise detection D6 INTE_DET_EDG Interlace detecting edge to work with CR94H to detect the ODD/EVEN E filed 0 : Falling edge. 1 : Rising Edge. use the normalized Vsync rising edge. D5-4 Reserve D3 CAPCLK_POL Invert the polarity of Pixel Clock from external YUV decoder or internal ADCPLL 1: Invert 0: Normal D2 YUV_SWAP Swap the Y & UV byte from external YUV decoder 1: Swap 0: Normal D1 VIDEO_SEL Select video input source 1: From digital YUV input port, VGA circuit entering power- down 0: From analog VGA input port, YUV circuit entering power- down D0 CAPCLK_SEL Capture clock source select 0: Internal clock, from PLL 1: External clock, from YUV_CLK pin Default：X0XX 0000B 13H: Capture VGA and YUV Control (R/W) Bits Name Description D7-6 Reserved D5-4 DEINTE_SEL Select the de-interlace method to display for interlace input [1:0] 11: Spatial interpolation. 10: Display only even field. 01: Display only odd field. 00: Display both odd and even field. 2003/4/15 37 Ver.1.0 NT68520X,E D3 CAP_HS_SOU D2 FIELD_POL D1 FIELD_SEL D0 INTE_SEL Decide the Hsync pulse source referenced by capture circuit 0: From external HSYNCI pin 1: From internal re-synchronized Hs(re-sync by CAPTURE CLOCK falling edge) Invert the polarity of input Field signal. Field signal ‘1’ is considered as ODD field 1: Invert 0: Normal Field Indicator Source Select 1: From YUV656 decoded FIELD signal. 0: From Internal Synchronization Processor detected FIELD signal Interlace or non-interlace input select 1: Interlace 0: Non-interlace Default：XX00 0000B 14H: Capture Vertical Start - Low Byte (R/W) Bits Name Description D7-0 CAP_VS [7:0] Define the low byte[7:0] of the start position of the input vertical active window. This register is double-buffered by REG 15H. Default：0000 0000B 15H: Capture Vertical Start - High Byte (R/W) and Capture Vertical Start Shift in odd/even field (works in interlace mode, CR13, D0 =1)(R/W) Bits Name Description D7 FIELD_CAP_SH_EN Enable either ODD or EVEN field Vertical Capture Start shift 1 line 0: Enable 1: Disable D6 FIELD_CAP_SH_SE Select the Field to shift vertical capture start L 1: ODD field 0: EVEN field D5 CAP_VS_SH_EN Enable either ODD or EVEN field Capture Vertical Sync. pulse shift 1 line 0: Enable 1: Disable D4 CAP_VS_SH_SEL Select the Field to shift Capture Vertical Synchronization pulse 1: ODD field 0: EVEN field D3 Reserved D2-0 CAP_VS [10:8] Define the high byte[10:8] of the start position of the input vertical active window. Write this register will transfer the data of double-buffered register 14H to the actual position. Default：0000 X000B 16H: Capture Vertical Height - Low Byte (R/W) Bits Name Description 2003/4/15 38 Ver.1.0 NT68520X,E D7-0 CAP_VH [7:0] Define the low byte[7:0] of the height of the input vertical active window. Default：0000 0000B 17H: Capture Vertical Height - High Byte (R/W) Bits Name Description D7-3 Reserved D2-0 CAP_VH [10:8] Define the high byte[10:8] of the height of the input vertical active window. Default：0000 0000B 18H: Capture Horizontal Start - Low Byte (R/W) Bits Name Description D7-0 CAP_HS [7:0] Define the low byte[7:0] of the start position of the input horizontal active window. This register is double-buffered by REG 19H. Default：0000 0000B 19H: Capture Horizontal Start - High Byte (R/W) Bits Name Description D7Reserved 3 D2- CAP_HS [10:8] Define the high byte[10:8] of the start position of the input horizontal active 0 window. Default：0000 0000B 1AH: Capture Horizontal Width - Low Byte (R/W) Bits Name Description D7-0 CAP_HW [7:0] Define the low byte[7:0] of the width of the input horizontal active window. Default：0000 0000B 1BH: Capture Horizontal Width - High Byte (R/W) Bits Name Description D7-3 Reserved D2-0 CAP_HW [10:8] Define the high byte[10:8] of the width of the input horizontal active window. Default：0000 0000B 1C: Capture Synchronous Lock Position in lines (W) Bits Name Description D7Reserved 6 D5- LAST_H_CH Change the position of the last abnormal Hsync 4 00 : In VFP 01 : Delay 1 line. 10 : Delay 2 line. 2003/4/15 39 Ver.1.0 NT68520X,E 11 : Delay 3 line. D3- VLOCK [3:0] Define the Lock Position in lines that display timing will be re-synchronized 0 to capture timing in Manual Display mode Default：0000 0001B 1C: Capture Synchronous Lock Position in lines Read Back(R) Bits Name Description D7Reserved 6 D5- LAST_H_CH Change the position of the last abnormal Hsync 4 00 : In VFP 01 : Delay 1 line. 10 : Delay 2 line. 11 : Delay 3 line. D3- VLOCK [3:0] Read Back Lock Position in lines in Auto Display mode 0 Default：XXXX XXXXB 1D: Capture Synchronous Lock Position in Pixels (W) Bits Name Description D7-0 HLOCK Define the Lock Position in pixels of CR1D defined line that display timing will be re-synchronized to capture timing in Manual Display mode Default：1000 0000B 1D: Capture Synchronous Lock Position in Pixels Read Back(R) Bits Name Description D7-0 HLOCK Read back the hardware auto Lock Position in pixels of CR1D defined line in Auto Display Mode Default：XXXX XXXXB AUTO TUNE 1EH: Auto Calibration Control (W) Bits Name Description D7Reserved 5 D3 AUTO_MS Auto Gain/Position Mode Select 0: Auto Gain Mode 1: Auto Position Mode D2 AUTO_GAIN_D Auto Gain Detecting Area Selection A_SEL 0: Between two V-sync trailing edges. 1: Specified by Reg14H ~ Reg1BH D1 Reserved D0 AUTO_EN Auto Gain/Position Start Enable 0: Disable 2003/4/15 40 Ver.1.0 NT68520X,E 1: Enable Default：XXX0 0000B 1FH: Auto Calibration Status (R) Bits Name Description D7-4 AUTO_DIFF Difference between Detected H width and H Reference Count 0000(0) ~ [3:0] 1111(15) = | Detected H width - H Reference Count |, Value 1111 means the difference ≥ 15 D3-2 AUTO_P_COM Auto Position comparing result for comparing the H Reference Count with P the detected H Active Count. It is useful for input pixel clock detection. [1:0] 00: Detected H width < H Reference Count (F/W should Increase the PLL divider value) 01: Detected H width = H Reference Count 10: Detected H width > H Reference Count (F/W should decrease the PLL divider value) 11: Reserved D1 Reserved D0 AUTO_RDY Auto Gain/Position ready flag. User should clear this bit after reading the status register to restart the next auto-calibration cycle. 0: Not ready 1: Ready Default：XXXX XXXXB 1FH: Auto Calibration Status (W) Bits Name Description D7-1 Reserved D0 CLR_RDY Writing this register will clear AUTO_RDY bit. Default: XXXX XXXXB AUTO PHASE 20H: Auto Phase/Histogram Calibration Control (R/W) Bits Name Description D7-6 Reserved D5-4 SEL_CAL_CH Select Auto Phase or Auto Histogram calibration channels 00: R&G&B channel (Auto phase) 01: R channel (Auto Phase / Histogram) 10: G channel (Auto Phase / Histogram) 11: B channel (Auto Phase / Histogram) D3-2 SEL_CAL_MET Select Auto Phase or Auto Histogram calibration method HOD 00: Auto Phase 01: Reserve 10: Auto Histogram method 0 (Low Bound(more than threshold value amount of pixel)), the threshold defined in CR27 11: Auto Histogram method 1 (High Bound(less than threshold value amount of pixel)) 2003/4/15 41 Ver.1.0 NT68520X,E D1 BURST_MODE Auto Phase/Histogram calibration is working in burst or single mode 0: single 1: burst D0 AUTO_PH_EN Auto Phase/Histogram Start Enable (W) 0: Disable 1: Enable D0 AUTO_PH_RE Auto Phase/Histogram calibration Ready ADY(R) 0: Ready 1: Not Ready Default：XX00 0000B 21H: Auto Phase/Histogram Calibration result BYTE 3 (Low Byte) (R) Bits Name Description D7- AUTO_PH_B3 Auto Phase/Histogram calibration result BYTE 3 0 Default：XXXX XXXXB 22H: Auto Phase/Histogram Calibration result BYTE 2 (R) Bits Name Description D7- AUTO_PH_B2 Auto Phase/Histogram calibration result BYTE 2 0 Default：XXXX XXXXB 23H: Auto Phase/Histogram Calibration result BYTE 1 (R) Bits Name Description D7- AUTO_PH_B1 Auto Phase/Histogram calibration result BYTE 1 0 Default：XXXX XXXXB 24H: Auto Phase/Histogram Calibration result BYTE 0 (High Byte) (R) Bits Name Description D7- AUTO_PH_B0 Auto Phase/Histogram calibration result BYTE 0 0 Default：XXXX XXXXB 25H: Auto Phase Red/Green Difference Mask (R/W) Bits Name Description D7 Reserved D6- PH_G_MASK Auto Phase Green difference mask, the difference will be masked before 4 summation. D3 Reserved 2003/4/15 42 Ver.1.0 NT68520X,E D2- PH_R_MASK Auto Phase Red difference mask, the difference will be masked before 0 summation Default：0000 0000B 26H: Auto Phase Blue Difference Mask (R/W) Bits Name Description D7Reserved 3 D2- PH_B_MASK Auto Phase Blue difference mask, the difference will be masked before 0 summation. Default：0000 0000B 27H: Auto Histogram Threshold (R/W) Bits Name Description D7- AUTO_HIS_T Auto Histogram threshold for R/G/B in high bound or low bound modes. 0 H Default：0000 0000B AUTO GAIN 28H: Auto Gain Red Max Value (R) Bits Name Description D7-0 AUTO_G_RMAX The max red value of Auto-Gain in the specified scan area [7:0] Default：XXXX XXXXB 29H: Auto Gain Green Max Value (R) Bits Name Description D7-0 AUTO_G_GMAX The max green value of Auto-Gain in the specified scan area [7:0] Default：XXXX XXXXB 2AH: Auto Gain Blue Max Value (R) Bits Name Description D7-0 AUTO_G_BMAX The max blue value of Auto-Gain in the specified scan area [7:0] Default：XXXX XXXXB 2BH: Auto Gain Red Min Value (R) Bits Name Description D7-0 AUTO_G_RMIN [7:0] The min red value of Auto-Gain in the specified scan area Default：XXXX XXXXB 2CH: Auto Gain Green Min Value (R) 2003/4/15 43 Ver.1.0 NT68520X,E Bits Description D7-0 AUTO_G_GMIN [7:0] The min green value of Auto-Gain in the specified scan area Default：XXXX XXXXB 2DH: Auto Gain Blue Min Value (R) Bits Name Description D7-0 AUTO_G_BMIN The min blue value of Auto-Gain in the specified scan area [7:0] Default：XXXX XXXXB AUTO POSITION 2EH: Auto Position Pixel Mask (R/W) Bits Name Description D7-0 Pixel_Mask[7:0] Auto position pixel mask area for H-back porch.(3C H-front porch) Default：0000 0000B 2FH: Auto Position Red Noise Margin (R/W) Bits Name Description D7-0 AUTO_P_RNM Define the red noise margin value for selecting between black and [7:0] non-black pixels. Default：0000 0000B 30H: Auto Position Green Noise Margin (R/W) Bits Name Description D7-0 AUTO_P_GNM Define the green noise margin value for selecting between black and [7:0] non-black pixels. Default：0000 0000B 31H: Auto Position Blue Noise Margin (R/W) Bits Name Description D7-0 AUTO_P_BNM Define the blue noise margin value for selecting between black and [7:0] non-black pixels. Default：0000 0000B 32H: Auto Position V Back-porch Count - Low Byte (R) Bits Name Description D7-0 AUTO_P_VBPC Auto position detected vertical start position low byte [7:0] [7:0] Default：XXXX XXXXB 33H: Auto Position V Back-porch Count - High Byte (R) 2003/4/15 44 Ver.1.0 NT68520X,E Bits Name Description D7-3 Reserved D2-0 AUTO_P_VBPC Auto position detected vertical start position high byte [10:8] [10:8] Default：XXXX XXXXB 34H: Auto Position V Active Count - Low Byte (R) Bits Name Description D7-0 AUTO_P_VAC Auto position detected vertical active height low byte [7:0] [7:0] Default：XXXX XXXXB 35H: Auto Position V Active Count - High Byte (R) Bits Name Description D7-3 Reserved D2-0 AUTO_P_VAC[10: Auto position detecting vertical active height high byte [10:8] 8] Default：XXXX XXXXB 36H: Auto Position H Back-porch Count - Low Byte (R) Bits Name Description D7-0 AUTO_P_HBPC[7: Auto position detected horizontal start position low byte [7:0] 0] Default：XXXX XXXXB 37H: Auto Position H Back-porch Count - High Byte (R) Bits Name Description D7-3 Reserved D2-0 AUTO_P_HBPC[10 Auto position detected horizontal start position high byte [10:8] :8] Default：XXXX XXXXB 38H: Auto Position H Active Count - Low Byte (R) Bits Name Description D7-0 AUTO_P_HAC [7:0] Auto position detected horizontal active width low byte [7:0] Default：XXXX XXXXB 39H: Auto Position H Active Count - High Byte (R) Bits Name Description D7-3 Reserved D2-0 AUTO_P_HAC Auto position detected horizontal active width high byte [10:8] [10:8] 2003/4/15 45 Ver.1.0 NT68520X,E Default：XXXX XXXXB 3AH: Auto Position H Active Reference Count - Low Byte (R/W) Bits Name Description D7-0 AUTO_P_HARC H active reference count low byte [7:0], Comparing this counter value [7:0] with the AUTO_P_HAC[10:0], it is easy to adjust the ADCPLL’s divider value to get the right clock frequency. Default：0000 0000B 3BH: Auto Position H Active Reference Count - High Byte (R/W) Bits Name Description D7-3 Reserved D2-0 AUTO_P_HARC[10: H active reference count high byte [10:8] 8] Default：XXXX X000B 3CH: Auto Position Pixel Mask (R/W) Bits Name Description D7-0 Pixel_Mask[7:0] Auto position pixel mask area for H-front porch.(2Eh H-back porch) Default：0000 0000B 3DH ~4BH: Reserved (R/W) 2003/4/15 46 Ver.1.0 NT68520X,E DISPLAY INTERFACE 4CH: Display Control (R/W) Bits Name Description D7 AUTO_SYNC_LO Auto Capture Synchronous Lock position stop CK_EN 0: Disable 1: Enable D6 DISP_AUTO Decide the working mode of Display Horizontal Timing generation. 0: Manual mode. H/W automatically adjusts the VT and VFP timings, others fully depend on Reg4EH ~ Reg5DH. Capture Synchronous Lock Position = Reg1CH ~ Reg1DH 1: Auto mode. H/W automatically adjusts the HT(only once), HFP, VT, VFP. H/W automatically adjusts Capture Synchronous Lock position, but can be Disabled by 4CH(D7) D5 DISP_AUTO_STE Decide the H-total adjust value even step P_HT_EVEN_ON 0 : Disable LY 1 : Enable D4 SKEW Skew output control for double pixel display. D3 DISP_EN Display Enable 0: Disable. Tri-state control lines and data lines. 1: Enable D2 DISP_CD Display Color Depth 0: 8-bit/color 1: 6-bit/color D1 DISP_BW Display Bus Width 0: Double pixel 48-bit 1: Single pixel 24-bit(A group) D0 DISP_DE Panel DE Mode Support 0: Panel supports Sync mode, display Hs/Vs signal is at normal state 1: Panel supports DE mode, display Hs/Vs signals will be pulled LOW or HIGH, it depends on REG 61H(D1-0), if DISP_HS_POL = 0 and DISP_VS_POL = 1, then Hs is pulled to LOW, and Vs is pulled to HIGH Default：0000 0000B 4DH: Display Mute Control (R/W) Bits Name Description D7 BYPASS Enable the captured data by-passing the scaler 0: Normal 1: Bypass D6 MUTE_AUTO Mute with OSD when VGA input sync fail 0: Disable 1: Enable D5 Reserved 2003/4/15 47 Ver.1.0 NT68520X,E D4-2 MUTE_CLR [2:0] D1-0 DISP_MUTE [1:0] Select background color while Mute Data With OSD On function is selected. D4 = 1 : Output red background color D3 = 1 : Output green background color D2 = 1 : Output blue background color Display Mute Mode Select 11: Mute All (control lines and data lines set to 0 ) 10: Mute Data with OSD on (free running mode) 01: Mute Data (data lines set to 0) 00: Normal display Default：0XX0 0000B 4EH: Display Vertical Total Height - Low Byte (R/W) Bits Name Description D7-0 DISP_VT [7:0] Define the low byte[7:0] of total number in scan lines per frame Default：0000 0000B 4FH: Display Vertical Total Height - High Byte (R/W) Bits Name Description D7-3 Reserved D2-0 DISP_VT [10:8] Define the high byte [10:8] of total number in scan lines per frame Default：XXXX X000B 50H: Display Vertical Active Height - Low Byte (R/W) Bits Name Description D7-0 DISP_VAE [7:0] Define the low byte [7:0] of vertical active end position in scan lines Default：0000 0000B 51H: Display Vertical Active Height - High Byte (R/W) Bits Name Description D7-3 Reserved D2-0 DISP_VAE Define the high byte [10:8] of vertical active end position in scan lines [10:8] Default：XXXX X000B 52H: Display Vertical Sync Start Height - Low Byte (R/W) Bits Name Description D7-0 DISP_VSS [7:0] Define the low byte [7:0] of Vsync start position in scan lines Default：0000 0000B 53H: Display Vertical Sync Start Height - High Byte (R/W) Bits Name Description D7-3 Reserved D2-0 DISP_VSS [10:8] Define the high byte [10:8] of Vsync start position in scan lines 2003/4/15 48 Ver.1.0 NT68520X,E Default：XXXX X000B 54H: Display Vertical Sync End Height - Low Byte (R/W) Bits Name Description D7-0 DISP_VSE [7:0] Define the low byte [7:0] of Vsync end position in scan lines Default：0000 0000B 55H: Display Vertical Sync End Height - High Byte (R/W) Bits Name Description D7-3 Reserved D2-0 DISP_VSE [10:8] Define the high byte [10:8] of Vsync end position in scan lines Default：XXXX X000B 56H: Display Horizontal Total Width - Low Byte (R/W) Bits Name Description D7-0 DISP_HT [7:0] Define the low byte [7:0] of total number in pixels per line Default：0000 0000B 57H: Display Horizontal Total Width - High Byte (R/W) Bits Name Description D7-3 Reserved D2-0 DISP_HT [10:8] Define the high byte [10:8] of total number in pixels per line Default：XXXX X000B 58H: Display Horizontal Active End Width - Low Byte (R/W) Bits Name Description D7-0 DISP_HAE [7:0] Define the low byte [7:0] of horizontal active end position in pixels Default：0000 0000B 59H: Display Horizontal Active End Width - High Byte (R/W) Bits Name Description D7-3 Reserved D2-0 DISP_HAE Define the high byte [10:8] of horizontal active end position in pixels [10:8] Default：XXXX X000B 5AH: Display Horizontal Sync Start Width - Low Byte (R/W) Bits Name Description D7-0 DISP_HSS [7:0] Define the low byte [7:0] of Hsync start position in pixels Default：0000 0000B 2003/4/15 49 Ver.1.0 NT68520X,E 5BH: Display Horizontal Sync Start Width - High Byte (R/W) Bits Name Description D7-3 Reserved D2-0 DISP_HSS Define the high byte [10:8] of Hsync start position in pixels [10:8] Default：XXXX X000B 5CH: Display Horizontal Sync End Width - Low Byte (R/W) Bits Name Description D7-0 DISP_HSE [7:0] Define the low byte [7:0] of Hsync end position in pixels Default：0000 0000B 5DH: Display Horizontal Sync End Width - High Byte (R/W) Bits Name Description D7-3 Reserved D2-0 DISP_HSE Define the high byte [10:8] of Hsync end position in pixels [10:8] Default：XXXX X000B 5EH: Display Drive Select 1 (R/W) Bits Name Description D7 DISP_CLK_SR Select panel interface CLOCK slew rate 0: Fast 1: Slow D6-4 DISP_CLK_DR Select panel interface CLOCK drive strength V 000: 2mA 100: 10mA [2:0] 001: 4mA 101: 12mA 010: 6mA 110: 14mA 011: 8mA 111: 16mA D3 DISP_DATA_SR Select panel interface DATA slew rate 0: Fast 1: Slow D2-0 DISP_DATA_DR Select panel interface DATA drive strength V 000: 2mA 100: 10mA [2:0] 001: 4mA 101: 12mA 010: 6mA 110: 14mA 011: 8mA 111: 16mA Default：1001 1001B 5FH: Display Drive Select 2 (R/W) Bits Name Description D7-4 Reserved D3 DISP_HVD_SR Select panel interface HS/VS/DE slew rate 2003/4/15 50 Ver.1.0 NT68520X,E 0: Fast 1: Slow D2-0 DISP_HVD_DR Select panel interface HS/VS/DE drive strength V 000: 2mA 100: 10mA [2:0] 001: 4mA 101: 12mA 010: 6mA 110: 14mA 011: 8mA 111: 16mA Default：XXXX 1001B 60H: Display Delay Select (R/W) Bits Name Description D7-4 Reserved D3-0 DISP Select panel interface CLOCK delay time, 1 ~ 16 nS ( 1nS/Step ) _CLK_DLY [3:0] Default：XXXX 0000B 61H: Display Polarity Control (R/W) Bits Name Description D7-4 Reserved D3 DISP_DE_POL Display DE 0: Active High 1: Active Low D2 DISP_CLK_PO Display Clock L 0: Normal 1: Inverted D1 DISP_HS_POL Display Hsync 0: Active High 1: Active Low D0 DISP_VS_POL Display Vsync 0: Active High 1: Active Low Default：XXXX 0000B 62H: Display Auto Control Ready (R) Bits Name Description D7-0 Reserved Default：XXXX XXXXB 63H ~ 66H: Reserved (R/W) Bits Description D7-0 Reserved Reserved Default：0000 0000B 2003/4/15 51 Ver.1.0 NT68520X,E 67H: Display Horizontal Total Read Back– Low Byte (R) Bits Name Description D7-0 DISP_HTRB Read back the low byte value of display horizontal total. [7:0] Default：XXXX XXXXB 68H: Display Horizontal Total Read Back – High Byte (R) Bits Name Description D7-3 Reserved D2-0 DISP_HTRB[10:8 Read back the high byte value of display horizontal total. ] Default：XXXX XXXXB VIDEO PROCESSOR 69H: Gain Control - Red (R/W) Bits Name Description D7-0 GAIN_R [7:0] Adjust the gain of red component, step size = 2/255, 00h (0) -> 80h (1) -> FFh (2). Default：1000 0000B 6AH: Gain Control – Green (R/W) Bits Name Description D7-0 GAIN_G [7:0] Adjust the gain of green component, step size = 2/255, 00h (0) -> 80h (1) ->FFh (2). Default：1000 0000B 6BH: Gain Control - Blue (R/W) Bits Name Description D7-0 GAIN_B [7:0] Adjust the gain of blue component, step size = 2/255, 00h (0) -> 80h (1) -> FFh (2). Default：1000 0000B 6CH: Offset Control - Red (R/W) Bits Name Description D7-0 OFFSET_R Adjust the offset of red component by 2’s complement value, [7:0] 80h (-128) -> 00h (0) -> 7Fh (127). Default：0000 0000B 6DH: Offset Control - Green (R/W) Bits Name Description D7-0 OFFSET_G Adjust the offset of green component by 2’s complement value. 2003/4/15 52 Ver.1.0 NT68520X,E [7:0] 80h (-128) -> 00h (0) -> 7Fh (127) Default：0000 0000B 6EH: Offset Control - Blue (R/W) Bits Name Description D7-0 OFFSET_B Adjust the offset of blue component by 2’s complement value [7:0] 80h (-128) -> 00h (0) -> 7Fh (127). Default：0000 0000B 6FH: Scaling and Dithering Control (R/W) Bits Name Description D7 GAMMA_EN Enable Display Gamma Table 0 : Disable 1 : Enable D6 GEN_GAMM Generator Gamma Adjust Pattern A_PATTERN 0 : Disable. 1 : Enable. D5-3 Reserved D2 INPUT_TIM 0 : Recalibrate input timing ready (R). E 1 : Recalibrate input timing enable (W). D1 SCAL_EN If the frequency of input video sampling clock or display clock is changed, it is needed to clear this bit to ‘0’ then set to ‘1’ to activate the scaling unit to accommodate the data racing. D0 DITHER_EN Dithering enable 0: Disable 1: Enable Default：00XX X001B 70H: Horizontal Interpolation Filter Type (R/W) Bits Name Description D7-6 Reserved D5 AF1 Advance Filter1 D4 AF2 Advance Filter1 D3 Reserved D2-0 HIFM [2:0] Horizontal Interpolation Filter Mode 000: Bi-linear 001: Little sharp 010: Middle sharp 011: High sharp 100: Ultra sharp 101: Duplicated, all the interpolated pixels are duplicated and not partial duplicated. 110: Programmable filter 111: Balance Default：XXXX X000B 2003/4/15 53 Ver.1.0 NT68520X,E 71H: Vertical Interpolation Filter Type (R/W) Bits Name Description D7-3 Reserved D2-0 VIFM Vertical Interpolation Filter Mode [2:0] 000: Bi-linear 001: Little sharp 010: Middle sharp 011: High sharp 100: Ultra sharp 101: Duplicated, all the interpolated pixels are duplicated and not partial duplicated. 110: Programmable filter 111: Balance Default：XXXX X000B 72H: Programmable Interpolation Filter Access index (W) Bits Name Description D7 FILTER_PORT_W_E 1: Enable Interpolation port write N D6 H_V_FILTER_SEL 0: V interpolation table 1: H interpolation table D5~ Reserved 0 Default：XXXX XXXXB 73H: Interpolation Filter Table Data Port(W) Bits Name Description D7-0 IN_F_TB Write 32 x 6bit Programmable Interpolation filter table data in this port. Default：XXXX XXXXB 74H ~ 76H: Reserved(W) Interpolation filter table 2003/4/15 54 Ver.1.0 NT68520X,E interpolation pixel point pixel point A pixel point C B x factor 1-x C=A*(1-x)+B*x User Programmable 6 2 -1 0 1 2003/4/15 32 55 x (bytes) Ver.1.0 NT68520X,E FIFO Build-In Self Test (BIST) 77H: FIFO BIST Control (R/W) Bits Name Description D7 FIFO_BIST_EN(W 1: Enable FIFO Build-In Self Test. ) D7 FIFO_BIST_EN(R 0: FIFO Build-In Self Test Ready ) 1: FIFO Build-In Self Test not Ready D6 FIFO_BIST_STAT 0 : Success E 1 : Fail D5-4 FIFO_SEL FIFO Select D3 FIFO_FAULT_GE Select FIFO test fault generation enable. N D2-0 Reserved Default：00XX XXXXB 78H: FIFO0 BIST Fail Start (R) Bits Name Description D7-0 FIFO0_BIST_F_S FIFO 0 BIST Fail Start Position[7:0] T[7:0] Default：XXXX XXX0B 79H: FIFO0 BIST Fail End (R) Bits Name Description D7-0 FIFO0_BIST_F_E FIFO 0 BIST Fail End Position[7:0] ND[7:0] Default：XXXX XXX0B 7AH ~ 84H : Reserved 2003/4/15 56 Ver.1.0 NT68520X,E Sync Processor 85H: Clamp Pulse Control (R/W) Bits Name Description D7-4 Reserved D3 CLMP_EDG Trigger Edge of the Clamp Pulse 0 : Clamp pulse is at the trailing edge of Hsync 1 : Clamp pulse is at the leading edge of Hsync D2 CLMP_POL Clamp Pulse Polarity Selection 0 : Negative polarity 1 : Positive polarity D1-0 CLMP_PW[1 Clamp Pulse Width Selection :0] 00 : 0.25us 01 : 0.5us 10 : 1us 11 : 2us Default: XXXX 0100B 86H: Sync Processor Control (R/W) Bits Name Description D7 EN_FRUN 0: Disable free-run function to save power consumption. 1: Enable free-run function. D6 AUTO_FLT 0: Disable Auto Filter function 1: Enable Auto Filter function of H/V extract circuit. D5 EN_SOG SOG function control bit 0: Disable SOGI pin 1: Enable SOGI pin, HSYNCI input will be discarded D4 Reserved D3 EN_POL_HI Hsync polarity user programming D 0 : Disable 1 : Enable D2 HI_POL_SE Hsync input polarity select L 0 : Active low 1 : Active high D1 EN_POL_VI Vsync polarity user programming D 0 : Disable 1 : Enable D0 VI_POL_SE Vsync input polarity select L 0 : Active low 1 : Active high Default: 000X 0000B 87H: H/V Sync Input Control (W) Bits Description D7-6 SYNCI_SEL Type Selection of Sync Input [1:0] 0X: Composite Sync from SOGI pin 10: Composite Sync from HSYNCI or YUV_HS pin 11: Separate Sync from HSYNCI/VSYNCI or YUV_HS/YUV_VS 2003/4/15 57 Ver.1.0 NT68520X,E D5 INS_HPW Pulse Width Selection of inserted Hsync pulse 0: Pulse Width = value HPW[7:0] 1: Pulse Width =1uS D4-0 Reserved Default: 110X XXXXB 87H: H/V Sync Input Control (R) Bits Description D7-5 Reserved D4 INTERLACE Interlace auto-detecting indicator flag. 0: Not interlace input sync 1: Interlace input sync D3 HS_LVL The input digital level of HSYNCI pin at the sampling moment.(for debug) 0: Low Level 1: High Level D2 VS_LVL The input digital level of VSYNCI pin at the sampling moment.(for debug) 0: Low Level 1: High Level D1 HI_POL H-Polarity Flag Detected by Input Polarity Detection Circuit. 0: Negative polarity. The high period is longer than 60% of input sync period 1: Positive polarity. The low period is longer than 60% of input sync period D0 VI_POL V-Polarity Flag Detected by Input Polarity Detection Circuit. 0: Negative polarity. The high period is longer than 60% of input sync period 1: Positive polarity. The low period is longer than 60% of input sync period Default：XXXX XXXXB 88H: H/V Sync Output Control (R/W) Bits Description D7 EN_HOUT HSYNCO output enable 0: Disable 1: Enable D6 EN_VOUT VSYNCO output enable 0: Disable 1: Enable D5 EN_HRUN Free-run horizontal output control 0: Disable 1: Enable D4 EN_VRUN Free-run vertical output control 0: Disable 1: Enable D3 EN_INS Insert Hsync pulse control 0: Disable 1: Enable D2 SYNCO_SE Source selection control of sync-out (HSYNCO and VSYNCO) L 0: Sync output from the external sync input pin 1: Sync output from the internal free-run generator. D1 HO_POL Hsync output polarity control 2003/4/15 58 Ver.1.0 NT68520X,E 0: Negative polarity 1: Positive polarity D0 VO_POL Vsync output polarity control 0: Negative polarity 1: Positive polarity Default: 0000 0000B 89H: Hsync Pulse Width (R) Bits Name Description D7-0 HPW Sync processor will detect the pulse width of the external HSYNCI/SOG Input. [7:0] Unit : 83.3ns/count Default：XXXX XXXXB 8AH: Hsync Filter Reference (R/W) Bits Name Description D7-0 HFLT Time width of Pulse Filter for Composite/SOG sync extraction. H sync pulse [7:0] with pulse width less than the reference value will be filtered out.(HPW+4) Unit : 83.3ns/count Default: 1111 1111B 4 HPW HFLT Spectrum 8BH: H/V Sync Counter Interval (R/W) Bits Name Description D7-4 Reserved D3-2 VOV_SEL Overflow time interval control bits of Vsync Counter [1:0] 00: 32.768ms 01: 65.536ms 10: 98.304ms 11: 131.072ms D1 HGATE_SR Gate Source control bit for Hsync Counter C 0: from Vsync Period 1: from Internal Time Gate; see HGATE_TME bit in this byte 2003/4/15 59 Ver.1.0 NT68520X,E D0 HGATE_TM Gate Time control bit for Hsync Counter E 0: 16.384ms 1: 32.768ms Default: XXXX 0000B 8CH: Hsync Counter Value – Low Byte (R) Bits Name Description D7-0 HCNT Low byte value of the Hsync counter [7:0] Default: XXXX XXXXB 8DH: Hsync Counter Value – High Byte (R) Bits Name Description D7 HCNTOV Overflow Flag of Hsync Counter 1: Overflow 0: Normal D6-4 Reserved D3-0 HCNT High byte value of the Hsync counter [11:8] Default: XXXX XXXXB 8EH: Vsync Counter Value – Low Byte (R) Bits Name Description D7-0 VCNT Low byte value of the Vsync counter [7:0] Default: XXXX XXXXB 8FH: Vsync Counter Value – High Byte (R) Bits Name Description D7 VCNTOV Overflow Flag of Vsync Counter 1: Overflow 0: Normal D6 Reserved D5-0 VCNT High byte value of the Vsync counter [13:8] Default: XXXX XXXXB 90H: H/V Interrupt flag (R) Bits Name Description D7 INT_H 1: Hsync leading edge interrupt from separate or composite signal 0: No interrupt D6 INT_V 1: Vsync leading edge interrupt from separate or composite signal 0: No interrupt 2003/4/15 60 Ver.1.0 NT68520X,E D5 D4 Reserved Line buffer overflow interrupt flag 0: No Overflow 1: Overflow D3 INT_UNDER Line buffer underflow interrupt flag 0: No Underflow 1: Underflow D2 INT_HP Input Hsync polarity change INT 1: Change 0: No change D1 INT_VP Input Vsync polarity change INT 1: Change 0: No change D0 INT_FM Fast mute INT 1: Fast mute occur 0: Not occur Default: XXXX XXXXB INT_OVER # Reset scaler by CR6F bit1 will clear all CR90’s flags. 91H: H/V Interrupt Clear (W) Bits Name Description D7 CLR_H 1:Clear INT_H bit 0: No effect D6 CLR_V 1:Clear INT_V bit 0: No effect D5 Reserved D4 CLR_OVER 1:Clear INT_OVER bit 0: No effect D3 CLR_UNDE 1:Clear INT_UNDER bit R 0: No effect D2 CLR_HP 1:Clear INT_HP bit 0: No effect D1 CLR_VP 1:Clear INT_VP bit 0: No effect D0 CLR_FM 1:Clear INT_FM bit 0: No effect Default: 00X0 0000B 92H: H/V Interrupt Enable (R/W) Bits Name Description D7 INTH_EN 1: Enable INT_H interrupt 0: Disable D6 INTV_EN 1: Enable INT_V interrupt 0: Disable D5 Reserved D4 INTOVER_EN 1: Enable INT_OVER interrupt 0: Disable 2003/4/15 61 Ver.1.0 NT68520X,E D3 INTUNDER_E 1: Enable INT_UNDER interrupt N 0: Disable D2 INTHP_EN 1: Enable INT_HP interrupt 0: Disable D1 INTVP_EN 1: Enable INT_VP interrupt 0: Disable D0 INTFM_EN 1: Enable INT_FM interrupt 0: Disable Default: 00X0 0000B 93H: Fast Mute Control (W) Bits Name Description D7 UPD_HT This bit is controlled by S/W if AUTO_UPD=0. 0: Hold B 1: Update B from A per Hsync; see Fast Mute block diagram D6 AUTO_UPD 0: Manually control the UPD_HT bit 1: H/W automatically sets UPD_HT to update B from A when the fast mute occurs, then it clears UPD_HT after the input Hsync has been stable for at least 3mS. D5 VINT_POL Invert the internal V-sync polarity. (for debug) 0: Normal 1: Invert D4 HINT_POL Invert the internal H-sync polarity. (for debug) 0: Normal 1: Invert D3-2 DIFF_CNT The FAST MUTE will occur if the number of times out of DIFF_VAL are larger [1:0] than the DIFF_CNT setting. 00: 4 times 01: 8 times 10: 16 times 11: 32 times D1-0 DIFF_VAL Difference Boundary of the H-Period Counter [1:0] 00: 4 counts 01: 8 counts 10: 16 counts 11: Reserved Default: 11XX 0101B 93H: Fast Mute Control (R) Bits Name Description D7-6 Reserved D5 HS_ACT 0: No Hsync in 3mS interval. (for debug) 1: Hsync is active. D4 VS_ACT 0: No Vsync in 132mS interval. (for debug) 1: Vsync is active. D3-0 Reserved 2003/4/15 62 Ver.1.0 NT68520X,E 94H: Interlaced Field Decision Window (R/W) Bits Name Description D7- WIN_END The 4-bit defines the Window End position. 4 D3- WIN_STR Divide the H-sync period into 16 parts; the 4-bit defines the Window Start 0 position. IF the input V-sync leading edge locates inside the window, it represents the occurrence of the ODD field. 2003/4/15 63 Ver.1.0 NT68520X,E OSD Function 95H: OSD and Window Enable Control (R/W) Bits Name Description D7Reserved 5 D4 WIN4_EN Enable Window 4 0: Disable 1: Enable D3 WIN3_EN Enable Window 3 0: Disable 1: Enable D2 WIN2_EN Enable Window 2 0: Disable 1: Enable D1 WIN1_EN Enable Window 1 0: Disable 1: Enable D0 OSD_EN Enable OSD 0: Disable 1: Enable Default: XXX0 0000B 96H: OSD Frame Horizontal Start - Low byte (R/W) Bits Name Description D7-0 OSD_HS OSD frame horizontal start low byte [7:0]. Specifies the horizontal starting [7:0] position of the OSD in pixel units. This register is double-buffered. Default: 0000 0000B 97H: OSD Frame Horizontal Start - High Byte (R/W) Bits Name Description D7-3 Reserved D2-0 OSD_HS OSD frame horizontal start high byte [10:8]. Specifies the horizontal starting [10:8] position of the OSD in pixel units. This register is double-buffered. Default: XXXX X000B 98H: OSD Frame Horizontal Width (R/W) Bits Name Description D7-5 Reserved D4-0 OSD_HW Specifies the width of the OSD in font units. Writing this register will transfer the [4:0] double-buffered registers 96h – 97h to the actual OSD frame control registers. Range: 0~20 Default: XXX0 0000B 99H: OSD Frame Vertical Start Low byte (R/W) 2003/4/15 64 Ver.1.0 NT68520X,E Bits Name Description D7-0 OSD_VS OSD frame vertical start low byte [7:0]. Specifies the vertical starting position [7:0] of the OSD in line units. This register is double-buffered. Default: 0000 0000B 9AH: OSD Frame Vertical Start High byte (R/W) Bits Name Description D7-3 Reserved D2-0 OSD_VS OSD frame vertical start high byte [10:8]. Specifies the vertical starting [10:8] position of the OSD in line units. This register is double-buffered. Default: XXXX X000B 9BH: OSD Frame Vertical Height (R/W) Bits Name Description D7-5 Reserved D4-0 OSD_VH Specifies the height of the OSD in font units. Writing to this register will [4:0] transfer the double-buffered registers 99h – 9Ah to the actual OSD frame control registers Range: 0~16 Default: XXX0 0000B 9CH: OSD SRAM Address Offset (R/W) Bits Name Description D7-5 Reserved D4-0 OSD_SRAM_OFF OSD SRAM address offset. Number of fonts between OSD rows. [4:0] Range: 0~31 Default: XXX0 0000B 9DH: Reserved (R/W) Bits Name D7-0 Default: XXXX XXXXB Description Reserved OSD Zoom Control 9EH: OSD Zoom Control (R/W) Bits Name Description D7-4 Reserved D3 VROW_ZMEN Vertical Row Zoom Enable; Vertical zoom for all characters in one row defined in RegA6H/RegA7H. 0: Disable 1: Enable. D2 HROW_ZMEN Horizontal Row Zoom Enable; Horizontal zoom for all characters in one 2003/4/15 65 Ver.1.0 NT68520X,E D1 VGLOB_ZMEN D0 HGLOB_ZMEN row defined in regA4H/RegA5H. 0: Disable 1: Enable. Vertical Global Zoom Enable; Vertical zoom for all characters in OSD frame. 0: Disable 1: Enable. Horizontal Global Zoom Enable; Horizontal zoom for all characters in OSD frame. 0: Disable 1: Enable. Default: XXXX 0000B 9FH: OSD Font Horizontal Zoom Pattern - Low Byte (R/W) Bits Name Description D7-0 HZM_PATN Least significant 8 bits(7:0) of the horizontal zoom pattern. This is a user [7:0] definable zoom pattern. Pixels with ‘1’ pattern are duplicated according to the zoom range. Default: 0000 0000B A0H: OSD Font Horizontal/Vertical Zoom Pattern - High Byte (R/W) Bits Name Description D7-6 Reserved D5-4 VZM_PATN Most significant 2 bits(17:16) of the vertical zoom pattern. This is a user [17:16] definable zoom pattern. Pixels with ‘1’ pattern are duplicated according to the zoom range. D3-0 HZM_PATN Most significant 4 bits(11:8) of the horizontal zoom pattern. This is a user [11:8] definable zoom pattern. Pixels with ‘1’ pattern are duplicated according to the zoom range. Default: XX00 0000B A1H: OSD Font Vertical Zoom Pattern - Low Byte (R/W) Bits Name Description D7-0 VZM_PATN [7:0] Least significant 8 bits(7:0) of the vertical zoom pattern. This is a user definable zoom pattern. Pixels with ‘1’ pattern are duplicated according to the zoom range. Default: 0000 0000B A2H: OSD Font Vertical Zoom Pattern - Mid Byte (R/W) Bits Name Description D7-0 VZM_PATN Bits (15:8) of the vertical zoom pattern. This is a user definable zoom [15:8] pattern. Pixels with ‘1’ pattern are duplicated according to the zoom range. Default: 0000 0000B 2003/4/15 66 Ver.1.0 NT68520X,E A3H: OSD Font Global Zoom Range (R/W) Bits Name Description D7-4 Reserved D3-2 VGLOB_ZMRN Vertical Global Zoom Range G 00: No Zoom [1:0] 01: Vertical Zoom Pattern (RegA0H-RegA2H) ‘1’ bits are duplicated once, ‘0’ bits are not duplicated (Zooms from 1x to 2x). 10: Vertical Zoom Pattern ‘1’ bits are duplicated twice, ‘0’ bits are duplicated once (Zooms from 2x to 3x). 11: Vertical Zoom Pattern ‘1’ bits are duplicated three times, ‘0’ bits are duplicated twice (Zooms from 3x to 4x). D1-0 HGLOB_ZMRN Horizontal Global Zoom Range G 00: No Zoom [1:0] 01: Horizontal Zoom Pattern (Reg9FH-RegA0H) ‘1’ bits are duplicated once, ‘0’ bits are not duplicated (Zooms from 1x to 2x). 10: Horizontal Zoom Pattern ‘1’ bits are duplicated twice, ‘0’ bits are duplicated once (Zooms from 2x to 3x). 11: Horizontal Zoom Pattern ‘1’ bits are duplicated three times, ‘0’ bits are duplicated twice (Zooms from 3x to 4x). Default: XXXX 0000B A4H: Horizontal Row Zoom Control Row 7 - 0 (R/W) Bits Name Description D7-0 HROW_ZMPN Horizontal Row Zoom Pattern 7-0 [7:0] Zooms each row horizontally defined as zoom range according to each bit. Each bit controls a row correspondingly. Reg9E[2] must be set to ‘1’. Default: 0000 0000B A5H: Horizontal Row Zoom Control Row 15 - 8 (R/W) Bits Name Description D7-0 HROW_ZMPN Horizontal Row Zoom Pattern 15-8, Zooms each row horizontally defined [15:8] as zoom range according to each bit. Each bit controls a row correspondingly. Reg9E[2] must be set to ‘1’. Default: 0000 0000B A6H: Vertical Row Zoom Control Row 7 - 0 (R/W) Bits Name Description D7-0 VROW_ZMPN Vertical Row Zoom Pattern 7-0, Zooms each row vertically defined as [7:0] zoom range according to each bit. Each bit controls a row correspondingly. Reg9E[3] must be set to ‘1’. Default: 0000 0000B A7H: Vertical Row Zoom Control Row 15 - 8 (R/W) Bits Name Description D7-0 VROW_ZMPN Vertical Row Zoom Pattern 15-8, Zooms each row vertically defined as 2003/4/15 67 Ver.1.0 NT68520X,E [15:8] zoom range according to each bit. Each bit controls a row correspondingly. Reg9E[3] must be set to ‘1’. Default: 0000 0000B A8H: OSD Font Row Zoom Range (R/W) Bits Name Description D7-4 Reserved D3-2 VROW_ZMRNG[1: Vertical Row Zoom Range; The rows assigned by Vertical Row Zoom 0] Control registers will be zoomed up. 00: Vertical Zoom 1x for all fonts in the row 01: Vertical Zoom 2x for all fonts in the row 10: Vertical Zoom 3x for all fonts in the row 11: Vertical Zoom 4x for all fonts in the row D1-0 HROW_ZMRNG[1: Horizontal Row Zoom Range; The rows assigned by Horizontal Row 0] Zoom Control registers will be zoomed up. 00: Horizontal Zoom 1x for all fonts in the row 01: Horizontal Zoom 2x for all fonts in the row 10: Horizontal Zoom 3x for all fonts in the row 11: Horizontal Zoom 4x for all fonts in the row Default: XXXX 0000B A9H: Reserved (R/W) Bits Name D7-0 Default: XXXX XXXXB Description Reserved OSD Attribute Control AAH: OSD Attribute (R/W) Bits Name Description D7-0 OSD_ATTR [7:0] This value is appended with the character font code when updating the OSD SRAM code from host and “attribute from Reg AAh” is selected in register E0[5:4]. Default: 0000 0000B ABH: OSD Blink Control (R/W) Bits Name Description D7 Reserved D6 OSD_BLINK Blink 1=OSD frame blink enable, and the attribute bit 0 is ignored. 0=Blink control from font attribute bit 0. D5 BS_BLINK Mask Border/Shadow at Blink 1=Character border/shadow will not blink with the foreground of the character. 0= Character border/shadow will blink with the foreground of the character. 2003/4/15 68 Ver.1.0 NT68520X,E D4-2 BLINK_RATE [2:0] D1 OSD_BG [3] D0 OSD_FG [3] Blink Rate 000: Character foreground is turned on/off every 16 frames. 001: Character foreground is turned on/off every 8 frames. 010: Character foreground is turned on/off every 4 frames. 011: Character foreground is turned on/off every 2 frames. 100: Character foreground is turned on/off every other frames. OSD Background bit BG[3], The most significant bit of the OSD background color attribute. This bit is appended with the attribute bits [4:2] to make up the 4-bit background color. OSD Foreground bit FG[3], The most significant bit of the OSD foreground color attribute. This bit is appended with the attribute bits [7:5] to make up the 4-bit background color. Default: X000 0000B OSD Window Control ACH: OSD Window 1 Horizontal Start (R/W) Bits Name Description D7-5 Reserved D4-0 WIN1_HS [4:0] Horizontal starting position relative to the OSD. The unit is in font. Range: 0~19 Default: XXX0 0000B ADH: OSD Window 1 Horizontal End (R/W) Bits Name Description D7-5 Reserved D4-0 WIN1_HE [4:0] Horizontal ending position relative to the OSD. Range: 0~19 fonts Default: XXX0 0000B AEH: OSD Window 1 vertical Start/End (R/W) Bits Name Description D7-4 WIN1_VE [3:0] Vertical ending position relative to the OSD. The unit is in font. Range: 0~15 D3-0 WIN1_VS [3:0] Vertical starting position relative to the OSD. The unit is in font. Range: 0~15 Default: 0000 0000B AFH: OSD Window 1 Attribute (R/W) Bits Name Description D7-4 WIN1_ATTR Attribute Color for the OSD Window 1. This color will cover the character [3:0] background color when Window 1 is enabled. D3-2 WIN1_SDSZ Shadow Size [1:0] 00: 2 pixels in width and 2 lines in height. 01: 4 pixels in width and 4 lines in height. 10: 6 pixels in width and 6 lines in height. 2003/4/15 69 Ver.1.0 NT68520X,E D1 WIN1_SDEN D0 Default: 0000 000XB 11: 8 pixels in width and 8 lines in height. Window Shadow Enable Shadow size is specified in bits 3:2. 1= Shows a shadow for Window 1. 0= No shadow Reserved B0H: OSD Window 2 Horizontal Start (R/W) Bits Name Description D7-5 Reserved D4-0 WIN2_HS [4:0] Horizontal starting position relative to the OSD. The unit is in font. Range: 0~19 Default: XXX0 0000B B1H: OSD Window 2 Horizontal End (R/W) Bits Name Description D7-5 Reserved D4-0 WIN2_HE [4:0] Horizontal ending position relative to the OSD. The unit is in font. 0~19 Default: XXX0 0000B Range: B2H: OSD Window 2 vertical Start/End (R/W) Bits Name Description D7-4 WIN2_VE Vertical ending position relative to the OSD. The unit is in font. Range: 0~15 D3-0 WIN2_VS Vertical starting position relative to the OSD. The unit is in font. Range: 0~15 Default: 0000 0000B B3H: OSD Window 2 Attribute (R/W) Bits Name Description D7-4 WIN2_ATTR Attribute Color for the OSD Window 2. This color will cover the character [3:0] background color when Window 2 is enabled. D3-2 WIN2_SDSZ Shadow Size [1:0] 00: 2 pixels in width and 2 lines in height. 01: 4 pixels in width and 4 lines in height. 10: 6 pixels in width and 6 lines in height. 11: 8 pixels in width and 8 lines in height. D1 WIN2_SDEN Window Shadow Enable, Shadow size is specified in bits 3:2. 0: Window2 no shadow 1: Shows a shadow for Window 2. D0 Reserved Default: 0000 000XB 2003/4/15 70 Ver.1.0 NT68520X,E B4H: OSD Window 3 Horizontal Start (R/W) Bits Name Description D7-5 Reserved D4-0 WIN3_HS [4:0] Horizontal starting position relative to the OSD. The unit is in font. Range: 0~19 Default: XXX0 0000B B5H: OSD Window 3 Horizontal End (R/W) Bits Name Description D7-5 Reserved D4-0 WIN3_HE [4:0] Horizontal ending position relative to the OSD. The unit is in font. Range: 0~19 Default: XXX0 0000B B6H: OSD Window 3 vertical Start/End (R/W) Bits Name Description D7-4 WIN3_VE Vertical ending position relative to the OSD. The unit is in font. Range: 0~15 D3-0 WIN3_VS Vertical starting position relative to the OSD. The unit is in font. Range: 0~15 Default: 0000 0000B B7H: OSD Window 3 Attribute (R/W) Bits Name Description D7-4 WIN3_ATTR Attribute Color for the OSD Window 3. This color will cover the character [3:0] background color when Window 3 is enabled. D3-2 WIN3_SDSZ Shadow Size [1:0] 00: 2 pixels in width and 2 lines in height. 01: 4 pixels in width and 4 lines in height. 10: 6 pixels in width and 6 lines in height. 11: 8 pixels in width and 8 lines in height. D1 WIN3_SDEN Window Shadow Enable, Shadow size is specified in bits 3:2. 0: Window3 no shadow 1: Shows a shadow for Window 3. D0 Reserved Default: 0000 000XB B8H: OSD Window 4 Horizontal Start (R/W) Bits Name Description D7-5 Reserved D4-0 WIN4_HS [4:0] Horizontal starting position relative to the OSD. Range: 0~19 Default: XXX0 0000B 2003/4/15 71 The unit is in font. Ver.1.0 NT68520X,E B9H: OSD Window 4 Horizontal End (R/W) Bits Name Description D7-5 Reserved D4-0 WIN4_HE [4:0] Horizontal ending position relative to the OSD. The unit is in font. Range: 0~19 Default: XXX0 0000B BAH: OSD Window 4 vertical Start/End (R/W) Bits Name Description D7-4 WIN4_VE Vertical ending position relative to the OSD. The unit is in font. Range: 0~15 D3-0 WIN4_VS Vertical starting position relative to the OSD. The unit is in font. Range: 0~15 Default: 0000 0000B BBH: OSD Window 4 Attribute (R/W) Bits Name Description D7-4 WIN4_ATTR Attribute Color for the OSD Window 4. This color will cover the character [3:0] background color when Window 4 is enabled. D3-2 WIN4_SDSZ Shadow Size [1:0] 00: 2 pixels in width and 2 lines in height. 01: 4 pixels in width and 4 lines in height. 10: 6 pixels in width and 6 lines in height. 11: 8 pixels in width and 8 lines in height. D1 WIN4_SDEN Window Shadow Enable, Shadow size is specified in bits 3:2. 0: Window 4 no shadow 1: Shows a shadow for Window 4. D0 Reserved Default: 0000 000XB BCH: OSD Window Shadow Color (R/W) Bits Name Description D7-4 Reserved D3-0 WIN_SDCL [3:0] Color index for all four window’s shadow Default: XXXX 0000B BDH: Reserved (R/W) Bits Name Description D7-0 Reserved Default: XXXX XXXXB OSD Border And Shadow Control 2003/4/15 72 Ver.1.0 NT68520X,E BEH: OSD Shadow Control Row 7 - 0 (R/W) Bits Name Description D7-0 OSD_SCR [7:0] Character Row Shadow Enable for 7-0. Each bit controls each row correspondingly. 1= Enable shadow for a row. Default: 0000 0000B BFH: OSD Shadow Control Row 15 - 8 (R/W) Bits Name Description D7-0 OSD_SCR Character Row Shadow Enable for 15-8. Each bit controls each row [15:8] correspondingly. 1= Enable shadow for a row. Default: 0000 0000B C0H: OSD Border Control Row 7 - 0 (R/W) Bits Name Description D7-0 OSD_BCR [7:0] Character Row Border Enable for 7-0. Each bit controls each row correspondingly. 1= Enable border for a row. Default: 0000 0000B C1H: OSD Border Control Row 15-8 (R/W) Bits Name Description D7-0 OSD_BCR Character Row Border Enable for 15-8. Each bit controls each row [15:8] correspondingly 1= Enable border for a row. Default: 0000 0000B C2H: OSD Border & Shadow Color Row 1 - 0 (R/W) Bits Description D7- OSD_BSCR1 Character Border/Shadow Color Index For Row 1 4 [3:0] D3- OSD_BSCR0 Character Border/Shadow Color Index For Row 0 0 [3:0] Default: 0000 0000B C3H: OSD Border & Shadow Color Row 3 - 2 (R/W) Bits Name Description D7- OSD_BSCR3 Character Border/Shadow Color Index For Row 3 4 [3:0] D3- OSD_BSCR2 Character Border/Shadow Color Index For Row 2 0 [3:0] Default: 0000 0000B 2003/4/15 73 Ver.1.0 NT68520X,E C4H: OSD Border & Shadow Color Row 5 - 4 (R/W) Bits Name Description D7- OSD_BSCR5 Character Border/Shadow Color Index For Row 5 4 [3:0] D3- OSD_BSCR4 Character Border/Shadow Color Index For Row 4 0 [3:0] Default: 0000 0000B C5H: OSD Border & Shadow Color Row 7- 6 (R/W) Bits Name Description D7- OSD_BSCR7 Character Border/Shadow Color Index For Row 7 4 [3:0] D3- OSD_BSCR6 Character Border/Shadow Color Index For Row 6 0 [3:0] Default: 0000 0000B C6H: OSD Border & Shadow Color Row 9 - 8 (R/W) Bits Name Description D7- OSD_BSCR9 Character Border/Shadow Color Index For Row 9 4 [3:0] D3- OSD_BSCR8 Character Border/Shadow Color Index For Row 8 0 [3:0] Default: 0000 0000B C7H: OSD Border & Shadow Color Row 11 - 10 (R/W) Bits Name Description D7- OSD_BSCR11 Character Border/Shadow Color Index For Row 11 4 [3:0] D3- OSD_BSCR10 Character Border/Shadow Color Index For Row 10 0 [3:0] Default: 0000 0000B C8H: OSD Border & Shadow Color Row 13 - 12 (R/W) Bits Name Description D7- OSD_BSCR13 Character Border/Shadow Color Index For Row 13 4 [3:0] D3- OSD_BSCR12 Character Border/Shadow Color Index For Row 12 0 [3:0] Default: 0000 0000B C9H: OSD Border & Shadow Color Row 15 - 14 (R/W) Bits Name Description 2003/4/15 74 Ver.1.0 NT68520X,E D7- OSD_BSCR15 4 [3:0] D3- OSD_BSCR14 0 [3:0] Default: 0000 0000B CAH: Reserved (R/W) Bits Name D7-0 Default: XXXX XXXXB Character Border/Shadow Color Index For Row 15 Character Border/Shadow Color Index For Row 14 Description Reserved OSD Fast Clear Control CBH: OSD SRAM Attribute Value For Fast Clear (R/W) Bits Name Description D7- ATTR_FC [7:0] SRAM attribute for fast clear. 0 Default: 0000 0000B CCH: OSD SRAM Code Value For Fast Clear (R/W) Bits Name Description D7-0 CODE_FC [7:0] SRAM code for fast clear. Writing in this register will fill the entire SRAM with the values in RegCBh ~ RegCCh (Attribute Code:). Default: 0000 0000B CDH: Fast Clear Status (R) Bits Name Description D7-1 Reserved D0 FC_RDY Fast Clear Ready. H/W will clear all bits after reading this register. 1: Ready 0: Not Ready Default: XXXX XXX0B CEH: Reserved (R/W) Bits Name D7-0 Default: XXXX XXXXB 2003/4/15 Description Reserved 75 Ver.1.0 NT68520X,E DPLL Clock Control Formula : Fout = ((N+2) x Fref) / (M+2) Fref = 12 MHz CFH: DPLL Control(R/W) Bits Name Description D7-2 Reserved D1 DPLL_EN Enable DPLL 0: Disable 1: Enable D0 Reserved Default: XXXX XX10B D0H: Reserved D1H: Reserved D2H: DPLL VCO Divider –N (R/W) Bits Name Description D7-6 RCZ1 [1:0] D5-0 DPLL_N [5:0] DPLL VCO Divider Value (N). Default: 0000 0000B This register is double-buffered. D3H: DPLL VCO Divider –M (R/W) Bits Name Description D7-6 FOA [1:0] D5-4 VCA [1:0] D3-0 DPLL_M [3:0] DPLL VCO Divider Value (M), Writing in this register will load the double-buffered register D2h to take affect Default: 0000 0000B D4H: DPLL Select and Power Up Control (R/W) Bits Name Description D7 PU_APLL Power up PLL internal circuit 0: Power down 1: Power up D6 PU_V Power up PLL internal circuit 0: Power down 1: Power up D5 EN_FOA 2003/4/15 76 Ver.1.0 NT68520X,E D4 EN_FOB D3 D2-1 VREG [1:0] D0 SEL_DPLL Reserved For PLL internal regulator adjust Select PLL 0: Reserve 1: DPLL Default: 1100 X001B D5H: Reserved D6H: DPLL VCO Adjust (R/W) Bits Name Description D7-6 DFRANGE [1:0] DPLL frequency range 00: 22~40 MHz KVCO= 17MHz/V 01: 37~64 MHz KVCO= 26MHz/V 10: 59~106 MHz KVCO= 48MHz/V 11: 97~167 MHz KVCO= 60MHz/V D5-4 DCPI [1:0] DPLL charge pump current 00: 100 uA 01: 200 uA 10: 400 uA 11: 800 uA D3 DLOWICP Lower the charge pump current by factor. 0: 1 1: 1.5 D2-0 DKVCO [2:0] KVCO adjust for process variation 100: Normal below 100: Lower KVCO above 100: Higher KVCO Default: 1000 0100B D7H: DPLL PFD Test (R/W) Bits Name Description D7 EN_MONT D6-5 MONT[1:0] D4 TPFD2 D3-2 PFDMONT [1:0] D1 TPFD D0 TCNT Default: 0000 0000B D8H~D9H: Reserved for testing(R/W) Bits Name Description D7-0 For scaler test Default: XXXX XXXXB 2003/4/15 77 Ver.1.0 NT68520X,E Miscellaneous DA: Syncprocessor Free Run Horizontal Divider - Low Byte (R/W) Bits Name Description D7-0 DCNT Written Content of Dot Divider for Horizontal free running: [7:0] ①Bit Number = 9 Bits ②Dot Clock = 12MHz ③Valid Range = 48 ~ 511 If out of this valid range, the reset default values will be loaded into DCNT & LCNT to protect the following circuit. ④Horizontal Frequency of the free running is Hfreq(free) = 12MHz / DCNT (ex) If 100KHz free-run horizontal frequency is required , then the following divider content will be set. DCNT = 12MHz / 100KHz =120(dec) = 78(hex) Default: 0111 1100B DB: Syncprocessor Free Run Horizontal Divider - High Byte (R/W) Bits Name Description D7-1 Reserved D0 DCNT[8] MSB of Free Run Horizontal Divider (double buffer) Default: XXXX XXX1B DC: Syncprocessor Free Run Vertical Divider - Low Byte (R/W) Bits Name Description Written Content of Line Divider for Vertical free running: D7-0 LCNT ①Bit Number = 11 Bits ②Line Clock = Hfreq(free) [7:0] ③Valid Range = 100 ~ 2047 If out of this valid range, the reset default values will be loaded into DCNT & LCNT to protect the following circuit. ④Vertical Frequency of the free running is Vfreq(free) = Hfreq(free)/LCNT = (12MHz / DCNT) / LCNT (ex) if 100Hz free-run vertical frequency is required wanted at Hfreq(free)=100KHz condition, then the following Line divider content will be set LCNT = 100KHz / 100Hz =1000(dec) = 3E8(hex) Default: 0000 1101B DD: Syncprocessor Free Run Vertical Divider - High Byte (R/W) Bits Name Description D7-3 Reserved D2-0 LCNT[10:8] MSB of Free Run Vertical Divider (double buffer) 2003/4/15 78 Ver.1.0 NT68520X,E Default: XXXX X010B DE: Capture Horizontal Total Read Back - Low Byte (R) Bits Name Description D7-0 CAP_HTRB Read back the low byte value of input Hsync Total (Unit: DCLK) (for [7:0] debug) Default: XXXX XXXXB DF: Capture Horizontal Total Read Back - High Byte (R) Bits Name Description D7-6 Reserved D5-0 LCNT[13:8] Read back the high byte value of input Hsync Total (Unit: DCLK) (for debug) Default: XXXX XXXXB Index Port Access Control E0H: Index Access Port (R/W) Bits Name Description D7-6 GAMA_SEL Gamma SRAM Select 00: Red Gamma Table 01: Green Gamma Table 10: Blue Gamma Table 11: R/G/B Gamma Tables modified simultaneously D5-4 SRAM_AC SRAM Access Control Controls different ways of updating the OSD SRAM. 00: Update SRAM code and attribute. 01: Update SRAM attribute only. 10: Update SRAM code only. 11: Update SRAM code from host and attribute from REG AAh. D3-2 PORT_AC Port Access Control Specifies which set of memory to access. 00: Read/Write OSD SRAM. 01: Read/Write OSD Palette. 10: Read/Write OSD Programmable Font. 11: Read/Write Gamma SRAM. D1 PORT_RW Port Read/Write 0: Write 1: Read D0 INDEX [8] Bit 8 of SRAM address for OSD. Bit 7-0 is in E1h Default: 0000 0000B E1H: Index Address Port (R/W) Bits Name Description D7-0 INDEX ♦ OSD SRAM: Indexed by font [7:0] SRAM: Least significant 7 bits of the SRAM index. 2003/4/15 79 Ver.1.0 NT68520X,E ♦ ♦ ♦ SRAM size is 320 fonts. Index range 0 – 0x13F (319). Bit 8 in E0h[0] Palette: Indexed by word Index range 0 – 0x0F. Gamma: Indexed by byte 256 bytes for each R/G/B component Index range 0 - 0xFF. Programmable Font: Indexed by font 64 characters available for programming. Index range 0 - 0x3F. Default: 0000 0000B E2H: Index Data Port (R/W) Bits Name Description D7-0 PORT_DATA Data port for the SRAM, Palette, Programmable Font and ROM. [7:0] Default: 0000 0000B E3H: Device ID (R) Bits Name Description D7-0 ID 01H Default: XXXX XX01B E4H~E6HReserve E7H: Test Mode Control (R/W) Bits Name Description D7 Dclk_ext Feed DCLK signal from external pin 1: Enable 0: Disable D6 Reserve D5 Refclk_out REFCLK output enable 1: Enable 0: Disable D4 Rgb_ext Feed RGB signal from external pins 1: Enable 0: Disable D3 Pll_out PLL output enable 1: Enable 0: Disable D2 Adc_out ADC output Enable 1: Enable 0: Disable D1 Pbus I2C parallel bus enable 2003/4/15 80 Ver.1.0 NT68520X,E 1: Enable 0: Disable D0 Tm_en Test Mode Enable Control 1: Enable 0: Disable Default：0X00 0000B E8H: Power Control (R/W) Bits Name Description D7 MPU1 Master power control 1: Power up except PLL circuit 0: Power down except PLL circuit D6 PU_pll1 Power up frequency PLL 1: Power up 0: Power down D5 Reserved D4 PU_tsen1 Power up on chip temperature sensor 1: Power up 0: Power down D3 Reserved D2 AC_coupl DC/AC Coupling Select e 1: AC Couple 0: DC Couple D1-0 Reserved Default：11X1 01XXB E9H: Temperature control (R) Bits Name Description D7-5 Temp[2:0] Temperature readout D4-0 Reserved Default：XXXX XXXXB EAH: VGA differential output control (R/W) Bits Name Description D7 Reserved D6-4 Test_Ctrl[2: Test control 0] 000 : none 001 : R channel VGA output,TestP=VGAoutP,TestN=VGAoutM 010 : G channel VGA output,TestP=VGAoutP,TestN=VGAoutM 011 : B channel VGA output,TestP=VGAoutP,TestN=VGAoutM 100 : TestP=Tpout1 101 : TestP=Tpout2 110 : TestP=Tpout3 2003/4/15 81 Ver.1.0 NT68520X,E D3 D2 Reserved EN_acmux 4 D1 EN_acmux 1 D0 EN_acmux _vga Default：X000 X000B EBH: DAC Clock Comparator Control (R/W) Bits Name Description D7 Reserved D6 Reserved D5 Reserved D4 Reserved D3 EN_intclp =1, Enable internal AC_couple clock for VGA and auto-zero clock ADC. D2 Rgc_sw Comparator gain control for R channel D1-0 Rrf_mg[1:0 Reference voltage controller R channel resistor ] ladder 00 : 0.75v~1.25v 01 : 0.70v~1.30v 10 : 0.65v~1.35v 11 : 0.60v~1.40v Default：000X 0000B ECH: ADC R channel gain control (R/W) Bits Name Description D7-4 Rbgc2[3:0] R channel comparator gain control bias 2 D3-0 Rbgc1[3]0] R channel comparator gain control bias 1 Default：0000 0000B EDH: DC readout control for VGA and comparator control for G channel (R/W) Bits Name Description D7 Reserved D6-5 SEL_TP_v Select DC output in VGA from R,G,B channels ga[1:0] 00 : no output 01 : R channel 10 : G channel 11 : B channel D4-3 MONT_vg Select DC output in VGA a[1:0] 00 : OUTP 01 : OUTM 10 : mvga4op 11 : mvga4om D2 Ggc_sw Comparator gain control for G channel 2003/4/15 82 Ver.1.0 NT68520X,E D1-0 Grf_mg[1: Reference voltage control G channel resistor 0] ladder 00 : 0.75v~1.25v 01 : 0.70v~1.30v 10 : 0.65v~1.35v 11 : 0.60v~1.40v Default：X000 0000B EEH: ADC G channel gain control (R/W) Bits Name Description D7-4 Gbgc2[3: G channel comparator gain control bias 2 0] D3-0 Gbgc1[3: G channel comparator gain control bias 1 0] Default：0000 0000B EFH: (R/W) Bits Name Description D7 EN_ckcop ad D6-5 SEL_TP_a Select DC output in ADC from R,G,B channel dc[1:0] 00 : no output 01 : R channel 10 : G channel 11 : B channel D4-3 Mont_adc[ Select DC output in ADC 1:0] 00 : none 01 : azcm<1> 10 : azcm<0> 11 : none D2 Bgc_sw Comparator gain control for B channel D1-0 Brf_mg[1:0 Reference voltage control for B channel resistor ] ladder 00 : 0.75v~1.25v 01 : 0.70v~1.30v 10 : 0.65v~1.35v 11 : 0.60v~1.40v Default：0000 0000B F0H: ADC B channel gain control (R/W) Bits Name Description D7-4 Bbgc2[3:0] B channel comparator gain control bias 2 D3-0 Bbgc1[3:0] B channel comparator gain control bias 1 Default：0000 0000B 2003/4/15 83 Ver.1.0 NT68520X,E F1H: Tri-state output and power up ADC bias control (R/W) Bits Name Description D7 EN_Rdatapa Enable ADC R channel. d D6 EN_Gdatapa Enable ADC G channel. d D5 PU_compa_R Power up A part bias for R channel. 1 D4 PU_compb_ Power up B part bias for R channel. R1 D3 PU_compa_ Power up A part bias for G channel. G1 D2 PU_compb_ Power up B part bias for G channel. G1 D1 PU_compa_B Power up A part bias for B channel. 1 D0 PU_compb_B Power up B part bias for B channel. 1 Default：0011 1111B F2H: PLL and IV source DC readout (R/W) Bits Name Description D7 EN_Bdatapa d D6 EN_Ivmont D5-4 IV_mont[1:0] Select DC output in ibblk. D3 EN_CPO D2-1 PLLmont[1:0 ] D0 Reserved Default：0000 000XB F3H: ADC data select control (R/W) Bits Name Description D7 TST_data_ Data output either A part or B part in R channel R enable 0 : Disable 1 : Enable D6 SEL_data_ R channel data output R 0 : Select A part data output 1 : Select B part data output D5 TST_data_ Data output either A part or B part in G channel G enable 0 : Disable 1 : Enable D4 SEL_data_ G channel data output G 0 : Select A part data output 2003/4/15 84 Ver.1.0 NT68520X,E 1 : Select B part data output TST_data_ Data output either A part or B part in B channel B enable 0 : Disable 1 : Enable D2 SEL_data_ B channel data output B 0 : Select A part data output 1 : Select B part data output D1 Reserved D0 Reserved Default：0000 00XXB D3 F4H: CKCO output select (R/W) Bits Name Description D7 Bypass D6 CAPTURE_CL 0:Capture clock from Internal PLL K 1:Capture clock from YUV_CLK D5 Reserved D4 EN_CKCO CKCO clock enable 0 : Disable 1 : Enable D3-2 Reserved D1 EN_CKBO CKBO clock enable 0 : Disable 1 : Enable D0 EN_CKAO CKAO clock enable 0 : Disable 1 : Enable Default：0XX0 XX10B F5H: Test Mode Control 2 (R/W) Bits Name Description D7-6 TESR_MOD E_SEL D5 TEST_MODE Logic test mode enable D4 CKAO_EN ADC CKAO output enable D3 FLASH 1:Flash noise detect function enable NOISE D2 SERIAL_OU FIFO test serial output enable T D1 DCLK_SEL 0 : Internal source. 1 : External source. D0 I2C_START I2C start for Pbus. 0 : None 1 : Send start condition. Default：0000 0X00B 2003/4/15 85 Ver.1.0 NT68520X,E ABSOLUTE MAXIMUM RATINGS Symbol Parameter DVDD,ADC_VA Supply voltage analog 3.3V , A,PLL_VCC digital 3.3V Vin Input Voltage ( 5V Tolerant ) VESD Electrostatic Discharge TA Ambient Operating Temperature TST Storage Temperature 2003/4/15 86 Min. -0.3 Typ. Max. 3.6 Unit V -0.3 5.5 V 0 ±2.5 70 KV ℃ -40 125 ℃ Ver.1.0 NT68520X,E DC ELECTRICAL CHARACTERISTICS Symbol Parameter VCC Conditions Min. Typ. Max. Unit DVDD,CVDD,VDD,RVAA, GVAA,BVAA,ADC_RVAA, ADC_GVAA,ADC_BVAA, BIAS_VAA,DPP_VAA, VCC 3.15 3.3 3.47 V 600 mA IDD Operating current No Loading IDDPD Power down current No Loading 20 mA (VOH = 2.5V) IOH1 Output high current DCLK,RA,GA,BA,RB,GB, BB,DISP_DE,DISP_HS,D ISP_VS -16 -2 mA 2 16 mA -4 mA (VOL = 0.4V) IOL1 Output low current IOH2 Output high current IOL2 Output low current VIH Input high voltage VIL Input low voltage TA TC TJ 2003/4/15 DCLK,RA,GA,BA,RB,GB BB,DISP_DE,DISP_HS,D ISP_VS (VOH = 2.5V) IRQn (VOL = 0.4V) IRQn Ambient Operating Temperature Storage Temperature Operating Junction Temperature 87 4 mA 2.0 V 0.8 V 0 70 ℃ -55 125 ℃ 100 ℃ Ver.1.0 NT68520X,E 3.0V VDD >10ms RSTn 1.4V Internal Register Initial Period Programmed Timing All output Power -up Sequence 2003/4/15 88 Ver.1.0 NT68520X,E AC ELECTRICAL CHARACTERISTICS (VDD=3.3V, TA=25°C, Oscillator freq.=12MHz, unless otherwise specified) ADCPLL Phase-locked loop Symbol jPLL Parameter short term jitter Conditions fclkout=135Mhz long term jitter fclkout=135Mhz DR divider ratio – 1 2048 fCLKIN input clock frequency range – 16 135 kHz fCLKOUT output clock frequency range – 16 135 MHz tCOAST maximum coast mode time – δ Clock out duty cycle 135 MHz output Clamping Pulse Symbol Parameter tDELAY tWIDTH clamp pulse delay time clamp pulse width tCOR1 clamp correction time to within ±10 mV tCOR2 clamp correction time to less than 1 LSB Variation Gain Amplifier Symbol Parameter Conditions Min ns ms 55 % Min Typ Max Unit CPC_delay<3:0>=0x00 0 CKOUT CPC_delay<3:0>=0x0F 15 CKOUT CPC_width<3:0>=0x00 0 CKOUT CPC_width<3:0>=0x0F ±100mV black level input variation; clamp capacitor=4.7nF ±100mV black level input variation; clamp capacitor=4.7nF 15 CKOUT 300 ns 10 Lines Conditions Min 150 G gain range — 0.8 GSTEP gain step size — GERROR gain step size error channel to channel match input signal voltage (peak-peak) amplifier gain adjustment speed — 2003/4/15 1.2 50 — tSTAB Unit ps 45 Bandwidth Vin(p-p) Max 500 3 B GMATCH Typ Hsync active 89 Max Unit Mhz 2.0 V/V V/V 1.7/255 1/4 — corresponding to full scale output Typ Step 5 0.5 0.7 25 % 1.0 V mdb/μs Ver.1.0 NT68520X,E Analog-to-Digital Converter Symbol Parameter maximum sampling fs frequency DC differential DNL non-linearity Conditions Min S/N 2003/4/15 signal-to-noise ratio Max 135 from analog input to digital output; ramp input fCLK = 135MHz from analog input to digital output; INL DC integral non linearity ramp input fCLK = 135MHz from analog input to digital output; 10KHz sine wave input; ramp ENOB effective number of bits input; fCLK=135MHz THD total harmonic distortion Input 1V(p-p) and 10MHz Signal-to-Noise Ratio Symbol Parameter Typ Unit MHz ±1.0 LSB ±1.5 LSB 7 bits 1 % Conditions Min Typ Max Unit maximum gain fCLK=135MHz — 45 — dB Minimum gain fCLK=135MHz — 44 — dB 90 Ver.1.0 NT68520X,E I2C Bus I2C Bus Timing symbol Parameter fSCL SCL clock frequency tSUSTO STOP setup time Bus free time between tBUF a STOP and START tHDSTA START hold time SCL clock pulse width tLOW low tIICR IIC bus rise time tHDDAT DATA hold time SCL clock pulse width tHIGH high tIICF IIC bus fall time tSUDAT Data setup time tSUSTA START setup Min 0.00 0.60 Max 400 Unit kHZ us 1.30 0.60 us us 1.30 us 0.00 300 ns us 0.60 us 300 ns ns us 100 0.60 SDA tBUF TIICF TIICR tLOW SCL tSUSTO tHDSTA tHDDAT tHIGH tSUDAT tSUSTA STOP 2003/4/15 91 Ver.1.0 NT68520X,E BONDING DIAGRAM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 2003/4/15 PAD GND:G VCC:P VCC:P PAD_VCON PAD_CZ GND:G GND:G VCC:P PAD_VREF PAD_TESTP PAD_TESTN VCC:P VCC:P GND:G GND:G VCC:P PAD_RIN GND:G VCC:P VCC:P GND:G GND:G PAD_VTOP PAD_VMID PAD_VBOT VCC:P PAD_GIN GND:G VCC:P VCC:P GND:G GND:G VCC:P PAD_BIN GND:G VCC:P GND:G VCC:P GND:G GND:G GND:G PAD_OSCI PAD_OSCO PAD_NC8 PAD_VSYNCI PAD_HSYNCI PAD_SOGI X -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.22 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.23 -2639.22 Y 2340.98 2238.64 2137.16 2034.82 1932.48 1831 1728.66 1627.18 1524.84 1423.36 1321.02 1219.54 1118.06 1015.72 914.24 811.9 710.42 608.08 506.6 405.12 302.78 201.3 98.96 -3.38 -104.86 -207.2 -308.68 -411.02 -512.5 -613.98 -716.32 -817.8 -920.14 -1022.48 -1123.96 -1225.44 -1326.92 -1428.4 -1529.88 -1631.36 -1732.84 -1830.36 -1901.74 -2001.16 -2305.6 -2102.64 -2204.11 QFP 1 2 3 4 5 6 7 8 9 10 11 12 12 13 13 14 15 16 17 17 18 18 19 20 21 22 23 24 25 25 26 26 27 28 29 30 31 32 33 34 34 35 36 37 38 39 40 92 PAD X Y 48 PAD_FASTMUTE -2302.22 -2639.45 49 VCC:P -2179.24 -2639.45 50 VCC:P -2053.68 -2639.45 51 PAD_TCON_ENABLE-1932.42 -2639.45 52 GND:G -1812.02 -2639.45 53 GND:G -1699.36 -2639.45 54 VCC:P -1554.02 -2639.45 55 VCC:P -1405.24 -2639.45 56 VCC:P -1257.32 -2639.45 57 PAD_BB_0 -1162.32 -2639.45 58 PAD_BB_1 -1067.32 -2639.45 59 PAD_BB_2 -972.32 -2639.45 60 PAD_BB_3 -877.32 -2639.45 61 PAD_BB_4 -782.32 -2639.45 62 PAD_BB_5 -687.32 -2639.45 63 PAD_BB_6 -592.32 -2639.45 64 PAD_BB_7 -497.32 -2639.45 65 GND:G -402.32 -2639.45 66 GND:G -307.32 -2639.45 67 PAD_GB_0 -212.32 -2639.45 68 PAD_GB_1 -117.32 -2639.45 69 PAD_GB_2 -22.32 -2639.45 70 PAD_GB_3 72.68 -2639.45 71 PAD_GB_4 167.68 -2639.45 72 PAD_GB_5 262.68 -2639.45 73 PAD_GB_6 357.68 -2639.45 74 PAD_GB_7 452.68 -2639.45 75 VCC:P 547.68 -2639.45 76 VCC:P 642.68 -2639.45 77 PAD_RB_0 737.68 -2639.45 78 PAD_RB_1 832.68 -2639.45 79 PAD_RB_2 927.68 -2639.45 80 PAD_RB_3 1022.68 -2639.45 81 PAD_RB_4 1117.68 -2639.45 82 PAD_RB_5 1212.68 -2639.45 83 PAD_RB_6 1307.68 -2639.45 84 PAD_RB_7 1402.68 -2639.45 85 PAD_DISP_POLA 1497.68 -2639.45 86 PAD_DISP_POLB 1592.68 -2639.45 87 GND:G 1687.68 -2639.45 88 GND:G 1807.68 -2639.45 89 VCC:P 1927.68 -2639.45 90 VCC:P 2047.68 -2639.45 91 PAD_DISP_DE 2167.68 -2639.45 92 PAD_DISP_VS 2287.68 -2639.45 QFP 41 42 42 44 44 44 45 45 46 47 48 49 50 51 52 53 54 55 55 56 57 58 59 60 61 62 63 64 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Ver.1.0 NT68520X,E 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 PAD VCC:P VCC:P VCC:P VCC:P PAD_DISP_HS PAD_DISP_SPA PAD_DISP_SPB GND:G VCC:P GND:G GND:G PAD_DISP_CLKB PAD_DISP_CLKA PAD_RA_7 PAD_RA_6 PAD_RA_5 PAD_RA_4 PAD_RA_3 PAD_RA_2 PAD_RA_1 PAD_RA_0 VCC:P VCC:P PAD_GA_7 PAD_GA_6 PAD_GA_5 PAD_GA_4 PAD_GA_3 PAD_GA_2 PAD_GA_1 PAD_GA_0 GND:G GND:G PAD_BA_7 PAD_BA_6 PAD_BA_5 PAD_BA_4 PAD_BA_3 PAD_BA_2 PAD_BA_1 PAD_BA_0 VCC:P GND:G GND:G VCC:P VCC:P 2003/4/15 X 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 2640.09 Y -2306.46 -2205.84 -2105.22 -2004.6 -1903.12 -1802.5 -1701.02 -1600.4 -1498.92 -1398.3 -1296.82 -1196.32 -1101.32 -1006.32 -911.32 -816.32 -721.32 -626.32 -531.32 -436.32 -341.32 -246.32 -151.32 -56.32 38.68 133.68 228.68 323.68 418.68 513.68 608.68 703.68 798.68 893.68 988.68 1083.68 1178.68 1273.68 1368.68 1463.68 1558.68 1653.68 1815.52 1935.06 2075.24 2186.18 QFP 81 81 82 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 100 101 102 103 104 105 106 107 108 109 109 110 111 112 113 114 115 116 117 118 119 119 120 120 93 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 PAD VCC:P VCC:P PAD_GPO0 PAD_GPO1 PAD_GPO2 PAD_GPO3 PAD_GPO4 PAD_GPO5 PAD_GPO6 PAD_GPO7 PAD_GPO8 PAD_GPO9 PAD_GPO10 PAD_GPO11 VCC:P VCC:P GND:G GND:G GND:G GND:G PAD_Y_0 PAD_Y_1 PAD_Y_2 PAD_Y_3 PAD_Y_4 PAD_Y_5 PAD_Y_6 PAD_Y_7 PAD_YUV_CLK VCC:P VCC:P VCC:P VCC:P VCC:P VCC:P VCC:P PAD_NC1 PAD_NC2 PAD_NC3 PAD_NC4 PAD_NC5 PAD_NC6 PAD_SDA PAD_SCL PAD_IRQN PAD_NC7 PAD_RSTN PAD_PBUSSEL GND:G X 2640.09 2342.64 2242.88 2143.98 2045.08 1946.18 1847.28 1748.38 1649.48 1550.58 1451.68 1352.78 1253.88 1154.98 1054.36 955.46 856.56 757.66 658.76 559.86 460.96 362.06 263.16 164.26 65.36 -33.54 -132.44 -231.34 -330.24 -429.12 -528.04 -626.94 -725.84 -824.74 -923.64 -1022.54 -1121.44 -1220.34 -1319.24 -1418.14 -1517.04 -1615.94 -1714.84 -1813.74 -1912.64 -2011.54 -2110.44 -2209.34 -2308.24 Y 2297.12 2639.97 2639.97 2639.97 2639.97 2639.97 2639.97 2639.97 2639.97 2639.97 2639.97 2639.97 2639.97 2639.97 2639.98 2639.98 2639.97 2639.97 2639.97 2639.97 2639.97 2639.97 2639.97 2639.97 2639.97 2639.97 2639.97 2639.97 2639.97 2639.99 2639.97 2639.97 2639.97 2639.97 2639.97 2639.97 2639.97 2639.97 2639.97 2639.97 2639.97 2639.97 2639.97 2639.98 2639.97 2639.97 2639.97 2639.98 2639.97 QFP 121 121 122 123 124 125 126 127 128 129 130 131 132 133 134 134 135 135 135 135 136 137 138 139 140 141 142 143 144 145 145 145 146 146 147 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Ver.1.0 NT68520X,E ORDERING INFORMATION Part No. NT68520XF NT68520EF 2003/4/15 Type Function For XGA solution For SXGA solution 94 Ver.1.0 NT68520X,E PACKAGE INFORMATION unit: inches/mm QFP 160 Outline Dimensions HD D 160 121 1 GE E F 40 HE 120 81 e GD 80 c b ~ ~ 41 A2 A GD y A1 D See Detail F Seating Plane θ L L1 DETAIL F Symbol Dimensions in inches Dimensions in mm 3.68 Max. A 0.145 Max. A1 0.004 Min. 0.10 Min. A2 0.127±0.005 3.23±0.13 b 0.012 +0.004 -0.002 0.30 +0.10 -0.05 c 0.006 +0.004 -0.002 0.15 +0.10 -0.05 D 1.102±0.005 28.00±0.13 E 1.102±0.005 28.00±0.13 e 0.026±0.006 0.65±0.15 F 0.998 NOM. 25.35 NOM. GD 1.197 NOM. 30.40 NOM. GE 1.197 NOM. 30.40 NOM. HD 1.228±0.012 31.20±0.30 HE 1.228±0.012 31.20±0.30 L 0.031±0.008 0.80±0.20 L1 0.063±0.008 1.60±0.20 y 0.006 Max. 0.15 Max. q 0° ~ 12° 0° ~ 12° Notes: 1. Dimensions D and E do not include resin fins. 2. Dimensions F, GD, GE are for PC Board surface mount pad pitch design reference only. 2003/4/15 95 Ver.1.0