T73227 27 MHz VCXO Clock Generator IC October 2002 1.0 Features 3.0 • One-chip tunable voltage controlled crystal oscillator (VCXO) allows precise system frequency tuning • 3.3V operation • 8 pin SOIC and MSOP packages • Uses inexpensive 20pF pullable crystals with no external capacitors required. • 12mA drive capability at TTL levels 2.0 Description The T73227 is a single-chip, low-jitter Voltage-ControlledCrystal-Oscillator. The device accepts a 27 MHz, 20 pF crystal, and produces a low jitter output at the same frequency. A 0 to 3.0V control signal is used to fine tune the output clock frequency in the ±100ppm range. This finds use in systems that have frequency matching requirements, such as digital satellite receivers. Applications • Set-top boxes • MPEG Video clock source • Oscillator replacement Figure 1: Block Diagram VDD1 VDD2 Load Cap Control VIN X2 27 MHz Pullable Crystal Load Caps Output Buffer CLK Oscillator X1 GND1 GND2 This document contains information on a preproduction product. Specifications and information herein are subject to change without notice. ISO9001 10.29.02 T73227 27 MHz VCXO Clock Generator IC October 2002 8-pin SOIC/MSOP X1 1 8 X2 VDD1 2 7 GND1 VIN 3 6 VDD2 GND2 4 5 CLK Table 1: Pin Descriptions PIN TYPE NAME 1 Xi X1 2 P VDD1 I VIN 4 P GND2 5 O CLK 6 P VDD2 Pad Driver VDD . Connect to 3.3V 7 P GND1 Connect to Ground. 8 Xi X2 3 DESCRIPTION Crystal Connection. Connect to a 27 MHz Pullable Crystal Core VDD. Connect to 3.3V Voltage input to VCXO. Zero to 3.3V Signal Controls the Frequency of the VCXO. Connect to Ground. Clock Output Crystal Connection. Connect to a 27 MHz pullable crystal. Legend: I = Input O = Output P = Power supply connection Xi = Crystal connections. 2 10.29.02 ISO9001 T73227 27 MHz VCXO Clock Generator IC October 2002 4.0 Functional Block Description The VCXO provides a tunable, low-jitter frequency reference. Loading capacitance for the crystal is internal to the T73227. No external components (other than the crystal resonator itself) are required for operation of the VCXO. Tuning of the VCXO frequency is accomplished by varying the voltage on Vin (Pin 3). The oscillator operates the crystal resonator in the parallel-resonant mode. Crystal warping, or the “pulling” of the crystal oscillation frequency, is accomplished by altering the effective load capacitance presented to the crystal by the oscillator circuit. The actual amount that changing the load capacitance alters the oscillator frequency will be dependent on the characteristics of the crystal as well as the oscillator circuit itself. Specifically, the motional capacitance of the crystal (usually referred to by crystal manufacturers as C1), the static capacitance of the crystal (C0), and the load capacitance (CL) of the oscillator determine the “warping” or “pulling” capability of the crystal in the oscillator circuit. A simple formula to obtain the warping capability of a crystal oscilT73227 Typical VCXO Deviation vs. Vin lator is: 6 C1 × (C L 2 − C L1)× 10 2 × (C 0 + C L 2 ) × (C 0 + C L1) 150 Deviation From 27 MHz ppm ∆f ( ppm) = where CL1 and CL2 are the two extremes of the applied load capacitance. EXAMPLE: A crystal with the following parameters is used. With C1 = 0.025pF, C0 = 6pF, CL1 = 10pF, and CL2 = 20pF, the tuning range is ∆f = 0.025 × (20 − 10 ) × 10 6 = 300 ppm . 2 × (6 + 20 ) × (6 + 10 ) 100 50 0 -50 -100 -150 0.1 0.4 0.7 0.9 1.2 1.5 1.8 2.0 2.3 2.5 2.7 Vin 5.0 Electrical Specifications Table 2: Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance, functionality, and reliability. PARAMETER Supply Voltage (VSS = ground) SYMBOL MIN. MAX. UNITS VDD VSS-0.5 5 V Input Voltage, dc VI VSS-0.5 VDD+0.5 V Output Voltage, dc VO VSS-0.5 VDD+0.5 V Input Clamp Current, dc (VI < 0 or VI > VDD) IIK -25 25 mA Output Clamp Current, dc (VI < 0 or VI > VDD) IOK -50 50 mA Storage Temperature Range (non-condensing) TS -65 150 °C Ambient Temperature Range, Under Bias TA -55 125 °C Junction Temperature TJ 125 °C Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection 260 °C 2 KV 3 10.29.02 ISO9001 T73227 27 MHz VCXO Clock Generator IC October 2002 Table 3: Operating Conditions PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS 3.3 3.45 V Core Supply Voltage (VDD) VDD 3.15 VCXO Control Voltage, VIN VIN 0 VDD V Ambient Operating Temperature Range TA 0 70 °C 30 MHz Crystal Resonator Frequency fXTAL Crystal Load Capacitance CL(xtal) Fundamental Mode 20 27 AT cut 20 pF Table 4: DC Electrical Specifications Unless otherwise stated, VDD = 3.15V to 3.45V , no load on any output, and ambient temperature range TA = 0°C to 70°C. PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS Overall Supply Current, Dynamic, with no load IDD fXTAL = 27MHz Output High Voltage VOH IOH = -12mA Output Low Voltage VOL IOL = 12mA 25 mA 2.4 V 0.4 V Voltage Controlled Crystal Oscillator - VDD=3.3V Crystal Loading Capacitance CL(xtal) Crystal Gamma CO/C1 As seen by a crystal connected to XIN and XOUT (@ VXTUNE = 1.65V) 20 pF 240 VCXO Tuning Range fXTAL = 27MHz; CL(xtal) = 20pF; gamma = 240 VCXO Tuning Characteristic Note: positive ∆F for positive ∆V 250 ppm 75 Crystal ESR ppm/V 50 Ω Table 5: AC Timing Specifications Unless otherwise stated, VDD = 3.15V to 3.45V, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. Ratio of high pulse width (as measured from rising edge to next falling edge at VDD/2) to one clock period 40 TYP. MAX. UNITS 60 % From rising edge to next rising edge at VDD/2, CL = 10pF 150 ps Clock Output (CLK) Duty Cycle * Jitter, Period (peak-peak) * tj(∆P) Rise Time * tr Measured 0.8V to 2.0V, CL = 10pF 1.5 ns Fall Time * tf Measured 2.0V to 0.8V; CL = 10pF 1.5 ns 4 10.29.02 ISO9001 T73227 27 MHz VCXO Clock Generator IC October 2002 Phase Noise vs. Frequency Offset Phase Noise, dBc/Hz - 50 - 70 - 90 - 110 - 130 - 150 100 1K 10K 100K 1M Frequency Offset from 27MHz 6.0 Ordering Information ORDERING PART NUMBER PACKAGE TYPE SHIPPING CONFIGURATION T73227-S08 8-pin SOIC Tubes T73227-S08-TNR 8-pin SOIC Tape and Reel T73227-M08 8-pin MSOP Tubes T73227-M08-TNR 8-pin MSOP Tape and Reel T73227-DIE DIE Waffle-Pack TLSI reserves the right to make changes to its products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TLSI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TLSI’s standard warranty. Testing and other quality control techniques are utilized to the extent TLSI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TLSI devices. Information furnished by TLSI is believed to be accurate and reliable. However, no responsibility is assumed by TLSI for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of TLSI. 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