Fiber Optic “Light to Logic” Receiver with Clock Recovery Preliminary Technical Data RGR2622 Features Applications Description • Light to Logic 20-Pin DIP Receiver Offers ECL Compatibility • Sensitivity: –31 dBm • Phase-Locked Loop (PLL) Timing Recovery Circuit • Meets All SONET Jitter Requirements (CCITT G.958) • Single +5 V Supply, Typically <1.00 W • SONET/SDH Compliant • Telecommunication Networks • SONET OC12 and SDH STM4 Compatible • Local and Metropolitan Area Networks • ATM Single Mode Public Network • Military Communications and Control Systems • Digital Cable TV Networks The RGR2622 receiver provides optical signal conversion and processing. It converts 1200 nm to 1600 nm wavelength lightwave information into an electrical signal at data rates of 622 Mb/s. Each receiver contains an InGaAs PIN photodiode, a high sensitivity, wide dynamic range transimpedance amplifier, capacitively coupled to a PLL based clock recovery circuit. The clock and data outputs are retimed complementary PECL. A complementary CMOS compatible low light alarm is also provided. Preliminary Product Disclaimer This preliminary data sheet is provided to assist you in the evaluation of engineering samples of the product which is under development. Until Hewlett-Packard releases this product for general sales, HP reserves the right to alter prices, specifications, features, capabilities, function, manufacturing release dates, and even general availability of the product at any time. 406 (5/97) Connection Diagram Top View FIBER PIGTAIL GND 1 20 NC GND 2 19 NC GND 3 18 NC CLOCK 4 17 NC CLOCK 5 16 GND GND 6 15 GND DATA 7 14 ALARM GND 8 13 GND DATA 9 12 ALARM 10 11 +5 V PD BIAS Pin Descriptions Pins 1, 2, 3, 6, 8, 13, 15, 16, GND: These pins should be connected to the circuit ground. Pins 4, 5, CLOCK, CLOCK: These pins provide complementary PECL CLOCK and CLOCK outputs. Pins 7, 9, DATA, DATA: These pins provide complementary PECL DATA and DATA outputs. The RGR2622 DATA output is noninverting, an optical pulse causes the DATA output to go to Pins 12, 14, ALARM, ALARM: These pins provide complementary ALARM and ALARM outputs. the PECL logic high state (+4 V nominal). Pin 10, PD Bias: This pin must be connected to any voltage from 0 V (GND) to –5 V. This provides the photodiode bias. The current drawn is directly proportional to the average received photocurrent. I = Responsivity x Mean Power. The Responsivity will be between 0.8 A/W and 1.0 A/W. Pin 11, +5 V: This pin should be connected to +5 V supply. The network shown below should be placed as close as possible to pin 11. This is the low light alarm. ALARM goes to a logic low (CMOS compatible) state when the optical power drops below the threshold level (insufficient optical power). The optical power must increase to a higher level than the level where the alarm went low before ALARM will return to a logic high. This difference is the alarm hysteresis. Pins 17, 18, 19, 20 NC: These pins are not connected. 1 µH +5 V PIN 11 10 µF 100 nF 100 nF 407 Functional Description Design The receiver contains an InGaAsP photodetector, transimpedance amplifier and interface amplifier circuit, including a clock recovery and data retiming function. It is designed with a multimode fiber pigtail to allow maximum flexibility in connector options. The interface amplifier is ac coupled to the preamplifier circuit. Terminating the Outputs The data outputs of the RGR2622 are PECL compatible. Care should be taken to match termination impedances to the interconnect to minimize reflection effects. In order to balance the drive currents drawn from the RGR2622 all serial data outputs (DATA and DATA, CLOCK and CLOCK) should be terminated identically, even if only one output is used. highly recommended for those users who are not familiar with these techniques. This will lower the power supply noise generated by the RGR2622 and improve performance at low optical input power levels. Signal traces should conform to ECL design rules to prevent reflections and ringing from degrading performance. Useful guidelines are contained in ECL manufacturer design manuals. Power Supplies The RGR2622 will operate to specifications with a single +5 V power supply (Pin 10 grounded). The –5 V pin bias is provided to maintain functional compatibility with second sources. Circuit Layout The RGR2622 uses very high bandwidth circuitry to achieve its high level of performance. Care must be taken to ensure stable operation. The use of ground planes and transmission line interconnects is required. The use of a standard evaluation board is Manufacturing The fiber pigtail on the device requires normal fiber handling considerations. Care should be taken to avoid tight bends as well as excessive tension on the fiber pigtail. The allowable temperature range for the RGR2622 is limited by the material used in the pigtail. Exposure to temperatures over +85°C is not recommended. Low profile sockets or hand soldering are recommended for this part. VCC (+5 V) +5 V TI AMP MID AMP ALARM ALARM LOW PASS FILTER 0V VNEG (-5 V OR GND) GND (0 V) Figure 1. Block Diagram. 408 PLL CLOCK AND DATA RECOVERY DATA DATA CLOCK CLOCK Performance Specifications Absolute Maximum Ratings Absolute maximum limits mean that no catastrophic damage will occur if the product is subjected to these ratings for short periods, provided that each limiting parameter is in isolation and all other parameters have values within the performance specification. It should not be assumed that limiting values of more than one parameter can be applied to the product at the same time. Parameter Supply Voltage Supply Voltage Symbol VCC VNEG Minimum –0.5 –10 Maximum +5.5 +0.5 Units V V Note 1 1 Symbol - Minimum –40 –40 - Maximum +85 +85 85 Units °C °C %RH Note - Minimum 4.75 3.8 3.1 4.5 0 Maximum 5.25 250 4.15 3.5 5.0 0.5 Units V mA V V V V Note 4 2, 3 2, 3 3 3 Environmental Parameters Parameter Operating Temperature Storage Temperature Humidity Electrical Parameters (–40°C to +85°C) Parameter Supply Voltage VCC Supply Current DATA Output Level (high) DATA Output Level (low) ALARM Output Level (high) ALARM Output Level (low) Symbol VCC V off V on Notes: 1. On an RGR2622 VCC of –0.5 V and VNEG of +0.5 V may not be applied simultaneously. 2. Output terminated to (VCC -2) with 50 Ω load or equivalent. 3. Output voltages are for VCC = 5.0 V. 4. Outputs not loaded. 409 Optical Parameters (–40°C to +85°C) Parameter Wavelength Receiver Sensitivity Maximum Input Power Alarm ON Hysteresis Alarm Response Time Reliability Target Jitter Tolerance Jitter Transfer Jitter Generation Symbol - Minimum 1200 –4 –40 1 - Typical –33.5 - Maximum 1600 –31 –30 6 600 2000 Units nm dBm dBm dBm dB µS FIT ITU G.958 Compliant ITU G.958 Compliant ITU G.958 Compliant Note: 1. At a BER of 1 x 10-10, 223-1 PRBS pattern NRZ data at the line rate with 10:1 extinction ratio. EOL. Fiber Parameters Fiber Pigtail Core Diameter Cladding Diameter Secondary Coating Diameter 410 Typical 50 125 900 Units microns microns microns Note 1 - Drawing Dimensions L 20 11 C 1 B 10 A D J H ∅G K DIM. MIN. NOM. MAX. A B C 32.9 – 16.0 – – – 33.2 D E F – 2.6 – – – 2.54 ∅G H J K – 2.7 – – 0.46 – – 10.16 L 400 – ALL DIMENSIONS IN MILLIMETERS F E 17.5 16.3 9.27 2.95 – – 3.2 4.64 – 1220 Ordering Information RGR2622 - XX Connector: FP = FC/PC Polish ST* = ST SC = SC DN = DN Allowable part numbers RGR2622 Handling Precautions 1. The RGR2622 can be damaged by current surges or overvoltage. Power supply transient precautions should be taken. 2. Normal handling precautions for electrostatic sensitive devices should be taken. *ST is a registered trademark of AT&T. 411