KODENSHI KK74AC193

TECHNICAL DATA
KK74AC193
Presettable 4-Bit Binary UP/DOWN Counter
High-Speed Silicon-Gate CMOS
The KK74AC193 is identical in pinout to the LS/ALS193,
HC/HCT193. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LS/ALS outputs.
The counter has two separate clock inputs, a Count Up Clock and
Count Down Clock inputs. The direction of counting is determined by
which input is clocked. The outputs change state synchronous with the
LOW-to-HIGH transitions on the clock inputs. This counter may be
preset by entering the desired data on the P0, P1, P2, P3 input. When the
Parallel Load input is taken low the data is loaded independently of either
clock input. This feature allows the counters to be used as devide-by-n by
modifying the count lenght with the preset inputs. In addition the counter
can also be cleared. This is accomplished by inputting a high on the
Master Reset input. All 4 internal stages are set to low independently of
either clock input.Both a Terminal Count Down (TCD) and Terminal
Count Up (TCU) Outputs are provided to enable cascading of both up and
down counting functions. The TCD output produces a negative going
pulse when the counter underflows and TCU outputs a pulse when the
counter overflows. The counter can be cascaded by connecting the TCU
and TCD outputs of one device to the Count Up Clock and Count Down
Clock inputs, respectively, of the next device.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA; 0.1 µA @ 25°C
• High Noise Immunity Characteristic of CMOS Devices
• Outputs Source/Sink 24 mA
ORDERING INFORMATION
KK74AC193N Plastic
KK74AC193D SOIC
TA = -40° to 85° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16 =VCC
PIN 8 = GND
1
KK74AC193
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
-0.5 to +7.0
V
VCC
DC Supply Voltage (Referenced to GND)
VIN
DC Input Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
DC Input Current, per Pin
±20
mA
IOUT
DC Output Sink/Source Current, per Pin
±50
mA
ICC
DC Supply Current, VCC and GND Pins
±50
mA
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
-65 to +150
°C
260
°C
VOUT
IIN
Tstg
TL
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIN, VOUT
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TJ
Junction Temperature (PDIP)
TA
Operating Temperature, All Package Types
IOH
Output Current - High
IOL
Output Current - Low
tr, tf
*
Parameter
Input Rise and Fall Time
(except Schmitt Inputs)
*
Min
Max
Unit
2.0
6.0
V
0
VCC
V
140
°C
+85
°C
-24
mA
24
mA
150
40
25
ns/V
-40
VCC =3.0 V
VCC =4.5 V
VCC =5.5 V
0
0
0
VIN from 30% to 70% VCC
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or
VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
2
KK74AC193
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
Symbol
Parameter
Test Conditions
Guaranteed Limits
V
25 °C
-40°C to
85°C
Unit
VIH
Minimum High-Level
Input Voltage
VOUT=0.1 V or VCC-0.1 V
3.0
4.5
5.5
2.1
3.15
3.85
2.1
3.15
3.85
V
VIL
Maximum Low -Level
Input Voltage
VOUT=0.1 V or VCC-0.1 V
3.0
4.5
5.5
0.9
1.35
1.65
0.9
1.35
1.65
V
VOH
Minimum High-Level
Output Voltage
IOUT ≤ -50 µA
3.0
4.5
5.5
2.9
4.4
5.4
2.9
4.4
5.4
V
3.0
4.5
5.5
2.56
3.86
4.86
2.46
3.76
4.76
3.0
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
VIN=VIH or VIL
IOL=12 mA
IOL=24 mA
IOL=24 mA
3.0
4.5
5.5
0.36
0.36
0.36
0.44
0.44
0.44
Maximum Input Leakage
Current
VIN=VCC or GND
5.5
±0.1
±1.0
µA
IOLD
+Minimum Dynamic
Output Current
VOLD=1.65 V Max
5.5
75
mA
IOHD
+Minimum Dynamic
Output Current
VOHD=3.85 V Min
5.5
-75
mA
ICC
Maximum Quiescent
Supply Current
(per Package)
VIN=VCC or GND
5.5
80
µA
*
VIN=VIH or VIL
IOH=-12 mA
IOH=-24 mA
IOH=-24 mA
VOL
Maximum Low-Level
Output Voltage
IOUT ≤ 50 µA
V
*
IIN
8.0
*
All outputs loaded; thresholds on input associated with output under test.
+Maximum test duration 2.0 ms, one output loaded at a time.
Note: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC
FUNCTION TABLE
MR
PL
Inputs
CPU
H
X
L
L
L
H
L
H
L
H
L
H
X = don’t care
X
X
H
H
Mode
CPD
X
X
H
H
Reset(Asyn.)
Preset(Asyn.)
No Count
Count Up
Count Down
No Count
The KK74AC193 is an UP/DOWN MODULO16 Binary Counter.
Logic equations
For Terminal Count:
TCU = Q0 • Q1 • Q2 • Q3 • CPU
TCD = Q0 • Q1 • Q2 • Q3 • CPD
3
KK74AC193
AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=3.0 ns)
VCC*
Symbol
Parameter
V
Guaranteed Limits
25 °C
Min
-40°C to 85°C
Max
88
120
Min
Unit
Max
fmax
Maximum Clock Frequency (Figure 1)
3.3
5.0
40
55
tPLH
Propagation Delay, CPU or CPD to TCU or
TCD (Figure 2)
3.3
5.0
20
13
22
14.5
ns
tPHL
Propagation Delay, CPU or CPD to TCU or
TCD (Figure 2)
3.3
5.0
19
11.5
21
13.0
ns
tPLH
Propagation Delay, CPU or CPD to Qn (Figure
1)
3.3
5.0
15
10
17.0
11.5
ns
tPHL
Propagation Delay, CPU or CPD to Qn (Figure
1)
3.3
5.0
15
9.5
17.0
11
ns
tPLH
Propagation Delay, Pn to Qn (Figure 3)
3.3
5.0
15
10
17.0
11.5
ns
tPHL
Propagation Delay, Pn to Qn (Figure 3)
3.3
5.0
15
9.5
17.0
11
ns
tPLH
Propagation Delay, PL to Qn (Figure 4)
3.3
5.0
15
10
17
11.5
ns
tPHL
Propagation Delay, PL to Qn (Figure 4)
3.3
5.0
20
12.5
22
14
ns
tPHL
Propagation Delay, MR to Qn (Figure 5)
3.3
5.0
20
12.5
22
14
ns
tPLH
Propagation Delay, MR to TCU (Figure 6)
3.3
5.0
18
12
20
13.5
ns
tPHL
Propagation Delay, MR to TCD (Figure 6)
3.3
5.0
19
11.5
21
13.0
ns
tPLH
Propagation Delay, PL to TCU or TCD (Figure
6)
3.3
5.0
20
13
22
14.5
ns
tPHL
Propagation Delay, PL to TCU or TCD (Figure
6)
3.3
5.0
15
8.5
17
10
ns
tPLH
Propagation Delay, Pn to TCU or TCD (Figure
6)
3.3
5.0
20
13
22
14.5
ns
tPHL
Propagation Delay, Pn to TCU or TCD (Figure
6)
3.3
5.0
20
12.5
22
14
ns
CIN
Maximum Input Capacitance
5.0
4.5
MHz
4.5
pF
Typical @25°C,VCC=5.0 V
CPD
Power Dissipation Capacitance
45
pF
Voltage Range 3.3 V is 3.3 V ±0.3 V
Voltage Range 5.0 V is 5.0 V ±0.5 V
*
4
KK74AC193
TIMING REQUIREMENTS (CL=50pF, Input tr=tf=3.0 ns)
VCC*
Symbol
Parameter
Guaranteed Limits
V
25 °C
-40°C to
85°C
Unit
tsu
Minimum Setup Time, Pn to PL (Figure 7)
3.3
5.0
9
6
10
7
ns
th
Minimum Hold Time, PL to Pn (Figure 7)
3.3
5.0
-1.0
-1.0
0
0
ns
tw
Minimum Pulse Width, PL (Figure 4)
3.3
5.0
17
12
21
13
ns
tw
Minimum Pulse Width, CPU or CPD
(Figure 1)
3.3
5.0
11
8
12
9
ns
tw
Minimum Pulse Width, MR (Figure 5)
3.3
5.0
14
10
16
12
ns
trec
Minimum Recovery Time, PL to CPU or CPD
(Figure 5)
3.3
5.0
9
12
10
13
ns
trec
Minimum Recovery Time, MR to CPU or CPD
(Figure 5)
3.3
5.0
17
12
21
14
ns
Voltage Range 3.3 V is 3.3 V ±0.3 V
Voltage Range 5.0 V is 5.0 V ±0.5 V
*
Figure 1. Switching Waveforms
Figure 3. Switching Waveforms
Figure 2. Switching Waveforms
Figure 4. Switching Waveforms
5
KK74AC193
Figure 5. Switching Waveforms
Figure 6. Switching Waveforms
Figure 7. Switching Waveforms
TIMING DIAGRAM
6
KK74AC193
EXPANDED LOGIC DIAGRAM
7
KK74AC193
N SUFFIX PLASTIC DIP
(MS - 001BB)
A
Dimension, mm
9
16
Symbol
MIN
MAX
A
18.67
19.69
B
6.1
7.11
B
1
8
5.33
C
F
L
C
D
0.36
0.56
F
1.14
1.78
G
2.54
H
7.62
-T- SEATING
PLANE
N
G
K
M
H
D
J
0.25 (0.010) M T
NOTES:
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
J
0°
10°
K
2.92
3.81
L
7.62
8.26
M
0.2
0.36
N
0.38
D SUFFIX SOIC
(MS - 012AC)
Dimension, mm
A
16
9
H
B
1
G
P
8
R x 45
C
-TK
D
SEATING
PLANE
J
0.25 (0.010) M T C M
NOTES:
1. Dimensions A and B do not include mold flash or protrusion.
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
for A; for B ‑ 0.25 mm (0.010) per side.
F
M
Symbol
MIN
MAX
A
9.8
10
B
3.8
4
C
1.35
1.75
D
0.33
0.51
F
0.4
1.27
G
1.27
H
5.72
J
0°
8°
K
0.1
0.25
M
0.19
0.25
P
5.8
6.2
R
0.25
0.5
8